| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 365233180 | Burst mode signal | 6 |
| 20090251988 | SYSTEM AND METHOD FOR PROVIDING A NON-POWER-OF-TWO BURST LENGTH IN A MEMORY SYSTEM - A memory system, memory interface device and method for a non-power-of-two burst length are provided. The memory system includes a plurality of memory devices with non-power-of-two burst length logic and a memory interface device including non-power-of-two burst length generation logic. The non-power-of-two burst length generation logic extends a burst length from a power-of-two value to insert an error-detecting code in a burst on data lines between the memory interface device and the plurality of memory devices. | 10-08-2009 |
| 20100177590 | Burst mode control circuit - A burst mode control unit includes a burst period signal generation unit for generating a burst period signal which is enabled during a burst mode operation period, a burst pulse generation unit for generating a burst pulse, which is generated at every predetermined number of cycles during the enabled period of the burst period signal, in response to a read command and a write command, and a column access signal generation unit for receiving the burst signal and a clock signal and generating a column access signal which controls input and output of data during the burst mode operation period. | 07-15-2010 |
| 20110128811 | INTERNAL COMMAND GENERATION CIRCUIT - The internal command generation circuit includes a burst pulse generation unit and a pulse shifting unit. The burst pulse generation unit is configured to receive a command for a read or write operation, and generate a first burst pulse. The pulse shifting unit is configured to shift the first burst pulse and generate an internal command. | 06-02-2011 |
| 20110158033 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a burst pulse generation unit configured to store a burst length information signal in response to a first control signal and output the burst length information signal as a burst pulse signal in response to a second control signal; and an input/output(I/O) control unit configured to generate the first and second control signals in response to a read pulse signal and a latency signal, respectively. | 06-30-2011 |
| 20120087201 | SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME - A semiconductor memory device includes an internal clock signal generator configured to generate an internal clock signal by dividing a frequency of an external clock signal; a default latency determiner configured to determine a default latency in outputting a signal; and a latency reflector configured to, for each of consecutive commands, selectively add a half latency equal to a half cycle of the internal clock signal to the default latency in response to a half latency selection information signal. | 04-12-2012 |
| 20120294106 | INTERNAL COMMAND GENERATION CIRCUIT - The internal command generation circuit includes a burst pulse generation unit and a pulse shifting unit. The burst pulse generation unit is configured to receive a command for a read or write operation, and generate a first burst pulse. The pulse shifting unit is configured to shift the first burst pulse and generate an internal command. | 11-22-2012 |
