Class / Patent application number | Description | Number of patent applications / Date published |
365233110 | Plural clock signals | 30 |
20090116331 | Semiconductor memory device and method for operating the same - Semiconductor memory device and method for operating the same includes a phase detection unit configured to compare a phase of a first reference clock and a phase of a second divided reference clock to output a comparison result signal and a phase control and division unit configured to generate the second divided reference clock by dividing a second reference clock by a predetermined ratio according to the comparison result signal outputted from the phase detection unit and adjusting a phase of the second reference clock. | 05-07-2009 |
20090129196 | SEMICONDUCTOR INTEGRATED CIRCUIT - A clock signal generation circuit into which a first clock signal and a control signal based on an address are inputted, and a second clock signal based on said first clock signal is generated after a lapse of predetermined time from said input of the control signal. | 05-21-2009 |
20090190431 | Double data rate-single data rate input block and method for using same - A disclosed embodiment is a double data rate (DDR) input block comprising first and second input registers corresponding to a DDR input of the DDR input block. The first and second input registers are coupled to the DDR input. The DDR input block is configured to load a first data into the first input register and a second data into the second input register during a single clock cycle of a system clock, thereby operating at double data input during a single clock cycle. In one embodiment a single data rate/double data rate (SDR/DDR) input block may be operated in either SDR or DDR mode. In one embodiment, the DDR input block may be used with a scannable output reduction block. The DDR input block may be used in systems utilizing a content addressable memory (CAM) or a random access memory (RAM), or other types of memory devices. | 07-30-2009 |
20090219779 | Dual Channel Memory Architecture Having a Reduced Interface Pin Requirements Using a Double Data Rate Scheme for the Address/Control Signals - Apparatuses and methods for dual channel memory architecture with reduced interface pin requirements are presented. One memory architecture includes a memory controller, a first memory device coupled to the memory controller by a shared address bus and a first clock signal, and a second memory device coupled to the memory controller by the shared address bus and a second clock signal, where the polarity of the second clock signal is opposite of the first clock signal. A method for performing data transactions is presented. The method includes providing addressing signals over a shared address bus to a first memory device and a second memory device, providing clock signals to the memory devices which are reversed in polarity, where the clock signals are derived from a common clock signal, and transferring data to the memory devices over separate narrow data buses in an alternating manner based upon the clock signals. | 09-03-2009 |
20090251987 | Memory Data Transfer - In one aspect, there is provided a method for controlling data output by a memory device. The method may include receiving a first clock signal having a first frequency. Moreover, a second and third clock signals may be produced from the first clock signal. The second and third clock signals may have second and third frequencies, respectively, that are about equal to the first frequency. The second and third frequencies may be out of phase relative to each other. A controller may output a first data in response to a rising edge of the second clock signal and output a second data in response to another rising edge of the third clock signal. | 10-08-2009 |
20100008177 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a clock input unit configured to receive a first clock and a second clock from the external. The memory device further includes a frequency conversion unit configured to convert a frequency of the second clock so that the frequency of the second clock becomes identical to a frequency of the first clock, a phase comparison unit configured to compare a phase of the first clock with that of a clock outputted from the frequency conversion unit, and output a comparison signal corresponding to the comparison result, a logic level change unit configured to change a logic level of a training information signal when a logic level of the comparison signal is fixed for a given time after being changed, and a signal transfer unit configured to transfer the training information signal to the external. | 01-14-2010 |
20100135100 | Adjusting Clock Error Across A Circuit Interface - A system is provided with clock skew measurement and correction technology. A first circuit or memory controller | 06-03-2010 |
20100177588 | CALIBRATION CIRCUIT AND CALIBRATION METHOD - A calibration circuit includes replica buffers that have a substantially same circuit configuration as at least a part of an output buffer, an oscillator circuit that generates an internal clock in response to issuance of a calibration command, and a control circuit that controls an impedance of the replica buffers in synchronization with the internal clock. According to the present invention, because a calibration operation that does not depend on an external clock is performed, even when a frequency of the external clock is changed according to an operation mode or the like, it is possible to maintain a constant period of time given to a single adjustment step or a constant time required for a series of calibration operations. | 07-15-2010 |
20100177589 | SEMICONDUCTOR DEVICE HAVING LATENCY COUNTER - A semiconductor device includes a latency setting circuit setting the latency, an input command circuit outputting a normal-phase (reverse-phase) command signal obtained by capturing an input command signal using a normal-phase (reverse-phase) clock, first and second counter circuits each including latch circuits sequentially shifting the normal-phase (reverse-phase) command signal based on the normal-phase (reverse-phase) clock, a selector circuit controlling a signal path so that the normal-phase (reverse-phase) command signal is transmitted through the first (second) counter circuit when an even latency is set and the normal-phase (reverse-phase) command signal is transmitted so as to be shifted from the first (second) counter circuit to the second (first) counter circuit when an odd latency is set, and a control circuit controlling so that the latch circuits of the first (second) counter circuit are activated in response to the input command signal and stopped after an operation period is elapsed. | 07-15-2010 |
20100246311 | CLOCK GENERATORS, MEMORY CIRCUITS, SYSTEMS, AND METHODS FOR PROVIDING AN INTERNAL CLOCK SIGNAL - A clock generator includes a first input end and a second input end. The first input end is capable of receiving a first clock signal including a first state transition and a second state transition defining a first pulse width. The second input end is capable of receiving a second clock signal having a third state transition. A time period ranges from the first state transition to the third state transition. The clock generator can compare the first pulse width and the time period. The clock generator can output a third clock signal having a second pulse width ranging from a fourth state transition to a fifth state transition. The fifth state transition of the third clock signal is capable of being triggered by the second state transition of the first clock signal or the third state transition of the second clock signal depending on the comparison of the first pulse width and the time period. | 09-30-2010 |
20100309744 | SEMICONDUCTOR MEMORY DEVICE FOR GUARANTEEING RELIABILITY OF DATA TRANSMISSION AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor device includes a system clock input unit configured to receive a system clock for synchronizing input times of an address signal and a command signal from a memory controller, a data clock input unit configured to receive first and second data clocks for synchronizing an input/output time of a data signal from the memory controller, wherein a phase of the second data clock is shifted according to a training information signal, and the second data clock having the shifted phase is inputted to the data clock input unit, and a phase detection unit configured to detect a logic level of the second data clock based on an edge of the first data clock, and generate the training information signal to transmit the generated signal to the memory controller according to the detected logic level. | 12-09-2010 |
20110116337 | Synchronising between clock domains - An integrated circuit | 05-19-2011 |
20110158031 | SIGNAL CALIBRATION METHODS AND APPARATUSES - In a signal calibration scheme, a desired phase relationship is maintained between a set of signals. For example, in some aspects the desired phase of a clock tree generated from a high speed reference clock signal may be maintained by detecting phase differences between a low speed reference clock signal and low speed clock signals associated with different phases of the clock tree. In some aspects, the desired phase of a clock tree may be maintained by detecting framing offsets that occur through the use of the clock tree. | 06-30-2011 |
20110211416 | CIRCUIT AND METHOD FOR RECOVERING CLOCK DATA IN HIGHLY INTEGRATED SEMICONDUCTOR MEMORY APPARATUS - Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus includes a plurality of signal receiving units configured to receive signals through a plurality of input/output pads and transfer the signals according to a receiving reference clock, the signal receiving units being divided into groups, a plurality of phase detection units configured to detect phases of signals output from the groups of the signal receiving units, a plurality of phase detection control units configured to control the phase detection units so that the phase detection units sequentially detect the phases of the signals output from each of the groups of the signal receiving units and a notification unit configured to output signals output from the phase detection units. | 09-01-2011 |
20110235459 | CLOCK-FORWARDING LOW-POWER SIGNALING SYSTEM - In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time. | 09-29-2011 |
20120014205 | SEMICONDUCTOR MEMORY DEVICE FOR GUARANTEEING RELIABILITY OF DATA TRANSMISSION AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor device includes a system clock input unit configured to receive a system clock for synchronizing input times of an address signal and a command signal from a memory controller, a data clock input unit configured to receive first and second data clocks for synchronizing an input/output time of a data signal from the memory controller, wherein a phase of the second data clock is shifted according to a training information signal, and the second data clock having the shifted phase is inputted to the data clock input unit, and a phase detection unit configured to detect a logic level of the second data clock based on an edge of the first data clock, and generate the training information signal to transmit the generated signal to the memory controller according to the detected logic level. | 01-19-2012 |
20120195153 | SEMICONDUCTOR SYSTEM AND SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes an odd data clock buffer group configured to maintain or shift a phase of a multi-phase source clock signal, and output a first multi-phase clock signal, an even data clock buffer group configured to maintain or shift a phase of the multi-phase source clock signal, and output a second multi-phase clock signal, an odd data output buffer group configured to drive odd data in response to the first multi-phase clock signal and output the driven data to an odd data pad group, and an even data output buffer group configured to drive even data in response to the second multi-phase clock signal and output the driven data to an even data pad group, wherein the phases of clock signals of the first and second multi-phase clock signal are different from each other. | 08-02-2012 |
20120230144 | SEMICONDUCTOR DEVICE - A device includes a first clock generation circuit that receives an external clock signal supplied to the device, delays the external clock signal to output a first clock signal synchronized with the external clock signal, and a circuit that generates a control signal to control output of data, based on second clock signals obtained by dividing an internal clock signal generated from the external clock signal, and third clock signals obtained by dividing the first clock signal. | 09-13-2012 |
20130039144 | MULTIPLE DEVICE APPARATUS, SYSTEMS, AND METHODS - Apparatus, systems, and methods are disclosed that operate to generate a clock signal in a die in a stack and to receive the clock signal in another die in the stack. Additional apparatus, systems, and methods are disclosed. | 02-14-2013 |
20130077430 | SEMICONDUCTOR SYSTEM - A semiconductor system includes a first clock channel and a second clock channel. The first clock channel transmits a first clock signal from a controller to a memory. The second clock channel transmits a second clock signal with a phase difference of 90° from the first clock signal, from the controller to the memory. | 03-28-2013 |
20130121100 | DEVICE AND METHOD TO PERFORM MEMORY OPERATIONS AT A CLOCK DOMAIN CROSSING - A device and method to perform memory operations at a clock domain crossing is disclosed. In a particular embodiment, a method includes providing a first clock signal to a write clock input of a memory to write data to the memory. The data is read from the memory according to a second clock signal that is different from the first clock signal. A third clock signal is provided to a read clock input of the memory. The third clock signal has a frequency that is substantially an integer multiple of a frequency of the second clock signal. The integer multiple is greater than one. | 05-16-2013 |
20130163367 | CLOCK GENERATION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE EMPLOYING THE SAME - A semiconductor memory device includes a first internal clock generation circuit configured to generate a first internal clock by compensating an external clock signal for a transfer delay thereof in the semiconductor memory device, a control voltage generation circuit configured to generate a control voltage in response to a profile selection signal, a second internal clock generation circuit configured to generate a second internal clock signal by delaying the first internal clock signal by a time corresponding to the control voltage, a selection output circuit configured to select one of the first internal clock signal and the second internal clock signal in response to a path selection signal and output a selected signal as a synchronization clock signal, and a data output circuit configured to output a data in synchronization with the synchronization clock signal. | 06-27-2013 |
20130182524 | SEMICONDUCTOR MEMORY DEVICES HAVING INTERNAL CLOCK SIGNALS AND MEMORY SYSTEMS INCLUDING SUCH MEMORY DEVICES - A semiconductor memory device has a clock input buffer that is turned ‘on’ or ‘off’ in response to a first control signal. The clock input buffer is configured to buffer an external clock signal in order to output a buffered clock signal. The memory device further includes an internal clock generator that is configured to generate an internal clock signal in response to the buffered clock signal. The generation of the internal clock signal is started in response to a second control signal. | 07-18-2013 |
20140086002 | SEMICONDUCTOR MEMORY DEVICE AND DETECTION CLOCK PATTERN GENERATING METHOD THEREOF - A clock pattern generating method of a semiconductor memory device is provided. The method includes generating the same clock pattern through a plurality of detection clock output pins when an output selection control signal is in a first state and generating clock patterns different from each other through the plurality of detection clock output pins when the output selection control signal is in a second state different from the first state. | 03-27-2014 |
20140092701 | MULTIPLE DEVICE APPARATUS, SYSTEMS, AND METHODS - Apparatus, systems, and methods are disclosed that operate to generate a clock signal in a die in a stack and to receive the clock signal in another die in the stack. Additional apparatus, systems, and methods are disclosed. | 04-03-2014 |
20140133260 | Reducing Signal Skew in Memory and Other Devices - Interconnections between signal lines help to reduce signal skew between signals carried on the signal lines. The interconnections may be resistive interconnections, and the signal lines may be clock lines. In a memory controller, for example, resistive traces may connect adjacent clock lines. The resistive traces reduce the clock signal skew between the adjacent clock lines, and throughout the memory controller as a whole. | 05-15-2014 |
20150071022 | APPARATUSES AND METHODS FOR PROVIDING ACTIVE AND INACTIVE CLOCK SIGNALS TO A COMMAND PATH CIRCUIT - Apparatuses and methods for providing active and inactive clock signals to a command path circuit are described. An example method includes providing an active clock signal to a command path for a first portion of a command cycle for a command of back-to-back commands. The command path decodes the command and provides an output command signal responsive to the clock signal. The method further includes providing an inactive clock signal to the command path for a second portion of the command cycle for the command of the back-to-back commands. | 03-12-2015 |
20150146495 | SEMICONDUCTOR DEVICE INCLUDING A CLOCK ADJUSTMENT CIRCUIT - Disclosed herein is an apparatus that includes a clock circuit configured to receive first and second clock signals and perform a phase control operation in which a phase relationship between the first and second clock signals is controlled, the clock circuit configured to initiate the phase control operation each time a first control signal is asserted, the clock circuit including a comparator circuit that is configured to produce a second control signal indicative of a phase difference between the first and second clock signals, and a timing generator configured to assert the first control signal cyclically, the timing generator configured to respond to the second control signal to control a cycle of producing the first control signal. | 05-28-2015 |
20160087618 | SEMICONDUCTOR INTEGRATED CIRCUIT, APPARATUS WITH SEMICONDUCTOR INTEGRATED CIRCUIT, AND CLOCK CONTROL METHOD IN SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes, a fixed frequency-division clock generation unit configured to generate a fixed frequency-division clock with a fixed frequency based on an output clock of a clock source, a variable frequency-division clock generation unit configured to generate a variable frequency-division clock with a variable frequency based on the output clock of the clock source, and a data path selection unit configured to select a data path. The data path selection unit selects a data path with or without a synchronization unit for converting the data into clock-synchronous data on a receiving side according to whether the variable frequency-division clock is or is not, respectively, generated by the variable frequency-division clock generation unit. | 03-24-2016 |
20160173074 | EDGE-AWARE SYNCHRONIZATION OF A DATA SIGNAL | 06-16-2016 |