| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 365233130 | DDR (double data rate) memory | 20 |
| 20080232186 | MEMORY INTERFACE AND ADAPTIVE DATA ACCESS METHOD - A data access method for an application circuit to access a memory. The method includes steps of: receiving a first data from the application circuit; duplicating the first data to obtain a duplicated first data; and writing the first data and the duplicated first data into the memory at continuously accessible addresses. For accessing to the first data, the first data and the duplicated first data are read from the memory in response to a rising edge and a falling edge of a data-triggering signal; and one of the first data and the duplicated first data is outputted while the other of the first data and the duplicated first data is discarded. | 09-25-2008 |
| 20090310433 | DATA ALIGNMENT AND DE-SKEW SYSTEM AND METHOD FOR DOUBLE DATA RATE INPUT DATA STREAM - A system for aligning data is provided. The system comprises a demultiplexing component adapted to bifurcate a double data rate (DDR) data stream into first and second single data rate (SDR) data streams, a delay architecture adapted to generate delayed SDR data streams from the SDR data streams, a logic circuit adapted to analyze the SDR data streams and delayed SDR data streams to detect a predetermined bit pattern conveyed in the DDR data stream and to indicate detection of the predetermined bit pattern, and a data aligning component adapted to determine the number of intervening bits between occurrences of the predetermined bit pattern and to frame the intervening bits, thereby producing aligned data. | 12-17-2009 |
| 20100027369 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits. | 02-04-2010 |
| 20100142308 | PIPE LATCH CIRCUIT AND DRIVING METHOD THEREOF - A pipe latch circuit includes a pipe input unit configured to receive a plurality of data in an order corresponding to address information, a control signal generator configured to generate first and second control clock signals by using the address information, where the first and second control clock signals correspond to a synchronization clock signal, and a pipe output unit configured to synchronize an output signal of the pipe input unit with the first and second control clock signals and output the synchronized output signal. | 06-10-2010 |
| 20110205831 | SYSTEM AND METHOD FOR PROCESSING SIGNALS IN HIGH SPEED DRAM - A method is disclosed for operating a memory device, including providing a timing signal comprising a plurality of clock cycles, providing an activate signal, and providing a bank address signal. An activate command executes on every first duration of clock cycles, and the bank address signal is high for at least a portion of the first duration of clock cycles. In one embodiment, the first duration of the activate signal is at least four clock cycles, and the bank address signal is at least one clock cycle. A memory device having a row decoder and an active driver is also provided. | 08-25-2011 |
| 20110228627 | DOUBLE DATA RATE MEMORY DEVICE HAVING DATA SELECTION CIRCUIT AND DATA PATHS - A double data rate memory device comprises first and second sense amplifiers, a data selection circuit, and a data processing circuit. The first sense amplifier is configured to provide even data loaded on a first input and output data line, and the second sense amplifier is configured to provide odd data loaded on a second input and output data line. The data selection circuit is connected to the first and second sense amplifiers and is configured to provide output data loaded on a single data line, and the data processing circuit connected to the data selection circuit and configured to transfer the even data and the odd data in first and second data paths. The even data and the odd data are combined into the output data of the data selection circuit, and the data selection circuit selects the output data in response to a least significant bit of a column address and transfers the selected data on the single data line in response to a clock signal. | 09-22-2011 |
| 20130176809 | SELF CLOCKING FOR DATA EXTRACTION - A self clocking data extraction method is shown that is tolerant of timing jitter, data skew and the presence of multiple edges per data bit. The data is sampled when the following criterion are met: There is at least one edge across any track (the clock assures this criteria is met), followed by no edges in any track for a defined period of time (T), and all edge activity must occur in a period of time less than T (to keep from detecting false samples). This method enables the handling of trace data signals with poor electrical characteristics that can not be recorded by methods known in the prior art. | 07-11-2013 |
| 20130201779 | ELECTRONIC APPARATUS, DRAM CONTROLLER, AND DRAM - The invention provides an electronic apparatus. The electronic apparatus includes a Dynamic Random Access Memory (DRAM) and a DRAM controller. The DRAM receives at least one control and address signal and a clock signal, delays the clock signal by a predetermined value to obtain a delayed clock signal, samples the control and address signal according to the clock signal to obtain a first sample signal, samples the control and address signal according to the delayed clock signal to obtain a second sample signal, and compares the first sample signal with the second sample signal to obtain a status signal. The DRAM controller sends the control and address signal and the clock signal to the DRAM, receives the status signal from the DRAM, and adjusts a phase difference between the clock signal and the control and address signal according to the status signal. | 08-08-2013 |
| 20130343144 | SEMICONDUCTOR INTEGRATED CIRCUIT WITH DATA TRANSMITTING AND RECEIVING CIRCUITS - Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit and a data receiving circuit that receives data transmitted from the data transmitting circuit. The data transmitting circuit includes a data output circuit that outputs the data or sets an output to a high impedance state, and a control circuit that outputs a control signal to the data output circuit so that the data output circuit outputs the data when the data transmitting circuit transmits the data, and the data output circuit keeps outputting data last output in the previous data transmission, during a predetermined period after the previous data transmission when the data transmitting circuit further transmits another data after transmitting the data. | 12-26-2013 |
| 20140029370 | SEMICONDUCTOR MEMORY DEVICE, METHOD OF CONTROLLING READ PREAMBLE SIGNAL THEREOF, AND DATA TRANSMISSION METHOD - A system, includes a controller including a plurality of first external terminals configured to supply a command, a clock signal and an address, and communicate a data, and communicate a strobe signal related to the data, and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of first external terminals, one of the plurality of first external terminals and one of the plurality of second external terminals transferring an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data, | 01-30-2014 |
| 20140071784 | FREQUENCY SELECTION GRANULARITY FOR INTEGRATED CIRCUITS - Clock signal generation circuitry. A frequency multiplier is coupled to receive a clock signal and to generate a frequency-multiplied clock signal. A switching circuit is coupled to receive at least two reference clock signals. The switching circuit provides one of the reference clock signals in response to a reference select signal. A phase locked loop (PLL) is coupled to receive the frequency-multiplied clock signal and the selected reference clock signal. The PLL generates an output clock signal. | 03-13-2014 |
| 20140071785 | INTEGRITY CHECK OF MEASURED SIGNAL TRACE DATA - A method of monitoring signals is disclosed, wherein a plurality of command signals and address signals are consecutively expressed, as a measurement target. The method includes setting a strobe timing that has a predetermined initial value; calculating an error rate by monitoring the plurality of command signals, in accordance with the strobe timing; monitoring the plurality of address signals, and calculating a burst rate from a difference between the consecutive plurality of address signals, in accordance with the strobe timing; identifying timing where the calculated error rate and calculated burst rate are both optimized; and in the event the timing where both the calculated error rate and calculated burst rate are optimized cannot be identified, altering a predetermined value of the set strobe timing, and repeating the calculating, monitoring, and identifying. | 03-13-2014 |
| 20140241103 | SEMICONDUCTOR DEVICE HAVING CAL LATENCY FUNCTION - A method for accessing a semiconductor device having a memory array, the method includes receiving a mode register command to set a command latency value in a mode register, receiving a chip select signal, activating a command receiver in response to the chip select signal, receiving, with the command receiver, an access command with a first latency from the chip select signal equal to the command latency value, accessing the memory array in response to the access command, and deactivating the command receiver with a second latency from the chip select signal equal to a deactivation latency value. | 08-28-2014 |
| 20140293726 | MEMORY CONTROLLER AND ASSOCIATED METHOD FOR GENERATING MEMORY ADDRESS - A memory controller is connected to a double-data-rate dynamic random access memory (DDR DRAM) and an accessing unit. The memory controller includes: a processing unit, configured to receive a system address generated by the accessing unit; and a mapping unit, located in the processing unit, configured to convert the system address to a memory address and transmitting the memory address to the DDR DRAM. When a burst length of the DDR DRAM is L and L=2 | 10-02-2014 |
| 20140293727 | SEMICONDUCTOR DEVICE OUTPUTTING READ DATA IN SYNCHRONIZATION WITH CLOCK SIGNAL - A method for outputting data in a semiconductor device includes receiving an external clock signal, synchronizing, in a delay locked loop of the semiconductor device, a first internal clock signal to the external clock signal during a read period, synchronizing, in the delay locked loop, a second internal clock signal to the external clock signal during an active period, the second internal clock signal having a period longer than the first internal clock signal, and outputting data synchronized with the first internal clock signal during the read period. | 10-02-2014 |
| 20140321229 | SYSTEM AND METHOD FOR PER-BIT DE-SKEW FOR DATAMASK IN A DOUBLE DATA-RATE MEMORY DEVICE INTERFACE - In a training mode, per-bit de-skew (PBDS) values for a datamask signal in a synchronous dynamic random access memory are iteratively adjusted in conjunction with writing test patterns to the memory and reading back test patterns from the memory until optimum datamask PBDS values are determined. | 10-30-2014 |
| 20140334243 | WRITE LEVEL TRAINING USING DUAL FREQUENCIES IN A DOUBLE DATA-RATE MEMORY DEVICE INTERFACE - A write leveling calibration system and method for double data-rate dynamic random access memory includes performing write leveling at two different frequencies to determine to which of two successive rising clock cycle edges each data strobe signal would be aligned as a result of applying the write leveling delay determined by the write-leveling procedure. The determination can then be used to ensure that the data strobe signals of all source synchronous groups are aligned with the same edge of the clock signal. | 11-13-2014 |
| 20150043299 | SEMICONDUCTOR DEVICE - A device includes an output circuit, a DLL (Delay Locked Loop) circuit including a first delay line receiving a first clock signal and outputting, in response to receiving the clock signal, a second clock signal supplied to the output circuit, and an ODT (On Die Termination) circuit receiving an ODT activation signal and outputting, in response to receiving the ODT activation signal, an ODT output signal supplied to the output circuit to set the output circuit in a resistance termination state, and the ODT circuit including a second delay line configured to be set by the DLL circuit in an equivalent delay amount that is equivalent to a delay amount of the first delay line, the ODT output signal being, in a first time-period during which the ODT activation signal is in an active state, generated by being conveyed via the second delay line in which the equivalent delay amount has been set. | 02-12-2015 |
| 20150092510 | Method and Apparatus for Amplifier Offset Calibration - According to at least one example embodiment, a method and corresponding system for calibrating an amplifier offset include applying an input value to both input leads of an amplifier. The amplifier includes one or more digital-to-analog converters (DACs) used to calibrate an offset of the amplifier. A digital value, provided as input to the DAC, is updated over a number of iterations, by a control logic coupled to the amplifier, based on an output of the amplifier. A final value of the digital value being updated, e.g., associated with the last iteration, is employed as input to the DAC of the one or more DACs in the amplifier for calibrating the offset of the amplifier during a data reception phase. | 04-02-2015 |
| 20160182061 | DIGITAL PHASE CONTROLLED DELAY CIRCUIT | 06-23-2016 |
