| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 365148000 |
Resistive
| 1649 |
| 365163000 |
Amorphous (electrical)
| 877 |
| 365158000 |
Magnetoresistive
| 870 |
| 365154000 |
Flip-flop (electrical)
| 748 |
| 365149000 |
Capacitors
| 324 |
| 365171000 |
Magnetic thin film
| 291 |
| 365145000 |
Ferroelectric
| 246 |
| 365174000 |
Semiconductive
| 212 |
| 365151000 |
Molecular or atomic
| 25 |
| 365157000 |
Magnetostrictive or piezoelectric
| 9 |
| 365164000 |
Electrical contacts
| 8 |
| 365130000 |
Three-dimensional magnetic array
| 7 |
| 365160000 |
Superconductive
| 6 |
| 365170000 |
Hall effect | 4 |
| 20100020596 | NON-VOLATILE MAGNETIC MEMORY DEVICE - A non-volatile magnetic memory cell having a magnetic element with multiple segments which are not co-linear. Each of the segments is magnetized with a remnant magnetic field using a single write line. The segments can be magnetized in a first direction or a second direction, corresponding to first and second orientations of the memory cell. A sensor is provided to determine the direction in which the segments are magnetized and thereby the orientation of the cell. The segments are oriented such that the magnetic flux fields created by their respective remnant magnetic fields have a cumulative effect at a sensing region of the sensor. The cumulative effect allows a less sensitive sensor to be used than in known device. In various embodiments, the magnetic element can have a number of linear segments or a curved profile. In another embodiment, multiple magnetic elements are magnetized by a single write line. The multiple magnetic elements are arranged such that remnant magnetic field stored in them can be cumulatively sensed. In another embodiment, the magnetic element is arranged to be magnetized in a single general direction, but is shaped such that magnetic flux lines emanate from it in different directions. The different directions are arranged to direct flux lines through the sensing region of a sensor, which measures their cumulative effect. | 01-28-2010 |
| 20100027330 | MAGNETIC MEMORY DEVICE AND METHOD FOR READING MAGNETIC MEMORY CELL USING SPIN HALL EFFECT - A magnetic memory device includes a substrate for reading and a magnetic memory cell. The substrate has a channel layer. The magnetic memory cell is formed on the substrate and has a magnetized magnetic material that transfers spin data to electrons passing the channel layer. Data stored in the magnetic memory cell are read by a voltage across both side ends of the channel layer that is generated when the electrons passing the channel layer deviate in the widthwise direction of the channel layer by a spin Hall effect. | 02-04-2010 |
| 20100074002 | TRI-STATE MEMORY DEVICE AND METHOD - A non-volatile tri-state random access memory device, including a permanent magnetic bit; a write module in functional communication with the permanent magnetic bit and configured to selectably alter the permanent magnetic bit between three magnetic states, a write module including a write coil disposed about the permanent magnetic bit and in communication with a source of electrical power; and a read module in functional communication with the permanent magnetic bit and configured to observe and communicate each of three magnetic states of the permanent magnetic bit, the read module including a read sensor coupled to a read return line. | 03-25-2010 |
| 20110075476 | SPINTRONIC DEVICE AND INFORMATION TRANSMITTING METHOD - A concrete means for making transmission over long distances possible using a spin-wave spin current is provided in a spintronic device and an information transmitting method. | 03-31-2011 |
| 365167000 |
Simulating biological cells | 3 |
| 20100220523 | STOCHASTIC SYNAPSE MEMORY ELEMENT WITH SPIKE-TIMING DEPENDENT PLASTICITY (STDP) - An active memory element is provided. One embodiment of the invention includes a bi-polar memory two-terminal element having polarity-dependent switching. A probability of switching of the bi-polar memory element between a first state and a second state decays exponentially based on time delay and a difference between received signals at the two terminals and a switching threshold magnitude. | 09-02-2010 |
| 20110176359 | CARBON NANOTUBE-BASED NEURAL NETWORKS AND METHODS OF MAKING AND USING SAME - Physical neural networks based nanotechnology include dendrite circuits that comprise non-volatile nanotube switches. A first terminal of the non-volatile nanotube switches is able to receive an electrical signal and a second terminal of the non-volatile nanotube switches is coupled to a common node that sums any electrical signals at the first terminals of the nanotube switches. The neural networks further includes transfer circuits to propagate the electrical signal, synapse circuits, and axon circuits. | 07-21-2011 |
| 20150103591 | SEMICONDUCTOR MEMORY WITH INTEGRATED BIOLOGIC ELEMENT - A memory includes cytokines, such as macromolecule proteins, as a poly-state data storage. Each fold state of multiple fold states of a protein are associated with a data value. Current flow through the protein is associated with a resistance of the protein associated with its current fold state. Application of light, electric fields or heat via an associated element or elements facilitates placement of a protein in a fold state that corresponds to an associated resistance and correlates with an incoming data value. Measuring of current or resistance allows for reading of a data value associated with the protein. | 04-16-2015 |
| 365159000 |
Negative resistance | 3 |
| 20090190392 | ELECTRONIC DEVICE, METHOD OF MANUFACTURING THE SAME, AND STORAGE DEVICE - An electronic device includes: a first conductor; an insulative supporting film formed in a part on one surface of the first conductor; and a second conductor, one surface of which is opposed to the one surface of the first conductor and a part of which is supported by the supporting film. An air gap is formed in a region in which the first conductor and the second conductor are opposed to each other excluding the supporting film. The thickness of the supporting film is larger than a space between the first conductor and the second conductor, at least a part of which forms the air gap. | 07-30-2009 |
| 20100027324 | VARIABLE INTEGRATED ANALOG RESISTOR - The invention relates to the use of chalcogenide devices exhibiting negative differential resistance in integrated circuits as programmable variable resistor components. The present invention is a continuously variable integrated analog resistor made of a chalcogenide material, such as a GeSeAg alloy. Continuously variable resistor states are obtained in the material via application of an electrical pulse to it. The pulse sequence, duration and applied potential determine the value of the resistance state obtained. | 02-04-2010 |
| 20140003139 | MEMORY DEVICES WITH IN-BIT CURRENT LIMITERS | 01-02-2014 |
| 365153000 |
Electrochemical | 2 |
| 20090231907 | NON-VOLATILE ELECTROCHEMICAL MEMORY DEVICE - A non-volatile electrochemical memory cell formed of a stack of thin films comprising at least one first active layer, suited to releasing and accepting, in a reversible manner, at least one ion species, at least one second active layer, suited to releasing and accepting said ion species, in a reversible manner, the active layers being based on materials having different compositions and electrochemical potential profiles. | 09-17-2009 |
| 20110267873 | NON-VOLATILE MEMORY WITH PROGRAMMABLE CAPACITANCE - Non-volatile memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region. A first insulating layer is over the substrate. A second insulating layer is over the substrate and between the source region and drain region. A solid electrolyte layer is between the first insulating layer and second insulating layer. The solid electrolyte layer has a capacitance that is controllable between at least two states. A first electrode is electrically coupled to a first side of the solid electrolyte layer and is electrically coupled to a voltage source. A second electrode is electrically coupled to a second side of the solid electrolyte layer and is electrically coupled to the voltage source. Multi-bit memory units are also disclosed. | 11-03-2011 |
| 365168000 |
Ternary | 1 |
| 20140204669 | SYSTEM AND METHOD OF QUANTUM COMPUTING USING THREE-STATE REPRESENTATION OF A QUBIT - A method (and structure) of quantum computing. Two independent magnitudes of a three-state physical (quantum) system are set to simultaneously store two real, independent numbers as a qubit. The three-state physical (quantum) system has a first energy level, a second energy level, and a third energy level capable of being degenerate with respect to one another, thereby forming basis states for the qubit. | 07-24-2014 |
| Entries |
| Document | Title | Date |
|---|
| 20080266929 | REFERENCE CELL LAYOUT WITH ENHANCED RTN IMMUNITY - A reference cell layout includes a plurality of active areas, in parallel to each other, and a first contact of the active areas, and a first gate, the first contact shorting the active areas. A memory device includes the reference cell layout and a corresponding array of memory cells having active areas sized substantially identical to the active areas of the reference cell layout and plural second contacts respectively contacting the active areas of the memory cells. | 10-30-2008 |
| 20090034318 | SWITCHING DEVICE, REWRITABLE LOGIC INTEGRATED CIRCUIT, AND MEMORY DEVICE - A switching device according to the present invention includes ion conductive layer | 02-05-2009 |
| 20090052222 | MEMORY ELEMENT WITH THERMOELECTRIC PULSE - A memory element comprises an addressable memory cell. A thermoelectric device couples to the memory cell. Electrical conductors provide a current pulse to the thermoelectric device. The current pulse generates a thermoelectric heat flow pulse between the thermoelectric device and the memory cell. | 02-26-2009 |
| 20090052223 | Switching Element, Method of Manufacturing the Switching Element, and Memory Element Array - Disclosed is a switching element including: an insulative substrate; a first electrode and a second electrode provided to the insulative substrate; an interelectrode gap between the first electrode and the second electrode, comprising a gap of a nanometer order which causes switching phenomenon of resistance by applying a predetermined voltage between the first electrode and the second electrode; and a sealing member to seal the interelectrode gap such that the gap is retained. | 02-26-2009 |
| 20090129139 | NANO-ELECTRO-MECHANICAL MEMORY CELLS AND DEVICES - A scalable nano-electro-mechanical memory cell design that requires only conventional semiconductor fabrication materials and surface micromachining technology, and is suited for use in cross-point memory arrays for very high density non-volatile storage. This design also leverages well established surface-micromachining technology and electro-mechanical device phenomena to achieve an elegantly simple and scalable memory cell structure that can potentially operate with low voltage. An elongate beam is held between a non-deflected state and a deflected state, or between two deflected states, therein defining two binary memory states. Stiction, buried charge layers, or a combination of stiction and buried charge layers can be incorporated to modify the stability of one or both deflected states for the cell. Current through the moveable portion of the elongate beam within the memory cell can be registered utilizing one or more access transistors for reading the data state. | 05-21-2009 |
| 20090154218 | MEMORY ARRAYS USING NANOTUBE ARTICLES WITH REPROGRAMMABLE RESISTANCE - A memory array includes a plurality of memory cells, each of which receives a bit line, a first word line, and a second word line. Each memory cell includes a cell selection circuit, which allows the memory cell to be selected. Each memory cell also includes a two-terminal switching device, which includes first and second conductive terminals in electrical communication with a nanotube article. The memory array also includes a memory operation circuit, which is operably coupled to the bit line, the first word line, and the second word line of each cell. The circuit can select the cell by activating an appropriate line, and can apply appropriate electrical stimuli to an appropriate line to reprogrammably change the relative resistance of the nanotube article between the first and second terminals. The relative resistance corresponds to an informational state of the memory cell. | 06-18-2009 |
| 20110110139 | MULTI-STATE MEMORY AND MULTI-FUNCTIONAL DEVICES COMPRISING MAGNETOPLASTIC OR MAGNETOELASTIC MATERIALS - Apparatus and methods are disclosed that enable writing data on, and reading data of, multi-state elements having greater than two states. The elements may be made of magnetoplastic and/or magnetoelastic materials, including, for example, magnetic shape-memory alloy or other materials that couple magnetic and crystallographic states. The writing process is preferably conducted through the application of a magnetic field and/or a mechanical action. The reading process is preferably conducted through atomic-force microscopy, magnetic-force microscopy, spin-polarized electrons, magneto-optical Kerr effect, optical interferometry or other methods, or other methods/effects. The multifunctionality (crystallographic, magnetic, and shape states each representing a functionality) of the multi-state elements allows for simultaneous operations including read&write, sense&indicate, and sense&control. Embodiments of the invention may be used, for example, for storing, modifying, and accessing data for device, sensor, actuator, logic and memory applications. Embodiments may be particularly effective for non-volatile memory or other read&write, sense&indicate, and/or sense&control functions in computer or other applications; such simultaneous operation of two (or more) of said multiple functionalities open new pathways for miniaturization of devices. | 05-12-2011 |
| 20110261605 | Graphene-based switching elements using a diamond-shaped nano-patch and interconnecting nano-ribbons - The use of diamond-shaped graphene nano-patches as novel non-volatile switching elements exhibiting transitions between high and low conductance states based on changes of magnetic ordering of these states. Non-magnetic reconstructed graphene nano-ribbons are used as non-invasive leads to implement the switching elements as carbon-nanoflake based memories and transistors. Switching of the elements may be implemented by electric-field-induced altering of the magnetic state. Graphene nano-patch shapes of certain geometries provide passive electric-field sources such as to establish initial bits of information saved in graphene-based memories. | 10-27-2011 |
| 20120106232 | Memory Cells, Methods of Programming Memory Cells, and Methods of Forming Memory Cells - Some embodiments include methods of programming a memory cell. A plurality of charge carriers may be moved within the memory cell, with an average charge across the moving charge carriers having an absolute value greater than 2. Some embodiments include methods of forming and programming an ionic-transport-based memory cell. A stack is formed to have programmable material between first and second electrodes. The programmable material has mobile ions which are moved within the programmable material to transform the programmable material from one memory state to another. An average charge across the moving mobile ions has an absolute value greater than 2. Some embodiments include memory cells with programmable material between first and second electrodes. The programmable material includes an aluminum nitride first layer, and includes a second layer containing a mobile ion species in common with the first layer. | 05-03-2012 |
| 20120224407 | INTEGRATED CIRCUIT HAVING A CLOCK DESKEW CIRCUIT THAT INCLUDES AN INJECTION-LOCKED OSCILLATOR - Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ILO can correspond to a phase tuning range. In some embodiments, a circuit can include circuitry to detect a phase boundary between two adjacent phase tuning ranges. In some embodiments, a circuit can use the detected phase boundary to switch between the two adjacent phase tuning ranges. | 09-06-2012 |
| 20120236622 | NON-VOLATILE GRAPHENE-DRUM MEMORY CHIP - The present invention relates to non-volatile memory chips having graphene drums. In some embodiments, the non-volatile memory chips have one or more layers that each includes a plurality of graphene-drum memory chip cells. | 09-20-2012 |
| 20130242636 | ELECTROMECHANICAL INTEGRATED MEMORY ELEMENT AND ELECTRONIC MEMORY COMPRISING THE SAME - An electromechanical memory element includes a fixed body and a deformable element attached to the fixed body. An actuator causes a deformation of the deformable element from a first position (associated with a first logic state) to a second position (associated with a second logic state) where a mobile element makes contact with a fixed element. A programming circuit then causes a weld to be formed between the mobile element and the fixed element. The memory element is thus capable of associating the first and second positions with two different logic states. The weld may be selectively dissolved to return the deformable element back to the first position. | 09-19-2013 |
| 20180024782 | METHOD AND APPARATUS FOR IMPLEMENTING HIGH-SPEED CONNECTIONS FOR LOGICAL DRIVES | 01-25-2018 |
