| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 365160000 | Superconductive | 6 |
| 20090086533 | SUPERCONDUCTING CIRCUIT FOR HIGH-SPEED LOOKUP TABLE - A high-speed lookup table is designed using Rapid Single Flux Quantum (RSFQ) logic elements and fabricated using superconducting integrated circuits. The lookup table is composed of an address decoder and a programmable read-only memory array (PROM). The memory array has rapid parallel pipelined readout and slower serial reprogramming of memory contents. The memory cells are constructed using standard non-destructive reset-set flip-flops (RSN cells) and data flip-flops (DFF cells). An n-bit address decoder is implemented in the same technology and closely integrated with the memory array to achieve high-speed operation as a lookup table. The circuit architecture is scalable to large two-dimensional data arrays. | 04-02-2009 |
| 20150364193 | VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE - A variable resistance nonvolatile memory device includes: a nonvolatile memory element; an NMOS transistor connected to the nonvolatile memory element; a source line connected to the NMOS transistor; a bit line connected to the nonvolatile memory element. When a control circuit causes the nonvolatile memory element to be in the low resistance state, the control circuit controls to flow a first current from a first voltage source to a reference potential point, and applies a first gate voltage to a gate of a NMOS transistor, and when the control circuit causes the nonvolatile memory element to be in the high resistance state, the control circuit controls to flow a second current from a second voltage source to the reference potential point, and applies a second gate voltage to the gate of the NMOS transistor, the second gate voltage being lower than the first gate voltage. | 12-17-2015 |
| 365162000 | Josephson | 4 |
| 20120320668 | PHASE QUBIT CELL HAVING ENHANCED COHERENCE - Methods and apparatuses are provided for storing a quantum bit. One apparatus includes a first phase qubit, a second phase qubit, and a common bias circuit configured to provide a first bias to the first phase qubit and a second bias to the second phase qubit, such that noise within the first bias is anti-correlated to noise within the second bias. | 12-20-2012 |
| 20130107617 | QUANTUM MEMORY | 05-02-2013 |
| 20150043273 | JOSEPHSON MAGNETIC MEMORY CELL SYSTEM - One aspect of the present invention includes a Josephson magnetic memory system. The system includes a superconducting electrode that conducts a read current. The system also includes a hysteretic magnetic Josephson junction (HMJJ). The HMJJ can store a binary value and convert superconducting pairs associated with the read current flowing through the HMJJ from a singlet-state to a triplet-state. The system further includes a write circuit magnetically coupled to the HMJJ and configured to write the binary value into the at HMJJ in response to at least one write current and a read circuit configured to determine the binary value stored in the HMJJ in response to application of the read current to the HMJJ. | 02-12-2015 |
| 20160012882 | Flux Latching Superconducting Memory | 01-14-2016 |
