| Entries |
| Document | Title | Date |
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| 20080205121 | Current driven memory cells having enhanced current and enhanced current symmetry - A method and system for providing and using a magnetic memory is described. The method and system include providing a plurality of magnetic storage cells. Each magnetic storage cell includes a magnetic element and a selection device coupled with the magnetic element. The magnetic element is programmed by write currents driven through the magnetic element in a first or second direction. In one aspect, the method and system include providing a voltage supply and a voltage pump coupled with the magnetic storage cells and the voltage supply. The voltage supply provides a supply voltage. The voltage pump provides to the selection device a bias voltage having a magnitude greater than the supply voltage. Another aspect includes providing a silicon on oxide transistor as the selection device. Another aspect includes providing to the body of the transistor a body bias voltage that is a first voltage when the transistor is off and a second voltage when the transistor is on. | 08-28-2008 |
| 20080205122 | MRAM MEMORY CONDITIONING - According to an example embodiment, a method (500) includes applying a magnetic field to an array of Magnetic Tunnel Junction (MTJ) bits, a magnitude of the magnetic field sufficient to eliminate a stuck-at-mid condition exhibited by one of the MTJ bits without causing other ones of the MTJ bits to develop the stuck-at-mid condition. | 08-28-2008 |
| 20080205123 | MAGNETIC RANDOM ACCESS MEMORY AND METHOD OF REDUCING CRITICAL CURRENT OF THE SAME - A magnetic random access memory includes a substrate, a free layer and a spacer layer. The substrate and the free layer are made of a vertical anisotropy ferrimagentic thin film. The spacer layer is sandwiched between the substrate and the free layer and is made of an insulating layer. The method uses a modified Landau-Lifshitz-Gilbert equation to obtain a critical current value as a function of exchange coupling constant. The critical current value is predictable under several external magnetic fields being applied. When the exchange coupling constant is proportionally varied, the critical current value is reduced to a third of its original value under an optimum state. | 08-28-2008 |
| 20080205124 | SEMICONDUCTOR MEMORY DEVICE AND DATA WRITE AND READ METHODS OF THE SAME - A semiconductor memory device includes first to third resistive memory elements, a first transistor having a first gate electrode, first and second source/drain electrodes, the first source/drain electrode being connected to one terminal of the first resistive memory element, and the second source/drain electrode being connected to one terminal of the third resistive memory element, a second transistor having a second gate electrode, third and fourth source/drain electrodes, the third source/drain electrode being connected to one terminal of the second resistive memory element, and the fourth source/drain electrode being connected to one terminal of the third resistive memory element, a first bit line connected to the other terminal of the third resistive memory element, a second bit line connected to the other terminal of each of the first and second resistive memory elements, and first and second word lines connected to each of the first and second gate electrodes. | 08-28-2008 |
| 20080205125 | MAGNETIC RANDOM ACCESS MEMORY AND WRITE METHOD THEREOF - A magnetic random access memory includes first and second bit lines extending in a first direction, the second bit line being adjacent to the first bit line in a second direction, a first magnetoresistive effect element being connected to the first bit line and having a first fixed layer, a first recording layer, and a first nonmagnetic layer, and a second magnetoresistive effect element being adjacent to the first magnetoresistive effect element in the second direction and being connected to the second bit line and having a second fixed layer, a second recording layer, and a second nonmagnetic layer, the first and second recording layers being formed by a same first layer extending in the second direction. | 08-28-2008 |
| 20080205126 | MAGNETIC RANDOM ACCESS MEMORY - A magnetic random access memory which is a memory cell array including a magnetoresistive effect element having a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is reversible, and a non-magnetic layer provided between the fixed layer and the recording layer, wherein all conductive layers in the memory cell array arranged below the magnetoresistive effect element are formed of materials each containing an element selected from a group including W, Mo, Ta, Ti, Zr, Nb, Cr, Hf, V, Co, and Ni. | 08-28-2008 |
| 20080219042 | Magnetic memory cell - By inserting a spin polarizing layer (typically pure iron) within the free layer of a MTJ or GMR memory cell, dR/R can be improved without significantly affecting other free layer properties such as Hc. Additional performance improvements can be achieved by also inserting a surfactant layer (typically oxygen) within the free layer. | 09-11-2008 |
| 20080219043 | Word Line Transistor Strength Control for Read and Write in Spin Transfer Torque Magnetoresistive Random Access Memory - Systems, circuits and methods for controlling word line voltage at a word line transistor in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A first voltage can be supplied to the word line transistor for write operations. A second voltage, which is less than the first voltage, can be supplied to the word line transistor during read operations. | 09-11-2008 |
| 20080219044 | Read Disturb Reduction Circuit for Spin Transfer Torque Magnetoresistive Random Access Memory - Systems, circuits and methods for reducing read disturbances in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A resistive element can be used during the read operation to control the read current and control read disturbances. An isolation element can be used to isolate the resistive element from the circuit during write operations. | 09-11-2008 |
| 20080219045 | Semiconductor memory device and magneto-logic circuit - Provided are a semiconductor memory device and a magneto-logic circuit which change the direction of a magnetically induced current according to a logical combination of logic states of a plurality of input values. The semiconductor memory device comprises a current driving circuit, a magnetic induction layer, and a resistance-variable element. The current driving circuit receives a plurality of input values and changes the direction of a magnetically induced current according to a logical combination of logic states of the input values. The magnetic induction layer induces magnetism having a direction varying according to the direction of the magnetically induced current. The resistance-variable element has a resistance varying according to the direction of the magnetism induced by the magnetic induction layer. | 09-11-2008 |
| 20080225576 | Method of magnetic tunneling junction pattern layout for magnetic random access memory - An MTJ pattern layout for a memory device is disclosed that includes two CMP assist features outside active MTJ device blocks. A first plurality of dummy MTJ devices is located in two dummy bands formed around an active MTJ device block. The inner dummy band is separated from the outer dummy band by the MTJ ILD layer and has a MTJ device density essentially the same as the MTJ device block. The outer dummy band has a MTJ device density at least 10% greater than the inner dummy band. The inner dummy band serves to minimize CMP edge effect in the MTJ device block while the outer dummy band improves planarization. A second plurality of dummy MTJ devices is employed in contact pads outside the outer dummy band and is formed between a WL ILD layer and a BIT ILD layer thereby minimizing delamination of the MTJ ILD layer. | 09-18-2008 |
| 20080225577 | MAGNETIC RANDOM ACCESS MEMORY, AND WRITE METHOD AND MANUFACTURING METHOD OF THE SAME - A magnetic random access memory includes a bit line running in a first direction, a first word line running in a second direction different from the first direction, and a memory element having a magnetoresistive effect element including a fixed layer having a fixed magnetization direction, a recording layer having a reversible magnetization direction, and a nonmagnetic layer formed between the fixed layer and the recording layer, the magnetization directions in the fixed layer and the recording layer being perpendicular to a film surface, and a heater layer in contact with the magnetoresistive effect element, the memory element being connected to the bit line, and formed to oppose a side surface of the first word line such that the memory element is insulated from the first word line. | 09-18-2008 |
| 20080239794 | Magnetoresistive random access memory device with small-angle toggle write lines - Disclosed herein are toggle-mode magnetoresistive random access memory (MRAM) devices having small-angle toggle write lines, and related methods of toggle-mode switching MRAM devices. Also disclosed are layouts for MRAM devices constructed according to the disclosed principles. Generally speaking, the disclosed principles provide for non-orthogonally aligned toggle-mode write lines used to switch toggle-mode MRAM devices that employ a bias field to decrease the threshold needed to switch the magnetic state of each device. While the conventional toggle-mode write lines provide for the desired orthogonal orientation of the applied magnetic fields to optimize device switching, the use of a bias field affects this orthogonal orientation. By non-orthogonally aligning the two write lines as disclosed herein, the detrimental affect of the bias field may be compensated for such that the net fields applied to the device for both lines are again substantially orthogonal, as is desired. | 10-02-2008 |
| 20080239795 | NONVOLATILE MEMORY DEVICE WITH WRITE ERROR SUPPRESSED IN READING DATA - A data write current from a pinned layer to a free layer is larger than a data write current from the free layer to the pinned layer. A data read current is smaller in value than the data write current. In the case where a difference in data read current between a high-resistance state and a low-resistance state is relatively small, a sense amplifier is connected so that the data read current flows from the pinned layer to the free layer, namely from a source line to a bit line. | 10-02-2008 |
| 20080239796 | MAGNETIC MEMORY DEVICE AND METHOD OF WRITING INTO THE SAME - A magnetic memory device includes a memory cell including magnetoresistance effect elements MTJ | 10-02-2008 |
| 20080247222 | Spin Transfer Torque Magnetoresistive Random Access Memory and Design Methods - Systems, circuits and methods for determining read and write voltages for a given word line transistor in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A first voltage can be supplied to the write operations so that the write operations occur in the saturation region of the word line transistor. A second voltage, which is less than the first voltage, can be supplied for read operations so that the read operations occur in the linear region of the word line transistor. | 10-09-2008 |
| 20080247223 | SPIN-INJECTION MAGNETIC RANDOM ACCESS MEMORY - A spin-injection magnetic random access memory of an aspect of the present invention includes a magnetoresistive element, a unit which writes data into the magnetoresistive element by use of spin-polarized electrons generated by a spin-injection current and which applies, to the magnetoresistive element, a magnetic field of a direction of a hard magnetization of the magnetoresistive element during the writing. | 10-09-2008 |
| 20080253173 | MAGNETIC RANDOM ACCESS MEMORY - A magnetic random access memory according to an example of the invention comprises a first reference bit line shared by first reference cells, a second reference bit line shared by second reference cells, a first driver-sinker to feed a first writing current, a second driver-sinker to feed a second writing current, and a control circuit which checks data stored in the first and second reference cells line by line, and executes writing simultaneously to all of the first and second reference cells by a uniaxial writing when the data is broken. | 10-16-2008 |
| 20080253174 | MAGNETORESISTANCE EFFECT ELEMENT AND MAGNETORESISTIVE RANDOM ACCESS MEMORY USING THE SAME - A magnetoresistive effect element includes a first magnetic layer, a second magnetic layer, and a first spacer layer. The first magnetic layer has an invariable magnetization direction. The second magnetic layer has a variable magnetization direction, and contains at least one element selected from Fe, Co, and Ni, at least one element selected from Ru, Rh, Pd, Ag, Re, Os, Ir, Pt, and Au, and at least one element selected from V, Cr, and Mn. The spacer layer is formed between the first magnetic layer and the second magnetic layer, and made of a nonmagnetic material. A bidirectional electric current flowing through the first magnetic layer, the spacer layer, and the second magnetic layer makes the magnetization direction of the second magnetic layer variable. | 10-16-2008 |
| 20080253175 | NONVOLATILE MAGNETIC MEMORY DEVICE AND PHOTOMASK - A nonvolatile magnetic memory device including a magntoresistance device having a recording layer formed of a ferromagnetic material for storing information by use of variation in resistance depending on the magnetization inversion state. The plan-view shape of the recording layer includes a pseudo-rhombic shape having four sides, at least two of the four sides each include a smooth curve having a central portion curved toward the center of the pseudo-rhombic shape. The easy axis of magnetization of the recording layer is substantially parallel to the longer axis of the pseudo-rhombic shape. The hard axis of magnetization of the recording layer is substantially parallel to the shorter axis of the pseudo-rhombic shape. The sides constituting the plan-view shape of the recording layer are smoothly connected to each other. | 10-16-2008 |
| 20080253176 | NONVOLATILE MAGNETIC MEMORY DEVICE AND PHOTOMASK - A nonvolatile magnetic memory device including a magntoresistance device having a recording layer formed of a ferromagnetic material for storing information by use of variation in resistance depending on the magnetization inversion state. The plan-view shape of the recording layer includes a pseudo-rhombic shape having four sides, at least two of the four sides each include a smooth curve having a central portion curved toward the center of the pseudo-rhombic shape. The easy axis of magnetization of the recording layer is substantially parallel to the longer axis of the pseudo-rhombic shape. The hard axis of magnetization of the recording layer is substantially parallel to the shorter axis of the pseudo-rhombic shape. The sides constituting the plan-view shape of the recording layer are smoothly connected to each other. | 10-16-2008 |
| 20080259673 | SPACE AND PROCESS EFFICIENT MRAM AND METHOD - Methods and apparatus are provided for magnetoresistive random access memory (MRAM) bits ( | 10-23-2008 |
| 20080259674 | Scalable Magnetic Memory Devices - A magnetic memory cell is provided. The magnetic memory cell includes at least one fixed magnetic layer, and a plurality of free magnetic layers, separated from the at least one fixed magnetic layer by at least one barrier layer. The free magnetic layers include a first free magnetic layer adjacent to the barrier layer, a second free magnetic layer separated from the first free magnetic layer by at least one first parallel coupling layer, and a third free magnetic layer separated from the second free magnetic layer by at least one second parallel coupling layer. A magnetic moment of the second free magnetic layer is greater than both a magnetic moment of the first free magnetic layer and a magnetic moment of the third free magnetic layer. The magnetic memory cell may be used in conjunction with a magnetic random access memory device. | 10-23-2008 |
| 20080259675 | Data Writing to Scalable Magnetic Memory Devices - A method is provided for writing data to an MRAM device having a plurality of magnetic memory cells configured in an array between a plurality of word lines and bit lines. At least one of the magnetic memory cells includes at least one fixed magnetic layer and a plurality of free magnetic layers, separated from the fixed magnetic layer by at least one barrier layer. The free magnetic layers include a first free magnetic layer adjacent to the barrier layer, a second free magnetic layer separated from the first free magnetic layer by at least one first parallel coupling layer, and a third free magnetic layer separated from the second free magnetic layer by at least one second parallel coupling layer. A magnetic moment of the second free magnetic layer is greater than both a magnetic moment of the first free magnetic layer and the third free magnetic layer. | 10-23-2008 |
| 20080266938 | MAGNETORESISTIVE DEVICE AND METHOD OF PACKAGING SAME - A magnetoresistive memory device | 10-30-2008 |
| 20080266939 | Magnetic memory device - A width and a thickness of a bit line are represented as W | 10-30-2008 |
| 20080273375 | INTEGRATED CIRCUIT HAVING A MAGNETIC DEVICE - An integrated circuit having a magnetic device is disclosed. In one embodiment, the integrated circuit includes a reference structure having a first blocking temperature. A storage structure is provided made of a ferromagnetic material. An antiferromagnetic structure is provided having a second blocking temperature lower than the first blocking temperature. | 11-06-2008 |
| 20080273376 | Intrusion Resistant Apparatus and Method - An intrusion-resistant apparatus may include a magnetic memory array disposed with an enclosure. The magnetic memory may include a plurality of magnetic memory elements, each adapted to store a binary value only in the presence of a predetermined bias magnetic field having a magnetic field strength and direction within predetermined limits. Means for providing the predetermined bias magnetic field and an encryption/decryption engine may be disposed within the enclosure. An encryption/decryption key may be stored in the magnetic memory array. The encryption/decryption key may be used by the encryption/decryption engine to encrypt and decrypt data. | 11-06-2008 |
| 20080273377 | METHODS OF WRITING DATA TO MAGNETIC RANDOM ACCESS MEMORY DEVICES WITH BIT LINE AND/OR DIGIT LINE MAGNETIC LAYERS - A magnetic random access memory (MRAM) device may include a substrate, a first magnetic layer on the substrate, and a digit line on the first magnetic layer. A magnetic tunnel junction structure may be provided adjacent the digit line, and a bit line may be provided on the magnetic tunnel junction structure such that the magnetic tunnel junction structure is between the bit line and the digit line. In addition, a second magnetic layer may be provided on the bit line. | 11-06-2008 |
| 20080278994 | MRAM Cell with Multiple Storage Elements - An improved MRAM cell may include a first, second, and third contact, a first MTJ between the first and second contact, and a MTJ between the second and third contact. The MRAM cell is nonconductive between the first and second MTJ. The first MTJ may include a first free layer with a first switching field, and the second MTJ may include a second free layer with a second switching field. If the first switching field is substantially higher than the second switching field, the first MTJ may be a reference element for the second MTJ. If the first switching field is adequately higher than the second switching field, the first and second MTJ may each contain a data bit. If the first switching field is substantially similar to the second switching field, the first and second MTJs may contain identical data bits connected in series. | 11-13-2008 |
| 20080278995 | Magnetic memory and memory cell thereof and method of manufacturing the memory cell - A magnetic memory, a memory cell thereof, and a method of manufacturing the memory cell are provided. The memory cell of the magnetic memory includes a bottom contact layer, a bit line, a magnetic stack structure and a dielectric material. The bit line is disposed over the bottom contact layer. The magnetic stack structure is disposed between the bottom contact layer and the bit line. The dielectric material at least fills between the bottom contact layer and the bit line and surrounds the magnetic stack structure. A gap is formed between the dielectric material and the magnetic stack structure. During programming of the memory cell, the magnetic stack structure generates heat, and the gap delays heat loss. | 11-13-2008 |
| 20080278996 | PROGRAMMABLE MAGNETIC READ ONLY MEMORY (MROM) - In one embodiment, there is provided a method for programming a memory device having magnetoresistive memory elements as storage elements. The method is performed during fabrication of the memory device and may be used to realize a Magnetic Read Only Memory (MROM) device. In accordance with the method, during fabrication of a memory device comprising a plurality of magnetoresistive memory elements (MRME) e.g. a MTJs, the memory device is programmed by selectively controlling the presence or absence of the magnetoresistive element at each intersection of a word line (WL) and a bit line (BL) in the device. | 11-13-2008 |
| 20080285331 | SCALABLE NONVOLATILE MEMORY - Various magnetoresistive memory cells and architectures are described which enable nonvolatile memories having high information density. | 11-20-2008 |
| 20080298119 | MAGNETIC MEMORY CELL WITH MULTIPLE-BIT IN STACKED STRUCRUTE AND MAGNETIC MEMORY DEVICE - A multi-bit magnetic memory cell in a stacked structure controlled by at least one read bit line and one read word line is provided. The multi-bit magnetic memory cell includes at least two magnetic memory units and a switching device. Each magnetic memory unit has a magneto-resistance value and at least the two magnetic memory units are stacked to form a circuit of serial connection or parallel connection. The circuit and the read bit line are connected. The switching device is connected to the circuit, wherein the switching device is controlled by the read word line to be conducting or non-conducting so as to connect the circuit with a ground voltage. Furthermore, a plurality of the multi-bit magnetic cells is used to form a magnetic memory device. | 12-04-2008 |
| 20080310213 | METHOD AND SYSTEM FOR PROVIDING SPIN TRANSFER TUNNELING MAGNETIC MEMORIES UTILIZING NON-PLANAR TRANSISTORS - A magnetic memory cell and a magnetic memory incorporating the cell are described. The magnetic memory cell includes at least one magnetic element and at least one non-planar selection device. The magnetic element(s) are programmable using write current(s) driven through the magnetic element. The magnetic memory may include a plurality of magnetic storage cells, a plurality of bit lines corresponding to the plurality of magnetic storage cells, and a plurality of source lines corresponding to the plurality of magnetic storage cells. | 12-18-2008 |
| 20080310214 | DEVICE AND METHOD OF PROGRAMMING A MAGNETIC MEMORY ELEMENT - Thus, the present disclosure provides a method of programming a memory array. At least one memory cell including a magnetic element is provided. At least one current source coupled to the magnetic element is provided. A unipolar current is supplied from the at least one current source to the magnetic element at a plurality of non-zero current levels. | 12-18-2008 |
| 20080310215 | MAGNETIC RANDOM ACCESS MEMORY AND WRITE METHOD OF THE SAME - A magnetic random access memory includes a memory unit including a memory cell array having a first memory cell for writing first information and a second memory cell for writing second information, and a controller connected to the memory unit, and configured to start supplying a write current in a first direction for writing the first information to the first memory cell and the second memory cell before a write data signal is determined, and, after the write data signal is determined, keep supplying the write current in the first direction to the first memory cell and supply the write current changed in a second direction for writing the second information to the second memory cell alone. | 12-18-2008 |
| 20080310216 | Memory element utilizing magnetization switching caused by spin accumulation and spin RAM device using the memory element - Provided is a spin memory that has excellent durability. The spin memory includes a ferromagnetic word line, a nonmagnetic bit line that crosses the ferromagnetic word line, a wiring disposed so as to be opposed to the ferromagnetic word line, and a magnetoresistive element formed between the wiring and the portion where the ferromagnetic word line and the nonmagnetic bit line cross each other. At the time of writing, current is made to flow between the ferromagnetic word line and the nonmagnetic bit line. The direction of magnetization for a free layer of the magnetoresistive element is switched by accumulating spins in the nonmagnetic bit line while the spins are injected from the ferromagnetic word line. At the time of reading, current is made to flow between the nonmagnetic bit line and the wiring, and to flow in the film-thickness direction of the magnetoresistive element. | 12-18-2008 |
| 20080316801 | Magnetic Memory System Using Mram-Sensor - The invention relates to a Magnetic memory system ( | 12-25-2008 |
| 20090003042 | MAGNETIC MEMORY DEVICE USING DOMAIN STRUCTURE AND MULTI-STATE OF FERROMAGNETIC MATERIAL - Disclosed is a memory device using a multi-domain state of a semiconductor material, and more particularly to a magnetic memory device, in which a ferromagnetic layer for recording magnetic data serves as a sensing layer so as to have a simple structure, shorten a manufacturing process, and reduce the unit cost of production. The planar hall effect or magneto-resistance is used to measure multi-domain states so as to read data stored in a multi-level state. | 01-01-2009 |
| 20090003043 | Method for switching magnetic moment in magnetoresistive random access memory with low current - A method for writing a memory cell of a magnetoresistive random access memory (MRAM) device includes, sequentially, providing a first magnetic field in a first direction, providing a second magnetic field in a second direction substantially perpendicular to the first direction, turning off the first magnetic field, providing a third magnetic field in a third direction opposite to the first direction, turning off the second magnetic field, and turning off the third magnetic field. A method for switching magnetic moments in an MRAM memory cell includes providing a magnetic field in a direction forming a blunt angle with a direction of a bias magnetic field. A method for reading an MRAM device includes partially switching magnetic moments in a reference memory cell to generate a reference current; measuring a read current through a memory cell to be read; and comparing the read current with the reference current. | 01-01-2009 |
| 20090010044 | Toggle Magnetic Random Access Memory and Write Method of Toggle Magnetic Random Access Memory - A toggle magnetic random access memory includes a first memory array, a second memory array and a controller. The first memory array includes a plurality of first memory cells including magnetoresistive elements. The second memory array includes a plurality of second memory cells including magnetoresistive elements and differs from the first memory array in write wirings used for writing. The controller controls the first memory array and the second memory array such that a first state in which a first burst write operation in the first memory array is executed and a second state in which a second burst write operation in the second memory array is executed are alternately executed in a continuous burst write mode. Accordingly, the continuous burst write operation can be executed at the high speed without any drop in the reliability and any increase in the circuit area. | 01-08-2009 |
| 20090010045 | MAGNETORESISTIVE RANDOM ACCESS MEMORY - A MRAM includes a first magnetoresistive effect (MR) element that takes a low and high resistance states. A second MR element is fixed to a low or high resistance state. First and second MOSFETs are connected to the first and second MR elements, respectively. A sense amplifier amplifies a difference between values of current flowing through the first and second MOSFETs. A current circuit outputs reference current whose value lies between current flowing through the first MR element of the low and high resistance states. A third MOSFET has one end that receives the reference current and is connected to its own gate terminal. The gate terminal of the second MOSFET receives the same potential as the gate terminal of the third MOSFET. A first resistance element is connected to the others end of the third MOSFET and has the same resistance as the second magnetoresistive effect element. | 01-08-2009 |
| 20090010046 | MAGNETIC MEMORY DEVICE WITH NON-RECTANGULAR CROSS SECTION CURRENT CARRYING CONDUCTORS - Embodiments of the invention magnetic memory device, comprising: a plurality of magnetic memory cells, each comprising: a magnetic memory element capable of being flipped between two stable spin orientations under the influence of an applied magnetic field; and current-carrying conductors proximate the magnetic element to carry a current that induces said applied magnetic field, wherein the current-carrying conductors have a non-rectangular cross section; and a read circuit for reading data from the selected magnetic memory cells. | 01-08-2009 |
| 20090016096 | Integrated Circuits; Method for Manufacturing an Integrated Circuit; Method for Decreasing the Influence of Magnetic Fields; Memory Module - Embodiments of the invention relate generally to integrated circuits, to a method for manufacturing an integrated circuit, to a method for decreasing the influence of magnetic fields, and to a memory module. In an embodiment of the invention, an integrated circuit having a magnetic tunnel junction is provided. The magnetic tunnel junction may include a free layer with a magnetization orientation that is selected by the application of a write current through the magnetic tunnel junction, and a retention layer that retains the selectable magnetization orientation of the free layer at temperatures below a retention temperature. | 01-15-2009 |
| 20090016097 | MAGNETOELECTRIC DEVICE AND METHOD FOR WRITING NON-VOLATILE INFORMATION INTO SAID MAGNETOELECTRIC DEVICE - This invention relates to a device comprising at least a first ferromagnetic layer ( | 01-15-2009 |
| 20090016098 | MAGNETORESISTIVE DEVICE - A method of operating a magnetoresistive device is described. The device comprises a ferromagnetic region configured to exhibit magnetic anisotropy and to allow magnetisation thereof to be switched between at least first and second orientations and a gate capacitively coupled to the ferromagnetic region. The method comprises applying an electric field pulse to the ferromagnetic region so as to cause orientation of magnetic anisotropy to change for switching magnetisation between the first and second orientations. | 01-15-2009 |
| 20090027948 | Integrated Circuits, Method of Programming a Cell, Thermal Select Magnetoresistive Element, Memory Module - An embodiment of the invention includes an integrated circuit that has a cell. The cell includes a first magnetic layer arrangement having a magnetization which corresponds to a predefined ground state magnetization, a non-magnetic spacer layer coupled to the first layer arrangement, a second magnetic layer arrangement disposed on the opposite side of the non-magnetic spacer layer with regard to the first magnetic layer arrangement, the second magnetic layer arrangement having a magnetization fixation temperature that is lower than the magnetization fixation temperature of the first magnetic layer arrangement, and at least a portion of the second magnetic layer arrangement having a closed magnetic flux structure in its demagnetized state. | 01-29-2009 |
| 20090027949 | Magnetic storage device - A magnetic storage device is provided which has significantly reduced power consumption. In the magnetic storage device, a yoke is arranged so as to circumferentially surround part of a line extending in an arbitrary direction, and a magneto-resistive element to which information can be written by utilizing a magnetic field generated by the line is arranged in the vicinity of the line. In this case, the length of the magnetic path of the yoke is set to 6 μm or less. | 01-29-2009 |
| 20090034321 | Magnetoresistive Element with a Biasing Layer - An improved magnetoresistive element may include a pinned magnetic structure, a free magnetic structure, and a spacer layer coupled between the pinned magnetic structure and the free magnetic structure, where the free magnetic structure includes (i) a synthetic anti-ferromagnetic structure (SAF) including two or more anti-ferromagnetically coupled ferromagnetic layers, and (ii) a first biasing layer coupled to the SAF that impedes a decoupling of the two or more anti-ferromagnetically coupled ferromagnetic layers. The first biasing layer may be an anti-ferromagnetic layer, and may be weakly coupled to the SAF. The free magnetic structure may also include (i) a second biasing layer coupled to the SAF that further impedes a decoupling of the two or more anti-ferromagnetically coupled ferromagnetic layers, and/or (ii) a non-magnetic layer coupled between the first biasing layer and the SAF that controls a coupling strength between the first biasing layer and the SAF. | 02-05-2009 |
| 20090034322 | MAGNETIC RANDOM ACCESS MEMORY AND OPERATION METHOD - A magnetic random access memory includes at least a first-direction write current line and multiple second-direction write current line, intersecting with the first-direction write current line in substantial perpendicular and forming several intersecting regions. Multiple magnetic memory cells are respectively located at the intersecting regions for receiving an induced magnetic field in a time sequence. Every at least two adjacent memory cells are in parallel or series connection, to form at least one memory unit. An easy axis of a free layer of each magnetic memory cell is substantially perpendicular to a magnetization of a pinned layer. The easy axis and the first-direction write current line form an including angle of about 45°. A read bit-line circuit connects to a first terminal of the memory unit. A read word-line circuit connects to a second terminal of the memory unit. | 02-05-2009 |
| 20090046497 | System and method for reducing critical current or magnetic random access memory - A system and a method for reducing critical current of magnetic random access memory (MRAM) are disclosed. The magnetic device includes at least a pinned layer, a spacer layer and a free layer, and the material of the pinned layer and the free layer is perpendicularly anisotropic ferrimagnetic. The spacer layer is an insulator. By the modified Landau-Lifshitz-Gilbert equations, the varying trend of the critical current can be estimated. | 02-19-2009 |
| 20090059656 | Method and Structure for Improved Lithographic Alignment to Magnetic Tunnel Junctions in the Integration of Magnetic Random Access Memories - A magnetic memory device including a Magnetic Tunnel Junction (MTJ) device comprises a substrate and Front End of Line (FEOL) circuitry. A Via level (VA) InterLayer Dielectric (ILD) layer, a bottom conductor layer, and an MTJ device formed over the top surface of the VA ILD layer are formed over a portion of the substrate. An alignment region including alignment marks extends through the bottom conductor layer and extends down into the device below the top surface of the VA ILD layers is juxtaposed with the MJT device. | 03-05-2009 |
| 20090067224 | MAGNETORESISTIVE ELEMENT, PARTICULARLY MEMORY ELEMENT OR LOGIC ELEMENT, AND METHOD FOR WRITING INFORMATION TO SUCH AN ELEMENT - A magnetoresistive element, in particular a memory element or a logic element and a method for writing information to such an element are disclosed. The element comprises a first contact of ferromagnetic material and a corresponding layer of magnetoelectric or ferromagnetic material, whereby the first contact is magnetically polarized, depending on an antiferromagnetic boundary surface polarization of the first layer. Said magnetic polarization forms binary information. | 03-12-2009 |
| 20090067225 | MODULAR MAGNETORESISTIVE MEMORY - A magnetoresistive memory element has a read module with a first pinned layer that has a magnetoresistance that is readable by a read current received from an external circuit. The element has a write module that receives a write current from the external circuit. A coupling module adjacent both the write module and the read module has a free layer that functions as a shared storage layer for both the read module and the write module. The shared storage layer receives spin torque from both the read module and the write module and has a magnetization that is rotatable by the write current. | 03-12-2009 |
| 20090073747 | MAGNETORESISTIVE SENSOR MEMORY WITH MULTIFERROIC MATERIAL - A memory cell includes a magnetoresistive sensor that comprises layers that include a free layer. The magnetoresistive sensor conducts a read current representative of data stored in the memory cell during a read interval. A first write conductor carries a write current that writes data in the free layer. At least one of the layers comprises a multiferroic layer formed of multiferroic material. | 03-19-2009 |
| 20090073748 | Integrated Circuits; Methods for Operating an Integrating Circuit; Memory Modules - Embodiments of the invention relate generally to integrated circuits, to methods for operating an integrating circuit, and to memory modules. In an embodiment of the invention, an integrated circuit having a magnetic random access memory cell is provided. The magnetic random access memory cell may include a reference layer structure being polarized in a first direction, a free layer structure including at least two anti-parallel coupled ferromagnetic layers and having an anisotropy in an axis parallel to the first direction, at least one of the at least two anti-parallel coupled ferromagnetic layers being made of a material having a temperature dependent saturation magnetization moment, and a non-magnetic tunnel barrier layer structure being disposed between the reference layer structure and the free layer structure. | 03-19-2009 |
| 20090073749 | INTEGRATED CIRCUIT, CELL ARRANGEMENT, METHOD OF OPERATING AN INTEGRATED CIRCUIT, MEMORY MODULE - An integrated circuit having a cell arrangement is provided. The cell arrangement includes at least one magnetoresistive memory cell, a first line providing a first line current, and a second line providing a second line current. The cell arrangement further includes a controller controlling the application of the first line current and the second line current, such that while the first line current is active, a transition of a magnetic field provided by a change of the second line current is provided such that the transition time of the magnetic field is shorter than the time required for the magnetization of the magnetoresistive memory cell to relax into a changed equilibrium state. | 03-19-2009 |
| 20090073750 | Method for Programming an Integrated Circuit, Methods for Programming a Plurality of Cells, Integrated Circuit, Cell Arrangement - Embodiment of the invention provide a method for programming an integrated circuit, methods for programming a plurality of cells, an integrated circuit, and a cell arrangement. An embodiment of the invention provides a method for programming an integrated circuit having a plurality of cells. The method includes grouping the plurality of cells into a first group of cells and a second group of cells depending on the cell state the cells should be programmed with. The first group of cells and the second group of cells each having a plurality of cells. The method further includes concurrently programming the cells of the first group of cells with a first cell state. After having programmed the cells of the first group of cells, the cells of the second group of cells are concurrently programmed with a second cell state, which is different from the first cell state. | 03-19-2009 |
| 20090080238 | MAGNETORESISTIVE ELEMENT AND MAGNETORESISTIVE RANDOM ACCESS MEMORY INCLUDING THE SAME - The present invention provides a low-resistance magnetoresistive element of a spin-injection write type. A crystallization promoting layer that promotes crystallization is formed in contact with an interfacial magnetic layer having an amorphous structure, so that crystallization is promoted from the side of a tunnel barrier layer, and the interface between the tunnel barrier layer and the interfacial magnetic layer is adjusted. With this arrangement, it is possible to form a magnetoresistive element that has a low resistance so as to obtain a desired current value, and has a high TMR ratio. | 03-26-2009 |
| 20090080239 | MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY - A magnetoresistive element includes a first reference layer having magnetic anisotropy perpendicular to a film surface, and an invariable magnetization, a recording layer having a stacked structure formed by alternately stacking magnetic layers and nonmagnetic layers, magnetic anisotropy perpendicular to a film surface, and a variable magnetization, and an intermediate layer provided between the first reference layer and the recording layer, and containing a nonmagnetic material. The magnetic layers include a first magnetic layer being in contact with the intermediate layer and a second magnetic layer being not in contact with the intermediate layer. The first magnetic layer contains an alloy containing cobalt (Co) and iron (Fe), and has a film thickness larger than that of the second magnetic layer. | 03-26-2009 |
| 20090080240 | METHOD FOR PRODUCTION OF MRAM ELEMENTS - Magneto-resistive random access memory elements include a ferromagnetic layer having uniaxial anisotropy provided by elongate structures formed in the ferromagnetic film. The magnetic dipole aligns with the long axis of each structure. The structures can be formed in a variety of ways. For example, the ferromagnetic film can be applied to a seed layer having a textured surface. Alternatively, the ferromagnetic film can be stressed to generate the textured structure. Chemical mechanical polishing also can be used to generated the structures. | 03-26-2009 |
| 20090086530 | System and method for reading multiple magnetic tunnel junctions with a single select transistor - A method for reading two or more magnetic tunnel junctions (MTJs) which are serially connected with a select transistor to form a memory string, the method comprises turning on the select transistor, measuring a first resistance of the memory string, storing the first resistance, toggling a predetermined one of the MTJs, measuring a second resistance of the memory string after the toggling, toggling back the predetermined one of the MTJs and comparing the first and second resistances with a plurality of predetermined resistance values, wherein the comparison result leads to a determination of the data stored in the MTJs. | 04-02-2009 |
| 20090086531 | Method and implementation of stress test for MRAM - Voltage and current stress for magnetic random access memory (MRAM) cells can weed out potential early failure cells. Method and circuit implementation of such a stress test for a MRAM comprise coupling a stress test circuit to the read bus of the MRAM and stressing the Magnetic Tunnel Junctions (MTJS) by tying them to ground by activating isolation transistors associated with them. Read word lines control which MTJs are stressed Both the method and implementation can be used for any memory cells based on resistance differences, such as Phase RAM or Spin Valve MRAM. | 04-02-2009 |
| 20090086532 | MAGNETIC RANDOM ACCESS MEMORY - A magnetic random access memory includes a memory cell having a first magnetoresistive effect element, a reference cell having a second magnetoresistive effect element set in a low-resistance state, a first bit line connected to the memory cell, and set at a first bias potential in a read operation, a second bit line connected to the reference cell, and set at a second bias potential in the read operation, and a reference voltage generator including a reference current generator having a third magnetoresistive effect element set in the high-resistance state, and a current-voltage converter having a fourth magnetoresistive effect element set in the low-resistance state, the reference current generator generating a first electric current by applying the first bias potential to the third magnetoresistive effect element, and the current-voltage converter generating the second bias potential by supplying a second electric current to the fourth magnetoresistive effect element. | 04-02-2009 |
| 20090097303 | MRAM with Resistive Property Adjustment - A magnetic random access memory (MRAM) and a method for reading an MRAM is described. The MRAM may include a magnetoresistive bit, a read architecture coupled to the magnetoresistive bit that forms a read path with the magnetoresistive bit for performing a read operation on the magnetoresistive bit, and a resistive element in the read path that adjusts resistive properties of the magnetoresistive bit during the read operation. Preferably, the resistive element will act in series with the magnetoresistive bit. The resistive element may be a resistive element between the magnetoresistive bit and the read architecture. Alternatively, the resistive element may be a layer of the magnetoresistive bit. Alternatively yet, the resistive element may be an element of the read architecture. | 04-16-2009 |
| 20090103354 | Ground Level Precharge Bit Line Scheme for Read Operation in Spin Transfer Torque Magnetoresistive Random Access Memory - Systems, circuits and methods for read operations in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A plurality of bit cells, each coupled to one of a plurality of bit lines, word lines and source lines are provided. A plurality of precharge transistors corresponding to one of the plurality of bit lines are configured to discharge the bit lines to ground prior to a read operation. | 04-23-2009 |
| 20090109734 | NON-VOLATILE SRAM CELL - Methods, devices and systems for non-volatile static random access memory (SRAM) are provided. One method embodiment for operating an SRAM includes transferring data from a pair of static storage nodes of the SRAM to a pair of non-volatile storage nodes when the SRAM is placed in a standby mode. The method further includes transferring data from the pair of non-volatile storage nodes to the pair of static storage nodes when the SRAM exits the standby mode. | 04-30-2009 |
| 20090109735 | DESIGN STRUCTURE FOR INITIALIZING REFERENCE CELLS OF A TOGGLE SWITCHED MRAM DEVICE - A design structure embodied in a machine readable medium used in a design process includes an apparatus for initializing a reference cell in a toggle switched MRAM device, with a first sense amplifier configured for performing a first read operation of the reference cell by comparing current through the reference cell with the average current passing through a pair of data cells; a first latch for storing the result of the first read operation; a second latch for storing the result of a second read operation by the first sense amplifier, wherein the second read operation is performed following the first read operation and the inversion of the value of one of the pair of the data cells; a third latch for storing the result of a third read operation by the first sense amplifier, wherein the third read operation is performed following the second read operation and the inversion of the value of the other of the pair of the data cells; and a majority compare device configured to compare of the results of the first, second and third operations respectively stored in the first, second and third latches, wherein an output of the majority compare operation is the initial state of the reference cell. | 04-30-2009 |
| 20090109736 | MAGNETIC RANDOM ACCESS MEMORY AND OPERATION METHOD THEREOF - The MRAM includes: a memory cell | 04-30-2009 |
| 20090122596 | Semconductor memory device and method of programming the same - Provided are a semiconductor memory device and a method of programming the same. The semiconductor memory device includes a mode input value generating unit and a logic operating unit. The mode input value generating unit changes a connection state between input values of a current driving circuit so as to correspond to each of at least two operating modes, and defines a logic function of a magnetic memory cell connected to the current driving circuit in response to each operating mode. The logic operating unit performs a logic operation on the logic functions of at least two magnetic memory cells defined according to each of the operating modes and generates a result of logic operation. | 05-14-2009 |
| 20090122597 | MAGNETIC RANDOM ACCESS MEMORY - An MRAM is provided with a memory main body ( | 05-14-2009 |
| 20090122598 | RESISTANCE CHANGE MEMORY DEVICE - A resistance change memory device includes: a memory cell array with memory cells arranged therein, the memory cell having a variable resistance element for storing a rewritable resistance value; a reference cell formed of the same memory cells as those set in a high resistance state in the memory cell array, the reference cell being trimmed with selection of the number of parallel-connected memory cells to have a reference current value used for detecting data in the memory cell array; and a sense amplifier configured to compare a cell current value of a memory cell selected in the memory cell array with the reference current value of the reference cell. | 05-14-2009 |
| 20090129143 | Spin transfer MRAM device with separated CPP assisted writing - A spin-transfer MRAM is described that has two sub-cells each having a conductive spacer between an upper CPP cell and a lower MTJ cell. The two conductive spacers in each bit cell are linked by a transistor which is controlled by a write word line. The two CPP cells in each bit cell have different resistance states and the MTJ cell and CPP cell in each sub-cell have different resistance states. The MTJ free layer rotates in response to switching in the CPP free layer because of a large demagnetization field exerted by the CPP free layer. An improved circuit design is disclosed that enables a faster and more reliable read process since the reference is a second MTJ within the same bit cell. When R | 05-21-2009 |
| 20090135644 | Magnetoresistive Element and Magnetic Random Access Memory - A magnetoresistive element includes a free layer a pinned layer; a nonmagnetic layer interposed between the free layer and the pinned layer; and two magnetic layers arranged adjacent to the free layer on an opposite side to the pinned layer. The free layer includes: a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer interposed between the first magnetic layer and the second magnetic layer. Magnetization of the first magnetic layer and magnetization of the second magnetic layer are antiferromagnetically coupled. One of the two magnetic layers is in contact with one end of the free layer in a long-axis direction, and the other of the two magnetic layers is in contact with the other end of the free layer in the long-axis direction. | 05-28-2009 |
| 20090141541 | MAGNETORESISTIVE MEMORY ELEMENTS WITH SEPARATE READ AND WRITE CURRENT PATHS - A magnetoresistive memory element has a free layer, and a write current path aligned with a free layer plane. The memory element has a pinned layer with a magnetization direction aligned with that of the free layer. A barrier layer is disposed between the free layer and the pinned layer. The free, barrier and pinned layers together form a layer stack that has a read current path that extends through the layer stack and that is not aligned with the write current path in the free layer. | 06-04-2009 |
| 20090141542 | MRAM DESIGN WITH LOCAL WRITE CONDUCTORS OF REDUCED CROSS-SECTIONAL AREA - Embodiments of the present invention disclose an MRAM device having a plurality of magnetic memory cells grouped into words, and write conductors for carrying write currents to write to the memory cells, wherein at least some of the write conductors have a reduced cross-sectional area in the vicinity of a group of memory cells. | 06-04-2009 |
| 20090141543 | MAGNETIC RANDOM ACCESS MEMORY, MANUFACTURING METHOD AND PROGRAMMING METHOD THEREOF - A magnetic random access memory (MRAM) and a manufacturing method and a programming method thereof are provided. The magnetic random access memory comprises a first magnetic tunnel junction structure and a second magnetic tunnel junction structure The second magnetic tunnel junction structure is electrically connected with the first magnetic tunnel junction structure, and the volume of the second magnetic tunnel junction structure is smaller than that of the first magnetic tunnel junction structure. | 06-04-2009 |
| 20090141544 | Mram and Operation Method of the Same - An operation method of an MRAM of the present invention is an operation method of the MRAM in which a data write operation is carried out in a toggle write. The operation method of the present invention includes: (A) reading a data from a data cell by using a reference signal which is generated by using a reference cell; (B) performing an error detection on the read data; (C) correcting the data stored in the data cell, when an error is detected in the read data; (D) reading the data from the data cell as a first re-read data after the (C), when the error is detected in the read data, (E) performing the error detection on the first re-read data; (F) correcting the data stored in the reference cell, when an error is detected in the first re-read data; (G) reading the data from the data cell as a second re-read data after the (F), when the error is detected in the first re-read data; (H) performing the error detection on the second re-read data; and (I) correcting the data stored in the data cell again, when the error is detected in the second re-read data. | 06-04-2009 |
| 20090147562 | COMPOUND CELL SPIN-TORQUE MAGNETIC RANDOM ACCESS MEMORY - A compound magnetic data storage cell, applicable to spin-torque random access memory (ST-RAM), is disclosed. A magnetic data storage cell includes a magnetic storage element and two terminals communicatively connected to the magnetic storage element. The magnetic storage element is configured to yield any of at least three distinct magnetoresistance output levels, corresponding to stable magnetic configurations, in response to spin-momentum transfer inputs via the terminals. | 06-11-2009 |
| 20090154224 | MAGNETIC RANDOM ACCESS MEMORY AND WRITE METHOD OF THE SAME - A spin transfer type magnetic random access memory includes a magnetoresistive effect element including a fixed layer, a recording layer, and a nonmagnetic layer, a source line connected to one terminal of the magnetoresistive effect element, a transistor having a current path whose one end is connected to the other terminal of the magnetoresistive effect element, a bit line connected to the other end of the current path of the transistor, and running parallel to the source line, and a source/sinker which supplies a write current between the source line and the bit line via the magnetoresistive effect element and the transistor, a direction in which a magnetic field generated by the write current having passed through the bit line is applied to the magnetoresistive effect element being opposite to a direction of the write current passing through the magnetoresistive effect element. | 06-18-2009 |
| 20090154225 | THIN FILM MAGNETIC MEMORY DEVICE HAVING A HIGHLY INTEGRATED MEMORY ARRAY - Read word lines and write word lines are provided corresponding to the respective MTJ (Magnetic Tunnel Junction) memory cell rows, and bit lines and reference voltage lines are provided corresponding to the respective MTJ memory cell columns. Adjacent MTJ memory cells share at least one of these signal lines. As a result, the pitches of signal lines provided in the entire memory array can be widened. Thus, the MTJ memory cells can be efficiently arranged, achieving improved integration of the memory array. | 06-18-2009 |
| 20090161413 | MRAM Device with Shared Source Line - In a particular embodiment, a memory device includes a first memory cell and a second memory cell. The memory device also includes a first bit line associated with the first memory cell and a second bit line associated with the second memory cell. The memory device also includes a source line coupled to the first memory cell and coupled to the second memory cell. | 06-25-2009 |
| 20090161414 | Spin Torque Magnetic Memory and Offset Magnetic Field Correcting Method Thereof - An object of the present invention corrects fluctuation of a writing current between cells in a magnetic random access memory using spin torque magnetization reversal. The present invention includes a magneto-resistive effect element that is disposed between a bit line and a word line, a first variable resistance element that is connected to one end of the bit line, a second variable resistance element that is connected to the other end of the bit line, a first voltage applying unit that applies voltage to the first variable resistance element, and a second voltage applying unit that applies voltage to the second variable resistance element, when a writing operation is performed, an offset magnetic field is applied to a free layer of the magneto-resistive effect element by flowing a variable current between the first voltage applying unit and the second voltage applying unit based on a predetermined resistance value. | 06-25-2009 |
| 20090168501 | Magnetic memory and method for writing to magnetic memory - Provided is a magnetic random access memory employing spin torque magnetization reversal having a small write current value is applied. The memory includes: a switching element the conduction of which is controlled by a gate electrode, and three magnetoresistance effect elements connected to the switching element in series. Each magnetoresistance effect element may be a TMR element or a GMR element that includes a multilayered film composed of a fixed layer, a non-magnetic layer and a free layer. The central element serves as a storage element. The magnetoresistance effect elements are manufactured such that an absolute value of current necessary for changing a magnetization direction of at least one of the magnetoresistance effect elements located at both ends is larger than an absolute value of current necessary for changing a magnetization direction of the central magnetoresistance effect element. | 07-02-2009 |
| 20090168502 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device that enables high-speed data read and reduces the area of a drive circuit for activating a word line. By signal transmission through a common word line having a low resistance and coupled at a plurality of points to a word line, it is possible to read data at high speed. Further, since the common word line is provided common to a plurality of memory blocks, a word line driver can be provided common to the memory blocks. Further, by disposing a latch circuit, corresponding to a sub-digit line, for holding the active state of the common word line, it is possible to transmit a row selection signal during data write through the common word line and thereby reduce a metal wiring layer. | 07-02-2009 |
| 20090185410 | METHOD AND SYSTEM FOR PROVIDING SPIN TRANSFER TUNNELING MAGNETIC MEMORIES UTILIZING UNIDIRECTIONAL POLARITY SELECTION DEVICES - A magnetic memory cell and a magnetic memory incorporating the cell are described. The magnetic memory cell includes at least one magnetic element and a plurality of unidirectional polarity selection devices. The magnetic element(s) are programmable using write current(s) driven through the magnetic element. The unidirectional polarity selection devices are connected in parallel and such that they have opposing polarities. The magnetic memory may include a plurality of magnetic storage cells, a plurality of bit lines corresponding to the plurality of magnetic storage cells, and a plurality of source lines corresponding to the plurality of magnetic storage cells. | 07-23-2009 |
| 20090190390 | Integrated Circuits, Cell, Cell Arrangement, Method of Reading a Cell, Memory Module - An embodiment of the invention provides an integrated circuit having a cell. The cell includes a first magnetic layer structure having a first magnetization along a first axis, a non-magnetic spacer layer structure disposed above the first magnetic layer structure, and a second magnetic layer structure disposed above the non-magnetic spacer layer structure. The second magnetic layer structure has a second magnetization along a second axis that is arranged in an angle with regard to the first axis such that by changing the direction of the second magnetization, the direction of the first magnetization along the first axis can be determined. | 07-30-2009 |
| 20090190391 | MAGNETORESISTIVE RANDOM ACCESS MEMORY - A word line voltage is applied to a plurality of word lines. A read/write voltage is applied to a plurality of bit lines. The read/write voltage is applied to a plurality of source lines. A word line selector selects the word line and applies the word line voltage. A driver applies a predetermined voltage to the bit line and the source line, thereby supplying a current to the memory cell. A read circuit reads a first current having flowed through the memory cell, and determines data stored in the memory cell. When performing the read, the driver supplies a second current to second bit lines among other bit lines, which are adjacent to the first bit line through which the first current has flowed. The second current generates a magnetic field in a direction to suppress a write error in the memory cell from which data is to be read. | 07-30-2009 |
| 20090201720 | MULTIBIT MAGNETIC RANDOM ACCESS MEMORY DEVICE - A multi-bit magnetic random access memory device and a method for writing to and sensing the multi-bit magnetic random access memory device. The magnetic memory includes a memory cell with a multilayer structure having a plurality of data layers which can each store one bit. The structure includes a plurality of magnetically changeable ferromagnetic layers, a ferromagnetic reference layer having a fixed magnetization state, a first spacer layer separating the magnetically changeable ferromagnetic layers, and a second spacer layer separating the ferromagnetic reference layer from the magnetically changeable ferromagnetic layers. This structure allows for more than one-bit to be stored as well as for efficient writing and reduced power consumption. | 08-13-2009 |
| 20090207651 | METHOD FOR SWITCHING MAGNETIC RANDOM ACCESS MEMORY ELEMENTS AND MAGNETIC ELEMENT STRUCTURES - A method for storing data in a magnetic memory element of an array of elements which avoids inadvertent switching of other elements is disclosed. First and second magnetic fields are applied to a selected magnetic element for a first time interval to switch the element into an intermediate state where minor domains are created. A second value of magnetic fields are then applied large enough to switch the magnetization of the minor domains, but not large enough to switch the magnetization of an adjacent memory cell. Once the minor domain is switched, the magnetization of the magnetic element assumes the state where the major domain has a magnetization direction representing the value of the stored data bit. Reducing the grain size of crystallites contained in a bit reduces the intrinsic anisotropy of the magnetic memory element thus improving bit selectivity. | 08-20-2009 |
| 20090213642 | Integrated Circuit, Memory Cell Arrangement, Memory Cell, Memory Module, Method of Operating an Integrated Circuit, and Method of Manufacturing a Memory Cell - According to an embodiment, an integrated circuit includes a magneto-resistive memory cell. The magneto-resistive memory cell includes: a first ferromagnetic layer; a second ferromagnetic layer; and a nonmagnetic layer being disposed between the first ferromagnetic layer and the second ferromagnetic layer. The integrated circuit further includes a programming circuit configured to route a programming current through the magneto-resistive memory cell, wherein the programming current programs the magnetizations of the first ferromagnetic layer and of the second ferromagnetic layer by spin induced switching effects. | 08-27-2009 |
| 20090219753 | MAGNETIC MEMORY DEVICE - A magnetic memory device including a plurality of word lines, a plurality of bit lines which intersect the word lines and are put into groups, a plurality of memory cells which are arranged at intersections between the bit lines and the word lines, each memory cell including a magnetic element and a transistor which are connected in series, a first decoder which sequentially selects the word lines, a second decoder which sequentially drives the bit lines of each group, a weighting adder which performs weighting addition of currents flowing on bit lines in a selected group to generate an added current signal, a current/voltage converter which converts the added current signal into a voltage signal, and an analog-to-digital converter which digitizes the voltage signal. | 09-03-2009 |
| 20090219754 | Magnetoresistive device and magnetic memory using the same - A magnetic film stack is composed of a synthetic antiferromagnet including a plurality of ferromagnetic layers, adjacent two of which are antiferromagnetically coupled through a non-magnetic layer; and a reversal inducing layer exhibiting ferromagnetism. The reversal inducing layer is ferromagnetically coupled to the synthetic antiferromagnet, and designed to have a coercive field smaller than a magnetic field at which antiferromagnetic coupling within the synthetic antiferromagnet starts to be decoupled. | 09-03-2009 |
| 20090231909 | Magnetoresistive Tunnel Junction Magnetic Device and Its Application to MRAM - The magnetic device comprises a magnetic device comprising a magnetoresistive tunnel junction ( | 09-17-2009 |
| 20090237982 | Magnetically De-Coupling Magnetic Tunnel Junctions and Bit/Word Lines for Reducing Bit Selection Errors in Spin-Momentum Transfer Switching - Techniques for shielding magnetic memory cells from magnetic fields are presented. In accordance with aspects of the invention, a magnetic storage element is formed with at least one conductive segment electrically coupled to the magnetic storage element. At least a portion of the conductive segment is surrounded with a magnetic liner. The magnetic liner is operative to divert at least a portion of a magnetic field created by a current passing through the conductive segment away from the magnetic storage element. | 09-24-2009 |
| 20090244957 | MULTILEVEL MAGNETIC STORAGE DEVICE - The present invention includes a memory configured to store data having a pinned layer and a plurality of stacked memory locations. Each memory location includes a nonmagnetic layer and a switchable magnetic layer. The plurality of stacked memory locations are capable of storing a plurality of data bits. | 10-01-2009 |
| 20090244958 | HYBRID SUPERCONDUCTING-MAGNETIC MEMORY CELL AND ARRAY - In one embodiment, the invention is a hybrid superconducting-magnetic memory cell and array. One embodiment of a memory cell includes a magnetoresistive element and at least one superconducting element wired in parallel with the magnetoresistive element. In a further embodiment, memory cells of the disclosed configuration are arranged to form a memory array. | 10-01-2009 |
| 20090244959 | THIN FILM MAGNETIC MEMORY DEVICE WRITING DATA WITH BIDIRECTIONAL CURRENT - An end of a selected bit line in a selected column is electrically coupled to an end of a corresponding current return line by one of first and second write column select gates, which are selectively turned on in response to results of column selection. A data write circuit sets the other end of the selected bit line and the other end of the current return line to one and the other of a power supply voltage and a ground voltage in accordance with a level of write data via one of first and second data buses and an inverted data bus, respectively. | 10-01-2009 |
| 20090244960 | MAGNETORESISTIVE EFFECT ELEMENT AND MAGNETIC MEMORY - It is made possible to provide a highly reliable magnetoresistive effect element and a magnetic memory that operate with low power consumption and current writing and without element destruction. The magnetoresistive effect element includes a first magnetization pinned layer comprising at least one magnetic layer and in which a magnetization direction is pinned, a magnetization free layer in which a magnetization direction is changeable, a tunnel barrier layer provided between the first magnetization pinned layer and the magnetization free layer, a non-magnetic metal layer provided on a first region in an opposite surface of the magnetization free layer from the tunnel barrier layer, a dielectric layer provided on a second region other than the first region in the opposite surface of the magnetization free layer from the tunnel barrier layer; and a second magnetization pinned layer provided to cover opposite surfaces of the non-magnetic metal layer and the dielectric layer from the magnetization free layer. | 10-01-2009 |
| 20090251949 | Array Structural Design of Magnetoresistive Random Access Memory (MRAM) Bit Cells - Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cells are disclosed. The bit cells include a source line formed in a first plane and a bit line formed in a second plane. The bit line has a longitudinal axis that is parallel to a longitudinal axis of the source line, and the source line overlaps at least a portion of the bit line. | 10-08-2009 |
| 20090251950 | Integrated Circuit, Memory Cell Arrangement, Thermal Select Magneto-Resistive Memory Cell, Method of Operating a Thermal Select Magneto-Resistive Memory Cell, and Method of Manufacturing a Thermal Select Magneto-Resistive Memory Cell - According to one embodiment of the present invention, an integrated circuit includes a thermal select magneto-resistive memory cell. The memory cell includes a stack of layers including a storage memory layer. The memory cell also includes a heating element which covers at least a part of the sidewalls of the stack of layers and which is electrically coupled to the stack of layers such that a heating current routed between the top end and the bottom end of the stack of layers is at least partly routed through the heating element. | 10-08-2009 |
| 20090251951 | MAGNETORESISTIVE ELEMENT AND MAGNETIC RANDOM ACCESS MEMORY - A magnetoresistive element includes a foundation layer, a first magnetic layer on the foundation layer, a tunnel barrier layer on the first magnetic layer, and a second magnetic layer on the tunnel barrier layer. The first magnetic layer is made of a ferromagnetic metal containing one or more elements selected from a first group consisting of Co, Fe, and Ni, and one or more elements selected from a second group consisting of Cu, Ag, Au, Pd, Pt, Ru, Rh, Ir, and Os. The foundation layer is made of a metal containing one or more elements selected from a third group consisting of Al, Ni, Co, Fe, Mn, Cr, and V. | 10-08-2009 |
| 20090257274 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes n resistance change elements which are arranged in one cell, have a low-resistance state and a high resistance state, are connected in series or parallel, have different resistance values in the same resistance state, and change between the low-resistance state and the high-resistance state under different conditions, and a write circuit which is connected to one end of the n resistance change elements, and applies a pulse current m (1≦m≦n) times to the n resistance change elements during a write operation. Letting Im be a current value of an mth pulse current, condition I | 10-15-2009 |
| 20090262570 | Giant magnetoresistance (GMR) memory device - The present magnetic memory device includes a pinned ferromagnetic layer, and a switchable ferromagnetic layer, the memory device being programmable to have a first programmed state wherein the resistance of the device is at a first level, a second programmed state wherein the resistance of the device is at a second level greater than the first level, and a third programmed state wherein the resistance of the device is at a third level greater than the second level. | 10-22-2009 |
| 20090262571 | Magnetic random access memory and operating method of magnetic random access memory - A magnetic random access memory includes: a first and second wirings, a plurality of third wirings, a plurality of memory cells and a terminating unit. The first and second wirings extend in a Y direction. The plurality of third wirings extends in an X direction. The memory cell is provided correspondingly to an intersection between the first and second wirings and the third wiring. The terminating unit is provided between the plurality of memory cells and connected to the first and second wirings. The memory cell includes transistors and a magnetoresistive element. The transistors are connected in series between the first and second wirings and controlled based on a signal of the third wiring. The magnetoresistive element is connected to a wiring through which the transistors are connected. At a time of a writing operation, when the write current Iw is supplied from one of the first and second wiring to the other through the transistors, the terminating unit grounds the other. | 10-22-2009 |
| 20090268512 | MRAM with cross-tie magnetization configuration - The incidence of half-select errors during MRAM programming has been significantly reduced by giving the free layer a shape that approximates an X so that, when the free layer switches, the magnetization in the arms of the X guides the magnetization in the central section (the X's intersection area) causing it to rotate towards the hard axis in two opposing directions. This raises the free layer's switching energy barrier, thereby reducing half-select errors. | 10-29-2009 |
| 20090273965 | Nonvolatile Memory Device - Ferromagnetic layers ( | 11-05-2009 |
| 20090273966 | Integrated Circuit, Memory Cell Array, Memory Module, and Method of Operating an Integrated Circuit - According to one embodiment of the present invention, an integrated circuit includes a plurality of thermal selectable memory cells, each memory cell being connected to a conductive line, the conductive line having a first portion for applying a heating current, and a second portion for applying a programming current. The integrated circuit is configured such that the heating current and the programming current can be routed respectively to the first and the second portion of the conductive line independently from each other. | 11-05-2009 |
| 20090273967 | METHOD AND INTEGRATED CIRCUIT FOR DETERMINING THE STATE OF A RESISTIVITY CHANGING MEMORY CELL - A method and an integrated circuit for determining the state of a resistivity changing memory cell. In one embodiment the method includes detecting a first resistance of the resistivity changing memory cell, determining whether the first resistance value is smaller than a predetermined threshold value thereby determining a first result value, initializing the resistivity changing memory cell into one of at least four resistivity changing memory states, detecting a second resistance value of the resistivity changing memory cell, determining whether the second resistance value is smaller than the predetermined threshold value determining a second result value, and determining the state of the resistivity changing memory cell state using the first and the second result values. | 11-05-2009 |
| 20090285012 | Integrated Circuit, Cell Arrangement, Method of Manufacturing an Integrated Circuit, Method of Operating an Integrated Circuit, and Memory Module - According to one embodiment of the present invention, an integrated circuit having a cell arrangement is provided. The cell arrangement includes: at least one reference memory cell set to a reference memory cell state; and a bias supplier to supply a bias condition to the reference memory cell when accessing the memory cell, such that the bias condition increases the stability of the set reference memory cell state. | 11-19-2009 |
| 20090285013 | MAGNETO-RESISTANCE EFFECT ELEMENT AND MAGNETIC MEMORY DEVICE - The invention relates to a magneto-resistance effect element and a magnetic memory device. Lowering the magnetic domain wall movement current and drive at room temperature in a current induction single magnetic domain wall movement phenomenon are achieved. A magneto-resistance effect element is formed by including at least: a magnet wire | 11-19-2009 |
| 20090290405 | MAGNETIC MEMORY CELL READING APPARATUS - There is provided a magnetic memory device capable of reading information even with a lower power supply voltage. | 11-26-2009 |
| 20090290406 | Low loading pad design for STT MRAM or other short pulse signal transmission - A low loading pad for a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell array is provided. The low loading pad includes a plurality of hollow-shaped lower metal layers and a top metal layer formed on an uppermost layer of the plurality of hollow-shaped lower metal layers. | 11-26-2009 |
| 20090290407 | Memory Cells, Memory Cell Constructions, and Memory Cell Programming Methods - Some embodiments include memory cells including a memory component having a first conductive material, a second conductive material, and an oxide material between the first conductive material and the second conductive material. A resistance of the memory component is configurable via a current conducted from the first conductive material through the oxide material to the second conductive material. Other embodiments include a diode comprising metal and a dielectric material and a memory component connected in series with the diode. The memory component includes a magnetoresistive material and has a resistance that is changeable via a current conducted through the diode and the magnetoresistive material. | 11-26-2009 |
| 20090290408 | RECONFIGURABLE MAGNETIC LOGIC DEVICE USING SPIN TORQUE - Spin torque magnetic logic devices that function as memory devices and that can be reconfigured or reprogrammed as desired. In some embodiments, the logic device is a single magnetic element, having a pinned layer, a free layer, and a barrier layer therebetween, or in other embodiments, the logic device has two magnetic elements in series. Two input currents can be applied through the element to configure or program the element. In use, logic input data, such as current, is passed through the programmed element, defining the resistance across the element and the resulting logic output. The magnetic logic device can be used for an all-function-in-one magnetic chip. | 11-26-2009 |
| 20090290409 | Pad design with buffers for STT-MRAM or other short pulse signal transmission - A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell array is provided. The STT-MRAM array includes a STT-MRAM bit cell and an input net coupled to the STT-MRAM bit cell. The STT-MRAM array includes a pulse signal input pad and a buffer coupled between the pulse signal input pad and the input net. In an aspect, the input net is one of a bit line, a word line, and a source line. | 11-26-2009 |
| 20090290410 | SPIN TORQUE TRANSFER MRAM DEVICE - The present disclosure provides a magnetic memory element. The memory element includes a magnetic tunnel junction (MTJ) element and an electrode. The electrode includes a pinning layer, a pinned layer, and a non-magnetic conductive layer. In one embodiment, the MTJ element includes a first surface having a first surface area, and the electrode includes a second surface. In the embodiment, the second surface of the electrode is coupled to the first surface of the MTJ element such that an interface area is formed and the interface area is less than the first surface area. | 11-26-2009 |
| 20090296454 | MAGNETIC MEMORY CELL AND MAGNETIC RANDOM ACCESS MEMORY - A magnetic memory cell | 12-03-2009 |
| 20090296455 | Spin transfer MRAM device with separated CCP assisted writing - A spin-transfer MRAM is described that has two sub-cells each having a conductive spacer between an upper CPP cell and a lower MTJ cell. The two conductive spacers in each bit cell are linked by a transistor which is controlled by a write word line. The two CPP cells in each bit cell have different resistance states and the MTJ cell and CPP cell in each sub-cell have different resistance states. The MTJ free layer rotates in response to switching in the CPP free layer because of a large demagnetization field exerted by the CPP free layer. An improved circuit design is disclosed that enables a faster and more reliable read process since the reference is a second MTJ within the same bit cell. When R | 12-03-2009 |
| 20090296456 | Spin transfer MRAM device with separated CPP assisted writing - A spin-transfer MRAM is described that has two sub-cells each having a conductive spacer between an upper CPP cell and a lower MTJ cell. The two conductive spacers in each bit cell are linked by a transistor which is controlled by a write word line. The two CPP cells in each bit cell have different resistance states and the MTJ cell and CPP cell in each sub-cell have different resistance states. The MTJ free layer rotates in response to switching in the CPP free layer because of a large demagnetization field exerted by the CPP free layer. An improved circuit design is disclosed that enables a faster and more reliable read process since the reference is a second MTJ within the same bit cell. When R | 12-03-2009 |
| 20090303779 | Spin Torque Transfer MTJ Devices with High Thermal Stability and Low Write Currents - An integrated circuit structure includes a first fixed magnetic element; a second fixed magnetic element; and a composite free magnetic element between the first and the second fixed magnetic elements. The composite free magnetic element includes a first free layer and a second free layer. | 12-10-2009 |
| 20090310399 | SEMICONDUCTOR DEVICE - In a memory using spin transfer torque, state of the spin is made unstable by applying a weak pulse before rewriting to reduce rewrite current. Reading of high-speed operation is performed with current in a regime where the current becomes non-linearly increases corresponding to the pulse width to suppress disturb. Further, fluctuation of respective memory cells is suppressed by a driving method setting the amount of spin constant by bit line charge to suppress read disturb. | 12-17-2009 |
| 20090310400 | SEMICONDUCTOR DEVICE - In MRAM using a spin-transfer torque switching, a sufficient writing operation with a small memory cell is realized, and a reading current is enlarged while a reading disturbance is suppressed. In the case where the free layer of the tunnel magneto-resistance element is located on the side of the bit line, using a PMOS transistor, and in the case where the fixed layer of the tunnel magneto-resistance element is located on the side of the bit line, using an NMOS transistor, an anti-parallel writing in a source grounding operation is performed. The reading and writing operation margin is improved by performing a reading operation in an anti-parallel writing direction. | 12-17-2009 |
| 20090316472 | MAGNETIC RANDOM ACCESS MEMORY - A magnetic random access memory (MRAM) including multiple memory cells for forming an array is provided. Each memory cell has a magnetic free stack layer and a pinned stack layer. A magnetization of the pinned stack layer is set toward a predetermined direction. The magnetic free stack layer has a magnetic easy axis. Two magnetic easy axes of adjacent two memory cells are substantially perpendicular to each other. | 12-24-2009 |
| 20090323402 | SPIN-TRANSFER TORQUE MEMORY SELF-REFERENCE READ METHOD - A spin-transfer torque memory apparatus and self-reference read schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage, the magnetic tunnel junction data cell having a first resistance state and storing the first bit line read voltage in a first voltage storage device. Then applying a low resistance state polarized write current through the magnetic tunnel junction data cell, forming a low second resistance state magnetic tunnel junction data cell. A second read current is applied through the low second resistance state magnetic tunnel junction data cell to forming a second bit line read voltage. The second bit line read voltage is stored in a second voltage storage device. The method also includes comparing the first bit line read voltage with the second bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state. | 12-31-2009 |
| 20090323403 | SPIN-TRANSFER TORQUE MEMORY NON-DESTRUCTIVE SELF-REFERENCE READ METHOD - A spin-transfer torque memory apparatus and non-destructive self-reference read schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage and storing the first bit line read voltage in a first voltage storage device. The magnetic tunnel junction data cell has a first resistance state. Then the method includes applying a second read current thorough the magnetic tunnel junction data cell having the first resistance state and forming a second bit line read voltage and storing the second bit line read voltage in a second voltage storage device. The first read current is less than the second read current. Then the stored first bit line read voltage is compared with the stored second bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state. | 12-31-2009 |
| 20090323404 | Write Operation for Spin Transfer Torque Magnetoresistive Random Access Memory with Reduced Bit Cell Size - Systems, circuits and methods for controlling write operations in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A reduced bit cell size is achieved by arranging the source lines (SL) substantially in parallel with the word lines (WL) and substantially perpendicular to the bit lines (BL). Further, in one embodiment during a write operation, a high logic/voltage level is applied to the bit lines of unselected bit cells to prevent an invalid write operation. | 12-31-2009 |
| 20090323405 | Controlled Value Reference Signal of Resistance Based Memory Circuit - Systems and methods of controlled value reference signals of resistance based memory circuits are disclosed. In a particular embodiment, a circuit device is disclosed that includes a first input configured to receive a reference control signal. The circuit device also includes an output responsive to the first input to selectively provide a controlled value reference voltage to a sense amplifier coupled to a resistance based memory cell. | 12-31-2009 |
| 20090323406 | MAGNETIC MEMORY ELEMENT, AND METHOD OF MANUFACTURING MEMORY ELEMENT - A magnetic memory element includes an impurity element, and magnetic thin lines to which the impurity element is added to adjust the movement of a magnetic domain wall in a magnetic field. Applying a voltage to the magnetic thin lines controls a position of the magnetic domain wall to invert a magnetization direction of a magnetic recording layer adjacent to the magnetic domain wall, by which information is recorded. | 12-31-2009 |
| 20100002497 | SPACE AND PROCESS EFFICIENT MRAM - Embodiments of a magnetoresistive random access memory (MRAM) array include multiple transistors having source and drain regions, and multiple substantially planar MRAM bits. The MRAM bits have upper and lower electrodes and intervening magnetics layers. The lower electrodes of at least some of the MRAM bits are formed substantially directly on at least some of the source or drain regions without an intervening via. Embodiments of an MRAM array also include a first conductive interconnect layer above and in electrical contact with the upper electrodes of at least some of the MRAM bits, with no metal layers intervening between the upper electrodes and the first conductive interconnect layer. | 01-07-2010 |
| 20100008130 | Method of operating magnetic random access memory device - Provided is a method of operating a magnetic random access memory device comprising a switch structure and a magnetoresistance structure. According to the method, current variation depending on the direction of the current can be reduced by controlling a gate voltage of the switch structure when supplying current to write data to the magnetoresistance structure. | 01-14-2010 |
| 20100008131 | MAGNETORESISTANCE EFFECT ELEMENT AND MRAM - A magnetoresistance effect element according to the present invention comprises a magnetization tree layer | 01-14-2010 |
| 20100020592 | MAGNETIC RANDOM ACCESS MEMORY AND WRITE METHOD OF THE SAME - A first magnetic layer has a magnetization fixed along one direction. A first nonmagnetic layer on the first magnetic layer functions as a first tunnel barrier. A second magnetic layer on the first nonmagnetic layer has a magnetization whose direction can be reversed by spin transfer current injection. A second nonmagnetic layer on the second magnetic layer functions as a second tunnel barrier. A third magnetic layer on the second nonmagnetic layer has a magnetization whose direction can be reversed by spin transfer through current injection at a current density different from the second magnetic layer. First magnetic, first nonmagnetic layer, and second magnetic layers exhibit a first magnetoresistive effect. Second magnetic, second nonmagnetic, and third magnetic layers exhibit a second magnetoresistive effect. A magnetoresistive effect element records and reads out data of at least three levels based on a synthetic resistance from the first and second magnetoresistive effects. | 01-28-2010 |
| 20100027323 | MAGNETIC RECORDING ELEMENT - A magnetic recording element is disclosed for which current density required for writing is low and structure of the element is simple. It comprises a ferromagnetic fine wire formed on a Si substrate, current electrodes that contact ends of the ferromagnetic fine wire, and voltage electrodes joined to the ferromagnetic fine wire and current electrodes to measure voltage across part of the ferromagnetic fine wire in cooperation with the current electrodes. A magnetic domain wall is induced in the ferromagnetic fine wire when the element is manufactured. A depression is formed in the surface on top of the ferromagnetic fine wire between the voltage electrodes, and between one of the current electrodes and one of the voltage electrodes. Voltage is measured between the two voltage electrodes when reading current is applied, to determine whether the magnetic domain wall is present between the two voltage electrodes, whereby recorded data can be identified. | 02-04-2010 |
| 20100034014 | Magnetoresistive Element, Magnetic Memory Cell and Magnetic Random Access Memory Using the Same - Provided is a high-speed and ultra-low-power-consumption nonvolatile memory having a high temperature stability at a zero magnetic field. In a tunnel magnetoresistive film constituting a nonvolatile magnetic memory that employs a writing method using a spin-transfer torque, an insulating layer and a nonmagnetic conductive layer are stacked above a ferromagnetic free layer. | 02-11-2010 |
| 20100034015 | SEMICONDUCTOR DEVICE - The invention provides a semiconductor device having a lower probability of erroneous inversion of data signal. The MRAM disclosed herein comprises (m+1)×(n+1) memory cells arranged in (m+1) rows and (n+1) columns, digit lines respectively provided in the rows, and bit lines respectively provided in the columns. A magnetizing current Im caused to flow through a digit line in a selected row makes all memory cells half-selected in the row, while a writing current is caused to flow through (n+1) bit lines to write data signals of (n+1) bits into the (n+1) memory cells, the direction of the writing current depending on the logic of each of these data signals. Thus, erroneous inversion of data signal due to a magnetic field in a digit line is avoided. | 02-11-2010 |
| 20100039855 | EXCHANGE-ASSISTED SPIN TRANSFER TORQUE SWITCHING - In general, the invention is directed to techniques for reducing the amount of switching current that is utilized within a magnetic storage (e.g., MRAM) device. An example apparatus includes a fixed magnetic layer that provides a fixed direction of magnetization, an exchange-coupled magnetic multi-layer structure, and a non-magnetic layer placed between the fixed magnetic layer and the exchange-coupled magnetic multi-layer structure. The exchange-coupled magnetic multi-layer structure includes a recording layer configured to record information and an assisting layer having a lower anisotropy than the recording layer. The exchange coupling between the recording and assisting layers is operable to switch a magnetization direction of the recording layer. In some cases, the exchange-coupled magnetic multi-layer structure may further include a spacer separating the recording and assisting layers and configured to weaken an exchange coupling between the recording and assisting layers. | 02-18-2010 |
| 20100046282 | Cross-point magnetoresistive memory - A ferromagnetic thin-film based digital memory system having memory cells interconnected in a grid that are selected through voltage values supplied coincidently on interconnections made thereto for changing states thereof and determining present states thereof through suitable biasing of grid interconnections. | 02-25-2010 |
| 20100046283 | MAGNETIC RANDOM ACCESS MEMORY AND OPERATION METHOD OF THE SAME - A magnetic random access memory of the present invention includes: a plurality of first wirings and a plurality of second wirings extending in a first direction; a plurality of third wirings and a plurality of fourth wirings extending in a second direction; and a plurality of memory cells provided at intersections of the plurality of first wirings and the plurality of third wirings, respectively. Each of the plurality of memory cells includes: a first transistor and a second transistor connected in series between one of the plurality of first wirings and one of the plurality of second wirings and controlled in response to a signal on one of the plurality of third wirings, a first magnetic resistance element having one end connected to a write wiring through which the first transistor and the second transistor are connected, and the other end grounded; and a second magnetic resistance element having one end connected to the write wiring, and the other end connected to the fourth wiring. | 02-25-2010 |
| 20100046284 | MRAM - An MRAM comprises: a plurality of magnetic memory cells each having a magnetoresistive element; and a magnetic field application section. The magnetic field application section applies an offset adjustment magnetic field in a certain direction to the plurality of magnetic memory cells from outside the plurality of magnetic memory cells. Respective data stored in the plurality of magnetic memory cells become the same when the offset adjustment magnetic field is removed. | 02-25-2010 |
| 20100054026 | MEMORY WITH SEPARATE READ AND WRITE PATHS - A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line and a magnetic tunnel junction data cell electrically coupled between a read bit line and a read source line. A write current passing through the giant magnetoresistance cell switches the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell. The magnetic tunnel junction data cell is read by a read current passing though the magnetic tunnel junction data cell. | 03-04-2010 |
| 20100054027 | Symmetric STT-MRAM Bit Cell Design - A symmetric Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell and STT-MRAM bit cell array are disclosed. The STT-MRAM bit cell includes a poly silicon layer, a magnetic tunnel junction (MTJ) storage element, and a bottom electrode (BE) plate. The storage element and bottom electrode (BE) plate are symmetric along a center line of the poly silicon layer. | 03-04-2010 |
| 20100054028 | STT-MRAM Bit Cell Having a Rectangular Bottom Electrode Plate And Improved Bottom Electrode Plate Width And Interconnect Metal Widths - A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell is provided. The STT-MRAM includes a rectangular bottom electrode (BE) plate, and a storage element on the rectangular bottom electrode (BE) plate. A difference between a width of the rectangular bottom electrode (BE) plate and a width of the storage element is equal to or greater than a predetermined minimum spacing requirement. A width of the bottom electrode (BE) plate is substantially equal to a width of an active layer or a width of a plurality of metal layers. | 03-04-2010 |
| 20100061144 | Memory Device for Resistance-Based Memory Applications - In a particular embodiment, a memory device is disclosed that includes a memory cell including a resistance-based memory element coupled to an access transistor. The access transistor has a first oxide thickness to enable operation of the memory cell at an operating voltage. The memory device also includes a first amplifier configured to couple the memory cell to a supply voltage that is greater than a voltage limit to generate a data signal based on a current through the memory cell. The first amplifier includes a clamp transistor that has a second oxide thickness that is greater than the first oxide thickness. The clamp transistor is configured to prevent the operating voltage at the memory cell from exceeding the voltage limit. | 03-11-2010 |
| 20100073998 | DATA WRITING METHOD FOR MAGNETORESISTIVE EFFECT ELEMENT AND MAGNETIC MEMORY - A data writing method for a magnetoresistive effect element of an aspect of the present invention including generating a write current in which a falling period from the start of a falling edge to the end of the falling edge is longer than a rising period from the start of a rising edge to the end of the rising edge, and flowing the write current through the magnetoresistive effect element which comprises a first magnetic layer having an invariable magnetizing direction, a second magnetic layer having a variable magnetizing direction, and a tunnel barrier layer provided between the first magnetic layer and the second magnetic layer, to change the magnetizing direction of the second magnetic layer. | 03-25-2010 |
| 20100080049 | THERMALLY ASSISTED MULTI-BIT MRAM - Methods of writing to a multi-bit MRAM memory unit are described. The method includes to self-detected writing to a multi-bit (i.e., multilevel) thermally assisted MRAM. The self-detected writing increases a reading margin between data state levels and decreases reading margin variability due to cell resistance variation. | 04-01-2010 |
| 20100080050 | MAGNETORESISTIVE EFFECT DEVICE AND MAGNETIC MEMORY - A magnetic memory includes a magnetoresistive effect device comprising: a first ferromagnetic layer that has magnetic anisotropy in a direction perpendicular to a film plane thereof; a first nonmagnetic layer that is provided on the first ferromagnetic layer; a first reference layer that is provided on the first nonmagnetic layer, has magnetic anisotropy in a direction perpendicular to a film plane thereof, has magnetization antiparallel to a magnetization direction of the first ferromagnetic layer, and has a film thickness that is 1/5.2 to 1/1.5 times as large as a film thickness of the first ferromagnetic layer in the direction perpendicular to the film plane; a second nonmagnetic layer that is provided on the first reference layer; and a storage layer that is provided on the second nonmagnetic layer, has magnetic anisotropy in a direction perpendicular to a film plane thereof, and has a magnetization direction varied by spin-polarized electrons caused by flowing the current to the magnetoresistive effect device. | 04-01-2010 |
| 20100085803 | ELECTRONIC DEVICES UTILIZING SPIN TORQUE TRANSFER TO FLIP MAGNETIC ORIENTATION - Electronic devices that include (i) a magnetization controlling structure; (ii) a tunnel barrier structure; and (iii) a magnetization controllable structure including: a first polarizing layer; and a first stabilizing layer, wherein the tunnel barrier structure is between the magnetization controlling structure and the magnetization controlling structure and the first polarizing layer is between the first stabilizing layer and the tunnel barrier structure, wherein the electronic device has two stable overall magnetic configurations, and wherein a first unipolar current applied to the electronic device will cause the orientation of the magnetization controlling structure to reverse its orientation and a second unipolar current applied to the electronic device will cause the magnetization controllable structure to switch its magnetization in order to obtain one of the two stable overall magnetic configurations, wherein the second unipolar current has an amplitude that is less than the first unipolar current. | 04-08-2010 |
| 20100091555 | MAGNETORESISTIVE EFFECT ELEMENT AND MAGNETIC RANDOM ACCESS MEMORY - A magnetic random access memory has a laminating structure including: a magnetization free layer; an insulating layer; and a magnetization fixed layer. The magnetization free layer includes: a sense layer; a first bonding layer being adjacent to the sense layer; and a storage layer being adjacent to the first bonding layer on an opposite side to the sense layer. At least a part of the sense layer and the storage layer is magnetically coupled to one another through the first bonding layer. A magnetic anisotropy of the storage layer is larger than that of the sense layer. A product of a saturation magnetization and a volume of the sense layer is larger than that of the storage layer. According to such a structure, a magnetic random access memory can be provided in which a current for writing is reduced while enough thermal stability is maintained. | 04-15-2010 |
| 20100091556 | MAGNETO-RESISTANCE EFFECT ELEMENT AND MAGNETIC MEMORY - It is possible to reduce a current required for spin injection writing. A magneto-resistance effect element includes: a first magnetization pinned layer; a magnetization free layer; a tunnel barrier layer; a second magnetization pinned layer whose direction of magnetization is pinned to be substantially anti-parallel to the direction of magnetization of the first magnetization pinned layer, and; a non-magnetic layer. When the second magnetization pinned layer is made of ferromagnetic material including Co, material for the non-magnetic layer is metal including at least one element selected from the group consisting of Zr, Hf, Rh, Ag, and Au; when the second magnetization pinned layer is made of ferromagnetic material including Fe, material for the non-magnetic layer is metal including at least one element selected from the group consisting of Rh, Pt, Ir, Al, Ag, and Au; and when the second magnetization pinned layer is made of ferromagnetic material including Ni, material for the non-magnetic layer is metal including at least one element selected from the group consisting of Zr, Hf, Au, and Ag. | 04-15-2010 |
| 20100091557 | MAGNETIC RANDOM ACCESS MEMORY HAVING IMPROVED READ DISTURB SUPPRESSION AND THERMAL DISTURBANCE RESISTANCE - Between the value of an electric current and the supply duration for which the electric current is supplied that cause magnetization reversal, there is the relation of monotonous decrease. This means that, as the supply duration is shortened, the threshold current value for causing the magnetization reversal is larger. Therefore, in terms of suppressing occurrence of read disturb, the read current supply duration may be shortened to increase the threshold value of the current causing the magnetization reversal and thereby ensure a sufficient read disturb margin. Therefore, the read current supply duration may be shortened relative to the write current supply duration ensure the read disturb margin and suppress occurrence of read disturb. | 04-15-2010 |
| 20100097845 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device is provided with a memory array including a plurality of memory cells. The plurality of memory cells includes: first and third memory cells arranged along one of an even-numbered row and an odd-numbered row, and a second memory cell arranged along the other. Each of the plurality of memory cells includes: a first transistor comprising first and second diffusion layers; a second transistor comprising third and fourth diffusion layers; and a magnetoresistance element having one of terminals thereof connected to an interconnection layer which provides an electrical connection between the second and third diffusion layers. The fourth diffusion layer of the first memory cell is also used as the first diffusion layer of the second memory cell. In addition, the fourth diffusion layer of the second memory cell is also used as the first diffusion layer of the third memory cell. | 04-22-2010 |
| 20100097846 | MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY - A magnetic memory includes an interlayer insulation layer provided on a substrate, a conductive underlying layer provided on the interlayer insulation layer, and a magnetoresistive element provided on the underlying layer and including two magnetic layers and a nonmagnetic layer interposed between the magnetic layers. The underlying layer has an etching rate lower than an etching rate of each of the magnetic layers. | 04-22-2010 |
| 20100097847 | Information storage element and method of writing/reading information into/from information storage element - An information storage element includes a strip-shaped ferromagnetic material layer; a first electrode disposed at a first end of the ferromagnetic material layer; and a second electrode disposed at a second end of the ferromagnetic material layer, wherein a current-induced domain wall motion is caused by applying a current between the first electrode and the second electrode, in the ferromagnetic material layer, a magnetization state is written into a magnetization region as information or a magnetization state is read from a magnetization region as information, a magnetization direction in each magnetization region is parallel to a direction of the thickness of the ferromagnetic material layer, and at the time of writing information or reading information, a temperature distribution that monotonically decreases from the second end of the ferromagnetic material layer to the first end thereof is generated in the ferromagnetic material layer. | 04-22-2010 |
| 20100097848 | Information storage element and method of writing/reading information into/from information storage element - In a method of writing information into and reading information from an information storage element which includes a strip-shaped ferromagnetic material layer, a first electrode disposed at an end of the ferromagnetic material layer, a second electrode disposed at another end of the ferromagnetic material layer, and an antiferromagnetic region composed of an antiferromagnetic material and disposed in contact with at least a part of the ferromagnetic material layer, the method includes the steps of applying a current between the first electrode and the second electrode to cause a current-induced domain wall motion; in the ferromagnetic material layer, writing a magnetization state into a magnetization region as information or reading a magnetization state from a magnetization region as information; and eliminating or decreasing exchange coupling between the ferromagnetic material layer and the antiferromagnetic region at the time of the motion of a domain wall. | 04-22-2010 |
| 20100103720 | BIOSENSOR AND SENSING CELL ARRAY USING THE SAME - A biosensor and a sensing cell array using a biosensor are disclosed. Adjacent materials containing plurality of different ingredients are analyzed to determine the ingredients based on their magnetic susceptibility or dielectric constant. A sensing cell array includes such as a magnetization pair detection sensor including a MTJ (Magnetic Tunnel Junction) or GMR to (Giant Magnetoresistive) device, a magnetoresistive sensor including a MTJ device and a magnetic material (current line), a dielectric constant sensor including a sensing capacitor and a switching device, a magnetization hole detection sensor including a MTJ or GMR device, a current line, a free ferromagnetic layer and a switching device, and a giant magnetoresistive sensor including a GMR device, a switching device and a magnetic material (or forcing wordline). Ingredients of adjacent materials are separated based on electrical characteristics of ingredients by sensing magnetic susceptibility and dielectric constant depending on the sizes of the ingredients. | 04-29-2010 |
| 20100110775 | Word Line Voltage Control in STT-MRAM - Systems, circuits and methods for controlling the word line voltage applied to word line transistors in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. One embodiment is directed to a STT-MRAM including a bit cell having a magnetic tunnel junction (MTJ) and a word line transistor. The bit cell is coupled to a bit line and a source line. A word line driver is coupled to a gate of the word line transistor. The word line driver is configured to provide a word line voltage greater than a supply voltage below a transition voltage of the supply voltage and to provide a voltage less than the supply voltage for supply voltages above the transition voltage. | 05-06-2010 |
| 20100110776 | Data Protection Scheme during Power-Up in Spin Transfer Torque Magnetoresistive Random Access Memory - A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) array including a plurality of bit cells, a power-up controller, and a first plurality of precharge transistors is disclosed. The plurality of bit cells are each coupled to one of a plurality of bit lines and word lines. The power-up controller is configured to provide a power-up control signal to control the voltage level of at least one of the bit lines or the word lines during power-up. The first plurality of precharge transistors are respectively coupled to at least one of the plurality of bit lines or the plurality of word lines, each precharge transistor being configured to discharge a corresponding bit line or word line to a desired voltage level based on the power-up control signal. | 05-06-2010 |
| 20100110777 | MAGNETIC RANDOM ACCESS MEMORY - An MRAM according to the present invention has a magnetoresistance element | 05-06-2010 |
| 20100118600 | MAGNETORESISTIVE ELEMENT - A magnetoresistive element which records information by supplying spin-polarized electrons to a magnetic material, includes a first pinned layer which is made of a magnetic material and has a first magnetization directed in a direction perpendicular to a film surface, a free layer which is made of a magnetic material and has a second magnetization directed in the direction perpendicular to the film surface, the direction of the second magnetization reversing by the spin-polarized electrons, and a first nonmagnetic layer which is provided between the first pinned layer and the free layer. A saturation magnetization Ms of the free layer satisfies a relationship 0≦Ms<√{square root over ( )}{Jw/(6πAt)}. Jw is a write current density, t is a thickness of the free layer, A is a constant. | 05-13-2010 |
| 20100135066 | BIT LINE CHARGE ACCUMULATION SENSING FOR RESISTIVE CHANGING MEMORY - A memory array includes a plurality of magneto-resistive changing memory cells. Each resistive changing memory cell is electrically between a source line and a bit line and a transistor electrically between the resistive changing memory cell and the bit line. The transistor has a gate electrically between a source region and a drain region and the source region being electrically between the magneto-resistive changing memory cell and the gate. A word line is electrically coupled to the gate. A bit line charge accumulation sensing for magneto-resistive changing memory is also disclosed. | 06-03-2010 |
| 20100135067 | NON-VOLATILE MEMORY WITH STRAY MAGNETIC FIELD COMPENSATION - A method and apparatus for stray magnetic field compensation in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a first tunneling barrier is coupled to a reference structure that has a perpendicular anisotropy and a first magnetization direction. A recording structure that has a perpendicular anisotropy is coupled to the first tunneling barrier and a nonmagnetic spacer layer. A compensation layer that has a perpendicular anisotropy and a second magnetization direction in substantial opposition to the first magnetization direction is coupled to the nonmagnetic spacer layer. Further, the memory cell is programmable to a selected resistance state with application of a current to the recording structure. | 06-03-2010 |
| 20100135068 | RESISTANCE-CHANGE MEMORY DEVICE - A resistance-change memory device is provided and includes a stack constituting a tunnel magnetoresistance effect element that has a magnetic layer in which a direction of magnetization is switchable and that is formed on a conductive layer, and the stack is included in a resistance-change memory cell performing data writing utilizing a spin transfer effect caused by current injection. The stack is formed such that a line connecting centers of respective layers of the stack is tilted with respect to a direction perpendicular to a surface of the conductive layer having the stack formed thereon. | 06-03-2010 |
| 20100135069 | RESISTANCE VARIABLE MEMORY DEVICE - A resistance variable memory device is provided and includes a resistance variable memory cell that writes data by utilizing a spin transfer effect based on an injection current. The memory device also includes a driving circuit that generates a combined pulse of a plurality of write pulses and an offset pulse defining the level between the write pulses and supplies the combined pulse to the memory cell at the time of the writing. | 06-03-2010 |
| 20100142259 | NANOGAPS: METHODS AND DEVICES CONTAINING SAME - Disclosed are methods of fabricating nanogaps and various devices composed of nanogaps. The nanogap devices disclosed herein can be used as in a number of electronic, photonic and quantum mechanical devices, including field-effect transistors and logic circuits. | 06-10-2010 |
| 20100142260 | Data Integrity Preservation In Spin Transfer Torque Magnetoresistive Random Access Memory - Systems, circuits and methods for controlling the word line voltage applied to word line transistors in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. One embodiment is directed to a STT-MRAM including a bit cell having a magnetic tunnel junction (MTJ) and a word line transistor. The bit cell is coupled to a bit line and a source line. A word line driver is coupled to a gate of the word line transistor. A write-back circuit configured to detect a read value of the bit cell and is configured to write back the read value to the bit cell after a read operation. | 06-10-2010 |
| 20100157662 | MRAM AND METHOD FOR WRITING IN MRAM - In one embodiment of the present invention, an MRAM is an MRAM including: a plurality of write word lines; a plurality of bit lines provided so as to intersect with the write word lines; and TMR elements provided at respective intersections of the write word lines and the bit lines. Each of the TMR elements includes a first ferromagnetic layer of which magnetization direction is variable, a second ferromagnetic layer of which magnetization direction is fixed, and a tunnel wall which is sandwiched between the first ferromagnetic layer and the second ferromagnetic layer. The bit line is provided, for example, so as to bulge in the direction in which the write word line extends at the intersection of the bit line and the write word line, so that a magnetic wall is introduced at a desired position of the bit line. Further, a current fed through the bit line is fed through the first ferromagnetic layer at the time of data writing. This makes it possible to provide the MRAM having a gigabit-class capacity. | 06-24-2010 |
| 20100157663 | Information storage device and method of operating the same - An information storage device includes a memory region having a magnetic track and a write/read unit, and a control circuit connected to the memory region. First and second switching devices are connected to both ends of the magnetic track, and a third switching device is connected to the write/read unit. The control circuit controls the first to third switching devices, and supplies operating current to at least one of the magnetic track and the write/read unit. | 06-24-2010 |
| 20100157664 | MAGNETORESISTIVE MEMORY CELL USING FLOATING BODY EFFECT, MEMORY DEVICE HAVING THE SAME, AND METHOD OF OPERATING THE MEMORY DEVICE - A magnetoresistive memory cell includes an MTJ device and a select transistor. The select transistor includes a first conduction-type semiconductor layer, a gate electrode formed by disposing a gate insulating layer on top of the semiconductor layer, and first and second diffusion regions formed in the semiconductor layer to be spaced apart from each other and to have a second conduction type. A part of the semiconductor layer between the first and second diffusion regions is formed as an electrically floating body region. By using a high-performance select transistor with a floating body effect, high integration of a magnetoresistive memory device may be achieved. | 06-24-2010 |
| 20100165710 | Random access memory architecture including midpoint reference - A random access memory architecture includes a first series connected pair of memory elements ( | 07-01-2010 |
| 20100172173 | System And Method To Read And Write Data A Magnetic Tunnel Junction Element - A system and method to read and write data in magnetic random access memories are disclosed. In a particular embodiment, a device includes a spin transfer torque magnetic tunnel junction (STT-MTJ) element and a transistor with a first gate and a second gate coupled to the STT-MTJ element. | 07-08-2010 |
| 20100177557 | STT-MRAM CELL STRUCTURES - A magnetic cell structure including a nonmagnetic bridge, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, and a nonmagnetic bridge electrically connecting the free layer and the pinned layer. The shape and/or configuration of the nonmagnetic bridge directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer of the structure is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell. | 07-15-2010 |
| 20100177558 | MRAM HAVING VARIABLE WORD LINE DRIVE POTENTIAL - An MRAM of a spin transfer type according to the invention is provided with a memory cell | 07-15-2010 |
| 20100182824 | MAGNETIC RANDOM ACCESS MEMORY - An MRAM according to the present invention has: a memory cell array; a first word line and a second word line each connected to a group of memory cells arranged in a first direction; a plurality of blocks arranged in a matrix form; a common word line connected to a group of blocks arranged in the first direction; and a bit line pair connected to a group of blocks arranged in a second direction. Each block has a plurality of memory cells, and each memory cell has a first transistor and a magnetoresistance element. Each block further has a second transistor to which the plurality of memory cells are connected in parallel. A gate of the second transistor is connected to the common word line. A gate of the first transistor is connected to the first word line. One of source/drain of the first transistor is connected to the first bit line, and the other thereof is connected to one end of the magnetoresistance element and connected to the second bit line through the second transistor. The other end of the magnetoresistance element is connected to the second word line. | 07-22-2010 |
| 20100188890 | MAGNETORESISTANCE EFFECT ELEMENT AND MAGNETIC RANDOM ACCESS MEMORY - A magnetoresistance effect element includes: a magnetization free layer; a spacer layer provided adjacent to the magnetization free layer; a first magnetization fixed layer provided adjacent to the spacer layer on a side opposite to the magnetization free layer; and at least two second magnetization fixed layers provided adjacent to the magnetization free layer. The magnetization free layer, the first magnetization fixed layer, and the second magnetization free layers respectively have magnetization components in a direction substantially perpendicular to film surfaces thereof. The magnetization free layer includes: two magnetization fixed portions; and a domain wall motion portion arranged between the two magnetization fixed portions. Magnetizations of the two magnetization fixed portions constituting the magnetization free layer are fixed substantially antiparallel to each other in directions substantially perpendicular to the film surface. The domain wall motion portion is provided with magnetic anisotropy in a direction perpendicular to the film surface. | 07-29-2010 |
| 20100188891 | SEMICONDUCTOR DEVICE - The semiconductor device has: a first magnetoresistance element; a second magnetoresistance element. The first and second magnetoresistance elements each includes a free layer which can be changed in spin orientation therein and a pinned layer which is fixed in spin orientation therein. The first magnetoresistance element is coupled to a first transistor at the free layer, and to a first power-source terminal at the pinned layer. The second magnetoresistance element is coupled to a second transistor at the free layer, and to the first power-source terminal at the pinned layer. In this device, the reliability of stored data is increased by preventing an undesired resistance condition's change in a magnetoresistance memory cell. | 07-29-2010 |
| 20100195376 | BIT LINE VOLTAGE CONTROL IN SPIN TRANSFER TORQUE MAGNETORESISTIVE RANDOM ACCESS MEMORY - A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) and associated read operations are disclosed. A bit cell includes a magnetic tunnel junction (MTJ) and a word line transistor, the bit cell being coupled to a bit line and a source line. A clamping circuit is coupled to the bit line and is configured to clamp the bit line voltage to a desired voltage level during a read operation of the STT-MRAM to prevent the bit line voltage from exceeding the desired voltage level. The desired voltage level is less than a write voltage threshold associated with a write operation of the STT-MRAM. | 08-05-2010 |
| 20100208513 | MEMORY WITH SEPARATE READ AND WRITE PATHS - A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer separated from a first pinned magnetic layer by a first non-magnetic electrically conducting layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer separated from a second pinned magnetic layer by an oxide barrier layer. A write current passes through the giant magnetoresistance cell to switch the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell. | 08-19-2010 |
| 20100214825 | Programming MRAM Cells Using Probability Write - A method of writing a magneto-resistive random access memory (MRAM) cell includes providing a writing pulse to write a value to the MRAM cell; and verifying a status of the MRAM cell immediately after the step of providing the first writing pulse. In the event of a write failure, the value is rewritten into the MRAM cell. | 08-26-2010 |
| 20100214826 | MAGNETIC RANDOM ACCESS MEMORY, WRITE METHOD THEREFOR, AND MAGNETORESISTANCE EFFECT ELEMENT - A magnetic random access memory includes: a first ferromagnetic layet; an insulating layer provided adjacent to the first ferromagnetic layer; and a first magnetization pinned layer provided adjacent to the insulating layer on a side opposite to the first ferromagnetic layer. The first ferromagnetic layer includes a magnetization free region, a first magnetization pinned region, and a second magnetization pinned region. The magnetization free region has reversible magnetization, and overlaps with the second ferromagnetic layer. The first magnetization pinned region has first pinned magnetization, and is connected to a part of the magnetization free region. The second magnetization pinned region has second pinned magnetization, and is connected to a part of the magnetization free region. The first ferromagnetic layer has magnetic anisotropy in a direction perpendicular to a film surface. The first pinned magnetization and the second pinned magnetization are pinned antiparallel to each other in the direction perpendicular to the film surface. | 08-26-2010 |
| 20100220516 | Reducing Source Loading Effect in Spin Torque Transfer Magnetoresisitive Random Access Memory (STT-MRAM) - Systems and methods to reduce source loading effects in STT-MRAM are disclosed. In a particular embodiment, a method includes determining a switching current ratio of a magnetic tunnel junction (MTJ) structure that enables stable operation of a memory cell. The memory cell includes the MTJ structure serially coupled to an access transistor. The method also includes modifying an offset magnetic field that is incident to a free layer of the MTJ structure. The modified offset magnetic field causes the MTJ structure to exhibit the switching current ratio. | 09-02-2010 |
| 20100220517 | SEMICONDUCTOR DEVICE - Data which sets up operation parameters, etc. of an internal circuit is supplied stably over a long period of time. In a cell array in which MRAM cells are arranged, read/write of test data is performed in a PROM mode. Finally, data writing is specifically performed to the memory cells in an OTP mode. | 09-02-2010 |
| 20100220518 | THERMALLY ASSISTED MULTI-BIT MRAM - Methods of writing to a multi-bit MRAM memory unit are described. The method includes to self-detected writing to a multi-bit (i.e., multilevel) thermally assisted MRAM. The self-detected writing increases a reading margin between data state levels and decreases reading margin variability due to cell resistance variation. | 09-02-2010 |
| 20100226167 | MAGNETIC MEMORY - A spin-transfer magnetic memory includes a magnetoresistive element having a pinned layer, a free layer and a tunnel insulating layer provided between the pinned layer and the free layer, a bit line connected to one terminal of the magnetoresistive element, a select transistor having a current path whose one terminal is connected to the other terminal of the magnetoresistive element, a source line connected to the other terminal of the current path of the select transistor, and a pulse generation circuit passing a microwave pulse current through the magnetoresistive element, and assisting a magnetization switching of the free layer in a write operation. | 09-09-2010 |
| 20100232215 | MRAM with coupling valve switching - The free layer in a magneto-resistive memory element is stabilized through being pinned by an antiferromagnetic layer. A control valve layer provides exchange coupling between this antiferromagnetic layer and the free layer. When writing data into the free layer, the control valve layer is heated above its curie point thereby temporarily uncoupling the free layer from said antiferromagnetic layer. Once the control valve cools, the free layer magnetization is once again pinned by the antiferromagnetic layer. | 09-16-2010 |
| 20100238717 | MAGNETORESISTIVE DEVICE AND MAGNETIC RANDOM ACCESS MEMORY - A magnetoresistive device includes: a magnetic recording layer including a first magnetic layer having perpendicular magnetic anisotropy, and a second magnetic layer having in-plane magnetic anisotropy and being exchange-coupled to the first magnetic layer, Curie temperature of the second magnetic layer being lower than Curie temperature of the first magnetic layer, and the magnetic recording layer having a magnetization direction perpendicular to a film plane; a magnetic reference layer having a magnetization direction which is perpendicular to a film plane and is invariable; and a nonmagnetic layer provided between the magnetic recording layer and the magnetic reference layer. The magnetization direction of the magnetic recording layer is changeable by spin-polarized electrons caused by flowing current between the magnetic recording layer and the magnetic reference layer in a direction perpendicular to the film plane. | 09-23-2010 |
| 20100238718 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a semiconductor substrate including an active area, a first select transistor in the active area, a first interconnection layer above the semiconductor substrate configured to run in a first direction, a first magnetoresistive element above the first interconnection layer including a fixed layer having a fixed magnetization direction, a nonmagnetic layer on the fixed layer, and a recording layer on the nonmagnetic layer having a variable magnetization direction, the fixed layer being electrically connected to the first interconnection layer, the recording layer being electrically connected to a first diffusion region of the first select transistor, and a second interconnection layer configured to run in the first direction and electrically connected to a second diffusion region of the first select transistor. | 09-23-2010 |
| 20100238719 | MAGNETIC RANDOM ACCESS MEMORY AND OPERATING METHOD OF THE SAME - A MRAM includes: first and second bit lines provided to extend in a first direction; a storage block including at least one magnetroresistive element for storing data; and a reading circuit. The reading circuit includes a first terminal electrically connected to the first bit line, and a second terminal electrically connected to the second bit line. The second terminal has a high impedance preventing a steady-state current from flowing into at a time of a reading operation. The reading circuit supplies a reading current from the first terminal to the first bit line at the time of the reading operation. The storage block is configured such that the reading current flows from the first bit line to the magnetroresistive element and the magnetroresistive element is connected to the second bit line at the time of the reading operation. The reading circuit controls the reading current on the basis of a voltage applied to the second terminal through the second bit line. | 09-23-2010 |
| 20100246244 | MAGNETORESISTIVE EFFECT MEMORY - A magnetoresistive effect memory of an aspect of the present invention including a magnetoresistive effect element including a first magnetic layer having an invariable magnetization direction, a second magnetic layer having a variable magnetization direction, and an interlayer provided between the first magnetic layer and the second magnetic layer, and a reading circuit which passes a pulse-shaped read current through the magnetoresistive effect element to read data stored in the magnetoresistive effect element, wherein the pulse width of the read current is shorter than a period from an initial state to a cooperative coherent precession movement of magnetizations included in the second magnetic layer. | 09-30-2010 |
| 20100246245 | SPIN-TORQUE MEMORY WITH UNIDIRECTIONAL WRITE SCHEME - Spin torque magnetic memory elements that have a pinned layer, two free layers, and a current-blocking insulating layer proximate to at least one of the free layers. The resistive state (e.g., low resistance or high resistance) of the memory elements is altered by passing electric current through the element in one direction. In other words, to change from a low resistance to a high resistance, the direction of electric current is the same as to change from a high resistance to a low resistance. The elements have a unidirectional write scheme. | 09-30-2010 |
| 20100254181 | Raising Programming Currents of Magnetic Tunnel Junctions Using Word Line Overdrive and High-k Metal Gate - A method of operating magneto-resistive random access memory (MRAM) cells includes providing an MRAM cell, which includes a magnetic tunneling junction (MTJ) device; and a selector comprising a source-drain path serially coupled to the MTJ device. The method further includes applying an overdrive voltage to a gate of the selector to turn on the selector. | 10-07-2010 |
| 20100254182 | MAGNETIC STORAGE DEVICE - A magnetic storage device which enables stable operation at the time of recording information into MRAM and the stable retention of recorded information. The die of the magnetic storage device has a substrate, first and second wirings, a magnetic storage element and a first magnetic shielding structure. The first magnetic shielding structure is formed to cover the magnetic storage element in a plan view. Second and third magnetic shielding structures sandwich the die in a thickness direction. A lead frame member has the die mounted thereon and contains a ferromagnetic material. The lead frame member overlaps with only part of the die in a plan view. | 10-07-2010 |
| 20100254183 | MAGNETORESISTANCE EFFECT ELEMENT AND MAGETIC RANDOM ACCESS MEMORY - A magnetoresistance effect element has: a first magnetization fixed layer whose magnetization direction is fixed; a first magnetization free layer whose magnetization direction is variable; a first nonmagnetic layer sandwiched between the first magnetization fixed layer and the first magnetization free layer; a second magnetization fixed layer whose magnetization direction is fixed; a second magnetization free layer whose magnetization direction is variable; and a second nonmagnetic layer sandwiched between the second magnetization fixed layer and the second magnetization free layer. The first magnetization fixed layer and the first magnetization free layer have perpendicular magnetic anisotropy, while the second magnetization fixed layer and the second magnetization free layer have in-plane magnetic anisotropy. The first magnetization free layer and the second magnetization free layer are magnetically coupled to each other. In a plane parallel to each layer, center of the second magnetization free layer is displaced from center of the first magnetization free layer. | 10-07-2010 |
| 20100265759 | Raising Programming Current of Magnetic Tunnel Junctions by Applying P-Sub Bias and Adjusting Threshold Voltage - A method of operating magneto-resistive random access memory (MRAM) cells includes providing an MRAM cell, which includes a magnetic tunneling junction (MTJ) device and a word line selector having a source-drain path serially coupled to the MTJ device. A negative substrate bias voltage is connected to a body of the word line selector to increase the drive current of the word line selector. The threshold voltage of the word line selector is also reduced. | 10-21-2010 |
| 20100265760 | NONVOLATILE LATCH CIRCUIT AND LOGIC CIRCUIT USING THE SAME - A nonvolatile latch circuit includes: a latch circuit; a first magnetoresistance element and a second magnetoresistance element; and a current supply portion. The latch circuit temporarily holds data. Each of the first magnetoresistance element and the second magnetoresistance element includes a first magnetic layer and a second magnetic layer that are stacked with an insulating film sandwiched therebetween. The current supply portion complementarily changes magnetization states of the first magnetoresistance element and the second magnetoresistance element based on a state of the latch circuit. The first magnetic layer of the first magnetoresistance element and the first magnetic layer of the second magnetoresistance element are series-connected to each other in. The latch circuit has a function that brings data corresponding to the magnetization states to data held by the latch circuit. | 10-21-2010 |
| 20100271866 | NONVOLATILE LATCH CIRCUIT - A nonvolatile latch circuit includes: first and second inverters cross-coupled to hold 1-bit data; first and second magnetoresistive elements each having first to third terminals; and a current supply circuitry configured to supply a magnetization reversal current for changing the magnetization states of the first and second maqnetoresistive elements in response to the 1-bit data. The power terminal of the first inverter is connected to the first terminal of the first magnetoresistive element and the power terminal of the second inverter is connected to the first terminal of the second magnetoresistive element. The current supply circuitry is configured to supply the magnetization reversal current to the second terminals of the first and second magnetoresistive elements. The third terminal of the first magnetoresistive element is electrically connected to the third terminal of the second magnetoresistive element. | 10-28-2010 |
| 20100277971 | METHOD FOR REDUCING CURRENT DENSITY IN A MAGNETOELECTRONIC DEVICE - A method for reducing spin-torque current density needed to switch a magnetoelectronic device ( | 11-04-2010 |
| 20100277972 | SEMICONDUCTOR MEMORY DEVICE INCLUDING A PLURALITY OF MEMORY CELL ARRAYS - First and second memory cell arrays are adjacent in a first direction. First and second areas are positioned adjacent to one and the other side of the first memory array in a second direction. Third and fourth areas are positioned adjacent to one and the other side of the second memory array in a second direction. A sense amplifier is arranged in the first area and a current sink is arranged in the fourth area. The sense amplifier compares a read current which flows into the current sink via a memory cell in the first memory cell array and the second area from the sense amplifier with a reference current which flows into the current sink via the third area and a reference memory cell in the second memory cell array from the sense amplifier. | 11-04-2010 |
| 20100290270 | MAGNETIC MEMORY ELEMENT, MAGNETIC MEMORY HAVING SAID MAGNETIC MEMORY ELEMENT, AND METHOD FOR DRIVING MAGNETIC MEMORY - An inadvertent write can be prevented when a read is performed. The duration of the write current pulse for writing information in the magnetic memory layer is longer than the duration of the read current pulse for reading the information from the magnetic memory layer. | 11-18-2010 |
| 20100302838 | Read disturb-free SMT reference cell scheme - We describe a reference cell structure for determining data storing cell resistances in an SMT (spin moment transfer) MTJ (magnetic tunneling junction) MRAM array by comparing data cell currents with those of the reference cell. Since the reference cell also utilizes spin moment transfer (SMT) magnetic tunneling junction (MTJ) cells, there would ordinarily be the danger that the act of reading the reference cell could change its magnetization orientations and be a source of error for subsequent comparisons. Therefore the present invention describes a new circuit arrangement for the reference cell that directs read currents through two SMT MTJ cells in opposite directions so that the transfer of spin moments cannot affect the relative magnetization directions of the cells. | 12-02-2010 |
| 20100302839 | STATIS SOURCE PLANE IN STRAM - A memory array includes a plurality of magnetic tunnel junction cells arranged in a 2 by 2 array. Each magnetic tunnel junction cell is electrically coupled between a bit line and a source line and each magnetic tunnel junction cell electrically coupled to a transistor. Each magnetic tunnel junction cell is configured to switch between a high resistance state and a low resistance state by passing a write current passing though the magnetic tunnel junction cell. A first word line is electrically coupled to a gate of first set of two of the transistors and a second word line is electrically coupled to a gate of a second set of two of the transistors. The source line is a common source line for the plurality of magnetic tunnel junctions. | 12-02-2010 |
| 20100309712 | MAGNETIC RANDOM ACCESS MEMORY - An MRAM has: a memory cell including a first magnetoresistance element; and a reference cell including a second magnetoresistance element. The first magnetoresistance element has a first magnetization free layer, a first magnetization fixed layer, a second magnetization free layer and a first nonmagnetic layer sandwiched between the first magnetization fixed layer and the second magnetization free layer. The first magnetization free layer has perpendicular magnetic anisotropy, and the first magnetization fixed layer and the second magnetization free layer has in-plane magnetic anisotropy. The first magnetization free layer has: first and second magnetization fixed regions whose magnetization directions are fixed; and a magnetization free region whose magnetization direction is reversible and connected to the first and second magnetization fixed regions. The magnetization free region and the second magnetization free layer are magnetically coupled to each other. In a plane parallel to each layer, center of the second magnetization free layer is displaced in a first direction from center of the magnetization free region. Whereas, the second magnetoresistance element has: a third magnetization free layer whose magnetization easy axis is parallel to a second direction; a second magnetization fixed layer whose magnetization direction is fixed in a third direction perpendicular to the second direction; and a second nonmagnetic layer sandwiched between the second magnetization fixed layer and the third magnetization free layer. The second magnetization fixed layer and the third magnetization free layer have in-plane magnetic anisotropy. | 12-09-2010 |
| 20100309713 | MAGNETIC RANDOM ACCESS MEMORY - An MRAM has: a memory cell including a first magnetoresistance element; and a reference cell including a second magnetoresistance element. The first magnetoresistance element has a first magnetization fixed layer, a first magnetization free layer, a first nonmagnetic layer sandwiched between the first magnetization fixed layer and the first magnetization free layer, a second magnetization fixed layer, a second magnetization free layer and a second nonmagnetic layer sandwiched between the second magnetization fixed layer and the second magnetization free layer. The first magnetization fixed layer and the first magnetization free layer have perpendicular magnetic anisotropy, and the second magnetization fixed layer and the second magnetization free layer have in-plane magnetic anisotropy. The first magnetization free layer and the second magnetization free layer are magnetically coupled to each other. Center of the second magnetization free layer is displaced in a first direction from center of the first magnetization free layer in a plane parallel to each layer. Whereas, the second magnetoresistance element has: a third magnetization free layer whose magnetization easy axis is parallel to a second direction; a third magnetization fixed layer whose magnetization direction is fixed in a third direction perpendicular to the second direction; and a third nonmagnetic layer sandwiched between the third magnetization fixed layer and the third magnetization free layer. The third magnetization fixed layer and the third magnetization free layer have in-plane magnetic anisotropy. | 12-09-2010 |
| 20100315863 | Magnetic Tunnel Junction Device and Fabrication - A magnetic tunneling junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, an apparatus is disclosed that includes an MTJ device. The MTJ device includes a free layer and a spin torque enhancing layer. The spin torque enhancing layer includes a nano-oxide layer. | 12-16-2010 |
| 20100315864 | MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY - A magnetoresistive element includes: a magnetization free layer having a first plane and a second plane located on the opposite side from the first plane, and having a variable magnetization direction; a magnetization pinned layer provided on the first plane side of the magnetization free layer, and having a pinned magnetization direction; a first tunnel barrier layer provided between the magnetization free layer and the magnetization pinned layer; a second tunnel barrier layer provided on the second plane of the magnetization free layer; and a non-magnetic layer provided on a plane on the opposite side of the second tunnel barrier layer from the magnetization free layer. The magnetization direction of the magnetization free layer is variable by applying current between the magnetization pinned layer and the non-magnetic layer, and a resistance ratio between the first tunnel barrier layer and the second tunnel barrier layer is in a range of 1:0.25 to 1:4. | 12-16-2010 |
| 20100315865 | DIODE ASSISTED SWITCHING SPIN-TRANSFER TORQUE MEMORY UNIT - A memory array includes a cross-point array of bit and source lines. A memory is disposed at cross-points of the cross-point array. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. A transistor is electrically between the magnetic tunnel junction data cell and the bit line or source line and a diode is in thermal or electrical contact with the magnetic tunnel junction data cell to assist in resistance state switching. | 12-16-2010 |
| 20100321985 | Boosted gate voltage programming for spin-torque MRAM array - A gate voltage boosting circuit provides a voltage boost to a gate of a select switching MOS transistor of a spin-torque MRAM cell to prevent a programming current reduction through an MTJ device of the spin-torque MRAM cell. A spin-torque MRAM cell array is composed of spin-torque MRAM cells that include a MTJ element and a select switching device. A local word line is associated with one row of the plurality of spin-torque MRAM cells and is connected to a gate terminal of the select switching devices of the row of MRAM cells to control activation and deactivation. One gate voltage boosting circuit is placed between an associated global word line and an associated local word line. The gate voltage boosting circuits boost a voltage of a gate of the selected switching device during writing of a logical “1” to the MTJ element of a selected spin-torque MRAM cell. | 12-23-2010 |
| 20100321986 | MULTI-BIT STRAM MEMORY CELLS - A multi-bit spin torque magnetic element that has a ferromagnetic pinned layer having a pinned magnetization orientation, a non-magnetic layer, and a ferromagnetic free layer having a magnetization orientation switchable among at least four directions, the at least four directions being defined by a physical shape of the free layer. The magnetic element has at least four distinct resistance states. Magnetic elements with at least eight magnetization directions are also provided. | 12-23-2010 |
| 20100328992 | MEMORY - A memory includes: a plurality of memory devices, each including a tunnel magnetic resistance effect device containing a magnetization free layer in which a direction of magnetization can be reversed, a tunnel barrier layer including an insulating material, and a magnetization fixed layer provided with respect to the magnetization free layer via the tunnel barrier layer with a fixed direction of magnetization; a random access memory area in which information is recorded using the direction of magnetization of the magnetization free layer of the memory device; and a read only memory area in which information is recorded depending on whether there is breakdown of the tunnel barrier layer of the memory device or not. | 12-30-2010 |
| 20100328993 | RECORDING METHOD OF NONVOLATILE MEMORY AND NONVOLATILE MEMORY - A recording method of a nonvolatile memory including a recording circuit that electrically performs recording of information for an information memory device having a resistance change connected to a power supply for information recording, includes the steps of: recording information in a low-resistance state by the recording circuit under a condition that an output impedance of the recording circuit for the information memory device is larger than a resistance value in the low-resistance state of the information memory device; and recording information in a high-resistance state by the recording circuit under a condition that an output impedance of the recording circuit for the information memory device is smaller than a resistance value in the high-resistance state of the information memory device. | 12-30-2010 |
| 20110002160 | METHOD OF OPERATING A MAGNETORESISTIVE RAM - A magnetoresistive random access memory (RAM) may include a plurality of variable resistance devices, a plurality of read bitlines electrically connected to respective variable resistance devices, and a plurality of write bitlines alternating with the read bitlines. The magnetoresistive RAM may be configured to apply a first write current through a first write bitline adjacent to a first variable resistance device when writing a first data to the first variable resistance device, and apply a first inhibition current through a second write bitline adjacent to a second variable resistance device, the second variable resistance device being adjacent to the first write bitline, and between the first write bitline and the second write bitline, and the first write current and the first inhibition current flowing in a same direction. | 01-06-2011 |
| 20110007558 | MODULAR MAGNETORESISTIVE MEMORY - A magnetoresistive memory element is provided with a read module having a first pinned layer with a magnetoresistance that is readable by a read current received from an external circuit. A write module has a nanocontact that receives a write current from the external circuit and, in turn, imparts a spin torque to a free layer that functions as a shared storage layer for both the read module and the write module. | 01-13-2011 |
| 20110019465 | MAGNETIC TUNNEL JUNCTION WITH COMPENSATION ELEMENT - A magnetic tunnel junction having a compensation element is disclosed. The magnetic tunnel junction includes a synthetic antiferromagnetic reference element, and a synthetic antiferromagnetic compensation element having an opposite magnetization moment to a magnetization moment of the synthetic antiferromagnetic reference element. A free magnetic layer is between the synthetic antiferromagnetic reference element and the synthetic antiferromagnetic compensation element, and an electrically insulating and non-magnetic tunneling barrier layer separates the free magnetic layer from the synthetic antiferromagnetic reference element. The free magnetic layer includes Co | 01-27-2011 |
| 20110019466 | Stuck-At Defect Condition Repair for a Non-Volatile Memory Cell - A method and apparatus for repairing a stuck-at defect condition in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a resistive sense element has a magnetic tunneling junction (MTJ) and a repair plane located adjacent to the resistive sense element. The repair plane injects a magnetic field in the MTJ to repair a stuck-at defect condition. | 01-27-2011 |
| 20110026316 | MAGNETORESISTIVE MEMORY ELEMENTS WITH SEPARATE READ AND WRITE CURRENT PATHS - A magnetoresistive memory element has a free layer, and a write current path aligned with a free layer plane. The memory element has a pinned layer with a magnetization direction aligned with that of the free layer. A barrier layer is disposed between the free layer and the pinned layer. The free, barrier and pinned layers together form a layer stack that has a read current path that extends through the layer stack and that is not aligned with the write current path in the free layer. | 02-03-2011 |
| 20110026317 | SPIN-TRANSFER TORQUE MEMORY SELF-REFERENCE READ AND WRITE ASSIST METHODS - A spin-transfer torque memory apparatus and self-reference read and write assist schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage. A magnetic field is applied through the free magnetic layer the forming a magnetic field modified magnetic tunnel junction data cell. Then a second read current is applied thorough the magnetic field modified magnetic tunnel junction data cell forming a second bit line read voltage and compared with the first bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state. Methods of applying a destabilizing magnetic field to the MTJ and then writing the desired resistance state are also disclosed. | 02-03-2011 |
| 20110038198 | ELECTRONIC DEVICES BASED ON CURRENT INDUCED MAGNETIZATION DYNAMICS IN SINGLE MAGNETIC LAYERS - The present invention generally relates to magnetic devices used in memory and information processing applications, such as giant magneto-resistance (GMR) devices and tunneling magneto-resistance devices. More specifically, the present invention is directed to a single ferromagnetic layer device in which an electrical current is used to control and change magnetic configurations as well as induce high frequency magnetization dynamics. The magnetic layer includes full spin-polarized magnetic material, which may also have non-uniform magnetization. The non-uniform magnetization is achieved by varying the shape or roughness of the magnetic material. The present invention may be used in memory cells, as well as high frequency electronics, such as compact microwave sources, detectors, mixers and phase shifters. | 02-17-2011 |
| 20110044096 | Magnetic Tunnel Junction Structure - In a particular illustrative embodiment, a magnetic tunnel junction (MTJ) structure is disclosed that includes a bottom electrode, a fixed layer, a tunnel barrier layer, a free layer, and a top electrode. The bottom electrode is coupled to a bottom surface of the fixed layer and extends along at least one sidewall of the fixed layer. | 02-24-2011 |
| 20110051502 | Flexible Word-Line Pulsing For STT-MRAM - A method for generating a variable pulse width signal on an integrated circuit (IC) chip, includes receiving a first clock signal on the IC chip and receiving a second clock signal on the IC chip having a variable delay relative to the first clock signal. A signal having a rising edge triggered by a rising edge of the first clock signal and a falling edge triggered by a rising edge of the second clock signal is output. The output signal is provided to circuitry on the chip, such as a magnetoresistive junction (MTJ) cell of a spin torque transfer magnetic random access memory (STT-MRAM). | 03-03-2011 |
| 20110051503 | Magnetic Devices and Structures - Magnetic devices, magnetoresistive structures, and methods and techniques associated with the magnetic devices and magnetoresistive structures are presented. For example, a magnetic device is presented. The magnetic device includes a ferromagnet, an antiferromagnet coupled to the ferromagnet, and a nonmagnetic metal proximate to the ferromagnet. The antiferromagnet provides uniaxial anisotropy to the magnetic device. A resistance of the nonmagnetic metal is dependent upon a direction of a magnetic moment of the ferromagnet. | 03-03-2011 |
| 20110058408 | MEMORY CELL ARRANGEMENTS; MEMORY CELL READER; METHOD FOR DETERMINING A MEMORY CELL STORAGE STATE - A memory cell arrangement is provided including a magnetoresistive memory cell; and a frequency determiner configured to determine a spin precession frequency provided by the magnetoresistive memory cell; and a storage state determiner configured to determine the magnetoresistive memory cell storage state of the magnetoresistive memory cell based on the determined spin precession frequency. | 03-10-2011 |
| 20110058409 | MRAM DIODE ARRAY AND ACCESS METHOD - A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode. | 03-10-2011 |
| 20110063897 | DIFFERENTIAL READ AND WRITE ARCHITECTURE - A memory cell includes a pair of magnetic tunnel junctions and a pair of associated transistors. The magnetic tunnel junctions of the pair are differentially disposed so that in response to the applied voltages, when one them stores a logic one, the other one stores a logic zero. Accordingly, the read operation margin is increased by a factor of two. The true and complementary bit lines of the differential memory cell are coupled to a sense amplifier. Consequently, the need for using reference bit lines is eliminated. | 03-17-2011 |
| 20110063898 | METHOD AND SYSTEM FOR PROVIDING A HIERARCHICAL DATA PATH FOR SPIN TRANSFER TORQUE RANDOM ACCESS MEMORY - A method and system for providing a magnetic memory are described. The method and system include providing memory array tiles (MATs), intermediate circuitry, global bit lines, global word lines, and global circuitry. Each MAT includes magnetic storage cells, bit lines, and word lines. Each of the magnetic storage cells includes at least one magnetic element and at least one selection device. The magnetic element(s) are programmable using write current(s) driven through the magnetic element(s). The bit lines and the word lines correspond to the magnetic storage cells. The intermediate circuitry controls read and write operations within the MATs. Each global bit line corresponds to a first portion of the plurality of MATs. Each global word line corresponds to a second portion of the MATs. The global circuitry selects and drives part of the global bit lines and part of the global word lines for the read and write operations. | 03-17-2011 |
| 20110063899 | MAGNETIC MEMORY ELEMENT, METHOD OF DRIVING SAME, AND NONVOLATILE STORAGE DEVICE - In order to obtain a memory cell of size 4 F | 03-17-2011 |
| 20110063900 | MAGNETIC MEMORY - According to one embodiment, a magnetic memory includes a magnetoresistive element includes a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is variable and a nonmagnetic layer disposed between the fixed layer and the recording layer. A direction of a read current is set to a first direction in a case where an expression of MR ratio ≧|I | 03-17-2011 |
| 20110063901 | STATIC SOURCE PLANE IN STRAM - A memory array includes a plurality of magnetic tunnel junction cells arranged in a 2 by 2 array. Each magnetic tunnel junction cell is electrically coupled between a bit line and a source line and each magnetic tunnel junction cell electrically coupled to a transistor. Each magnetic tunnel junction cell is configured to switch between a high resistance state and a low resistance state by passing a write current passing though the magnetic tunnel junction cell. A first word line is electrically coupled to a gate of first set of two of the transistors and a second word line is electrically coupled to a gate of a second set of two of the transistors. The source line is a common source line for the plurality of magnetic tunnel junctions. | 03-17-2011 |
| 20110069534 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes bit line pairs extending in a column direction, each of the bit line pairs includes a first bit line and a second bit line, and memory cell groups connected to the bit line pairs, respectively, and each includes memory cells. Each of the memory cells comprises a first transistor, a second transistor and a resistive memory element. One end of the resistive memory element is connected to the first bit line. A drain region of the first transistor and a drain region of the second transistor are connected to each other and connected to the other end of the resistive memory element. A source region of the first transistor and a source region of the second transistor are connected to the second bit line. | 03-24-2011 |
| 20110069535 | MAGNETIC RANDOM ACCESS MEMORY WITH DUAL SPIN TORQUE REFERENCE LAYERS - A magnetic data storage cell, applicable to spin-torque random access memory (ST-RAM), is disclosed. A magnetic cell includes first and second fixed magnetic layers and a free magnetic layer positioned between the fixed magnetic layers. The magnetic cell also includes terminals configured for providing a spin-polarized current through the magnetic layers. The first fixed magnetic layer has a magnetization direction that is substantially parallel to the easy axis of the free magnetic layer, and the second fixed magnetic layer has a magnetization direction that is substantially orthogonal to the easy axis of the free magnetic layer. The dual fixed magnetic layers provide enhanced spin torque in writing to the free magnetic layer, thereby reducing the required current and reducing the feature size of magnetic data storage cells, and increasing the data storage density of magnetic spin torque data storage. | 03-24-2011 |
| 20110069536 | RECONFIGURABLE MAGNETIC LOGIC DEVICE USING SPIN TORQUE - Spin torque magnetic logic devices that function as memory devices and that can be reconfigured or reprogrammed as desired. In some embodiments, the logic device is a single magnetic element, having a pinned layer, a free layer, and a barrier layer therebetween, or in other embodiments, the logic device has two magnetic elements in series. Two input currents can be applied through the element to configure or program the element. In use, logic input data, such as current, is passed through the programmed element, defining the resistance across the element and the resulting logic output. The magnetic logic device can be used for an all-function-in-one magnetic chip. | 03-24-2011 |
| 20110069537 | Magnetic Storage Element Responsive to Spin Polarized Current - The present invention relates to a memory cell including a first reference layer having a first magnetization with a first magnetization direction and a second reference layer having a second magnetization with a second magnetization direction substantially perpendicular to the first magnetization direction. A storage layer is disposed between the first reference layer and second reference layer and has a third magnetization direction about 45° from the first magnetization direction and about 135° from the second magnetization direction when the memory cell is in a first data state, and a fourth magnetization direction opposite the third magnetization direction when the memory cell is in a second data state. | 03-24-2011 |
| 20110075471 | Enhancing Read and Write Sense Margins in a Resistive Sense Element - An apparatus and method for enhancing read and write sense margin in a memory cell having a resistive sense element (RSE), such as but not limited to a resistive random access memory (RRAM) element or a spin-torque transfer random access memory (STRAM) element. The RSE has a hard programming direction and an easy programming direction. A write current is applied in either the hard programming direction or the easy programming direction to set the RSE to a selected programmed state. A read circuit subsequently passes a read sense current through the cell in the hard programming direction to sense the selected programmed state of the cell. | 03-31-2011 |
| 20110075472 | MAGNETORESISTIVE DEVICE HAVING SPECULAR SIDEWALL LAYERS - A multilayered magnetoresistive device includes a specular layer positioned on at least one sidewall and a copper layer positioned between the specular layer and the sidewall. | 03-31-2011 |
| 20110080773 | CIRCUIT FOR GENERATING ADJUSTABLE TIMING SIGNALS FOR SENSING A SELF-REFERENCED MRAM CELL - Controllable readout circuit for performing a self-referenced read operation on a memory device comprising a plurality of magnetic random access memory (MRAM) cells comprising a selecting device for selecting one of the MRAM cells, and a sense circuit for sourcing a sense current to measure the first and second resistance value; the sense circuit comprising a sample and hold circuit for performing said storing said first resistance value, and a differential amplifier circuit for performing said comparing the second resistance value to the stored first resistance value; wherein the controllable readout circuit further comprises a control circuit adapted to provide a pulse-shaped timing signal with a pulse duration controlling the duration of the first read cycle and the second read cycle. The controllable readout circuit allows for controlling the duration of the first and second read cycles after completion of the MRAM cell and readout circuit fabrication. | 04-07-2011 |
| 20110085373 | SPIN-TRANSFER TORQUE MEMORY SELF-REFERENCE READ METHOD - Self-reference reading a magnetic tunnel junction data cell methods are disclosed. An illustrative method includes applying a read voltage across a magnetic tunnel junction data cell and forming a read current. The magnetic tunnel junction data cell has a first resistance state. The read voltage is sufficient to switch the magnetic tunnel junction data cell resistance. The method includes detecting the read current and determining if the read current remains constant during the applying step. If the read current remains constant during the applying step, then the first resistance state of the magnetic tunnel junction data cell is the resistance state that the read voltage was sufficient to switch the magnetic tunnel junction data cell to. | 04-14-2011 |
| 20110085374 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device that enables high-speed data read and reduces the area of a drive circuit for activating a word line. By signal transmission through a common word line having a low resistance and coupled at a plurality of points to a word line, it is possible to read data at high speed. Further, since the common word line is provided common to a plurality of memory blocks, a word line driver can be provided common to the memory blocks. Further, by disposing a latch circuit, corresponding to a sub-digit line, for holding the active state of the common word line, it is possible to transmit a row selection signal during data write through the common word line and thereby reduce a metal wiring layer. | 04-14-2011 |
| 20110090732 | Magnetic Tunnel Junction Cell Adapted to Store Multiple Digital Values - A particular magnetic tunnel junction (MTJ) cell includes a side wall defining a first magnetic domain adapted to store a first digital value. The MTJ cell also includes a bottom wall coupled to the side wall and defining a second magnetic domain adapted to store a second digital value. | 04-21-2011 |
| 20110090733 | MEMORY WITH SEPARATE READ AND WRITE PATHS - A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer separated from a first pinned magnetic layer by a first non-magnetic electrically conducting layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer separated from a second pinned magnetic layer by an oxide barrier layer. A write current passes through the giant magnetoresistance cell to switche the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell. | 04-21-2011 |
| 20110096591 | INFORMATION STORAGE ELEMENT AND METHOD FOR DRIVING THE SAME - Disclosed herein is an information storage element including: a word electrode includes a first magnetic material that is continuously formed and is electrically conductive; a non-magnetic film formed in contact with the first magnetic material of the word electrode; a second magnetic material connected to the first magnetic material via the non-magnetic film; a magnetization setting mechanism disposed near at least one end part of both end parts of the word electrode and sets direction of magnetization of the end part of the word electrode; a coercivity decreasing mechanism decreases coercivity of the second magnetic material; and an electrically-conductive bit electrode so formed as to serve also as the second magnetic material or be formed in parallel to the second magnetic material, the bit electrode being so continuously formed as to intersect with the word electrode. | 04-28-2011 |
| 20110096592 | THIN FILM MAGNETIC MEMORY DEVICE WRITING DATA WITH BIDIRECTIONAL CURRENT - An end of a selected bit line in a selected column is electrically coupled to an end of a corresponding current return line by one of first and second write column select gates, which are selectively turned on in response to results of column selection. A data write circuit sets the other end of the selected bit line and the other end of the current return line to one and the other of a power supply voltage and a ground voltage in accordance with a level of write data via one of first and second data buses and an inverted data bus, respectively. | 04-28-2011 |
| 20110096593 | LOW CURRENT SWITCHING MAGNETIC TUNNEL JUNCTION DESIGN FOR MAGNETIC MEMORY USING DOMAIN WALL MOTION - A multi-state low-current-switching magnetic memory element (magnetic memory element) comprising a free layer, two stacks, and a magnetic tunneling junction is disclosed. The stacks and magnetic tunneling junction are disposed upon surfaces of the free layer, with the magnetic tunneling junction located between the stacks. The stacks pin magnetic domains within the free layer, creating a free layer domain wall. A current passed from stack to stack pushes the domain wall, repositioning the domain wall within the free layer. The position of the domain wall relative to the magnetic tunnel junction corresponds to a unique resistance value, and passing current from a stack to the magnetic tunnel junction reads the magnetic memory element's resistance. Thus, unique memory states may be achieved by moving the domain wall. | 04-28-2011 |
| 20110103138 | SINGLE-CHARGE TUNNELING DEVICE - A single-electron transistor ( | 05-05-2011 |
| 20110110147 | COMPOUND CELL SPIN-TORQUE MAGNETIC RANDOM ACCESS MEMORY - A compound magnetic data storage cell, applicable to spin-torque random access memory (ST-RAM), is disclosed. A magnetic data storage cell includes a magnetic storage element and two terminals communicatively connected to the magnetic storage element. The magnetic storage element is configured to yield any of at least three distinct magnetoresistance output levels, corresponding to stable magnetic configurations, in response to spin-momentum transfer inputs via the terminals. | 05-12-2011 |
| 20110116303 | Magnetic Tunnel Junction and Memristor Apparatus - A magnetic memory device includes a magnetic tunnel junction having a free magnetic layer having a magnetization orientation that is switchable between a high resistance state magnetization orientation and a low resistance state magnetization orientation and a memristor solid state element electrically coupled to the magnetic tunnel junction. The memristor has a device response that is an integrated voltage versus an integrated current. | 05-19-2011 |
| 20110116304 | SPIN CURRENT GENERATOR FOR STT-MRAM OR OTHER SPINTRONICS APPLICATIONS - Spin current generators and systems and methods for employing spin current generators. A spin current generator may be configured to generate a spin current polarized in one direction, or a spin current selectively polarized in two directions. The spin current generator may by employed in spintronics applications, wherein a spin current is desired. | 05-19-2011 |
| 20110116305 | MAGNETORESISTIVE ELEMENT - A magnetoresistive element includes a first magnetic layer which includes a first surface and a second surface and has a first standard electrode potential, a second magnetic layer, a barrier layer which is provided between the second magnetic layer and the first surface of the first magnetic layer, and a nonmagnetic cap layer which contacts the second surface of the first magnetic layer and is formed from an alloy of a first metal material and a second metal material, the first metal material having a second standard electrode potential lower than the first standard electrode potential, the second metal material having a third standard electrode potential higher than the first standard electrode potential. | 05-19-2011 |
| 20110116306 | MAGNETIC RANDOM ACCESS MEMORY AND INITIALIZING METHOD FOR THE SAME - A domain wall motion type MRAM has: a magnetic recording layer | 05-19-2011 |
| 20110128778 | Predictive Thermal Preconditioning and Timing Control for Non-Volatile Memory Cells - A method and apparatus for using thermal preconditioning to write data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a logical state is written to an unconditioned non-volatile first memory cell associated with a first block address. Thermal preconditioning is concurrently applied to a non-volatile second memory cell associated with a second block address selected in response to the first block address. | 06-02-2011 |
| 20110141796 | Magnetic Tunnel Junction Device and Fabrication - A magnetic tunneling junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, an apparatus is disclosed that includes an MTJ device. The MTJ device includes a barrier layer, a free layer, and a magnesium (Mg) capping layer. The free layer is positioned between the barrier layer and the magnesium (Mg) capping layer. | 06-16-2011 |
| 20110141797 | CREATING SPIN-TRANSFER TORQUE IN OSCILLATORS AND MEMORIES - A structure includes an electrically conductive material possessing spontaneous magnetization (“free magnet”) not in contact with an electrically resistive material possessing spontaneous magnetization (“pinned magnet”), and a spacer having free electrons to transfer spin between the electrically resistive material and the electrically conductive material. During operation, an existing direction of magnetization of the free magnet is changed to a new direction of magnetization, by a spin current generated by transfer of heat between at least the spacer and the pinned magnet. Thereafter, the new direction of magnetization of the free magnet is sensed. Many such structures are fabricated to have an easy axis of magnetic anisotropy in the free magnet, to implement memories that write data by transferring heat. Several such structures are fabricated to have an easy plane of magnetic anisotropy in the free magnet, to implement oscillators that generate an oscillating signal, on transfer of heat. | 06-16-2011 |
| 20110149640 | MAGNETIC STORAGE DEVICE - A magnetic storage device includes a plurality of MRAM memory cells connected to a data transfer line, a clamp transistor connected between the data transfer line and a reading signal line and configured to fixedly hold the potential of the data transfer line, and a reading circuit which is connected to the reading signal line and which reads the storage information of the memory cell. The reading circuit includes a hold switch connected between the reading signal line and a reading node N and configured to hold the potential of the node N, a capacitor connected between the node N and a ground end, a precharging switch connected between the node N and a power source and configured to charge the capacitor, and an inverter to which the potential of the node N is input to generate a digital signal. | 06-23-2011 |
| 20110149641 | Static Magnetic Field Assisted Resistive Sense Element - Apparatus and associated method for writing data to a non-volatile memory cell, such as spin-torque transfer random access memory (STRAM). In accordance with some embodiments, a resistive sense element (RSE) has a heat assist region, magnetic tunneling junction (MTJ), and pinned region. When a first logical state is written to the MTJ with a spin polarized current, the pinned and heat assist regions each have a substantially zero net magnetic moment. When a second logical state is written to the MTJ with a static magnetic field, the pinned region has a substantially zero net magnetic moment and the heat assist region has a non-zero net magnetic moment. | 06-23-2011 |
| 20110149642 | Static Magnetic Field Assisted Resistive Sense Element - Apparatus and associated method for writing data to a non-volatile memory cell, such as spin-torque transfer random access memory (STRAM). In accordance with some embodiments, a resistive sense element (RSE) has a heat assist region, magnetic tunneling junction (MTJ), and pinned region. When a first logical state is written to the MTJ with a spin polarized current, the pinned and heat assist regions each have a substantially zero net magnetic moment. When a second logical state is written to the MTJ with a static magnetic field, the pinned region has a substantially zero net magnetic moment and the heat assist region has a non-zero net magnetic moment. | 06-23-2011 |
| 20110157966 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device comprises a memory cell configured to store or output data in a magneto-resistance device in response to a write current applied to a bit line and a source line. A voltage detector is configured to sense potentials loaded in the bit line and the source line. A write current controller configured to control activation of a write control signal in response to an output of the voltage detector, and a write driver configured to control amounts of write current applied to the memory cell according to the activation of the write control signal. | 06-30-2011 |
| 20110157967 | MAGNETIC RANDOM ACCESS MEMORY, METHOD OF INITIALIZING MAGNETIC RANDOM ACCESS MEMORY AND METHOD OF WRITING MAGNETIC RANDOM ACCESS MEMORY - A magnetic memory includes a magnetization recording layer, a first terminal, a second terminal, a magnetization pinned layer and a non-magnetic layer. The magnetization recording layer has a vertical magnetic anisotropy and includes a ferromagnetic layer. The first terminal is connected to one end of a first region in the magnetization recording layer. The second terminal is connected to the other end of the first region. The non-magnetic layer is arranged on the first region. The magnetization pinned layer is arranged on the non-magnetic layer and is located on the side opposite to the first region. The magnetization recording layer includes: a first extension portion located outside the first terminal in the magnetization recording layer; and a property changing structure that is arranged in the first extension portion and substantially changes a magnetization switching property of the magnetization recording layer. | 06-30-2011 |
| 20110164448 | Tunneling magnetoresistance (TMR) device, its manufacture method, magnetic head and magnetic memory using TMR device - A barrier layer is disposed over a pinned layer made of ferromagnetic material having a fixed magnetization direction, the barrier layer having a thickness allowing electrons to transmit therethrough by a tunneling phenomenon. A first free layer is disposed over the barrier layer, the first free layer being made of amorphous or fine crystalline soft magnetic material which changes a magnetization direction under an external magnetic field. A second free layer is disposed over the first free layer, the second free layer being made of crystalline soft magnetic material which changes a magnetization direction under an external magnetic field and being exchange-coupled to the first free layer. A tunneling magnetoresistance device is provided which has good magnetic characteristics and can suppress a tunnel resistance change rate from being lowered. | 07-07-2011 |
| 20110170338 | System and Method to Control A Direction of a Current Applied to a Magnetic Tunnel Junction - A system and method to control a direction of a current applied to a magnetic tunnel junction is disclosed. In a particular embodiment, an apparatus comprises a magnetic tunnel junction (MTJ) storage element and a sense amplifier. The sense amplifier is coupled to a first path and to a second path. The first path includes a first current direction selecting transistor and the second path includes a second current direction selecting transistor. The first path is coupled to a bit line of the MTJ storage element and the second path is coupled to a source line of the MTJ storage element. | 07-14-2011 |
| 20110170339 | MAGNETORESISTIVE DEVICE - A method of operating a magnetoresistive device is described. The device comprises a ferromagnetic region configured to exhibit magnetic anisotropy and to allow magnetisation thereof to be switched between at least first and second orientations and a gate capacitively coupled to the ferromagnetic region. The method comprises applying an electric field pulse to the ferromagnetic region so as to cause orientation of magnetic anisotropy to change for switching magnetisation between the first and second orientations. | 07-14-2011 |
| 20110188297 | MAGNETIC MEMORY ELEMENT, DRIVING METHOD FOR SAME, AND NONVOLATILE STORAGE DEVICE - In accordance with one aspect of the invention, a magnetic memory element records information in a spin valve structure having a free layer, a pinning layer, and a nonmagnetic layer sandwiched therebetween. The magnetic memory element further has, on the free layer, a separate nonmagnetic layer and a magnetic change layer having magnetic characteristics which change according to temperature. Multiple cutouts, including one cutout with a different shape, are provided in a peripheral portion of the spin valve structure. A method of driving the magnetic memory element is characterized in that information is recorded by applying unipolar electric pulses. | 08-04-2011 |
| 20110188298 | MAGNETORESISTANCE ELEMENT, MRAM, AND INITIALIZATION METHOD FOR MAGNETORESISTANCE ELEMENT - A magnetoresistance element is provided with: a magnetization recording layer that is a ferromagnetic layer. The magnetization recording layer includes: a magnetization reversal region having a reversible magnetization; a first magnetization fixed region connected to a first boundary of the magnetization reversal region and having a magnetization direction fixed in a first direction; and a second magnetization fixed region connected to a second boundary of the magnetization reversal region and having a magnetization direction fixed in a second direction. At least one magnetization reversal facilitation structure which is a structure in which a magnetization is reversed more easily than the remaining portion is provided for a portion of the second magnetization fixed region. | 08-04-2011 |
| 20110188299 | DATA STORAGE DEVICE - A data storage device ( | 08-04-2011 |
| 20110188300 | NON-VOLATILE MEMORY WITH STRAY MAGNETIC FIELD COMPENSATION - A method and apparatus for stray magnetic field compensation in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a first tunneling barrier is coupled to a reference structure that has a perpendicular anisotropy and a first magnetization direction. A recording structure that has a perpendicular anisotropy is coupled to the first tunneling barrier and a nonmagnetic spacer layer. A compensation layer that has a perpendicular anisotropy and a second magnetization direction in substantial opposition to the first magnetization direction is coupled to the nonmagnetic spacer layer. Further, the memory cell is programmable to a selected resistance state with application of a current to the recording structure. | 08-04-2011 |
| 20110188301 | SHARED BIT LINE AND SOURCE LINE RESISTIVE SENSE MEMORY STRUCTURE - A resistive sense memory apparatus includes a first semiconductor transistor having a first contact electrically connected to a first source line and a second contact electrically connected to a first resistive sense memory element and a second semiconductor transistor having a first contact electrically connected to a second source line and a second contact electrically connected to a second resistive sense memory element. A bit line is electrically connected to the first resistive sense memory element and the second resistive sense memory element. | 08-04-2011 |
| 20110194333 | System and Method to Select a Reference Cell - A system and method to select a reference cell is disclosed. In a particular embodiment, a method is disclosed that includes receiving an address corresponding to a bit cell within a first bank of a memory. The method also includes accessing a second reference cell of a second bank of the memory in response to a first reference cell in the first bank being indicated as bypassed. | 08-11-2011 |
| 20110194334 | DIODE ASSISTED SWITCHING SPIN-TRANSFER TORQUE MEMORY UNIT - A memory array includes a cross-point array of bit and source lines. A memory is disposed at cross-points of the cross-point array. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. A transistor is electrically between the magnetic tunnel junction data cell and the bit line or source line and a diode is in thermal or electrical contact with the magnetic tunnel junction data cell to assist in resistance state switching. | 08-11-2011 |
| 20110194335 | MAGNETIC MEMORY WITH PHONON GLASS ELECTRON CRYSTAL MATERIAL - A magnetic memory unit includes a tunneling barrier separating a free magnetic element and a reference magnetic element. A first phonon glass electron crystal layer is disposed on a side opposing the tunneling barrier of either the free magnetic element or the reference magnetic element. A second phonon glass electron crystal layer also be disposed on a side opposing the tunneling barrier of either the free magnetic element or the reference magnetic element to provide a Peltier effect on the free magnetic element and the reference magnetic element. | 08-11-2011 |
| 20110194336 | Memory Cells, Memory Cell Constructions, and Memory Cell Programming Methods - Some embodiments include memory cells including a memory component having a first conductive material, a second conductive material, and an oxide material between the first conductive material and the second conductive material. A resistance of the memory component is configurable via a current conducted from the first conductive material through the oxide material to the second conductive material. Other embodiments include a diode comprising metal and a dielectric material and a memory component connected in series with the diode. The memory component includes a magnetoresistive material and has a resistance that is changeable via a current conducted through the diode and the magnetoresistive material. | 08-11-2011 |
| 20110194337 | Non-Volatile Memory Cell With Precessional Switching - A method and apparatus for writing data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a selected resistive state is written to a magnetic tunneling structure by applying a succession of indeterminate write pulses thereto until the selected resistive state is verified. | 08-11-2011 |
| 20110194338 | Memory Devices Including Multi-Bit Memory Cells Having Magnetic and Resistive Memory Elements and Related Methods - An integrated circuit memory device may include an integrated circuit substrate, and a multi-bit memory cell on the integrated circuit substrate. The multi-bit memory cell may be configured to store a first bit of data by changing a first characteristic of the multi-bit memory cell and to store a second bit of data by changing a second characteristic of the multi-bit memory cell. Moreover, the first and second characteristics may be different. Related methods are also discussed. | 08-11-2011 |
| 20110205788 | Spin-Torque Bit Cell With Unpinned Reference Layer and Unidirectional Write Current - Method and apparatus for using a uni-directional write current to store different logic states in a non-volatile memory cell, such as a modified STRAM cell. In some embodiments, the memory cell has an unpinned ferromagnetic reference layer adjacent a cladded conductor, a ferromagnetic storage layer and a tunneling barrier between the reference layer and the storage layer. Passage of a current along the cladded conductor induces a selected magnetic orientation in the reference layer, which is transferred through the tunneling barrier for storage by the storage layer. Further, the orientation of the applying step is provided by a cladding layer adjacent a conductor along which a current is passed and the current induces a magnetic field in the cladding layer of the selected magnetic orientation. | 08-25-2011 |
| 20110211387 | SCALABLE NONVOLATILE MEMORY - Various magnetoresistive memory cells and architectures are described which enable nonvolatile memories having high information density. | 09-01-2011 |
| 20110211388 | HIGH GMR STRUCTURE WITH LOW DRIVE FIELDS - Multi-period structures exhibiting giant magnetoresistance (GMR) are described in which the exchange coupling across the active interfaces of the structure is ferromagnetic. | 09-01-2011 |
| 20110211389 | MAGNETORESISTIVE ELEMENT AND MAGNETORESISTIVE RANDOM ACCESS MEMORY INCLUDING THE SAME - The present invention provides a low-resistance magnetoresistive element of a spin-injection write type. A crystallization promoting layer that promotes crystallization is formed in contact with an interfacial magnetic layer having an amorphous structure, so that crystallization is promoted from the side of a tunnel barrier layer, and the interface between the tunnel barrier layer and the interfacial magnetic layer is adjusted. With this arrangement, it is possible to form a magnetoresistive element that has a low resistance so as to obtain a desired current value, and has a high TMR ratio. | 09-01-2011 |
| 20110216580 | MRAM-BASED MEMORY DEVICE WITH ROTATED GATE - A memory device comprising: a plurality of magnetoresistive random access memory (MRAM) cells arranged in rows and columns, each MRAM cell comprising a magnetic tunnel junction and a select transistor, one end of the magnetic tunnel junction being electrically coupled to the source of the select transistor; a plurality of word lines, each word line connecting MRAM cells along a row via the gate of their select transistor; a plurality of bit lines, each bit line connecting MRAM cells along a column, each bit line connecting the MRAM cells via the drain of their select transistor; wherein the memory device further comprises a plurality of source lines, each source line connecting MRAM cells along a row; and wherein each source line connecting the MRAM cells via the other end of the magnetic tunnel junction. | 09-08-2011 |
| 20110216581 | SPIN TORQUE TRANSFER CELL STRUCTURE UTILIZING FIELD-INDUCED ANTIFERROMAGNETIC OR FERROMAGNETIC COUPLING - A magnetic memory cell including a soft magnetic layer and a coupling layer, and methods of operating the memory cell are provided. The memory cell includes a stack with a free ferromagnetic layer and a pinned ferromagnetic layer, and a soft magnetic layer and a coupling layer may also be formed as layers in the stack. The coupling layer may cause antiferromagnetic coupling to induce the free ferromagnetic layer to be magnetized in a direction antiparallel to the magnetization of the soft magnetic layer, or the coupling layer may cause ferromagnetic coupling to induce the free ferromagnetic layer to be magnetized in a direction parallel to the magnetization of the soft magnetic layer. The coupling layer, through a coupling effect, reduces the critical switching current of the memory cell. | 09-08-2011 |
| 20110222333 | MAGNETIC MEMORY CELL AND MAGNETIC RANDOM ACCESS MEMORY - Provided is a highly-integrated magnetic memory which employs applied spin torque magnetization reversal and does not require the switching of the current direction at the time of rewrite. The magnetic memory includes a memory cell in which a fixed layer made of a ferromagnetic material, a nonmagnetic layer, a recording layer made of a ferromagnetic material, a nonmagnetic layer, and a magnetization rotation assist layer made of a ferromagnetic material are stacked one on top of another. The magnetic memory performs recording by making the magnetization direction of the recording layer substantially parallel or substantially antiparallel to the magnetization direction of the fixed layer. The magnetization directions of the fixed layer, the recording layer, and the magnetization rotation assist layer are all oriented in substantially in-plane directions of the respective magnetic layers, and the magnetization direction of the magnetization rotation assist layer is at substantially 90 degrees to the magnetization direction of the fixed layer. The write current is caused to flow in a direction from the fixed layer to the recording layer in both cases where the magnetization direction of the recording layer is rewritten from a direction parallel to the magnetization direction of the fixed layer to a direction antiparallel thereto and where the magnetization direction of the recording layer is rewritten from the antiparallel direction to the parallel direction parallel. | 09-15-2011 |
| 20110222334 | SPIN TRANSFER TORQUE MRAM, AND WRITE METHOD AND READ METHOD THEREFOR - A method of writing data into a memory cell of spin transfer torque magnetoresistive random access memory includes writing a first data into a first memory cell that includes a first magnetic-tunnel-junction element and a first selection transistor wherein an end of the first memory cell is connected to a first signal line and a different end of the first memory cell is connected to a common signal line during a first period, and writing a second data which is an opposite of the first data into the second memory cell that includes a second magnetic-tunnel-junction element and a second selection transistor wherein an end of the second memory cell is connected to a second signal line and a different end of the second memory cell is connected to the common signal line during a second period following the first period. | 09-15-2011 |
| 20110222335 | MAGNETORESISTIVE ELEMENT AND MAGNETORESISTIVE RANDOM ACCESS MEMORY INCLUDING THE SAME - The present invention provides a low-resistance magnetoresistive element of a spin-injection write type. A crystallization promoting layer that promotes crystallization is formed in contact with an interfacial magnetic layer having an amorphous structure, so that crystallization is promoted from the side of a tunnel barrier layer, and the interface between the tunnel barrier layer and the interfacial magnetic layer is adjusted. With this arrangement, it is possible to form a magnetoresistive element that has a low resistance so as to obtain a desired current value, and has a high TMR ratio. | 09-15-2011 |
| 20110228594 | Multi-Port Non-Volatile Memory that Includes a Resistive Memory Element - A system and method to access a multi-port non-volatile memory that includes a resistive memory element is disclosed. In a particular embodiment, a multi-port non-volatile memory device is disclosed that includes a resistive memory cell and multiple ports coupled to the resistive memory cell. | 09-22-2011 |
| 20110228595 | Memory Cell That Includes Multiple Non-Volatile Memories - A system and method to read and write data at a memory cell that includes multiple non-volatile memories is disclosed. In a particular embodiment, a memory device is disclosed that includes a plurality of memory cells, where at least one of the memory cells comprises a first non-volatile memory including a first resistive memory element and a second multi-port non-volatile memory including a second resistive memory element. | 09-22-2011 |
| 20110228596 | SPIN MEMORY AND SPIN TRANSISTOR - Certain embodiments provide a spin memory including a memory cell including a ferromagnetic stacked film that has a stacked structure in which a first ferromagnetic layer, a first nonmagnetic layer, a second ferromagnetic layer, a second nonmagnetic layer, and a third ferromagnetic layer are stacked in this order or reverse order, the third ferromagnetic layer and the second ferromagnetic layer being antiferromagnetically exchange-coupled via the second nonmagnetic layer. The ferromagnetic stacked film includes a current path in which a first and second write currents flow from the first ferromagnetic layer to the third ferromagnetic layer to write a first and second magnetization states into the first ferromagnetic layer respectively, and the second write current is higher than the first write current. | 09-22-2011 |
| 20110228597 | Static Magnetic Field Assisted Resistive Sense Element - Apparatus and associated method for writing data to a non-volatile memory cell, such as spin-torque transfer random access memory (STRAM). In accordance with some embodiments, a resistive sense element (RSE) has a heat assist region, magnetic tunneling junction (MTJ), and pinned region. When a first logical state is written to the MTJ with a spin polarized current, the pinned and heat assist regions each have a substantially zero net magnetic moment. When a second logical state is written to the MTJ with a static magnetic field, the pinned region has a substantially zero net magnetic moment and the heat assist region has a non-zero net magnetic moment. | 09-22-2011 |
| 20110228598 | TRANSMISSION GATE-BASED SPIN-TRANSFER TORQUE MEMORY UNIT - A transmission gate-based spin-transfer torque memory unit is described. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. A NMOS transistor is in parallel electrical connection with a PMOS transistor and they are electrically connected with the source line and the magnetic tunnel junction data cell. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. The PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor. | 09-22-2011 |
| 20110242883 | THERMALLY ASSISTED MULTI-BIT MRAM - Methods of writing to a multi-bit MRAM memory unit are described. The method includes to self-detected writing to a multi-bit (i.e., multilevel) thermally assisted MRAM. The self-detected writing increases a reading margin between data state levels and decreases reading margin variability due to cell resistance variation. | 10-06-2011 |
| 20110267874 | Invalid Write Prevention for STT-MRAM Array - In a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) a bit cell array can have a source line substantially parallel to a word line. The source line can be substantially perpendicular to bit lines. A source line control unit includes a common source line driver and a source line selector configured to select individual ones of the source lines. The source line driver and source line selector can be coupled in multiplexed relation. A bit line control unit includes a common bit line driver and a bit line selector in multiplexed relation. The bit line control unit includes a positive channel metal oxide semiconductor (PMOS) element coupled between the common source line driver and bit line select lines and bit lines. | 11-03-2011 |
| 20110273926 | Method and Apparatus of Probabilistic Programming Multi-Level Memory in Cluster States Of Bi-Stable Elements - A probabilistic programming current is injected into a cluster of bi-stable probabilistic switching elements, the probabilistic programming current having parameters set to result in a less than unity probability of any given bi-stable switching element switching, and a resistance of the cluster of bi-stable switching elements is detected. The probabilistic programming current is injected and the resistance of the cluster state detected until a termination condition is met. Optionally the termination condition is detecting the resistance of the cluster of bi-stable switching elements at a value representing a multi-bit data. | 11-10-2011 |
| 20110280062 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device uses a magnetic tunnel junction device (MTJ) and includes a memory cell connected between a first driving line and a second driving line and configured to store data having a data state that is determined based on a direction of a current flowing through the first and the second driving lines, and a current controlling block configured to control a supply current provided to the first and second driving lines in response to temperature information in a writing operation. | 11-17-2011 |
| 20110280063 | SPINTRONIC DEVICES WITH INTEGRATED TRANSISTORS - The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated Giant-Magneto-resistive (GMR) structures. The present teachings relates to integrated latch memory and logic devices and, in particular, concerns a spin dependent logic device that may be integrated with conventional semiconductor-based logic devices to construct high-speed non-volatile static random access memory (SRAM) cells. | 11-17-2011 |
| 20110280064 | COMPOSITE RESISTANCE VARIABLE ELEMENT AND METHOD FOR MANUFACTURING THE SAME - A composite resistance variable element includes a first resistance variable element in which a resistance value varies corresponding to a direction of inner magnetization, and a second resistance variable element connected in series to the first resistance variable element. A resistance value of the second resistance variable element varies corresponding to a magnitude of at least one of a voltage applied to the second resistance variable element and a current flowing through the second resistance variable element, irrespective of whether the voltage and the current are positive or negative. | 11-17-2011 |
| 20110292718 | NON-VOLATILE LOGIC CIRCUIT - A non-volatile logic circuit includes an input section, a control section and an output section. The input section has perpendicular magnetic anisotropy and has a ferromagnetic layer whose magnetization state is changeable. The control section includes a ferromagnetic layer. The output section is provided in a neighborhood of the input section and the control section and includes a magnetic tunnel junction element whose magnetization state is changeable. The magnetization state of the input section is changed based on the magnetization state. A magnetization state of the magnetic tunnel junction element of the output section which state is changed based on the magnetization state of the ferromagnetic material of the control section and the magnetization state of the ferromagnetic material of the input section. | 12-01-2011 |
| 20110310660 | MAGNETORESISTANCE ELEMENT AND STORAGE DEVICE USING THE SAME - A magnetic memory element having a memory cell of size 4F | 12-22-2011 |
| 20110317479 | Shared bit line SMT MRAM array with shunting transistors between the bit lines - An array of rows and columns of SMT MRAM cells has each of the columns associated with one of its adjacent columns. Each of the SMT MRAM cells of the column is connected to a true data bit line and each of the SMT MRAM cells of the associated pair of columns is connected to a shared complement data bit line. A shunting switch device is connected between each of the true data bit lines and the shared complement data bit line for selectively connecting one of the true data bit lines to the shared complement data bit line to effectively reduce the resistance of the complement data bit line and to eliminate program disturb effects in adjacent non-selected columns of the SMT MRAM cells. | 12-29-2011 |
| 20120002461 | NON-VOLATILE MEMORY WITH OVONIC THRESHOLD SWITCH AND RESISTIVE MEMORY ELEMENT - The present disclosure relates to the fabrication of non-volatile memory devices. In at least one embodiment, the non-volatile memory of the present disclosure may include a resistive memory element with an ovonic threshold switch. The ovonic threshold switch may be connected in series with the resistive memory element and may act as an isolation device for the resistive memory element. | 01-05-2012 |
| 20120002462 | RESISTANCE-CHANGE SEMICONDUCTOR MEMORY - According to one embodiment, a memory includes first to fourth memory cells aligned in a first direction. Each of the first to fourth memory cells comprises a cell transistor having a gate connected to a word line extending in a second direction crossing the first direction and a resistive memory element having one end connected to a first source/drain region of the cell transistor. A second source/drain region of the cell transistor is connected to one of a first bit line extending in the first direction and a second bit line extending in the second direction. The other end of the resistive memory element is connected to one of the first and second bit lines which is apart from the second source/drain region. The second source/drain regions in the first and second memory cells are shared, and the second source/drain regions in the third and fourth memory cells are shared. | 01-05-2012 |
| 20120002463 | HIGH CAPACITY LOW COST MULTI-STATE MAGNETIC MEMORY - A multi-state current-switching magnetic memory element includes a stack of magnetic tunneling junction (MTJ) separated by a non-magnetic layer for storing more than one bit of information, wherein different levels of current applied to the memory element cause switching to different states. | 01-05-2012 |
| 20120008380 | METHOD FOR WRITING IN A MRAM-BASED MEMORY DEVICE WITH REDUCED POWER CONSUMPTION - A method of writing in a memory device comprising a plurality of MRAM cells, each cell including a magnetic tunnel junction having a resistance that can be varied during a write operation when heated at a high threshold temperature; a plurality of word lines connecting cells along a row; and a plurality of bit lines connecting cells along a column; the method comprising supplying a bit line voltage to one of the bit lines and a word line voltage to one of the word lines for passing a heating current through the magnetic tunnel junction of a selected cell; said word line voltage is a word line overdrive voltage being higher than the core operating voltage of the cells such that the heating current has a magnitude that is high enough for heating the magnetic tunnel junction at the predetermined high threshold temperature. The memory device can be written with low power consumption. | 01-12-2012 |
| 20120008381 | MAGNETORESISTIVE ELEMENT - A magnetoresistive element which records information by supplying spin-polarized electrons to a magnetic material, includes a first pinned layer which is made of a magnetic material and has a first magnetization directed in a direction perpendicular to a film surface, a free layer which is made of a magnetic material and has a second magnetization directed in the direction perpendicular to the film surface, the direction of the second magnetization reversing by the spin-polarized electrons, and a first nonmagnetic layer which is provided between the first pinned layer and the free layer. A saturation magnetization Ms of the free layer satisfies a relationship 0≦Ms<√{square root over ( )}{Jw/(6πAt)}. Jw is a write current density, t is a thickness of the free layer, A is a constant. | 01-12-2012 |
| 20120008382 | MAGNETIC RECORDING ELEMENT - A magnetic recording element is disclosed for which current density required for writing is low and structure of the element is simple. It comprises a ferromagnetic fine wire formed on a Si substrate, current electrodes that contact ends of the ferromagnetic fine wire, and voltage electrodes joined to the ferromagnetic fine wire and current electrodes to measure voltage across part of the ferromagnetic fine wire in cooperation with the current electrodes. A magnetic domain wall is induced in the ferromagnetic fine wire when the element is manufactured. A depression is formed in the surface on top of the ferromagnetic fine wire between the voltage electrodes, and between one of the current electrodes and one of the voltage electrodes. Voltage is measured between the two voltage electrodes when reading current is applied, to determine whether the magnetic domain wall is present between the two voltage electrodes, whereby recorded data can be identified. | 01-12-2012 |
| 20120014174 | Programmable Write Driver For STT-MRAM - A non-volatile memory structure comprises programmable write drivers for controlling drive strengths of write operations to storage elements. The memory structure comprises a storage element coupled to a bit line, a switching element coupled to the storage element, a source line and a word line, wherein the switching element is configured to change a logic state of the storage element. A first and a second write driver with programmable drive strengths are coupled to the bit line and source line respectively to enable control of drive strengths of write operations to the storage element. | 01-19-2012 |
| 20120014175 | Magnetic Tunnel Junction and Memristor Apparatus - A magnetic memory device includes a magnetic tunnel junction having a free magnetic layer having a magnetization orientation that is switchable between a high resistance state magnetization orientation and a low resistance state magnetization orientation and a memristor solid state element electrically coupled to the magnetic tunnel junction. The memristor has a device response that is an integrated voltage versus an integrated current. | 01-19-2012 |
| 20120014176 | CREATING SPIN-TRANSFER TORQUE IN OSCILLATORS AND MEMORIES - A structure includes an electrically conductive material possessing spontaneous magnetization (“free magnet”) not in contact with an electrically resistive material possessing spontaneous magnetization (“pinned magnet”), and a spacer having free electrons to transfer spin between the electrically resistive material and the electrically conductive material. During operation, an existing direction of magnetization of the free magnet is changed to a new direction of magnetization, by a spin current generated by transfer of heat between at least the spacer and the pinned magnet. Thereafter, the new direction of magnetization of the free magnet is sensed. Many such structures are fabricated to have an easy axis of magnetic anisotropy in the free magnet, to implement memories that write data by transferring heat. Several such structures are fabricated to have an easy plane of magnetic anisotropy in the free magnet, to implement oscillators that generate an oscillating signal, on transfer of heat. | 01-19-2012 |
| 20120020147 | MAGNETIC MEMORY ELEMENT, MAGNETIC MEMORY DEVICE, INFORMATION RECORDING/REPRODUCING APPARATUS - A magnetic memory element includes a pair of electrodes, a junction layer, at least one carbon nanotube, and at least one nanowire. The at least one nanowire is made of a ferromagnetic material and extends through a hole of each the at least one carbon nanotube with both ends being electrically connected to the pair of electrodes, respectively. The junction layer is made of a non-magnetic material and disposed between one of the pair of electrodes and one end of each the at least one nanowire. The one of the pair of electrodes is made of a ferromagnetic material. Magnetization of the at least one nanowire is reversed by spin injection performed through the junction layer with the one of the pair of electrodes. When a DC bias current and a detection current having a frequency coinciding with a magnetic resonance frequency of the nanowire are applied in a superimposed manner, between the electrodes, within a range not reaching a critical current density of the magnetization reversal, the pair of electrodes have a voltage corresponding to a magnetization direction of the nanowire. | 01-26-2012 |
| 20120020148 | MULTI-BIT STRAM MEMORY CELLS - A multi-bit spin torque magnetic element that has a ferromagnetic pinned layer having a pinned magnetization orientation, a non-magnetic layer, and a ferromagnetic free layer having a magnetization orientation switchable among at least four directions, the at least four directions being defined by a physical shape of the free layer. The magnetic element has at least four distinct resistance states. Magnetic elements with at least eight magnetization directions are also provided. | 01-26-2012 |
| 20120026783 | Latching Circuit - A non-volatile latch circuit includes a pair of cross-coupled inverters, a pair of resistance-based memory elements, and write circuitry configured to write data to the pair of resistance-based memory elements. The pair of resistance-based memory elements is isolated from the pair of cross-coupled inverters during a latching operation. A sensing circuit includes a first current path that includes a first resistance-based memory element and an output of the sensing circuit. The sensing circuit includes a second current path to reduce current flow through the first resistance-based memory element at a first operating point of the sensing circuit. The sensing circuit may also include an n-type metal-oxide-semiconductor (NMOS) transistor to provide a step down supply voltage to the first current path. | 02-02-2012 |
| 20120026784 | RANDOM NUMBER GENERATOR - According to an aspect of embodiments, there is provided a random number generating circuit including at least one magnetic tunnel junction (MTJ) element and a control circuit. The MTJ element comes into a high resistance state corresponding to a first logical value and also comes into a low resistance state corresponding to a second logical value different from the first logical value. The control circuit supplies the MTJ element with a first current for stochastically reversing the MTJ element from the high resistance state to the low resistance state when the MTJ element is in the high resistance state, and supplies the MTJ element with a second current for stochastically reversing the MTJ element from the low resistance state to the high resistance state when the MTJ element is in the low resistance state. | 02-02-2012 |
| 20120026785 | Non-Volatile Magnetic Memory Element with Graded Layer - A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound. | 02-02-2012 |
| 20120039115 | STRAM WITH COMPOSITE FREE MAGNETIC ELEMENT - Spin-transfer torque memory includes a composite free magnetic element, a reference magnetic element having a magnetization orientation that is pinned in a reference direction, and an electrically insulating and non-magnetic tunneling barrier layer separating the composite free magnetic element from the magnetic reference element. The free magnetic element includes a hard magnetic layer exchanged coupled to a soft magnetic layer. The composite free magnetic element has a magnetization orientation that can change direction due to spin-torque transfer when a write current passes through the spin-transfer torque memory unit. | 02-16-2012 |
| 20120057400 | System and Method for Shared Sensing MRAM - Resistance memory cells of MRAM arrays are designated as reference cells and programmed to binary 0 and binary 1 states, reference cells from one MRAM array at binary 0 and at binary 1 are concurrently accessed to obtain a reference voltage to read resistance memory cells of another MRAM array, reference cells from the other MRAM array at binary 0 and binary 1 are concurrently accessed to obtain a reference voltage to read resistance memory cells of the one MRAM array. | 03-08-2012 |
| 20120063214 | Pulse field assisted spin momentum transfer MRAM design - An MRAM array structure and a method of its operation that is not subject to accidental writing on half-selected elements. Each element of the MRAM is an MTJ (magnetic tunneling junction) cell operating in accord with an STT (spin torque transfer) scheme for changing its free layer magnetization state and each cell is patterned to have a C-shape in the horizontal plane. The cell thereby operates by C-mode switching to provide stability against accidental writing by half-selection. During operation, switching of a cell's magnetization is accomplished with the assist of the pulsed magnetic fields of additional word lines that are formed either orthogonal to or parallel to the existing bit lines and that can carry currents in either direction as required to provide the assist. | 03-15-2012 |
| 20120063215 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes first to fourth switch circuit. The semiconductor storage device includes a row decoder which controls a voltage of a word line. The semiconductor storage device includes a first selection transistor of which a control terminal is connected to the word line. The semiconductor storage device includes a first resistance change element which is connected in series to the first selection transistor between the first bit line and the second bit line, and of which a resistance value changes according to a flowing current. The semiconductor storage device includes a second selection transistor of which a control terminal is connected to the word line. The semiconductor storage device includes a second resistance change element which is connected in series to the second selection transistor between the second bit line and the third bit line, and of which a resistance value changes according to a flowing current. | 03-15-2012 |
| 20120063216 | SEMICONDUCTOR STORAGE DEVICE - A memory includes bit lines, word lines, and memory cells connected between first and second BLs. The cells arranged in an extending direction of the BLs constitute columns. The second BL is shared between two columns. The cells in a first pair of columns are arranged to be shifted in the extending direction of the BLs by a half-pitch from the cells in a second pair of columns. The device includes a dummy cell having an equal distance from the adjacent memory elements. Further, the device includes a row decoder driving the cells in the first pair of columns by driving paired word lines, and driving the cells in the second pair of columns by driving paired word lines. Each cell includes selection transistors. The selection transistors are connected in parallel between the memory element and the first BL. Gates of the transistors are connected to different WLs. | 03-15-2012 |
| 20120063217 | MEMORY ELEMENT AND MEMORY DEVICE - There is disclosed a memory element including a memory layer that has a magnetization perpendicular to a film face and a magnetization direction thereof varies corresponding to information; a magnetization-fixed layer that has a magnetization that is perpendicular to the film face; and an insulating layer that is provided between the memory layer and the magnetization-fixed layer, wherein the memory layer has a lamination structure of a Co—Fe—B layer and an element belonging to any one of 1A group, 2A group, 3A group, 5A group, or 6A group, an electron that is spin-polarized is injected in a lamination direction of a layered structure, and thereby the magnetization direction of the memory layer varies and a recording of information is performed with respect to the memory layer, a magnitude of an effective diamagnetic field which the memory layer receives is smaller than a saturated magnetization amount of the memory layer. | 03-15-2012 |
| 20120069638 | SEMICONDUCTOR DEVICE - A semiconductor device which it can accommodate variations in a write current threshold in each memory cell and can secure a write margin is provided. An MRAM device includes an MTJ memory cell arranged in a matrix, plural bit lines each arranged corresponding to a memory cell column, plural digit lines each arranged corresponding to a memory cell row, and a write current adjusting unit which adjusts a current amount of a write current to be flowed through a bit line and/or a digit line, in order to perform a data write to each MTJ memory cell normally. The write current adjusting unit divides the plural bit lines and/or the plural digit lines into units of at least one write current line as division units, and includes plural write current adjusting circuits which adjust the current amount of write current in each of the division units. | 03-22-2012 |
| 20120069639 | SEMICONDUCTOR STORAGE DEVICE - A memory according to an embodiment includes bit lines, word lines, source lines, magnetic tunnel junction elements and transistors that are serially connected between the bit lines and the source lines, respectively, and a sense amplifier that detects data stored in the magnetic tunnel junction elements. The semiconductor storage device includes multiplexers between the bit lines and the sense amplifier in order to select one of the bit lines to be connected to the sense amplifier, and write amplifiers that are located corresponding to memory cell blocks each of which includes memory cells each including the magnetic tunnel junction element and the transistor and are connected to the bit lines or connected via the multiplexers to the bit lines. To write data, the sense amplifier applies a write voltage to the bit lines and then the write amplifiers hold the write voltage. | 03-22-2012 |
| 20120069640 | MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY - A magnetoresistive element according to an embodiment includes: a first and second magnetic layers having an easy axis of magnetization in a direction perpendicular to a film plane; and a first nonmagnetic layer interposed between the first and second magnetic layers, at least one of the first and second magnetic layers including a structure formed by stacking a first and second magnetic films, the second magnetic film being located closer to the first nonmagnetic layer, the second magnetic film including a structure formed by repeating stacking of a magnetic material layer and a nonmagnetic material layer at least twice, the nonmagnetic material layers of the second magnetic film containing at least one element selected from the group consisting of Ta, W, Hf, Zr, Nb, Mo, Ti, V, and Cr, one of the first and second magnetic layers having a magnetization direction that is changed by applying a current. | 03-22-2012 |
| 20120069641 | MAGNETIC MEMORY - According to one embodiment, a magnetic memory includes a magnetoresistive element includes a first reference layer, a first nonmagnetic layer, a recording layer, a second nonmagnetic layer, and a second reference layer which are sequentially stacked, the recording layer being connected to a terminal to which a high-level voltage is applied, a magnetization direction of the recording layer being variable, magnetization directions of the first and second reference layers being invariable and antiparallel, a first selection transistor connected between a first bit line and the first reference layer, and constituted of an N-channel MOSFET, a second selection transistor connected between a second bit line and the second reference layer, and constituted of an N-channel MOSFET, and a word line connected to gates of the first and second selection transistors. | 03-22-2012 |
| 20120069642 | MAGNETORESISTIVE ELEMENT AND MAGNETIC RANDOM ACCESS MEMORY - According to one embodiment, a magnetoresistive element includes an electrode layer, a first magnetic layer, a second magnetic layer and a nonmagnetic layer. The electrode layer includes a metal layer including at least one of Mo, Nb, and W. The first magnetic layer is disposed on the metal layer to be in contact with the metal layer and has a magnetization easy axis in a direction perpendicular to a film plane and is variable in magnetization direction. The second magnetic layer is disposed on the first magnetic layer and has a magnetization easy axis in the direction perpendicular to the film plane and is invariable in magnetization direction. The nonmagnetic layer is provided between the first and second magnetic layers. The magnetization direction of the first magnetic layer is varied by a current that runs through the first magnetic layer, the nonmagnetic layer, and the second magnetic layer. | 03-22-2012 |
| 20120069643 | NON-UNIFORM SWITCHING BASED NON-VOLATILE MAGNETIC BASED MEMORY - A non-uniform switching based non-volatile magnetic memory element includes a fixed layer, a barrier layer formed on top of the fixed layer, a first free layer formed on top of the barrier layer, a non-uniform switching layer (NSL) formed on top of the first free layer, and a second free layer formed on top of the non-uniform switching layer. Switching current is applied, in a direction that is substantially perpendicular to the fixed layer, barrier layer, first free layer, non-uniform switching layer and the second free layer causing switching between states of the first free layer, second free layer and non-uniform switching layer with substantially reduced switching current. | 03-22-2012 |
| 20120075921 | SEMICONDUCTOR DEVICE - A semiconductor device using a segment writing method capable of achieving a normal write operation is provided. The first DL driver and the second DL driver each cause a magnetizing current to flow through a digit line of a selected block. A BL driver causes a write current to flow in a direction corresponding to the logic of a data signal to all bit lines in a selected segment, and writes the data signal to a memory cell of the selected block. A segment decoder, when the address of one segment has been input from the outside, selects one segment corresponding to the address and couples the same to the selected first DL driver, and the segment decoder, when the addresses of two or more segments have been input from the outside, selects two or more segments corresponding to the addresses and couples the selected two or more segments to the first DL driver and the second DL driver, respectively. | 03-29-2012 |
| 20120075922 | MAGNETIC MEMORY ELEMENT AND STORAGE DEVICE USING THE SAME - A magnetic memory element capable of maintaining high thermal stability (retention characteristics) while reducing a writing current. The magnetic memory element includes a magnetic tunnel junction having a first magnetic body including a perpendicular magnetization film, an insulating layer, and a second magnetic body serving as a storage layer including a perpendicular magnetization film, which are sequentially stacked. A thermal expansion layer is disposed in contact with the magnetic tunnel junction portion. The second magnetic body is deformed in a direction in which the cross section thereof increases or decreases by the thermal expansion or contraction of the thermal expansion layer due to the flow of a current, thereby reducing a switching current threshold value required to change the magnetization direction. | 03-29-2012 |
| 20120081950 | STRUCTURES AND METHODS FOR A FIELD-RESET SPIN-TORQUE MRAM - An apparatus and method of programming a spin-torque magnetoresistive memory array includes a conductive reset line positioned near each of a plurality of magnetoresistive bits and configured to set the plurality of magnetoresistive memory elements to a known state having magnetization perpendicular to the film plane of the magnetoresistive bits by generating a magnetic field when an electrical current flows therethrough. The conductive reset line is positioned such that the magnetic field is applied with a predominant component perpendicular to the film plane when an electrical current of predetermined magnitude, duration, and direction flows through the first conductive reset line. Another conductive reset line may be positioned wherein the magnetic field is created between the two conductive reset lines. A permeable ferromagnetic material may be positioned around a portion of the conductive reset line or lines to focus the magnetic field in the desired direction by positioning edges of permeable ferromagnetic material on opposed sides of the film plane. A spin torque transfer current is applied to selected ones of the magnetoresistive bits to switch the selected bit to a programmed state. | 04-05-2012 |
| 20120081951 | NON-VOLATILE MEMORY WITH STRAY MAGNETIC FIELD COMPENSATION - A method and apparatus for stray magnetic field compensation in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a first tunneling barrier is coupled to a reference structure that has a perpendicular anisotropy and a first magnetization direction. A recording structure that has a perpendicular anisotropy is coupled to the first tunneling barrier and a nonmagnetic spacer layer. A compensation layer that has a perpendicular anisotropy and a second magnetization direction in substantial opposition to the first magnetization direction is coupled to the nonmagnetic spacer layer. Further, the memory cell is programmable to a selected resistance state with application of a current to the recording structure. | 04-05-2012 |
| 20120081952 | SEMICONDUCTOR STORAGE DEVICE - To write information on a memory cell of SPRAM formed of an MOS transistor and a tunnel magnetoresistive element, the memory cell is supplied with a current in a direction opposite to a direction of a current required for writing the information on the memory cell, and then, the memory cell is supplied with a current required for writing. In this manner, even when the same information is sequentially written on the memory cell, since the currents in the two directions are caused to flow in pairs in the tunnel magnetoresistive element of the memory cell each time information is rewritten, deterioration of a film that forms the tunnel magnetoresistive element can be suppressed. Therefore, reliability of the SPRAM can be improved. | 04-05-2012 |
| 20120087179 | MAGNETO-RESISTANCE ELEMENT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A magneto-resistance element is provided. The magneto-resistance element includes an underlying layer including a main metal selected from electrically conductive metals and an auxiliary metal selected from transition metals, a first magnetic layer stacked on the underlying layer, an insulation layer stacked on the first magnetic layer, and a second magnetic layer stacked on the insulation layer. | 04-12-2012 |
| 20120087180 | SEMICONDUCTOR INTEGRATED CIRCUIT FOR LOW AND HIGH VOLTAGE OPERATIONS - A semiconductor integrated circuit comprising a first circuit area for a low voltage operation and a second circuit area for a high voltage operation. The circuit areas comprise two vertically stacked backend patterned metal layers that are separated by an inter-metallic dielectric (IMD). The two metal layers and the IMD form a combination that is operable at the low voltage. The first circuit area uses a first portion of the combination for operating at the low voltage and the second circuit area uses a second portion of the combination for routing at the high voltage, the two metal layers in the second portion being interconnected through the IMD by via hole, for withstanding the high voltage. The first portion may comprise an array of magnetic random access memory (MRAM) devices and the second circuit area may comprise a display drive circuit. | 04-12-2012 |
| 20120099369 | MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY - According to one embodiment, a magnetoresistive element includes a first magnetic layer with a variable magnetization and an easy-axis in a perpendicular direction to a film surface, a second magnetic layer with an invariable magnetization and an easy-axis in the perpendicular direction, and a first nonmagnetic layer between the first and second magnetic layers. The first magnetic layer comprises a ferromagnetic material including an alloy in which Co and Pd, or Co and Pt are alternately laminated on an atomically close-packed plane thereof. The first magnetic layer has C-axis directing the perpendicular direction. And a magnetization direction of the first magnetic layer is changed by a current flowing through the first magnetic layer, the first nonmagnetic layer and the second magnetic layer. | 04-26-2012 |
| 20120106239 | Magnetic Memory Element With Multi-Domain Storage Layer - An apparatus and method for enhancing data writing and retention to a magnetic memory element, such as in a non-volatile data storage array. In accordance with various embodiments, a programmable memory element has a reference layer and a storage layer. The reference layer is provided with a fixed magnetic orientation. The storage layer is programmed to have a first region with a magnetic orientation antiparallel to said fixed magnetic orientation, and a second region with a magnetic orientation parallel to said fixed magnetic orientation. A thermal assist layer may be incorporated into the memory element to enhance localized heating of the storage layer to aid in the transition of the first region from parallel to antiparallel magnetic orientation during a write operation. | 05-03-2012 |
| 20120106240 | COMPOUND CELL SPIN-TORQUE MAGNETIC RANDOM ACCESS MEMORY - A compound magnetic data storage cell, applicable to spin-torque random access memory (ST-RAM), is disclosed. A magnetic data storage cell includes a magnetic storage element and two terminals communicatively connected to the magnetic storage element. The magnetic storage element is configured to yield any of at least three distinct magnetoresistance output levels, corresponding to stable magnetic configurations, in response to spin-momentum transfer inputs via the terminals. | 05-03-2012 |
| 20120106241 | SPIN-TRANSFER TORQUE MEMORY SELF-REFERENCE READ METHOD - A spin-transfer torque memory apparatus and self-reference read schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage, the magnetic tunnel junction data cell having a first resistance state and storing the first bit line read voltage in a first voltage storage device. Then applying a low resistance state polarized write current through the magnetic tunnel junction data cell, forming a low second resistance state magnetic tunnel junction data cell. A second read current is applied through the low second resistance state magnetic tunnel junction data cell to forming a second bit line read voltage. The second bit line read voltage is stored in a second voltage storage device. The method also includes comparing the first bit line read voltage with the second bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state. | 05-03-2012 |
| 20120120718 | Multi-Bit Magnetic Memory with Independently Programmable Free Layer Domains - An apparatus and associated method for a non-volatile memory cell, such as a multi-bit magnetic random access memory cell. In accordance with various embodiments, a magnetic tunnel junction (MTJ) has a ferromagnetic free layer with multiple magnetic domains that are each independently programmable to predetermined magnetizations. Those magnetizations can then be read as different logical states of the MTJ. | 05-17-2012 |
| 20120120719 | NON-VOLATILE MAGNETIC TUNNEL JUNCTION TRANSISTOR - An example embodiment is an apparatus for controlling a magnetic direction of a magnetic free layer. The apparatus includes a writer with a first magnetic write layer and a second magnetic write layer. Applying a write voltage across first and second magnetic write layers causes a magnetic anisotropy of one of the magnetic write layers to switch from parallel to the plane of the magnetic write layers to orthogonal to the plane of the magnetic write layers. The magnetic write layer with the magnetic anisotropy parallel to the plane of the magnetic write layers induces the magnetic direction in the magnetic free layer. | 05-17-2012 |
| 20120120720 | MULTILEVEL MAGNETIC ELEMENT - The present disclosure concerns a multilevel magnetic element comprising a first tunnel barrier layer between a soft ferromagnetic layer having a magnetization that can be freely aligned and a first hard ferromagnetic layer having a magnetization that is fixed at a first high temperature threshold and freely alignable at a first low temperature threshold. The magnetic element further comprises a second tunnel barrier layer and a second hard ferromagnetic layer having a magnetization that is fixed at a second high temperature threshold and freely alignable at a first low temperature threshold; the soft ferromagnetic layer being comprised between the first and second tunnel barrier layers. The magnetic element disclosed herein allows for writing four distinct levels using only a single current line. | 05-17-2012 |
| 20120120721 | UNIDIRECTIONAL SPIN TORQUE TRANSFER MAGNETIC MEMORY CELL STRUCTURE - Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells having two pinned layers and a free layer therebetween. By utilizing two pinned layers, the spin torque effect on the free layer from each of the two pinned layers, respectively, allows the memory cells to be programmed with unidirectional currents. | 05-17-2012 |
| 20120127785 | Using a Nearby Cell to Provide Field Assisted Switching in a Magnetic Memory Array - Method and apparatus for writing data to a magnetic memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In accordance with various embodiments, a write current is applied through a selected magnetic memory cell to initiate magnetic precession of the selected cell to a desired magnetic state. A field assist current is concurrently flowed through an adjacent memory cell to generate a magnetic field that assists in the precession of the selected cell to the desired magnetic state. | 05-24-2012 |
| 20120127786 | FLUX PROGRAMMED MULTI-BIT MAGNETIC MEMORY - An apparatus and associated method for a non-volatile memory cell, such as a multi-bit magnetic random access memory cell. In accordance with various embodiments, a first magnetic tunnel junction (MTJ) is adjacent to a second MTJ having a magnetic filter. The first MTJ is programmed to a first logical state with a first magnetic flux while the magnetic filter absorbs the first magnetic flux to prevent the second MTJ from being programmed. | 05-24-2012 |
| 20120127787 | SPIN-TRANSFER TORQUE MEMORY NON-DESTRUCTIVE SELF-REFERENCE READ METHOD - A method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage. The magnetic tunnel junction data cell has a first resistance state. Then the method includes applying a second read current thorough the magnetic tunnel junction data cell having the first resistance state. The first read current is less than the second read current. Then the first bit line read voltage is compared with the second bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state. | 05-24-2012 |
| 20120127788 | MRAM Cells and Circuit for Programming the Same - A circuit includes magneto-resistive random access memory (MRAM) cell and a control circuit. The control circuit is electrically coupled to the MRAM cell, and includes a current source configured to provide a first writing pulse to write a value into the MRAM cell, and a read circuit configured to measure a status of the MRAM cell. The control circuit is further configured to verify whether a successful writing is achieved through the first writing pulse. | 05-24-2012 |
| 20120134199 | Magnetic Switching Cells and Methods of Making and Operating Same - Logic circuits based, at least in part, on use of spin-torque transfer (STT) to switch the magnetization—and hence the logic state—of a magnetic material are disclosed. Aspects of the invention include novel STT-based switching devices, new configurations of known STT-based devices into useful logic circuits, common logic circuits and system building blocks based on these new devices and configurations, as well as methods for inexpensively mass-producing such devices and circuits. | 05-31-2012 |
| 20120134200 | Magnetic Memory Cell With Multi-Level Cell (MLC) Data Storage Capability - Method and apparatus for writing data to a magnetic memory element, such as a spin-torque transfer random access memory (STRAM) memory cell. In accordance with various embodiments, a multi-level cell (MLC) magnetic memory cell stack has first and second magnetic memory elements connected to a first control line and a switching device connected to a second control line. The first memory element is connected in parallel with the second memory element, and the first and second memory elements are connected in series with the switching device. The first and second memory elements are further disposed at different non-overlapping elevations within the stack. Programming currents are passed between the first and second control lines to concurrently set the first and second magnetic memory elements to different programmed resistances. | 05-31-2012 |
| 20120134201 | MAGNETIC MEMORY ELEMENT AND DRIVING METHOD FOR SAME - A magnetic memory element and a method of driving such an element are disclosed. The magnetic memory element has a magnetic tunnel junction portion with a spin-valve structure having a perpendicular magnetization free layer formed of a perpendicular magnetization film, a perpendicular magnetization pinned layer formed of a perpendicular magnetization film, and a nonmagnetic layer sandwiched between the perpendicular magnetization free layer and the perpendicular magnetization pinned layer, and records information by application of an electric pulse to the magnetic tunnel junction portion. An in-plane magnetization film, interposed in the path of the electric pulse, is disposed in the magnetic tunnel junction portion. The in-plane magnetization film is configured so as to exhibit antiferromagnetic (low-temperature)-ferromagnetic (high-temperature) phase transitions depending on temperature changes based on application of the electric pulse to the magnetic tunnel junction portion. | 05-31-2012 |
| 20120147663 | NONVOLATILE MEMORY WITH ENHANCED EFFICIENCY TO ADDRESS ASYMETRIC NVM CELLS - This application describes embodiments of MRAM cells that utilize a PMOS transistor as an access transistor. The MRAM cells are configured to mitigate the effects of applying asymmetric current loads to transition a Magnetic-Tunnel Junction of the MRAM cell between magnetoresistive states. | 06-14-2012 |
| 20120147664 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR CONTROLLING THE SAME - A non-volatile memory and method for controlling the same prevents a faulty operation from being generated in a read operation, resulting in increase in operation reliability. The non-volatile memory device includes a cell array configured to include a plurality of unit cells in which a read or write operation of data is achieved in a unit cell in response to a variation of resistance, a reference cell array configured to include a plurality of reference cells, each of which has the same structure as that of the unit cell, a global reference current generation circuit configured to generate a global reference current corresponding to a position of the reference cell so as to verify data stored in the reference cell array, and a sense-amplifier configured to compare a current flowing in the reference cell array with the global reference current during a write verification operation of the reference cell array, and thus sense data. | 06-14-2012 |
| 20120147665 | Predictive Thermal Preconditioning and Timing Control for Non-Volatile Memory Cells - Method and apparatus for using thermal preconditioning to write data to a non-volatile memory cell. In accordance with some embodiments, a semiconductor memory has an array of non-volatile memory cells, and a control circuit which stores a first write command from a host to write data to said array. A write circuit flows a write current through an unconditioned first selected cell having a first block address associated with the first write command to write the first selected cell to a selected data state, and concurrently passes a thermal preconditioning current through a second selected cell having a second block address associated with the first block address. The write circuit further passes a thermal preconditioning current through a third selected cell having a third block address associated with the second block address in response to receipt by the control circuit of a second write command from the host associated with the second block address. | 06-14-2012 |
| 20120155153 | Scalable Magnetic Memory Cell With Reduced Write Current - A magnetic memory cell comprising a magnetoresistive element including a free layer with a changeable orientation of a magnetization oriented substantially perpendicular to a layer plane in its equilibrium state, a pinned layer with a fixed orientation of a magnetization oriented substantially perpendicular to a layer plane, and a tunnel barrier layer disposed between the free and pinned layers; means for providing a bias magnetic field pulse along magnetic hard axis of both the free and pinned layers, means for providing a spin-polarized current pulse through the magnetoresistive element along magnetic easy axis of both the free layer and the pinned layer, wherein the orientation of magnetization in the free layer will be reversed by a collective effect of the bias magnetic field pulse and the spin-polarizing current pulse; and wherein the magnetoresistive element comprises at least one magnetic layer whose magnetization having a perpendicular orientation in its equilibrium state can be tilted by the bias magnetic field to facilitate the magnetization reversal in the free layer by the spin-polarized current. | 06-21-2012 |
| 20120155154 | Three-Dimensional Magnetic Random Access Memory With High Speed Writing - A magnetic random access memory with perpendicular magnetization comprising a selection transistor with a gate width, that is formed on a substrate and is electrically connected to a word line; a plurality of memory layers sequentially disposed above the substrate, wherein each of the plurality of the memory layers includes a plurality of magnetoresistive elements with perpendicular magnetization and wherein each of the plurality of the magnetoresistive elements comprises an element width and includes at least a pinned layer comprising a fixed magnetization, a free layer comprising a changeable magnetization, and a tunnel barrier layer residing between the pinned layer and the free layer; a plurality of conductor layers disposed alternately with the memory layers beginning with the memory layer positioned adjacent to the substrate, wherein each of the plurality of the conductor layers comprises a plurality of parallel bit lines intersecting the word line, and wherein the bit line is disposed adjacent to the free layer and is electrically connected with the magnetoresistive element; wherein the gate width is substantially larger than the element width, and wherein the magnetoresistive elements of the memory layer are electrically connected in parallel to the selection transistor. | 06-21-2012 |
| 20120155155 | GENERATING A TEMPERATURE-COMPENSATED WRITE CURRENT FOR A MAGNETIC MEMORY CELL - This disclosure describes write current temperature compensation techniques for use in programming a data storage device that includes one or more memory cells. The techniques may include programming a programmable magnetization state of a magnetoresistive device included within a resistance network based on a signal indicative of the operating temperature of a magnetic memory cell. The techniques may further include generating a write current having a magnitude that is determined at least in part by the programmable magnetization state of the magnetoresistive device. The techniques may further include supplying the write current to the magnetic memory cell for programming a programmable magnetization state of the magnetic memory cell. | 06-21-2012 |
| 20120155156 | METHOD AND SYSTEM FOR PROVIDING MAGNETIC TUNNELING JUNCTION ELEMENTS HAVING IMPROVED PERFORMANCE THROUGH CAPPING LAYER INDUCED PERPENDICULAR ANISOTROPY AND MEMORIES USING SUCH MAGNETIC ELEMENTS - A method and system for providing a magnetic element and a magnetic memory utilizing the magnetic element are described. The magnetic element is used in a magnetic device that includes a contact electrically coupled to the magnetic element. The method and system include providing pinned, nonmagnetic spacer, and free layers. The free layer has an out-of-plane demagnetization energy and a perpendicular magnetic anisotropy corresponding to a perpendicular anisotropy energy that is less than the out-of-plane demagnetization energy. The nonmagnetic spacer layer is between the pinned and free layers. The method and system also include providing a perpendicular capping layer adjoining the free layer and the contact. The perpendicular capping layer induces at least part of the perpendicular magnetic anisotropy in the free layer. The magnetic element is configured to allow the free layer to be switched between magnetic states when a write current is passed through the magnetic element. | 06-21-2012 |
| 20120155157 | MAGNETIC RANDOM ACCESS MEMORY APPARATUS, METHODS FOR PROGRAMMING AND VERIFYING REFERENCE CELLS THEREFOR - A magnetic random access memory apparatus includes a memory cell array including a plurality of magnetic memory cells; a reference cell array including a pair of reference magnetic memory cells; a write driver configured to program data in the memory cell array and the reference cell array; and a first switching unit configured to form a current path which extends from a bit line connected to the write driver via the reference cell array including the pair of reference magnetic memory cells to a source line connected to the write driver or a current path which extends from a source line connected to the write driver via the reference cell array including the pair of reference magnetic memory cells to a bit line connected to the write driver. | 06-21-2012 |
| 20120155158 | STORAGE DEVICE AND WRITING CONTROL METHOD - A storage device is provided with a plurality of pairs of memory blocks, which have a storage layer which stores information and is configured to have a plurality of storage elements which store the information in the storage layer by the orientation of the magnetization of the storage layer being changed in accordance with the application of a writing voltage and so that selective application of the writing voltage is possible in accordance with input information to one storage element, and writing control sections, which store information which is to be written into each of the storage elements in a shift register, output one piece of information from the shift register, determine whether or not writing of the output information succeeds, and when writing has failed, the same information is output again, and when writing is successful, the next piece of information is output from the shift register. | 06-21-2012 |
| 20120155159 | MULTIBIT MAGNETIC RANDOM ACCESS MEMORY CELL WITH IMPROVED READ MARGIN - A magnetic random access memory (MRAM) cell including a magnetic tunnel junction including a tunnel barrier layer between a first magnetic layer having a first magnetization direction, and a second magnetic layer having a second adjustable magnetization to vary a junction resistance of the magnetic tunnel junction from a first to a second junction resistance level; said magnetic tunnel junction further including a switching resistant element electrically connected to the magnetic tunnel junction and having a switching resistance switchable from a first to a second switching resistance level when a switching current is passed through the switching resistant element, such that a resistance of the MRAM cell can have at least four different cell resistance levels depending of the resistance level of the junction resistance and the switching resistance. The disclosed MRAM cell achieves improved read margin and allows for writing at least four different cell resistance levels. | 06-21-2012 |
| 20120155160 | MEMORY CONTROLLER AND METHOD FOR INTERLEAVING DRAM AND MRAM ACCESSES - A memory controller and method for interleaving volatile and non-volatile memory different latencies and page sizes are described wherein a single DDR3 memory controller communicates with a number of memory modules comprising of at least non-volatile memory, e.g., spin torque magnetic random access memory, integrated in a different Rank or Channel with a volatile memory, e.g., dynamic random access memory (DRAM). | 06-21-2012 |
| 20120163069 | Memristor Device with Resistance Adjustable by Moving a Magnetic Wall by Spin Transfer and Use of Said Memristor in a Neural Network - A device with adjustable resistance includes two magnetic elements separated by an insulating or semi-conductor element. The resistance of the device depends on the position of a magnetic wall in one of the magnetic elements, the magnetic wall separating two areas of said magnetic element each having a separate homogeneous direction of magnetization. The device comprises means for moving the magnetic wall in the magnetic element by applying a spin-polarized electric current, such that the resistance of the device is adjustable in a continuous range of values. The invention is useful in neuromimetic circuits, neural networks and bio-inspired computers. | 06-28-2012 |
| 20120163070 | MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY - According to one embodiment, a magnetoresistive element includes a first magnetic layer with a perpendicular and variable magnetization, a second magnetic layer with a perpendicular and invariable magnetization, and a first nonmagnetic layer between the first and second magnetic layer. The first magnetic layer has a laminated structure of first and second ferromagnetic materials. A magnetization direction of the first magnetic layer is changed by a current which pass through the first magnetic layer, the first nonmagnetic layer and the second magnetic layer. A perpendicular magnetic anisotropy of the second ferromagnetic material is smaller than that of the first ferromagnetic material. A film thickness of the first ferromagnetic material is thinner than that of the second ferromagnetic material. | 06-28-2012 |
| 20120170357 | METHOD AND SYSTEM FOR PROVIDING MULTIPLE LOGIC CELLS IN A SINGLE STACK - A method and system for providing a magnetic junction usable in a magnetic device are described. The magnetic junction includes a pinned layer, a plurality of nonmagnetic spacer layers, and a plurality of free layers. The free layers are interleaved with the nonmagnetic spacer layers. A first nonmagnetic spacer layer of the nonmagnetic spacer layers is between the free layers and the pinned layer. Each of the free layers is configured to be switchable between stable magnetic states when a write current is passed through the magnetic junction. Each of the free layers has a critical switching current density. The critical switching current density of one of the free layers changes monotonically from the critical switching current density of an adjacent free layer. The adjacent free layer is between the pinned layer and the one of the plurality of free layers. | 07-05-2012 |
| 20120170358 | MRAM cell structure - Disclosed herein is an improved memory device, and related methods of manufacturing, wherein the area occupied by a conventional landing pad is significantly reduced to around | 07-05-2012 |
| 20120195112 | METHOD OF WRITING TO A SPIN TORQUE MAGNETIC RANDOM ACCESS MEMORY - A method includes destructively reading bits of a spin torque magnetic random access memory and immediately writing back the original or inverted values. A detection of the majority state of the write back bits and a conditional inversion of write back bits are employed to reduce the number of write back pulses. A subsequent write command received within a specified time or before an original write operation is commenced will cause a portion of the write back pulses or the original write operation pulses to abort. Write pulses during subsequent write operations will follow the conditional inversion determined for the write back bits during destructive read. | 08-02-2012 |
| 20120201073 | Memory Devices with Series-Interconnected Magnetic Random Access Memory Cells - A memory device includes magnetic random access memory (“MRAM”) cells that are electrically connected in series, each one of the MRAM cells having a storage magnetization direction and a sense magnetization direction. During a write operation, multiple ones of the MRAM cells are written in parallel by switching the storage magnetization directions of the MRAM cells. During a read operation, a particular one of the MRAM cells is read by varying the sense magnetization direction of the particular one of the MRAM cells, relative to the storage magnetization direction of the particular one of the MRAM cells. | 08-09-2012 |
| 20120201074 | Magnetic Random Access Memory Devices Configured for Self-Referenced Read Operation - A magnetic random access memory cell includes a sense layer, a storage layer, and a spacer layer disposed between the sense layer and the storage layer. During a write operation, the storage layer has a magnetization direction that is switchable between m directions to store data corresponding to one of m logic states, with m>2. During a read operation, the sense layer has a magnetization direction that is varied, relative to the magnetization direction of the storage layer, to determine the data stored by the storage layer. | 08-09-2012 |
| 20120201075 | MAGNETIC MEMORY WITH ASYMMETRIC ENERGY BARRIER - A magnetic tunnel junction memory cell includes a ferromagnetic reference layer, a ferromagnetic free layer, and a non-magnetic barrier layer separating the ferromagnetic reference layer from the ferromagnetic free layer. The magnetic tunnel junction cell has an asymmetric energy barrier for switching between a high resistance data state and a low resistance data state. Memory devices and methods are also described. | 08-09-2012 |
| 20120201076 | SPINTRONIC DEVICES WITH INTEGRATED TRANSISTORS - The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated Giant-Magneto-resistive (GMR) structures. The present teachings relates to integrated latch memory and logic devices and, in particular, concerns a spin dependent logic device that may be integrated with conventional semiconductor-based logic devices to construct high-speed non-volatile static random access memory (SRAM) cells. | 08-09-2012 |
| 20120212998 | Non-Volatile Perpendicular Magnetic Memory with Low Switching Current and High Thermal Stability - A non-volatile current-switching magnetic memory element includes a bottom electrode, a pinning layer formed on top of the bottom electrode, and a fixed layer formed on top of the pinning layer. The non-volatile current-switching magnetic memory element further includes a tunnel layer formed on top of the pinning layer, a first free layer with a perpendicular anisotropy that is formed on top of the tunnel layer, a granular film layer formed on top of the free layer, a second free layer formed on top of the granular film layer, a cap layer formed on top of the second layer, and a top electrode formed on top of the cap layer. | 08-23-2012 |
| 20120218813 | Magnetic Memory Devices - Magnetic memory devices are provided, the devices include at least memory cell and a reference cell on a substrate. The memory cells include a first base magnetic layer, a free layer, and a first tunnel barrier layer between the first base magnetic layer and free layer. The reference memory cell includes a second base magnetic layer, a reference magnetic layer, and a second tunnel barrier layer between the second base magnetic layer and reference magnetic layer. The reference magnetic layer has a magnetic direction substantially perpendicular to that of the free layer. | 08-30-2012 |
| 20120224416 | MAGNETIC MEMORY AND MAGNETIC MEMORY APPARATUS - A magnetic memory includes a first magnetic layer, a second magnetic layer, a third magnetic layer, a first intermediate layer, a second intermediate layer, an insulator film, and an electrode. The third magnetic layer is provided between the first magnetic layer and the second magnetic layer in a first direction being perpendicular to the plane of both the first magnetic layer and the second magnetic layer. The insulator film is provided on the third magnetic layer in a second direction perpendicular to the first direction. The electrode is provided on the insulator film so that the insulator is sandwiched between the third magnetic layer and the electrode in the second direction. In addition, a positive voltage is applied to the electrode and a first current passes from the first magnetic layer to the second magnetic layer, thereby writing information to the second magnetic layer. | 09-06-2012 |
| 20120224417 | DIODE ASSISTED SWITCHING SPIN-TRANSFER TORQUE MEMORY UNIT - A memory array includes a cross-point array of bit and source lines. A memory is disposed at cross-points of the cross-point array. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. A transistor is electrically between the magnetic tunnel junction data cell and the bit line or source line and a diode is in thermal or electrical contact with the magnetic tunnel junction data cell to assist in resistance state switching. | 09-06-2012 |
| 20120230089 | MAGNETORESISTANCE ELEMENT AND NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE USING SAME MAGNETORESISTANCE ELEMENT - A magnetoresistance element is disclosed. The magnetoresistance element includes a magnetic tunnel junction portion configured by sequentially stacking a perpendicularly magnetized first magnetic body, an insulation layer, and a perpendicularly magnetized second magnetic body. The second magnetic body has a configuration wherein a ferromagnetic layer and a rare earth-transition metal alloy layer are stacked sequentially from the insulation layer side interface. A heat assist layer that heats the second magnetic body with a heat generated based on a current flowing through the magnetic tunnel junction portion is further provided. | 09-13-2012 |
| 20120230090 | SEMICONDUCTOR MEMORY - A semiconductor memory has a first switch circuit and a second switch circuit. The semiconductor memory has a row decoder that controls a voltage of a word line. The semiconductor memory has a first writing circuit including a first signal terminal connected to one end of the first switch circuit to input and output a writing current. The semiconductor memory has a second writing circuit including a second signal terminal connected to a one end of the second switch circuit to input and output the writing current. The semiconductor memory has a select transistor including a control terminal connected to the word line. The semiconductor memory has a resistance change element that is connected in series with the select transistor between the first bit line and the second bit line and varies in resistance value depending on an applied current. | 09-13-2012 |
| 20120230091 | MAGNETIC MEMORY - According to one embodiment, a magnetic memory includes at least one memory cell including a magnetoresistive element, and first and second electrodes. The element includes a first magnetic layer, a tunnel barrier layer, a second magnetic layer, and a third magnetic layer provided on the second magnetic layer and having a magnetization antiparallel to the magnetization direction of the second magnetic layer. A diameter of an upper surface of the first magnetic layer is smaller than that of a lower surface of the tunnel barrier layer. A diameter of a lower surface of the second magnetic layer is not more than that of an upper surface of the tunnel barrier layer. | 09-13-2012 |
| 20120230092 | THERMALLY ASSISTED MULTI-BIT MRAM - Methods of writing to a multi-bit MRAM memory unit are described. The method includes to self-detected writing to a multi-bit (i.e., multilevel) thermally assisted MRAM. The self-detected writing increases a reading margin between data state levels and decreases reading margin variability due to cell resistance variation. | 09-13-2012 |
| 20120230093 | TRANSMISSION GATE-BASED SPIN-TRANSFER TORQUE MEMORY UNIT - A transmission gate-based spin-transfer torque memory unit is described. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. A NMOS transistor is in parallel electrical connection with a PMOS transistor and they are electrically connected with the source line and the magnetic tunnel junction data cell. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. The PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor. | 09-13-2012 |
| 20120230094 | BIT LINE CHARGE ACCUMULATION SENSING FOR RESISTIVE CHANGING MEMORY - A memory array includes a plurality of magneto-resistive changing memory cells. Each resistive changing memory cell is electrically between a source line and a bit line and a transistor electrically between the resistive changing memory cell and the bit line. The transistor has a gate electrically between a source region and a drain region and the source region being electrically between the r magneto-resistive changing memory cell and the gate. A word line is electrically coupled to the gate. A bit line charge accumulation sensing for magneto-resistive changing memory is also disclosed. | 09-13-2012 |
| 20120230095 | NON-VOLATILE MAGNETIC MEMORY ELEMENT WITH GRADED LAYER - A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound. | 09-13-2012 |
| 20120236631 | MAGNETIC TUNNELING JUNCTION DEVICES, MEMORIES, ELECTRONIC SYSTEMS, AND MEMORY SYSTEMS, AND METHODS OF FABRICATING THE SAME - Provided is a magnetic tunneling junction device including a fixed magnetic structure; a free magnetic structure; and a tunnel barrier between the fixed magnetic structure and the free magnetic structure, at least one of the fixed magnetic structure and the free magnetic structure including a perpendicular magnetization preserving layer, a magnetic layer between the perpendicular magnetization preserving layer and the tunnel barrier, and a perpendicular magnetization inducing layer between the perpendicular magnetization preserving layer and the magnetic layer. | 09-20-2012 |
| 20120236632 | DATA STORAGE METHODS AND DEVICES - A data storage method includes writing data to a ferromagnetic shape-memory material in its ferromagnetic state, the material exhibiting more than two stable states. A data storage device includes a non-volatile memory element containing a ferromagnetic shape-memory alloy in a martensite state, the shape-memory alloy being ferromagnetic in a plurality of stable states of the memory element. | 09-20-2012 |
| 20120243303 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device according to the present embodiment includes a magnetic tunnel junction element capable of storing data according to a change in resistance state and rewriting the data using a current. A cell transistor is provided for the magnetic tunnel junction element and is placed in a conducting state when a current is allowed to flow through the magnetic tunnel junction element. A current limiter limits a current flowing through the cell transistor and the magnetic tunnel junction element upon data writing. | 09-27-2012 |
| 20120243304 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device according to the present embodiment comprises a plurality of bit lines, a plurality of word lines, and a plurality of memory cells corresponding to intersections between the bit lines and the word lines, respectively, and including magnetic tunnel junction elements capable of storing data. A plurality of sense amplifiers respectively correspond to the bit lines and are configured to detect data stored in the memory cells via a bit line selected from among the corresponding bit lines. A plurality of read latch parts correspond to the sense amplifiers, respectively, and are configured to latch data detected by the corresponding sense amplifiers. A plurality of read global data buses are connected to the read latch parts, respectively, and are configured to consecutively transmit data latched by the read latch parts at a time of a data read operation. | 09-27-2012 |
| 20120243305 | MAGNETORESISTANCE EFFECT ELEMENT AND MAGNETIC MEMORY - According to one embodiment, a magnetoresistance effect element includes first and second magnetic layers having an axis of easy magnetization in a direction perpendicular to a film surface, a first nonmagnetic layer formed between the first and second magnetic layers, a first interface magnetic layer formed between the first magnetic layer and the first nonmagnetic layer, and a second nonmagnetic layer formed in the first interface magnetic layer and having an amorphous structure. An electric current flowing through the first magnetic layer, the first nonmagnetic layer, and the second magnetic layer makes a magnetization direction in the first magnetic layer variable. | 09-27-2012 |
| 20120250399 | MEMORY CIRCUIT USING SPIN MOSFETS, PATH TRANSISTOR CIRCUIT WITH MEMORY FUNCTION, SWITCHING BOX CIRCUIT, SWITCHING BLOCK CIRCUIT, AND FIELD PROGRAMMABLE GATE ARRAY - A memory circuit according to an embodiment includes: a first transistor including a first source/drain electrode, a second source/drain electrode, and a first gate electrode; a second transistor including a third source/drain electrode connected to the second source/drain electrode, a fourth source/drain electrode, and a second gate electrode; a third transistor and a fourth transistor forming an inverter circuit, the third transistor including a fifth source/drain electrode, a sixth source/drain electrode, and a third gate electrode connected to the second source/drain electrode, the fourth transistor including a seventh source/drain electrode connected to the sixth source/drain electrode, an eighth source/drain electrode, and a fourth gate electrode connected to the second source/drain electrode; and an output terminal connected to the sixth source/drain electrode. At least one of the third transistor and the fourth transistor is a spin MOSFET, and an output of the inverter circuit is sent from the output terminal. | 10-04-2012 |
| 20120250400 | SEMICONDUCTOR MEMORY DEVICE - The control circuit selects, as the first reference cell, the first memory cell having a maximum reading current supplied by turning on the first select transistor in a state in which resistance values of the first memory cells are all increased. The control circuit selects, as the second reference cell, the second memory cell having a maximum reading current supplied by turning on the second select transistor in a state in which resistance values of the second memory cells are all increased. | 10-04-2012 |
| 20120257444 | WRITE DRIVER CIRCUIT FOR MRAM, MRAM AND LAYOUT STRUCTURE THEREOF - A write driver circuit for a magnetic random access memory includes a memory cell array including a plurality of magnetic memory cells in which a pair of magnetic memory cells adjacent to each other in a direction of a bit line share a source line, and each magnetic memory cell is connected between the bit line and the source line. The write driver circuit includes a switching unit connected between a terminal for supplying a positive recording voltage and a terminal for supplying a negative recording voltage to selectively supply current generated by the positive recording voltage or the negative recording voltage to the bit line according to a write enable signal and a data signal. | 10-11-2012 |
| 20120257445 | NONVOLATILE MEMORY APPARATUS HAVING MAGNETORESISTIVE MEMORY ELEMENTS AND METHOD FOR DRIVING THE SAME - A semiconductor memory apparatus includes a source line, a first bit line disposed over the source line, a second bit line disposed under the source line, a first memory cell between the source line and the first bit line, and a second memory cell between the source line and the second bit line. | 10-11-2012 |
| 20120257446 | UNIPOLAR SPIN-TRANSFER SWITCHING MEMORY UNIT - A memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a word line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a unipolar voltage across the magnetic tunnel junction data cell. A diode is electrically coupled between the magnetic tunnel junction data cell and the word line or bit line. A voltage source provides the unipolar voltage across the magnetic tunnel junction data cell that writes the high resistance state and the low resistance state. | 10-11-2012 |
| 20120257447 | MAGNETIC TUNNEL JUNCTION WITH COMPENSATION ELEMENT - A magnetic tunnel junction having a compsensation element is disclosed. The magnetic tunnel junction includes a reference element, and a compensation element having an opposite magnetization moment to a magnetization moment of the reference element. A free magnetic layer is between the reference element and the compensation element, and an electrically insulating and non-magnetic tunneling barrier layer separates the free magnetic layer from the reference element. The free magnetic layer includes Co | 10-11-2012 |
| 20120275218 | SPIN TORQUE TRANSFER CELL STRUCTURE UTILIZING FIELD-INDUCED ANTIFERROMAGNETIC OR FERROMAGNETIC COUPLING - A magnetic memory cell including a soft magnetic layer and a coupling layer, and methods of operating the memory cell are provided. The memory cell includes a stack with a free ferromagnetic layer and a pinned ferromagnetic layer, and a soft magnetic layer and a coupling layer may also be formed as layers in the stack. The coupling layer may cause antiferromagnetic coupling to induce the free ferromagnetic layer to be magnetized in a direction antiparallel to the magnetization of the soft magnetic layer, or the coupling layer may cause ferromagnetic coupling to induce the free ferromagnetic layer to be magnetized in a direction parallel to the magnetization of the soft magnetic layer. The coupling layer, through a coupling effect, reduces the critical switching current of the memory cell. | 11-01-2012 |
| 20120275219 | Shared Transistor in a Spin-Torque Transfer Magnetic Random Access Memory (STTMRAM) Cell - A spin-torque transfer memory random access memory (STTMRAM) cell is disclosed comprising a selected magnetic tunnel junction (MTJ) identified to be programmed; a first transistor having a first port, a second port and a gate, the first port of the first transistor coupled to the selected MTJ; a first neighboring MTJ coupled to the selected MTJ through the second port of the first transistor; a second transistor having a first port, a second port, and a gate, the first port of the second transistor coupled to the selected MTJ; a second neighboring MTJ coupled to the selected MTJ through the second port of the second transistor; a first bit/source line coupled to the second end of the selected MTJ; and a second bit/source line coupled to the second end of the first neighboring MTJ and the second end of the second neighboring MTJ. | 11-01-2012 |
| 20120281460 | NONCONTACT WRITING OF NANOMETER SCALE MAGNETIC BITS USING HEAT FLOW INDUCED SPIN TORQUE EFFECT - A mechanism is provided for noncontact writing. Multiple magnetic islands are provided on a nonmagnetic layer. A reference layer is provided under the nonmagnetic layer. A spin-current is caused to write a state to a magnetic island of the multiple magnetic islands by moving a heat source to heat the magnetic island. | 11-08-2012 |
| 20120281461 | SEMICONDUCTOR STORAGE DEVICE - A memory includes MTJ elements. Active areas are separated to correspond to cell transistors, respectively, and extend in a first direction substantially orthogonal to an extending direction of gates of the cell transistors. The active areas are arranged in the first direction and constitute a plurality of active area columns. Two active area columns adjacent in a second direction are arranged to be half-pitch staggered in the first direction. As viewed from above surfaces of the active areas, each MTJ element is arranged to overlap with one end of each of the active areas. The first and second wirings extend while being folded back in a direction inclined with respect to the first and second directions in order to overlap with the MTJ elements alternately in the adjacent active area columns. | 11-08-2012 |
| 20120281462 | STORAGE ELEMENT AND STORAGE DEVICE - A storage element includes a storage layer that stores information on the basis of a magnetization state of a magnetic material; a fixed magnetization layer that has a magnetization serving as a reference of the information stored in the storage layer; an interlayer that is formed of a nonmagnetic material and interposed between the storage layer and the fixed magnetization layer; a cap layer that is provided to be adjacent to the storage layer and opposite to the interlayer; and a metal cap layer that is provided to be adjacent to the cap layer and opposite to the storage layer. | 11-08-2012 |
| 20120281463 | MAGNETORESISTIVE EFFECT ELEMENT, AND MAGNETIC RANDOM ACCESS MEMORY - A magnetoresistive effect element includes: a
| 11-08-2012 |
| 20120281464 | Raising Programming Currents of Magnetic Tunnel Junctions Using Word Line Overdrive and High-k Metal Gate - A method of operating magneto-resistive random access memory (MRAM) cells includes providing an MRAM cell, which includes a magnetic tunneling junction (MTJ) device; and a selector comprising a source-drain path serially coupled to the MTJ device. The method further includes applying an overdrive voltage to a gate of the selector to turn on the selector. | 11-08-2012 |
| 20120281465 | High Density Magnetic Random Access Memory - One embodiment of a magnetic memory device comprises a substrate and a plurality of planar memory arrays stacked on the substrate, each memory array includes a plurality of parallel first conductive lines, each first conductive line includes a ferromagnetic cladding, a plurality of parallel second conductive lines overlapping the first conductive lines at a plurality of intersection regions, a plurality of magnetic tunnel junctions, each magnetic tunnel junction has a controllable electrical resistance, is disposed at an intersection region and electrically coupled to one of the first conductive lines at its first end and to one of the second conductive lines at its second end. The electrical resistance of the magnetic tunnel junction is controlled by a joint effect of a spin-polarized current running between the first and second ends and a bias magnetic field applied simultaneously to said each magnetic tunnel junction. Other embodiments are described and shown. | 11-08-2012 |
| 20120287704 | SPIN CURRENT GENERATOR FOR STT-MRAM OR OTHER SPINTRONICS APPLICATIONS - Spin current generators and systems and methods for employing spin current generators. A spin current generator may be configured to generate a spin current polarized in one direction, or a spin current selectively polarized in two directions. The spin current generator may by employed in spintronics applications, wherein a spin current is desired. | 11-15-2012 |
| 20120287705 | Spin-Torque Transfer Magneto-Resistive Memory Architecture - A method for operating a memory array device, includes initiating a write “0” state in the device, wherein the initiating the write “0” state includes inducing a first voltage in a word line of the device; and inducing a second voltage in a first bit line (BLT | 11-15-2012 |
| 20120294071 | Spin-Torque Transfer Magneto-Resistive Memory Architecture - A system includes a processor and a memory array connected to the processor comprising a first memory cell comprising a first magnetic tunnel junction device having a first terminal connected to a first bit line and a second terminal, and a first field effect transistor having a source terminal connected to a second bit line, a gate terminal connected to a word line, and a drain terminal connected to the second terminal of the first magnetic tunnel junction device, and a second memory cell comprising a second magnetic tunnel junction device having a first terminal connected to a third bit line and a second terminal, and a second field effect transistor having a source terminal connected to the second bit line, a gate terminal connected to the word line, and a drain terminal connected to the second terminal of the second magnetic tunnel junction device. | 11-22-2012 |
| 20120300539 | MULTIBIT CELL WITH SYNTHETIC STORAGE LAYER - Method for writing and reading more than two data bits to a MRAM cell comprising a magnetic tunnel junction formed from a read magnetic layer having a read magnetization, and a storage layer comprising a first storage ferromagnetic layer having a first storage magnetization, a second storage ferromagnetic layer having a second storage magnetization; the method comprising: heating the magnetic tunnel junction above a high temperature threshold; and orienting the first storage magnetization at an angle with respect to the second storage magnetization such that the magnetic tunnel junction reaches a resistance state level determined by the orientation of the first storage magnetization relative to that of the read magnetization. The method allows for storing at least four distinct state levels in the MRAM cell using only one current line to generate a writing field. | 11-29-2012 |
| 20120300540 | TRANSIENT HEAT ASSISTED STTRAM CELL FOR LOWER PROGRAMMING CURRENT - A memory cell including magnetic materials and heating materials, and methods of programming the memory cell are provided. The memory cell includes a free region, a pinned region, and a heating region configured to generate and transfer heat to the free region when a programming current is directed to the cell. The heat transferred from the heating region increases the temperature of the free region, which decreases the magnetization and the critical switching current density of the free region. In some embodiments, the heating region may also provide a current path to the free region, and the magnetization of the free region may be switched according to the spin polarity of the programming current, programming the memory cell to a high resistance state or a low resistance state. | 11-29-2012 |
| 20120314487 | Magnetic Random Access Memory Devices Including Multi-Bit Cells - A magnetic random access memory (“MRAM”) cell includes: (1) a first magnetic layer having a first magnetization direction and a magnetic anisotropy axis; (2) a second magnetic layer having a second magnetization direction; and (3) a spacer layer disposed between the first magnetic layer and the second magnetic layer. The MRAM cell also includes a field line magnetically coupled to the MRAM cell and configured to induce a write magnetic field along a magnetic field axis, and the magnetic anisotropy axis is tilted relative to the magnetic field axis. During a write operation, the first magnetization direction is switchable between m directions to store data corresponding to one of m logic states, with m>2, at least one of the m directions is aligned relative to the magnetic anisotropy axis, and at least another one of the m directions is aligned relative to the magnetic field axis. | 12-13-2012 |
| 20120314488 | Magnetic Random Access Memory Devices Including Multi-Bit Cells - A magnetic random access memory (MRAM) cell includes a storage layer, a sense layer, and a spacer layer between the storage layer and the sense layer. A field line is magnetically coupled to the MRAM cell to induce a magnetic field along a magnetic field axis, and at least one of the storage layer and the sense layer has a magnetic anisotropy axis that is tilted relative to the magnetic field axis. During a write operation, a storage magnetization direction is switchable between m directions to store data corresponding to one of m logic states, with m>2, where at least one of the m directions is aligned relative to the magnetic anisotropy axis, and at least another one of the m directions is aligned relative to the magnetic field axis. During a read operation, a sense magnetization direction is varied, relative to the storage magnetization direction, to determine the data stored by the storage layer. | 12-13-2012 |
| 20120314489 | SYSTEMS AND METHODS FOR DIRECT COMMUNICATION BETWEEN MAGNETIC TUNNEL JUNCTIONS - Systems and methods that enable direct communications between magnetic tunnel junctions are provided. In one embodiment, a device includes multiple input magnetic tunnel junctions and an output magnetic tunnel junction. The multiple input magnetic tunnel junctions are connected in parallel, and the output magnetic tunnel junction is connected in series to the input magnetic tunnel junctions. In another embodiment, a device includes a first magnetic tunnel junction, a second magnetic tunnel junction, and a nano-magnetic channel. Each of the first and the second magnetic tunnel junctions has a free layer, a nonmagnetic layer, and a fixed layer. The nano-magnetic channel connects the free layer of the first magnetic tunnel junction to the free layer of the second magnetic tunnel junction. | 12-13-2012 |
| 20120314490 | MAGNETIC MEMORY SYSTEM AND METHODS IN VARIOUS MODES OF OPERATION - A magnetic memory system includes a superconductor circuit and one or more magnetic memory elements to store data. To write data, a driver circuit in the superconductor circuit generates a magnetic signal for transmission over a superconductor link extending between the superconductor circuit and the magnetic memory element. To read data, a sensing circuit in the superconductor circuit monitors a superconductor link extending from sensing circuit to the magnetic memory element. The magnetic memory element can be a spin-transfer type magnetic memory element. | 12-13-2012 |
| 20120320665 | SEMICONDUCTOR MEMORY - A semiconductor memory includes a first memory cell including: a first resistance change element and a first select transistor. The semiconductor memory includes a second memory cell including: a second select transistor and a second resistance change element. The semiconductor memory includes a third memory cell including: a third select transistor and a third resistance change element, the third memory cell acting as a reference cell. The semiconductor memory includes a fourth memory cell including: a fourth resistance change element and a fourth select transistor, the fourth memory cell acting as a reference cell. | 12-20-2012 |
| 20120320666 | Magnetoresistive Element and Magnetic Memory - There is provided a magnetoresistive element whose magnetization direction is stable in a direction perpendicular to the film surface and whose magnetoresistance ratio is controlled, as well as magnetic memory using such a magnetoresistive element. By having the material of a ferromagnetic layer forming the magnetoresistive element comprise a ferromagnetic material containing at least one type of | 12-20-2012 |
| 20120320667 | MAGNETIC RANDOM ACCESS MEMORY - A magnetic random access memory according to the present invention is provided with: a magnetic recording layer including a magnetization free region having a reversible magnetization, wherein a write current is flown through the magnetic recording layer in an in-plane direction; a magnetization fixed layer having a fixed magnetization; a non-magnetic layer provided between the magnetization free region and the magnetization fixed layer; and a heat sink structure provided to be opposed to the magnetic recording layer and having a function of receiving and radiating heat generated in the magnetic recording layer. The magnetic random access memory thus-structured radiates heat generated in the magnetic recording layer by using the heat sink structure, suppressing the temperature increase caused by the write current flown in the in-plane direction. | 12-20-2012 |
| 20120327706 | SPIN-TORQUE TRANSFER MEMORY CELL STRUCTURES WITH SYMMETRIC SWITCHING AND SINGLE DIRECTION PROGRAMMING - Techniques are provided for programming a spin torque transfer magnetic random access memory (STT-MRAM) cell using a unidirectional and/or symmetrical programming current. A unidirectional programming current flows through the free region of the STT-MRAM cell in one direction to switch the magnetization of the free region in at least two different directions. A symmetrical programming current switches the magnetization of the free region to either of the two different directions using a substantially similar current magnitude. In some embodiments, the STT-MRAM cell includes two fixed regions, each having fixed magnetizations in opposite directions and a free region configured to be switched in magnetization to be either parallel with or antiparallel to the magnetization of one of the fixed regions. Switching the free region to different magnetization directions may involve directing the programming current through one of the two oppositely magnetized fixed regions. | 12-27-2012 |
| 20120327707 | MAGNETIC RANDOM ACCESS MEMORY DEVICE AND METHOD OF WRITING DATA THEREIN - In a method of writing data in an MRAM device, a first operation unit is selected in a plurality of memory cells of the MRAM device. First to n-th switching pulses are sequentially applied to the first operation unit to write data in first to n-th groups of memory cells of the first operation unit, respectively. The n-th switching pulse may have a current level lower than that of an (n−1)th switching pulse, where n is an integer larger than at least 1. The n-th switching pulse may have a pulse width narrower than that of an (n−1)th switching pulse, where n is an integer larger than at least 1. The technique can be repeated for a second operation unit. A device and system are disclosed in which different current switching pulses are applied to multiple groups of memory cells within the first and/or second operation units. | 12-27-2012 |
| 20130003447 | SENSING CIRCUIT - A circuit includes a degeneration p-channel metal-oxide-semiconductor (PMOS) transistor, a load PMOS transistor, and a clamp transistor configured to clamp a voltage applied to a resistance based memory element during a sensing operation. A gate of the load PMOS transistor is controlled by an output of a not-AND (NAND) circuit. | 01-03-2013 |
| 20130003448 | MRAM DIODE ARRAY AND ACCESS METHOD - A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode. | 01-03-2013 |
| 20130010532 | MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY USING THE SAME - According to one embodiment, a magnetoresistive element includes first and second magnetic layers and a first nonmagnetic layer. The first magnetic layer has an axis of easy magnetization perpendicular to a film plane, and a variable magnetization. The second magnetic layer has an axis of easy magnetization perpendicular to a film plane, and an invariable magnetization. The first nonmagnetic layer is provided between the first and second magnetic layers. The second magnetic layer includes third and fourth magnetic layers, and a second nonmagnetic layer formed between the third and fourth magnetic layers. The third magnetic layer is in contact with the first nonmagnetic layer and includes Co and at least one of Zr, Nb, Mo, Hf, Ta, and W. | 01-10-2013 |
| 20130016553 | MRAM Sensing with Magnetically Annealed Reference CellAANM Rao; Hari M.AACI San DiegoAAST CAAACO USAAGP Rao; Hari M. San Diego CA USAANM Zhu; XiaochunAACI San DiegoAAST CAAACO USAAGP Zhu; Xiaochun San Diego CA US - Systems and method for reading/sensing data stored in magnetoresistive random access memory (MRAM) cells using magnetically annealed reference cells. A MRAM includes a reference circuit comprising at least one magnetic storage cell, wherein each magnetic storage cell in the MRAM is programmed to the same state. The reference circuit includes a load element coupled to the magnetic storage cell, wherein the load element is configured to establish a reference voltage during a read operation. | 01-17-2013 |
| 20130016554 | METHOD AND APPARATUS FOR INCREASING THE RELIABILITY OF AN ACCESS TRANSITOR COUPLED TO A MAGNETIC TUNNEL JUNCTION (MTJ) - A method of writing to a magnetic tunnel junction (MTJ) of a magnetic memory array includes an access transistor coupled to the MTJ for reading of and writing to the MTJ, where when the MTJ is written to, at times, by switching its magnetic orientation from an anti-parallel to a parallel magnetic orientation, a bit line that is coupled to one end of the MTJ is raised to Vcc and a voltage that is the sum of Vcc and Vx is applied to the gate of the access transistor, with Vx being approximately the voltage at an opposite end of the MTJ. Further, the voltage of a Source Line (SL), which is coupled to the MTJ using a first transistor of a write driver that is also coupled to the SL, is regulated such that SL remains sufficiently above 0 volts to avoid violation of Vgs exceeding Vcc where Vgs is the gate to source voltage of the access transistor. | 01-17-2013 |
| 20130021841 | PERPENDICULAR MAGNETIC RANDOM ACCESS MEMORY (MRAM) DEVICE WITH A STABLE REFERENCE CELL - A magnetic random access memory (MRAM) element is configured to store a state when electric current flows and includes a first magnetic tunnel junction (MTJ) for storing a data bit and a second MTJ for storing a reference bit. The direction of magnetization of the FL is determinative of the data bit stored in the at least one MTJ. Further, the MTJ includes a magnetic reference layer (RL) having a magnetization with a direction that is perpendicular to the film plane, and a magnetic pinned layer (PL) having a magnetization with a direction that is perpendicular to the film plane. The direction of magnetization of the RL and the PL are anti-parallel relative to each other in the first MTJ. The direction of magnetization of the FL, the RL and the PL are parallel relative to each other in the second MTJ. | 01-24-2013 |
| 20130021842 | INITIALIZATION METHOD OF A PERPENDICULAR MAGNETIC RANDOM ACCESS MEMORY (MRAM) DEVICE WITH A STABLE REFERENCE CELL - A method of initializing a magnetic random access memory (MRAM) element that is configured to store a state when electric current flows therethrough is disclosed. The MRAM element includes a first magnetic tunnel junction (MTJ) for storing a data bit and a second MTJ for storing a reference bit. Each MTJ further includes a magnetic reference layer (RL) having a magnetization with a direction that is perpendicular to the film plane, and a magnetic pinned layer (PL) having a magnetization with a direction that is perpendicular to the film plane. The direction of magnetization of the RL and the PL are anti-parallel relative to each other in the first MTJ. The direction of magnetization of the FL, the RL and the PL are parallel relative to each other in the second MTJ for storing reference bit. | 01-24-2013 |
| 20130021843 | SEMICONDUCTOR DEVICE INCORPORATING MULTI-VALUE MAGNETIC MEMORY CELLS - A semiconductor device includes a memory cell. The memory cell includes: a magnetic recording layer formed of ferromagnetic material; first and second magnetization fixed layers coupled to the magnetic recording layer; a plurality of reference layers opposed to the magnetic recording layer; and a plurality of tunnel barrier films respectively inserted between the magnetic recording layer and the reference layers. The first magnetization fixed layer has a magnetization fixed in a first direction, and the second magnetization fixed layer has a magnetization fixed in a second direction opposite to first direction. The reference layers each have a magnetization fixed in the first direction or the second direction. The reference layers and the tunnel barrier layers are positioned between the first and second magnetization fixed layers. | 01-24-2013 |
| 20130028009 | NON-VOLATILE MEMORY SAVING CELL INFORMATION IN A NON-VOLATILE MEMORY ARRAY - Systems and methods for saving repair cell address information in a non-volatile magnetoresistive random access memory (MRAM) having an array of MRAM cells are disclosed. A memory access circuit is coupled to the MRAM, and is configured to store failed cell address information in the MRAM. | 01-31-2013 |
| 20130028010 | Fast MTJ Switching Write Circuit For MRAM Array - A transmission gate is arranged between a current source and a resistive memory element, a PMOS gate of the transmission gate has no source loading effect and a write current passes from the current source, and in a first direction through the resistive memory element, setting the resistive memory element to a magnetization state. An NMOS gate of the of the transmission gate has no source loading effect and another write current, passes through the resistive memory element, in a second direction opposite the first direction, and through the transmission gate, setting the resistive memory element to an opposite magnetization state. | 01-31-2013 |
| 20130028011 | MAGNETORESISTIVE DEVICE AND MAGNETIC MEMORY - A magnetoresistive device of an embodiment includes: first and second devices each including, a first magnetic layer having a changeable magnetization perpendicular to a film plane, a second magnetic layer having a fixed and perpendicular magnetization, and a nonmagnetic layer interposed between the first and second magnetic layers, the first and second devices being disposed in parallel on a first face of an interconnect layer; and a TMR device including a third magnetic layer having perpendicular magnetic anisotropy and having a changeable magnetization, a fourth magnetic layer having a fixed magnetization parallel to a film plane, and a tunnel barrier layer interposed between the third and fourth magnetic layers, the TMR device being disposed on a second face of the interconnect layer, and the third magnetic layer being magnetostatically coupled to the first magnetic layers of the first and second devices. | 01-31-2013 |
| 20130028012 | SEMICONDUCTOR INTEGRATED CIRCUIT AND PROCESSOR - In one embodiment, there is provided a semiconductor integrated circuit that includes: a first inverter; a second inverter; a first transistor, wherein one end of the first transistor is connected to a first bit line and the other end of the first transistor is connected to a first input terminal of the first inverter; a first element group including second transistors, wherein one end of the first element group is connected to a first output terminal of the first inverter and the other end of the first element group is connected to a second bit line; and a second element group including third transistors and a magnetoresistive element whose magnetic resistance is varied. The second element group is disposed between the second output terminal of the second inverter and a first terminal or disposed between the first transistor and the first terminal. | 01-31-2013 |
| 20130028013 | MAGNETORESISTIVE EFFECT ELEMENT, MAGNETIC MEMORY CELL USING SAME, AND RANDOM ACCESS MEMORY - Provided is a magnetoresistive effect element which uses a perpendicularly magnetized material and has a high TMR ratio. Intermediate layers | 01-31-2013 |
| 20130033927 | MAGENTIC RESISTANCE MEMORY APPARATUS HAVING MULTI LEVELS AND METHOD OF DRIVING THE SAME - A magnetic resistance memory apparatus capable of implementing various levels and a method of driving the same are provided. The magnetic resistance memory apparatus includes a first magnetic device that includes a fixed layer having a fixed magnetization direction, a tunnel layer disposed on the fixed layer, and a first free layer disposed on the tunnel layer having a variable magnetization direction, and a second magnetic device disposed on the first magnetic device including a plurality of free layers insulated with a spacer layer interposed. | 02-07-2013 |
| 20130033928 | SEMICONDUCTOR STORAGE DEVICE AND DATA PROCESSING METHOD - Since a nonvolatile RAM allows random reading and writing operations, an erasing mode is unnecessary. From the system side, however, it is desirable to have the erasing mode because of its nonvolatile characteristic. Moreover, the erasing operation is desirably carried out at high speed with low power consumption. Therefore, memory cell arrays COA and DTA containing a plurality of memory cells MC each having a magnetoresistive element are provided, a series of data is written to the memory cell arrays COA and DTA, and at the time of erasing, an erasing operation is carried out by writing predetermined data only to the memory cell array COA. | 02-07-2013 |
| 20130039121 | MAGNETIC TUNNEL JUNCTION AND SPIN TRANSFER TORQUE RANDOM ACCESS MEMORY HAVING THE SAME - A magneto-resistance memory device includes a first pinned layer having a first magnetic polarity regardless of current applied to the first pinned layer, a first tunnel insulating layer arranged on the first pinned layer, a first free layer arranged on the first tunnel insulating layer and having a magnetic polarity that changes in response to current of a first amount, a second pinned layer coupled to the first free layer and having the first magnetic polarity regardless of current applied to the first pinned layer, a second tunnel insulating layer arranged on the second pinned layer, a second free layer arranged on the second tunnel insulating layer and having a magnetic polarity that changes in response to current of a second amount, wherein the second amount is smaller than the first amount, and a connection layer. | 02-14-2013 |
| 20130039122 | MAGNETORESISTIVE RANDOM ACCESS MEMORY - A magnetoresistive random access memory includes a memory cell line in which memory cells are formed and write bit lines. The memory cell line | 02-14-2013 |
| 20130044537 | MAGNETIC MEMORY, METHOD OF MANUFACTURING THE SAME, AND METHOD OF DRIVING THE SAME - There is provided a magnetic memory with using a magnetoresistive effect element of a spin-injection magnetization reversal type, in which a multi-value operation is possible and whose manufacturing and operation are simple. A preferred aim of this is solved by providing two or more magnetoresistive effect elements which are electrically connected in series to each other and by selecting one of the series-connected elements depending on a direction of a current carried in the series-connected elements, a magnitude thereof, and an order of the current thereof for performing the writing operation. For example, it is solved by differentiating plane area sizes of the respective magnetoresistive effect elements which have the same film structure from each other so as to differentiate resistance change amounts caused by respective magnetization reversal and threshold current values required for respective magnetization reversal from each other. | 02-21-2013 |
| 20130044538 | STACKED MRAM DEVICE AND MEMORY SYSTEM HAVING THE SAME - Provided is a stacked magnetic random access memory (MRAM) in which memory cell arrays having various characteristics or functions are included in memory cell layers. The stacked MRAM device includes a semiconductor substrate and at least one memory cell layers. The semiconductor substrate includes a first memory cell array. Each of the memory cell layers includes a memory cell array having a different function from the first memory cell array and is stacked on the first memory cell array. As a result, the stacked MRAM device has high density, high performance, and high reliability. | 02-21-2013 |
| 20130051133 | ANTI-FUSE CIRCUIT USING MTJ BREAKDWON AND SEMICONDUCTOR DEVICE INCLUDING SAME - An anti-fuse circuit includes an array of anti-fuses. Each anti-fuse has a tunneling magneto-resistance (TMR) element series connected with a transistor, such that breakdown of a magnetic tunnel junction (MTJ) in response to an applied first voltage stores fuse information. A sensing circuit senses and amplifies respective output signals provided by the anti-fuses. | 02-28-2013 |
| 20130051134 | SEMICONDUCTOR RECORDING DEVICE - The disclosed semiconductor recording device achieves multi-valued reading and writing using a spin-injection magnetization-reversal tunneling magnetoresistive element (TMR element). A first current that has at least the same value as that of the element requiring the highest current to reverse the magnetization thereof among a plurality of TMR elements is, in the direction that causes reversal to either a parallel state or an anti-parallel state, applied to a memory cell having the plurality of TMR elements, and then a second current which is in the reverse direction from the first current and of which only the value needed to reverse the magnetoresistance state of at least one TMR element excluding the element requiring the maximum current among the plurality of TMR elements is applied to each, and multi-valued writing is performed. | 02-28-2013 |
| 20130051135 | COMPOUND CELL SPIN-TORQUE MAGNETIC RANDOM ACCESS MEMORY - A compound magnetic data storage cell, applicable to spin-torque random access memory (ST-RAM), is disclosed. A magnetic data storage cell includes a magnetic storage element and two terminals communicatively connected to the magnetic storage element. The magnetic storage element is configured to yield any of at least three distinct magnetoresistance output levels, corresponding to stable magnetic configurations, in response to spin-momentum transfer inputs via the terminals. | 02-28-2013 |
| 20130058156 | MAGNETIC MEMORY CELL AND MAGNETIC RANDOM ACCESS MEMORY - A relation between a drive current of a selection transistor of a magnetic memory and a threshold magnetization switching current of the magnetoresistance effect element is optimized. In order to optimize the relation between the drive current of the selection transistor and the threshold magnetization switching current of the magnetoresistance effect element | 03-07-2013 |
| 20130058157 | MAGNETIC RANDOM ACCESS MEMORY DEVICE - The present invention proposes an electronic memory device comprising a memory line including a memory domain. The memory line may contain a number of memory domains and a number of fixed domains, wherein each memory domain stores a single binary bit value. A multiferroic element may be disposed proximate to each memory domain allowing the magnetization of the memory domain to be changed using a spin torque current, and ensuring the stability of the magnetization of the domain when it is not being written. The domain boundary between the memory domain and one of its adjacent fixed domains may thereby be moved. An antiferromagnetic element may be disposed proximate to each fixed domain to ensure the stability of the magnetization of these. The value of each memory domain may be read by applying a voltage to a magnetic tunnel junction comprising the memory domain and measuring the current flowing through it. | 03-07-2013 |
| 20130064008 | DATA READ CIRCUIT, NONVOLATILE MEMORY DEVICE COMPRISING DATA READ CIRCUIT, AND METHOD OF READING DATA FROM NONVOLATILE MEMORY DEVICE - A nonvolatile memory device comprises a nonvolatile cell array comprising a memory cell and a reference cell, a clamping circuit electrically connected to the memory cell and configured to clamp a voltage applied to a data sensing line during a read operation, and a clamping voltage generation unit configured to generate a clamping voltage responsive to a first voltage having a level based on the reference cell, and to feed back the clamping voltage to the clamping circuit. | 03-14-2013 |
| 20130064009 | SIZE-REDUCED MAGNETIC MEMORY CELL - A semiconductor device includes: a first memory cell, a second memory cell adjacent to the first memory cell, first and second write bitlines and a common bitline. The first memory cell includes: a first magnetization fixed layer, a first magnetic recording layer, a first reference layer, a first tunnel barrier film, and a first transistor. The second memory cell includes: a second magnetization fixed layer, a second magnetic recording layer, a second reference layer, a second tunnel barrier layer and a second transistor. Each of the first and second reference layer has a fixed magnetization. A common magnetization fixed layer having a fixed magnetization is coupled to the first and second magnetic recording layers. The common magnetization fixed layer and the common bitline is connected so that the common magnetization fixed layer and the common bitline are unable to be electrically unconnected. | 03-14-2013 |
| 20130070518 | ANTIFERROMAGNETIC STORAGE DEVICE - An antiferromagnetic nanostructure according to one embodiment includes an array of at least two antiferromagnetically coupled magnetic atoms having at least two magnetic states that are stable for at least one picosecond even in the absence of interaction with an external structure, the array having a net magnetic moment of zero or about zero, wherein the array has 100 atoms or less along a longest dimension thereof. An atomic-scale structure according to one embodiment has a net magnetic moment of zero or about zero; two or more stable magnetic states; and having an array of atoms that has magnetic moments that alternate between adjacent magnetic atoms along one or more directions. Such structures may be used to store data at ultra-high densities. | 03-21-2013 |
| 20130070519 | READ ARCHITECTURE FOR MRAM - A read architecture for reading random access memory (RAM) cells includes a multi-level sense amplifier, the multi-level sense amplifier including a plurality of sense amplifiers, each sense amplifier having a respective sense threshold and a respective sense output, and a storage module coupled to the multi-level sense amplifier for storing the sense outputs of the multi-level sense amplifier. The storage module stores a first set of sense outputs corresponding to a first read of an RAM cell and stores a second set of sense outputs corresponding to a second read of the RAM cell. The architecture also includes a decision module for comparing the first and second set of sense outputs and determining a data state of the RAM cell based on the comparison. | 03-21-2013 |
| 20130070520 | Magnetic Random Access Memory Devices Including Shared Heating Straps - A memory device includes: (1) multiple magnetic random access memory (“MRAM”) cells each including a first end and a second end; (2) a bit line electrically coupled to the first end of at least one of the MRAM cells; and (3) a strap electrically coupled to the second end of each one of the MRAM cells. During a write operation, the bit line is configured to apply a first heating current, and the strap is configured to apply a second heating current, such that at least one of the MRAM cells is heated to at least a threshold temperature according to the first heating current and the second heating current. | 03-21-2013 |
| 20130070521 | Magnetic Random Access Memory Devices Including Heating Straps - A memory device includes at least one magnetic random access memory cell, which includes: (1) a magnetic tunnel junction having a first end and a second end; and (2) a strap electrically coupled to the second end of the magnetic tunnel junction. The memory device also includes a bit line electrically coupled to the first end of the magnetic tunnel junction. During a write operation, the bit line is configured to apply a first heating current through the magnetic tunnel junction, and the strap is configured to apply a second heating current through the strap, such that the magnetic tunnel junction is heated to at least a threshold temperature according to the first heating current and the second heating current. | 03-21-2013 |
| 20130077388 | MAGNETIC MEMORY ELEMENT, MAGNETIC MEMORY DEVICE, SPIN TRANSISTOR, AND INTEGRATED CIRCUIT - One embodiment provides a magnetic memory element, including: a first ferromagnetic layer whose magnetization is variable; a second ferromagnetic layer which has a first band split into a valence band and a conduction band and a second band being continuous at least from the valence band to the conduction band; and a nonmagnetic layer provided between the first ferromagnetic layer and the second ferromagnetic layer. | 03-28-2013 |
| 20130077389 | MAGNETIC RANDOM ACCESS MEMORY USING MAGNETORESISTIVE ELEMENT, DIODE, AND TRANSISTOR - A magnetic memory according to an embodiment includes: a magnetoresistive element including a first magnetic layer having a magnetization direction not to be changed by spin-injection writing, a second magnetic layer having a magnetization direction to be changeable by the spin-injection writing, and a tunnel barrier layer provided between the first and second magnetic layers; a first interconnect electrically connected to one of the first and second magnetic layers; a select transistor, with one of a source and drain thereof being electrically connected to the other one of the first and second magnetic layers; a second interconnect electrically connected to the other one of the source and drain; a diode having one terminal electrically connected to the other one of the first and second magnetic layers; a third interconnect electrically connected to the other terminal of the diode; and a sense amplifier electrically connected to the third interconnect. | 03-28-2013 |
| 20130077390 | MAGNETIC RANDOM ACCESS MEMORY (MRAM) CELL, METHOD FOR WRITING AND READING THE MRAM CELL USING A SELF-REFERENCED READ OPERATION - The present disclosure concerns a magnetic random access memory (MRAM) cell comprising a magnetic tunnel junction comprising a synthetic storage layer; a sense layer having a sense magnetization that is reversible; and a tunnel barrier layer between the sense layer and the storage layer; wherein a net local magnetic stray field couples the storage layer with the sense layer; and wherein the net local magnetic stray field being such that the net local magnetic stray field coupling the sense layer is below | 03-28-2013 |
| 20130077391 | Magnetoresistive Device and a Writing Method for a Magnetoresistive Device - According to embodiments of the present invention, a magnetoresistive device is provided. The magnetoresistive device includes at least two ferromagnetic soft layers, wherein the at least two ferromagnetic soft layers have different ranges of magnetization switching frequencies. Further embodiments provide a magnetoresistive device including at least two oscillating ferromagnetic structures, wherein ranges of operating current amplitudes at which oscillations are induced for the at least two oscillating ferromagnetic structures are different. According to further embodiments of the present invention, writing methods for the magnetoresistive devices are provided. | 03-28-2013 |
| 20130083593 | SELF-REFERENCE MAGNETIC RANDOM ACCESS MEMORY (MRAM) CELL COMPRISING FERRIMAGNETIC LAYERS - MRAM cell comprising a magnetic tunnel junction comprising a storage layer having a net storage magnetization being adjustable when the magnetic tunnel junction is at a high temperature threshold and being pinned at a low temperature threshold; a sense layer having a reversible sense magnetization; and a tunnel barrier layer between the sense and storage layers; at least one of the storage and sense layer comprising a ferrimagnetic 3d-4f amorphous alloy material comprising a sub-lattice of 3d transition metals atoms providing a first magnetization and a sub-lattice of 4f rare-earth atoms providing a second magnetization, such that at a compensation temperature of said at least one of the storage layer and the sense layer, the first magnetization and the second magnetization are substantially equal. The disclosed MRAM cell can be written and read using a small writing and reading field, respectively. | 04-04-2013 |
| 20130094282 | MULTI-BIT SPIN-MOMENTUM-TRANSFER MAGNETORESISTENCE RANDOM ACCESS MEMORY WITH SINGLE MAGNETIC-TUNNEL-JUNCTION STACK - A magneto resistive random access memory system includes a first magnetic-tunnel-junction device coupled to a first bit-line, a second magnetic-tunnel-junction device coupled to a second bit-line, a selection transistor coupled to the first and second bit-lines and a word-line coupled to the selection transistor. | 04-18-2013 |
| 20130094283 | Apparatus, System, and Method for Writing Multiple Magnetic Random Access Memory Cells with a Single Field Line - A memory device includes a plurality of magnetic random access memory (MRAM) cells, a field line, and a field line controller configured to generate a write sequence that traverses the field line. The write sequence is for writing a multi-bit word to the plurality of MRAM cells. The multi-bit word includes a first subset of bits having a first polarity and a second subset of bits having a second polarity. The write sequence writes concurrently to at least a subset of the plurality of MRAM cells corresponding to the first subset of bits having the first polarity, then subsequently writes concurrently to a remaining subset of the plurality of MRAM cells corresponding to the second subset of bits having the second polarity. | 04-18-2013 |
| 20130094284 | MAGNETORESISTANCE EFFECT ELEMENT AND MAGNETIC MEMORY - Provided are a magneto resistive effect element with a stable magnetization direction perpendicular to a film plane and with a controlled magnetoresistance ratio, and a magnetic memory using the magneto resistive effect element. Ferromagnetic layers | 04-18-2013 |
| 20130100732 | Array Structural Design of Magnetoresistive Random Access Memory (MRAM) Bit Cells - Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cells are disclosed. The bit cells include a source line formed in a first plane and a bit line formed in a second plane. The bit line has a longitudinal axis that is parallel to a longitudinal axis of the source line, and the source line overlaps at least a portion of the bit line. | 04-25-2013 |
| 20130107611 | Memory Device with Soft-Decision Decoding | 05-02-2013 |
| 20130107612 | Spin-Torque Transfer Magnetic Random Access Memory (STTMRAM) Device with Shared Transistor and Minimal Written Data Disturbance | 05-02-2013 |
| 20130107613 | MEMORY SENSING CIRCUIT | 05-02-2013 |
| 20130107614 | MEMORY SENSING CIRCUIT | 05-02-2013 |
| 20130107615 | MEMORY SENSING CIRCUIT | 05-02-2013 |
| 20130107616 | MAGNETORESISTIVE EFFECT ELEMENT AND RANDOM ACCESS MEMORY USING SAME | 05-02-2013 |
| 20130114334 | Magnetoresistive random access memory cell with independently operating read and write components - A new class of the memory cell is proposed. There are two separated pulse data writing and sensing current paths. The in-plane pulse current is used to flip the magnetization direction of the perpendicular-anisotropy data storage layer sandwiched between a heavy metal writing current-carrying layer and a dielectric layer. The magnetization state within data storage layer is detected by the patterned perpendicular-anisotropy tunneling magnetoresistive (TMR) stack via the output potential of the stack. Two detailed memory cells are proposed: in one proposed cell, the data storage layer is independent from but kept close to the sensing TMR stack, whose magnetization orientation affects magnetization configuration within the free layer of the TMR stack, therefor ultimately affects the output potential of the stack; in the other proposed cell, the perpendicular-anisotropy data storage layer is the free layer of the sensing TMR stack, whose magnetization state will directly affect the output potential of the stack when sensing current passes through. | 05-09-2013 |
| 20130114335 | MEMORY SENSING CIRCUIT - A sensing circuit includes a sense amplifier circuit having a first and second nodes through which a magnetic memory element is sensed. A first current source is coupled to the first node a second current source is coupled to the second node. A reference magnetic memory element has a resistance associated therewith and is coupled to the first node, the reference magnetic memory element receives current from the first current source. At least one memory element, having a resistance associated therewith, is coupled to the second node and receives current from the second current source. Current from the first current source and current from the second current source are substantially the same. The logic state of the at least one memory element is sensed by a comparison of the resistance of the at least one memory element to the resistance of the reference magnetic memory element. | 05-09-2013 |
| 20130121066 | CIRCUIT AND METHOD FOR GENERATING A REFERENCE LEVEL FOR A MAGNETIC RANDOM ACCESS MEMORY ELEMENT - A method of establishing a reference level includes providing first and second non-overlapping paths from a first node to a second node, providing first and second reference magnetic random access memory (MRAM) elements in the first path, providing third and fourth reference MRAM elements in the second path, measuring a first value indicative of a resistance between the first node and the second node, and setting the reference level based at least in part on the measured value. Also an associated reference circuit. | 05-16-2013 |
| 20130121067 | HIGH SPEED LOW POWER MAGNETIC DEVICES BASED ON CURRENT INDUCED SPIN-MOMENTUM TRANSFER - A high speed, low power method to control and switch the magnetization direction and/or helicity of a magnetic region in a magnetic device for memory cells using spin polarized electrical current. The magnetic device comprises a reference magnetic layer with a fixed magnetic helicity and/or magnetization direction and a free magnetic layer with a changeable magnetic helicity and/or magnetization direction. The fixed magnetic layer and the free magnetic layer are preferably separated by a non-magnetic layer. The fixed and free magnetic layers may have magnetization directions at a substantially non-zero angle relative to the layer normal. A current can be applied to the device to induce a torque that alters the magnetic state of the device so that it can act as a magnetic memory for writing information. The resistance, which depends on the magnetic state of the device, is measured to read out the information stored in the device. | 05-16-2013 |
| 20130121068 | MAGNETIC MEMORY CELL - The disclosed subject matter relates to a non-volatile memory bit cell ( | 05-16-2013 |
| 20130128657 | HYBRID READ SCHEME FOR SPIN TORQUE MRAM - A method of reading data from a plurality of bits in a spin-torque magnetoresistive memory array includes performing one or more referenced read operations of the bits, and performing a self-referenced read operation, for example, a destructive self-referenced read operation, of any of the bits not successfully read by the referenced read operation. The referenced read operations can be initiated at the same time or prior to that of the destructive self-referenced read operation. | 05-23-2013 |
| 20130128658 | WRITE DRIVER CIRCUIT AND METHOD FOR WRITING TO A SPIN-TORQUE MRAM - A write driver for writing to a spin-torque magnetoresistive random access memory (ST-MRAM) minimizes sub-threshold leakage of the unselected (off) word line select transistors in the selected column. An effective metal resistance in the bit line and/or source line is reduced and power supply noise immunity is increased. Write driver bias signals are isolated from global bias signals, and a first voltage is applied at one end of a bit line using one of a first NMOS-follower circuit or a first PMOS-follower circuit. A second voltage is applied at opposite ends of a source line using, respectively, second and third PMOS-follower circuits, or second and third NMOS-follower circuits. | 05-23-2013 |
| 20130128659 | SELF-REFERENCED MRAM CELL WITH OPTIMIZED RELIABILITY - Magnetic random access memory (MRAM) element suitable for a thermally-assisted write operation and for a self-referenced read operation, comprising a magnetic tunnel junction portion having a first portion and a second portion, each portion comprising a storage layer, a sense layer, and a tunnel barrier layer; the magnetic tunnel junction further comprising an antiferromagnetic layer between the two storage layers and pinning a storage magnetization of each of the storage layers below a critical temperature, and freeing them at and above the critical temperature; such that, during a write operation, a free magnetization of each of the sense layer is magnetically saturable according to a direction of a write magnetic field when applied; and the storage magnetizations are switchable in a direction substantially parallel and corresponding to the direction of the saturated free magnetizations. | 05-23-2013 |
| 20130141964 | MEMORY ELEMENT AND MEMORY APPARATUS - A memory element has a layered structure, including a memory layer that has magnetization perpendicular to a film face in which a magnetization direction is changed depending on information, and includes a Co—Fe—B magnetic layer, the magnetization direction being changed by applying a current in a lamination direction of the layered structure to record the information in the memory layer, a magnetization-fixed layer having magnetization perpendicular to a film face that becomes a base of the information stored in the memory layer, and an intermediate layer that is formed of a non-magnetic material and is provided between the memory layer and the magnetization-fixed layer, a first oxide layer and a second oxide layer. | 06-06-2013 |
| 20130141965 | HIGH DENSITY SEMICONDUCTOR MEMORY DEVICES - High density semiconductor memory devices are provided. The device may include a cell array region including a lower structure, an upper structure, and a selection structure, the selection structure being interposed between the lower and upper structures and including word lines, and a decoding circuit controlling voltages applied to the word lines. The decoding circuit may be configured to apply a first voltage to a pair of the word lines adjacent to each other and to apply a second voltage different from the first voltage to the remaining ones of the word lines, in response to word line address information input thereto. | 06-06-2013 |
| 20130141966 | MAGNETORESISTANCE EFFECT ELEMENT AND MAGNETIC MEMORY - Provided are a magnetoresistance effect element with a stable magnetization direction perpendicular to film plane and a controlled magnetoresistance ratio, in which writing can be performed by magnetic domain wall motion, and a magnetic memory including the magnetoresistance effect element. The magnetoresistance ratio is controlled by forming a ferromagnetic layer of the magnetoresistance effect element from a ferromagnetic material including at least one type of 3d transition metal or a Heusler alloy. The magnetization direction is changed from a direction in the film plane to a direction perpendicular to the film plane by controlling the film thickness of the ferromagnetic layer on an atomic layer level. | 06-06-2013 |
| 20130148417 | METHOD FOR MAGNETIC SCREENING OF ARRAYS OF MAGNETIC MEMORIES - A testing method is described that applies a sequence external magnetic fields of varying strength to MRAM cells (such as those with MTJ memory elements) in chips or wafers to selectively screen out cells with low or high thermal stability factor. The coercivity (Hc) is used as a proxy for thermal stability factor (delta). In the various embodiments the sequence, direction and strength of the external magnetic fields is used to determine the high coercivity cells that are not switched by a normal field and the low coercivity cells that are switched by a selected low field. In some embodiment the MRAM's standard internal electric current can be used to switch the cells. Standard circuit-based resistance read operations can be used to determine the response of each cell to these magnetic fields and identify the abnormal high and low coercivity cells. | 06-13-2013 |
| 20130148418 | MAGNETORESISTIVE DEVICE AND A WRITING METHOD FOR A MAGNETORESISTIVE DEVICE - A magnetoresistive device including a fixed magnetic layer structure, a first free magnetic layer structure, and a second free magnetic layer structure, wherein the fixed magnetic layer structure is arranged in between the first free magnetic layer structure and the second free magnetic layer structure, wherein the magnetization orientation of the first free magnetic layer structure is variable in response to a first electrical signal of a first polarity and the magnetization orientation of the second free magnetic layer structure is at least substantially non-variable in response to the first electrical signal, and wherein the magnetization orientation of the second free magnetic layer structure is variable in response to a second electrical signal of a second polarity and the magnetization orientation of the first free magnetic layer structure is at least substantially non-variable in response to the second electrical signal, wherein the second polarity is opposite to the first polarity. | 06-13-2013 |
| 20130148419 | SELF-REFERENCED MAGNETIC RANDOM ACCESS MEMORY ELEMENT COMPRISING A SYNTHETIC STORAGE LAYER - The present disclosure concerns a MRAM element comprising a magnetic tunnel junction comprising: a storage layer, a sense layer, and a tunnel barrier layer included between the storage layer and the sense layer; the storage layer comprising a first magnetic layer having a first storage magnetization; a second magnetic layer having a second storage magnetization; and a non-magnetic coupling layer separating the first and second magnetic layers such that the first storage magnetization is substantially antiparallel to the second storage magnetization; the first and second magnetic layers being arranged such that: at a read temperature the first storage magnetization is substantially equal to the second storage magnetization; and at a write temperature which is higher than the read temperature the second storage magnetization is larger than the first storage magnetization. The disclosed MRAM element generates a low stray field when the magnetic tunnel junction is cooled at a low temperature. | 06-13-2013 |
| 20130148420 | RESISTANCE-CHANGE SEMICONDUCTOR MEMORY - According to one embodiment, a memory includes first to fourth memory cells aligned in a first direction. Each of the first to fourth memory cells comprises a cell transistor having a gate connected to a word line extending in a second direction crossing the first direction and a resistive memory element having one end connected to a first source/drain region of the cell transistor. A second source/drain region of the cell transistor is connected to one of a first bit line extending in the first direction and a second bit line extending in the second direction. The other end of the resistive memory element is connected to one of the first and second bit lines which is apart from the second source/drain region. The second source/drain regions in the first and second memory cells are shared, and the second source/drain regions in the third and fourth memory cells are shared. | 06-13-2013 |
| 20130155759 | Test Structures, Methods of Manufacturing Thereof, Test Methods, and MRAM Arrays - Test structures, methods of manufacturing thereof, test methods, and magnetic random access memory (MRAM) arrays are disclosed. In one embodiment, a test structure is disclosed. The test structure includes an MRAM cell having a magnetic tunnel junction (MTJ) and a transistor coupled to the MTJ. The test structure includes a test node coupled between the MTJ and the transistor, and a contact pad coupled to the test node. | 06-20-2013 |
| 20130155760 | METHOD OF WRITING TO A SPIN TORQUE MAGNETIC RANDOM ACCESS MEMORY - A method for determining an optimized write pattern for low write error rate operation of a spin torque magnetic random access memory. The method provides a way to optimize the write error rate without affecting the memory speed. The method comprises one or more write pulses. The pulses may be independent in amplitude, duration and shape. Various exemplary embodiments adjust the write pattern based on the memory operating conditions, for example, operating temperature. | 06-20-2013 |
| 20130155761 | MAGNETIC MEMORY DEVICE AND READING METHOD OF MAGNETIC MEMORY DEVICE - A magnetic memory device including a multivalued magnetic memory cell whose electric resistances become first to fourth resistance value when first to fourth information are respectively stored, a first reference cell larger than the first resistance value and smaller than the second resistance value, a second reference cell larger than the second resistance value and smaller than the third resistance value, a third reference cell larger than the third resistance value and smaller than the fourth resistance value, and a read circuit including first to third comparators comparing a signal corresponding to the resistance of the magnetic memory cell and respective signals corresponding to the resistances of the first to third reference cells. | 06-20-2013 |
| 20130155762 | RANDOM ACCESS MEMORY ARCHITECTURE FOR READING BIT STATES - An architecture and method includes providing an oscillatory signal through each magnetic tunnel junction (MTJ), or in a line adjacent each MTJ, in a magnetoresistive random access memory array. A rectified signal appearing across each MTJ is measured and compared to a reference signal for determining the state of the MTJ. | 06-20-2013 |
| 20130155763 | CIRCUIT AND METHOD FOR SPIN-TORQUE MRAM BIT LINE AND SOURCE LINE VOLTAGE REGULATION - Circuitry and a method for regulating voltages applied to source and bit lines of a spin-torque magnetoresistive random access memory (ST-MRAM) reduces time-dependent dielectric breakdown stress of the word line transistors. During a read or write operation, only the selected bit lines and source lines are pulled down to a low voltage and/or pulled up to a high voltage depending on the operation (write | 06-20-2013 |
| 20130155764 | MAGNETORESISTANCE ELEMENT AND SEMICONDUCTOR MEMORY DEVICE - A magnetoresistance element includes: a first magnetoresistance subelement including a first free magnetization layer, a first tunnel insulating layer and a first fixed magnetization layer, the first tunnel insulating layer interposed between the first free magnetization layer and the first fixed magnetization layer; and a second magnetoresistance subelement including a second free magnetization layer, a second tunnel insulating layer and a second fixed magnetization layer, the second tunnel insulating layer interposed between the second free magnetization layer and the second fixed magnetization layer, wherein the first and second magnetoresistance subelements are stacked each other, and an order of the first free magnetization layer and the first fixed magnetization layer is opposite to an order of the second free magnetization layer and the second fixed magnetization layer in a thickness direction of the magnetoresistance element. | 06-20-2013 |
| 20130163314 | MEMORY ELEMENT AND MEMORY APPARATUS - A memory element includes a layered structure. The layered structure includes a memory layer, a magnetization-fixed layer, and an intermediate layer. The memory layer has magnetization perpendicular to a film face in which a direction of the magnetization is changed depending on information, and the direction of the magnetization is changed by applying a current in a lamination direction of the layered structure to record the information in the memory layer. The magnetization-fixed layer has magnetization perpendicular to a film face that becomes a base of the information stored in the memory layer, has a laminated ferri-pinned structure including at least two ferromagnetic layers and a non-magnetic layer, and includes an anti-ferromagnetic oxide layer formed on any of the at least two ferromagnetic layers. The intermediate layer is formed of a non-magnetic material and is provided between the memory layer and the magnetization-fixed layer. | 06-27-2013 |
| 20130163315 | MEMORY ELEMENT AND MEMORY APPARATUS - A memory element includes a layered structure. The layered structure includes a memory layer, a magnetization-fixed layer, and an intermediate layer. The memory layer has magnetization perpendicular to a film face in which a direction of the magnetization is changed depending on information, and the direction of the magnetization is changed by applying a current in a lamination direction of the layered structure to record the information in the memory layer. The magnetization-fixed layer has magnetization perpendicular to a film face that becomes a base of the information stored in the memory layer, and has a laminated ferri-pinned structure including at least two ferromagnetic layers and a non-magnetic layer. The non-magnetic layer includes Cr. The intermediate layer is formed of a non-magnetic material and is provided between the memory layer and the magnetization-fixed layer. | 06-27-2013 |
| 20130163316 | MEMORY ELEMENT AND MEMORY APPARATUS - A memory element has a layered configuration, including a memory layer in which a magnetization direction is changed corresponding to information; the magnetization direction being changed by applying a current in a lamination direction of the layered configuration to record the information in the memory layer, a magnetization-fixed layer in which a magnetization direction is fixed, an intermediate layer that is formed of a non-magnetic material and is provided between the memory layer and the magnetization-fixed layer, and a perpendicular magnetic anisotropy inducing layer, the memory layer including a first ferromagnetic layer, a first bonding layer, a second ferromagnetic layer, a second bonding layer and a third ferromagnetic layer laminated in the stated order. | 06-27-2013 |
| 20130163317 | MEMORY ELEMENT AND MEMORY APPARATUS - There is provided a memory element having a layered structure, including a memory layer having magnetization perpendicular to a film face in which a magnetization direction is changed corresponding to information, and including a Co—Fe—B magnetic layer and at least on non-magnetic layer; the magnetization direction being changed by flowing a current in a lamination direction of the layered structure to record the information in the memory layer, a magnetization-fixed layer having magnetization perpendicular to the film face that becomes a base of the information stored in the memory layer, and an intermediate layer that is formed of a non-magnetic material and is provided between the memory layer and the magnetization-fixed layer, further including a laminated structure where an oxide layer, the Co—Fe—B magnetic layer and the non-magnetic layer are laminated is formed. | 06-27-2013 |
| 20130163318 | Self-Referenced MRAM Cell and Method for Writing the Cell Using a Spin Transfer Torque Write Operation - The present disclosure concerns a method for writing to a self-referenced MRAM cell comprising a magnetic tunnel junction comprising: a storage layer including a first ferromagnetic layer having a first storage magnetization, a second ferromagnetic layer having a second storage magnetization, and a non-magnetic coupling layer separating the first and second ferromagnetic layers; a sense layer having a free sense magnetization; and a tunnel barrier layer included between the sense and storage layers; the first and second ferromagnetic layers being arranged such that a dipolar coupling between the storage) and the sense layers is substantially null; the method comprising: switching the second ferromagnetic magnetization by passing a spin-polarized current in the magnetic tunnel junction; wherein the spin-polarized current is polarized when passing in the sense layer, in accordance with the direction of the sense magnetization. The MRAM cell can be written with low power consumption. | 06-27-2013 |
| 20130163319 | MULTI-PORT NON-VOLATILE MEMORY THAT INCLUDES A RESISTIVE MEMORY ELEMENT - A particular method of accessing a multi-port non-volatile memory device includes executing a first memory operation with respect to a first memory cell while executing a second memory operation with respect to a second memory cell. The first memory operation is via a first port and the second memory operation is via a second port. The first memory cell includes a first non-volatile memory that includes a first resistive memory structure. The second memory cell includes a second non-volatile memory that includes a second resistive memory structure. The first memory cell and the second memory cell are each accessible via the first port and the second port. | 06-27-2013 |
| 20130170290 | SPIN DEVICE, DRIVING METHOD OF THE SAME, AND PRODUCTION METHOD OF THE SAME - The present disclosure provides a spin device including: a graphene; a first ferromagnetic electrode and a second electrode that are in electrical contact with and sandwich the graphene; a third ferromagnetic electrode and a fourth electrode that sandwich the graphene at a position apart from the first and second electrodes in electrical contact with the graphene; a current applying portion that applies an electric current between the first ferromagnetic electrode and the second electrode; and a voltage-signal detecting portion that detects spin accumulation information as a voltage signal via the third ferromagnetic electrode and the fourth electrode. The spin accumulation information is generated, by application of the electric current, in a part of the graphene that is sandwiched between the third and fourth electrodes. The first and third ferromagnetic electrodes are disposed on the same surface of the graphene, and the second and fourth electrodes are non-magnetic or ferromagnetic electrodes. | 07-04-2013 |
| 20130176773 | Reference Averaging for MRAM Sense Amplifiers - A sense amplifier comprising a reference current developed from a programmed and a non-programmed reference cell is used to read a signal from a magnetic random access memory (MRAM) comprising magnetic tunnel junction (MTJ) cells. The average current is determined from reference cells in as few as one sense amplifier and as many as n sense amplifiers, and is an average current between the programmed reference cell and the non-programmed reference cell that approximates the mid point between the two states. The sense amplifier can be fully differential or a non differential sense amplifier. | 07-11-2013 |
| 20130176774 | SYSTEM AND METHOD OF REFERENCE CELL TESTING - Systems and methods of testing a reference cell in a memory array are disclosed. In a particular embodiment, a method includes coupling a first reference cell of a first reference cell pair of a memory array to a first input of a first sense amplifier of the memory array. The method also includes providing a reference signal to a second input of the first sense amplifier. The reference signal is associated with a second reference cell pair of the memory array. | 07-11-2013 |
| 20130182496 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes plural bit lines and plural word lines. The memory cell array has plural memory cells that are connected with the bit lines and word lines, and can store data. Plural sense amplifiers detect the data stored in the memory cells. Plural write drivers write data in the memory cells. A comparison buffer temporarily stores the write data to be written in the memory cells by the write driver. In a series of write sequences, the comparison buffer stores the read data from the memory cells selected as the write object and the write data to be written in the selected memory cells. After a series of write sequences, when the pre-charge command for resetting the voltage of the bit lines is received, the write execution command is executed so that the comparison buffer executes write in the selected memory cells. | 07-18-2013 |
| 20130182497 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device having tunnel magnetoresistive elements in memory cells. | 07-18-2013 |
| 20130182498 | MAGNETIC MEMORY DEVICE AND DATA WRITING METHOD FOR MAGNETIC MEMORY DEVICE - A magnetic memory device including a plurality of memory cells, each of which stores therein 2 | 07-18-2013 |
| 20130182499 | MRAM Cell and Method for Writing to the MRAM Cell using a Thermally Assisted Write Operation with a Reduced Field Current - The present disclosure concerns a method for writing to a MRAM cell comprising a magnetic tunnel junction formed from a storage layer having a storage magnetization; a reference layer having a reference magnetization; and a tunnel barrier layer included between the sense and storage layers; and a current line electrically connected to said magnetic tunnel junction; the method comprising: passing a heating current in the magnetic tunnel junction for heating the magnetic tunnel junction; passing a field current for switching the storage magnetization in a written direction in accordance with the polarity of the field current. The magnitude of the heating current is such that it acts as a spin polarized current and can adjust the storage magnetization; and the polarity of the heating current is such as to adjust the storage magnetization substantially towards said written direction. | 07-18-2013 |
| 20130182500 | LATCHING CIRCUIT - A non-volatile latch circuit includes a pair of cross-coupled inverters, a pair of resistance-based memory elements, and write circuitry configured to write data to the pair of resistance-based memory elements. The pair of resistance-based memory elements is isolated from the pair of cross-coupled inverters during a latching operation. A sensing circuit includes a first current path that includes a resistance-based memory element and an output of the sensing circuit. The sensing circuit includes a second current path to reduce current flow through the resistance-based memory element at a first operating point of the sensing circuit. | 07-18-2013 |
| 20130182501 | SEMICONDUCTOR STORAGE DEVICE AND ITS MANUFACTURING METHOD - A magnetoresistive element | 07-18-2013 |
| 20130188418 | MAGNETORESISTIVE RANDOM ACCESS MEMORY - A magnetoresistive random access memory (MRAM) cell includes a magnetic tunnel junction (MTJ), a top electrode disposed over the MTJ, a bottom electrode disposed below the MTJ, and an induction line disposed above or below the MTJ. The induction line is configured to induce a magnetic field at the MTJ. | 07-25-2013 |
| 20130188419 | MEMORY WITH SEPARATE READ AND WRITE PATHS - A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer. A write current passes through the giant magnetoresistance cell to switche the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell. | 07-25-2013 |
| 20130188420 | NON-DESTRUCTIVE SELF-REFERENCE SPIN-TRANSFER TORQUE MEMORY - A non-destructive self-reference spin-transfer torque memory unit is disclosed. | 07-25-2013 |
| 20130188421 | MAGNETIC DEVICE, AND METHOD FOR READING FROM AND WRITING TO SAID DEVICE - A magnetic device includes a reference layer, the magnetization direction of which is fixed, and a storage layer, the magnetization direction of which is variable. In a write mode, the magnetization direction of the storage layer is changed so as to store a “1” or a “0” in the storage layer. In a reading mode, the resistance of the magnetic device is measured so as to know what is stored in the storage layer. The magnetic device also includes a control layer, the magnetization direction of which is variable. The magnetization direction of the control layer is controlled so as to increase the effectiveness of the spin-transfer torque in the event writing to the storage layer is desired, and to decrease the effectiveness of the spin-transfer torque in the event reading the information contained in the storage layer, without modifying the information, is desired. | 07-25-2013 |
| 20130194862 | NON-VOLATILE FLIP-FLOP - A flip-flop has an output control node and an isolation switch selectively couples a retention sense node to the output control node. A sense circuit selectively couples an external sense current source to the retention sense node and to magnetic tunneling junction (MTJ) elements. Optionally a write circuit selectively injects a write current through one MTJ element and then another MTJ element. Optionally, a write circuit injects a write current through a first MTJ element concurrently with injecting a write current through a second MTJ element. | 08-01-2013 |
| 20130194863 | INITIALIZATION METHOD OF A PERPENDICULAR MAGNETIC RANDOM ACCESS MEMORY (MRAM) DEVICE - Methods using a sequence of externally generated magnetic fields to initialize the magnetization directions of each of the layers in perpendicular MTJ MRAM elements for data and reference bits when the required magnetization directions are anti-parallel are described. The coercivity of the fixed pinned and reference layers can be made unequal so that one of them can be switched by a magnetic field that will reliably leave the other one unswitched. Embodiments of the invention utilize the different effective coercivity fields of the pinned, reference and free layers to selectively switch the magnetization directions using a sequence of magnetic fields of decreasing strength. Optionally the chip or wafer can be heated to reduce the required field magnitude. It is possible that the first magnetic field in the sequence can be applied during an annealing step in the MRAM manufacture process. | 08-01-2013 |
| 20130201754 | MRAM WITH CURRENT-BASED SELF-REFERENCED READ OPERATIONS - A magnetoresistive memory stores logic values in high and low resistance states of magnetic tunnel junction elements. Instead of comparing the resistance of elements to a fixed threshold to discern a logic state, the resistances of elements are self-compared before and after imposing a low resistance state. A measure of the resistance of an element in its unknown resistance state is stored, for example by charging a capacitor to a voltage produced when read current bias is applied. Then the element is written into its low resistance state and read current bias is applied again to develop another voltage, representing the low resistance state. A comparison circuit using current summing and an offset providing a minimum difference tolerance determines whether the resistance of the element was changed or remained the same. This determines the logic state of the element. | 08-08-2013 |
| 20130201755 | MTJ CELL FOR AN MRAM DEVICE AND A MANUFACTURING METHOD THEREOF - An MTJ cell includes a first metal layer elongated in the X-direction; a second metal layer separated from the first metal layer and elongated in the Y-direction; a magnetic tunnel junction (MTJ) interposed between the overlapping parts of the first and second metal layers and having extended parts not covered by the second metal layer, the MTJ including a pinned layer, a barrier layer, and a storage layer sequentially laminated; and a yoke spanning across the second metal layer, with both ends in the X-direction contacting the top surface of the extended parts of the storage layer not covered by the second metal layer, either directly or through an insulator. The planar shapes of the MTJ and the yoke possess a quantum easy axis in the X-direction and Y-direction, respectively. The storage layer at its extended parts possesses a relaxed coupling with the yoke that essentially achieves continuity of flux return directly or indirectly through a nonmagnetic insulating layer, while maintaining a quantum easy axis orthogonal to that of the yoke. The YZ cross-sectional area of the yoke is greater than the YZ cross-sectional area of the storage layer. | 08-08-2013 |
| 20130201756 | Self-Referenced MRAM Element with Linear Sensing Signal - The present disclosure concerns a self-referenced MRAM element, comprising a magnetic tunnel junction having a magnetoresistance, comprising: a storage layer having a storage magnetization that is pinned along a first direction when the magnetic tunnel junction is at a low temperature threshold; a sense layer having a sense magnetization; and a tunnel barrier layer included between the storage layer and the sense layer; and an aligning device arranged for providing the sense magnetization with a magnetic anisotropy along a second direction that is substantially perpendicular to the first direction such that the sense magnetization is adjusted about the second direction; the aligning device being further arranged such that, when a first read magnetic field is provided, a resistance variation range of the magnetic tunnel junction is at least about 20% of the magnetoresistance. The self-referenced MRAM cell can be read with an increased reliability and has reducing power consumption. | 08-08-2013 |
| 20130208535 | RESISTIVE MEMORY DEVICE AND METHOD OF WRITING DATA USING MULTI-MODE SWITCHING CURRENT - A method of writing data in a resistive memory device includes performing a test operation to distinguish normal memory cells from weak memory cells, during a write operation directed to normal memory cells using a write current and during a weak write operation directed to weak memory cells using a higher write current. | 08-15-2013 |
| 20130208536 | MAGNETIC RANDOM ACCESS MEMORY DEVICE AND METHOD FOR PRODUCING A MAGNETIC RANDOM ACCESS MEMORY DEVICE - A magnetic random access memory (MRAM) device has read word lines, write word lines, bit lines, and a plurality of memory bit cells interconnected via the read word lines, the write word lines and the bit lines. Each memory bit cell has a fixed ferromagnetic layer element and a free ferromagnetic layer element separated by a dielectric tunnel barrier element. Each write word line and a respective number of free ferromagnetic layer elements are formed as a single continuous ferromagnetic line. | 08-15-2013 |
| 20130215671 | MEMORY BIT REPAIR SCHEME - A memory device for providing memory bit repair. The memory device may include memory cells. Each of the memory cells may include a measurable characteristic that identifies a stored data value. At least one of the memory cells may have a measurable characteristic set to a defective bit state. A defective bit state may refer to a measurable characteristic set to be outside of a working measureable characteristic range. The defective bit state may enable memory bit repair by identifying the at least one memory cell as being defective. | 08-22-2013 |
| 20130215672 | MAGNETORESISTIVE LOGIC CELL AND METHOD OF USE - A magnetoresistive logic cell (MRLC) is described that includes two MTJs in series that share a common free layer (CFL). The relative magnetization orientations of the CFL and the switchable reference layer (SRL) in MTJ- | 08-22-2013 |
| 20130215673 | MAGNETORESISTIVE LOGIC CELL AND METHOD OF USE - A magnetoresistive logic cell (MRLC) is described that includes two MTJs in series that share a common free layer (CFL). The relative magnetization orientations of the CFL and the switchable reference layer (SRL) in MTJ-1 dominate the overall resistance of the MRLC without regard to the fixed magnetization orientation of the nonswitchable reference layer in MTJ-2. High and low resistance states of the MRLC occurs based on the relative magnetization orientations of SRL and CFL. This behavior allows the MRLC to be used as a logical comparator. The CFL is switched by STT effect by application of selected relatively short voltage pulses that do not switch the SRL. A voltage-induced switching principle can be used with MRLC embodiments of the present invention to switch the SRL to parallel or anti-parallel with respect to the magnetization CFL in both perpendicular and in-plane anisotropy embodiments. | 08-22-2013 |
| 20130215674 | SPIN-TRANSFER TORQUE MEMORY SELF-REFERENCE READ METHOD - A spin-transfer torque memory apparatus and self-reference read schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage. Then applying a low resistance state polarized write current through the magnetic tunnel junction data cell, forming a low second resistance state magnetic tunnel junction data cell. A second read current is applied through the low second resistance state magnetic tunnel junction data cell to forming a second bit line read voltage. The method also includes comparing the first bit line read voltage with the second bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state. | 08-22-2013 |
| 20130215675 | INVALID WRITE PREVENTION FOR STT-MRAM ARRAY - In a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) a bit cell array can have a source line substantially parallel to a word line. The source line can be substantially perpendicular to bit lines. A source line control unit includes a common source line driver and a source line selector configured to select individual ones of the source lines. The source line driver and source line selector can be coupled in multiplexed relation. A bit line control unit includes a common bit line driver and a bit line selector in multiplexed relation. The bit line control unit includes a positive channel metal oxide semiconductor (PMOS) element coupled between the common source line driver and bit line select lines and bit lines. | 08-22-2013 |
| 20130223140 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of memory banks in a first region, a data terminal to which an input data signal is input, the data terminal being in a second region, and an inverting circuit that inverts or non-inverts the input data signal in response to an inversion control signal indicating whether the input data signal has been inverted, wherein at least one inverting circuit is disposed for each of the plurality of memory banks. | 08-29-2013 |
| 20130223141 | MAGENTIC MEMORY WITH A DOMAIN WALL - A multi-state low-current-switching magnetic memory element (magnetic memory element) comprising a free layer, two stacks, and a magnetic tunneling junction is disclosed. The stacks and magnetic tunneling junction are disposed upon surfaces of the free layer, with the magnetic tunneling junction located between the stacks. The stacks pin magnetic domains within the free layer, creating a free layer domain wall. A current passed from stack to stack pushes the domain wall, repositioning the domain wall within the free layer. The position of the domain wall relative to the magnetic tunnel junction corresponds to a unique resistance value, and passing current from a stack to the magnetic tunnel junction reads the magnetic memory element's resistance. Thus, unique memory states may be achieved by moving the domain wall. | 08-29-2013 |
| 20130229861 | DRIVING METHOD OF SEMICONDUCTOR STORAGE DEVICE AND SEMICONDUCTOR STORAGE DEVICE - In a memory, a signal holder holds voltages according to data in the storage elements. A busy-signal controller controls a busy-signal. The busy-signal determines whether to permit or reject reception of a read/write enable signal. During reception of the read/write enable signal is rejected, the signal holder holds a first to a third voltages. The first voltage corresponds to target data stored in a first storage element. The second voltage corresponds to first sample data of first logic written to the first storage element. The third voltage corresponds to second sample data of second logic. A sense amplifier detects logic of the target data by comparing a read signal of the first voltage with a reference signal generated by the second and third voltages. The write driver writes the target data/write data to the first storage element. After writing, the reception of the read/write enable signal is permitted. | 09-05-2013 |
| 20130229862 | STRAM WITH COMPOSITE FREE MAGNETIC ELEMENT - Spin-transfer torque memory includes a composite free magnetic element, a reference magnetic element having a magnetization orientation that is pinned in a reference direction, and an electrically insulating and non-magnetic tunneling barrier layer separating the composite free magnetic element from the magnetic reference element. The free magnetic element includes a hard magnetic layer exchanged coupled to a soft magnetic layer. The composite free magnetic element has a magnetization orientation that can change direction due to spin-torque transfer when a write current passes through the spin-transfer torque memory unit. | 09-05-2013 |
| 20130235653 | MAGNETIC MEMORY - A magnetic memory according to an embodiment includes: a magnetic structure extending in a first direction and having a circular ring-like shape in cross-section in a plane perpendicular to the first direction; a nonmagnetic layer formed on an outer surface of the magnetic structure, the outer surface extending in the first direction; and at least one reference portion formed on part of a surface of the nonmagnetic layer, the surface being on the opposite side from the magnetic structure, the at least one reference portion containing a magnetic material. | 09-12-2013 |
| 20130242646 | MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM) DIE INCLUDING AN INTEGRATED MAGNETIC SECURITY STRUCTURE - An MRAM die may include a first write line, a second write line, an MRAM cell disposed between the first write line and the second write line, and a magnetic security structure adjacent to the MRAM cell. The magnetic security structure may include a permanent magnetic layer and a soft magnetic layer. | 09-19-2013 |
| 20130242647 | MAGNETIC MEMORY - A magnetic memory according to an embodiment includes: a magnetic layer including a plurality of magnetic domains and a plurality of domain walls, and extending in a direction; a pinning layer formed with nonmagnetic phases and magnetic phases, extending in an extending direction of the magnetic layer and being located adjacent to the magnetic layer; an electrode layer located on the opposite side of the pinning layer from the magnetic layer; an insulating layer located between the pinning layer and the electrode layer; a current introducing unit flowing a shift current to the magnetic layer, the shift current causing the domain walls to shift; a write unit writing information into the magnetic layer; a read unit reading information from the magnetic layer; and a voltage generating unit generating a voltage to be applied between the pinning layer and the electrode layer. | 09-19-2013 |
| 20130250661 | MEMORY CELLS, SEMICONDUCTOR DEVICE STRUCTURES, SYSTEMS INCLUDING SUCH CELLS, AND METHODS OF FABRICATION - Memory cells including cell cores having free regions are disclosed. The free regions exhibit a strain that affects a magnetization orientation within the cell core. A stressor structure may exert a stress upon at least a portion of the cell core to effect the strain state of the free region. Also disclosed are semiconductor device structures and systems including such memory cells as well as methods for forming such memory cells. | 09-26-2013 |
| 20130250662 | TAMPER-RESISTANT MRAM UTILIZING CHEMICAL ALTERATION - A magnetoresistive random access memory (MRAM) die may include an MRAM cell, a reservoir defined by the MRAM die, and a chemical disposed in the reservoir. At least one boundary of the reservoir may be configured to be damaged in response to attempted tampering with the MRAM die, such that at least some of the chemical is released from the reservoir when the at least one boundary of the reservoir is damaged. In some examples, at least some of the chemical is configured to contact and alter or damage at least a portion of the MRAM cell when the chemical is released from the reservoir. | 09-26-2013 |
| 20130250663 | ANTI-TAMPERING DEVICES AND TECHNIQUES FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY - A system may include circuitry and a magnetoresistive random access memory (MRAM) die including at least one MRAM cell. The circuitry may be configured to detect attempted tampering with the MRAM die and generate a signal based on the detected attempted tampering. The signal may be sufficient to damage or destroy at least one layer of the at least one MRAM cell or a fuse electrically connected to a read line of the at least one MRAM cell. | 09-26-2013 |
| 20130250664 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD OF THE SAME - A non-volatile semiconductor memory device that can reduce power consumption includes plural memory banks containing nonvolatile plural memory cells. A common data bus is shared by plural memory banks and transmits the data of the memory cells. The plural switches are provided respectively between the electric source and plural memory banks. A controller controls the plural switches. The controller, in the data reading-out action or the data writing-in action, makes at least one of the switches corresponding to at least one of the memory banks accessible in a conduction state, and other switches in a non-conduction state. | 09-26-2013 |
| 20130250665 | MAGNETIC MEMORY - According to one embodiment, a magnetic memory includes a magnetoresistive element. The element includes a first magnetic film having a variable magnetization perpendicular to a film surface, a second magnetic film having an invariable magnetization perpendicular to the film surface, a nonmagnetic film between the first and second magnetic films, a magnetic field application layer including a third magnetic film having a magnetization parallel to the film surface. The third magnetic film applies a magnetic field parallel to the film surface to the first magnetic film. A magnitude of the magnetization of the third magnetic film when supplying a read current is larger than a magnitude of the magnetization of the third magnetic film when supplying a write current. | 09-26-2013 |
| 20130250666 | MAGNETIC MEMORY - A magnetic memory according to an embodiment includes: a first MTJ element including a first storage layer including a first magnetic film having a changeable magnetization direction, a first reference layer including a second magnetic film having a fixed magnetization direction, and a first tunnel barrier layer provided therebetween; and a second MTJ element including a second storage layer including a third magnetic film having a changeable magnetization direction and magnetically connected to the first storage layer, a second reference layer including a fourth magnetic film having a fixed magnetization direction parallel to the magnetization direction of the first reference layer, and a second tunnel barrier layer provided therebetween, the second MTJ element being arranged in parallel with the first MTJ element in a direction perpendicular to a stacking direction of the first MTJ element. | 09-26-2013 |
| 20130250667 | METHOD OF READING FROM AND WRITING TO MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A method of writing to a magnetic memory cell that includes selecting a magnetic memory cell having a pair of MTJs, and based on whether the selected magnetic memory cell is an ‘odd’ magnetic memory cell or an ‘even’ magnetic memory cell and a state to which the selected magnetic memory cell is being written, setting a distinct bit line (BL), coupled to a first MTJ of the pair of MTJs or a second MTJ of the pair of MTJs, to a voltage level indicative of a certain state that causes current to flow through the pair of MTJs in a manner that causes the direction of current flow through one of the first or second MTJs to be in a direction opposite to that of the other one of the first or second MTJs to program the first and second MTJs in opposite states. | 09-26-2013 |
| 20130250668 | MAGNETIC MEMORY ELEMENT, MAGNETIC MEMORY, AND MAGNETIC MEMORY DEVICE - According to one embodiment, a magnetic memory element includes: a magnetic wire, a stress application unit, and a recording/reproducing unit. The magnetic wire includes a plurality of domain walls and a plurality of magnetic domains separated by the domain walls. The magnetic wire is a closed loop. The stress application unit is configured to cause the domain walls to circle around along the closed loop a plurality of times by applying stress to the magnetic wire. The recording/reproducing unit is configured to write memory information by changing magnetizations of the circling magnetic domains as the domain walls circle around and to read the written memory information by detecting the magnetizations of the circling magnetic domains. | 09-26-2013 |
| 20130250669 | Scalable Magnetic Memory Cell With Reduced Write Current - One embodiment of a magnetic random access memory includes a magnetic memory cell comprising a magnetoresistive element including a free ferromagnetic layer comprising a reversible magnetization direction directed substantially perpendicular to a film plane in its equilibrium state, a pinned ferromagnetic layer comprising a fixed magnetization direction directed substantially perpendicular to the film plane, a tunnel barrier layer disposed between the free and pinned layers, and an assist ferromagnetic layer disposed adjacent to the free layer; means for providing a bias magnetic field pulse along a magnetic hard axis of the free layer, means for providing a spin-polarized current pulse through the magnetoresistive element in a direction perpendicular to the film plane, wherein the magnetization direction in the free layer is reversed by a collective effect of the bias magnetic field pulse and the spin-polarizing current pulse. Other embodiments are described and shown. | 09-26-2013 |
| 20130250670 | MAGNETORESISTIVE ELEMENT AND WRITING METHOD OF MAGNETIC MEMORY - According to one embodiment, a magnetoresistive element includes a first magnetic layer, a second magnetic layer, a non-magnetic layer formed between the first magnetic layer and the second magnetic layer, a charge storage layer having a first surface and a second surface different from the first surface, the first surface facing the second magnetic layer, a first insulating layer formed between the second magnetic layer and the first surface of the charge storage layer, and a second insulating layer formed on the second surface of the charge storage layer. | 09-26-2013 |
| 20130250671 | THERMALLY ASSISTED MAGNETIC WRITING DEVICE - A thermally assisted magnetic writing device including a first magnetic layer known as the “reference layer,” a second magnetic layer known as the “storage layer” that presents a variable magnetization direction, a spacer situated between the reference layer and the storage layer and a first antiferromagnetic layer in contact with the storage layer, the first antiferromagnetic layer being able to trap the magnetization direction of the storage layer. The magnetic device also includes a stabilization layer made of a ferromagnetic material, the stabilization layer being in contact with the first antiferromagnetic layer. | 09-26-2013 |
| 20130250672 | SHARED BIT LINE SMT MRAM ARRAY WITH SHUNTING TRANSISTORS BETWEEN BIT LINES - An array of rows and columns of SMT MRAM cells has each of the columns associated with one of its adjacent columns. Each of the SMT MRAM cells of the column is connected to a true data bit line and each of the SMT MRAM cells of the associated pair of columns is connected to a shared complement data bit line. A shunting switch device is connected between each of the true data bit lines and the shared complement data bit line for selectively connecting one of the true data bit lines to the shared complement data bit line to effectively reduce the resistance of the complement data bit line and to eliminate program disturb effects in adjacent non-selected columns of the SMT MRAM cells. | 09-26-2013 |
| 20130250673 | Shared Bit Line SMT MRAM Array with Shunting Transistors Between Bit Lines - An array of rows and columns of SMT MRAM cells has each of the columns associated with one of its adjacent columns. Each of the SMT MRAM cells of the column is connected to a true data bit line and each of the SMT MRAM cells of the associated pair of columns is connected to a shared complement data bit line. A shunting switch device is connected between each of the true data bit lines and the shared complement data bit line for selectively connecting one of the true data bit lines to the shared complement data bit line to effectively reduce the resistance of the complement data bit line and to eliminate program disturb effects in adjacent non-selected columns of the SMT MRAM cells. | 09-26-2013 |
| 20130258762 | REFERENCE CELL CONFIGURATION FOR SENSING RESISTANCE STATES OF MRAM BIT CELLS - A reference circuit discerns high or low resistance states of a magneto-resistive memory element such as a bit cell. The reference circuit has magnetic tunnel junction (MTJ) elements in complementary high and low resistance states R | 10-03-2013 |
| 20130258763 | HIGH CAPACIY LOW COST MULTI-STATE MAGNETIC MEMORY - One embodiment of the present invention includes a multi-state current-switching magnetic memory element includes a stack of two or more magnetic tunneling junctions (MTJs), each MTJ having a free layer and being separated from other MTJs in the stack by a seeding layer formed upon an isolation layer, the stack for storing more than one bit of information, wherein different levels of current applied to the memory element causes switching to different states. | 10-03-2013 |
| 20130258764 | MULTI-STATE SPIN-TORQUE TRANSFER MAGNETIC RANDOM ACCESS MEMORY - A multi-state spin-torque transfer magnetic random access memory (STTMRAM) is formed on a film and includes a first magnetic tunneling junctions (MTJ) having a first fixed layer, a first sub-magnetic tunnel junction (sub-MTJ) layer and a first free layer. The first fixed layer and first free layer each have a first magnetic anisotropy. The STTMRAM further includes a non-magnetic spacing layer formed on top of the first MTJ layer and a second MTJ formed on top of the non-magnetic spacing layer. The second MTJ has a second fixed layer, a second sub-MTJ layer and a second free layer. The second fixed and second free layers each have a second magnetic anisotropy, wherein at least one of the first or second magnetic anisotropy is perpendicular to the plane of the film. | 10-03-2013 |
| 20130265820 | ADJUSTING REFERENCE RESISTANCES IN DETERMINING MRAM RESISTANCE STATES - Magneto-resistive memory bit cells in an array have high or low resistance states storing logic values. During read operations, a bias source is coupled to an addressed memory word, coupling a parameter related to cell resistance to a sense amplifier at each bit position. The sense amplifiers determine whether the parameter value is greater or less than a reference value between the high and low resistance states. The reference value is derived by averaging or splitting a difference of resistances of reference cells at high and/or low resistance states. Bias current is conducted over address lines with varying resistance, due to different distances between the sense amplifiers and addressed memory words, which is canceled by inserting into the comparison circuit a resistance from a dummy addressing array, equal to the resistance of the conductor addressing the selected word line and bit position. | 10-10-2013 |
| 20130265821 | SHARED BIT LINE SMT MRAM ARRAY WITH SHUNTING TRANSISTORS BETWEEN BIT LINES - An array of rows and columns of SMT MRAM cells has each of the columns associated with one of its adjacent columns. Each of the SMT MRAM cells of the column is connected to a true data bit line and each of the SMT MRAM cells of the associated pair of columns is connected to a shared complement data bit line. A shunting switch device is connected between each of the true data bit lines and the shared complement data bit line for selectively connecting one of the true data bit lines to the shared complement data bit line to effectively reduce the resistance of the complement data bit line and to eliminate program disturb effects in adjacent non-selected columns of the SMT MRAM cells. | 10-10-2013 |
| 20130272059 | DIFFERENTIAL MRAM STRUCTURE WITH RELATIVELY REVERSED MAGNETIC TUNNEL JUNCTION ELEMENTS ENABLING WRITING USING SAME POLARITY CURRENT - A magnetoresistive memory has first and second magnetic tunnel junction (MTJ) elements operated differentially, each with a pinned magnetic layer and a free magnetic layer that can have field alignments that are parallel or anti-parallel, producing differential high and low resistance states representing a bit cell value. Writing a high resistance state to an element requires an opposite write current polarity through the pinned and free layers, and differential operation requires that the two MTJ elements be written to different resistance states. One aspect is to arrange or connect the layers in normal and reverse order relative to a current bias source, thereby achieving opposite write current polarities relative to the layers using the same current polarity relative to the current bias source. The differentially operated MTJ elements can supplement or replace single MTJ elements in a nonvolatile memory bit cell array. | 10-17-2013 |
| 20130272060 | SELF-REFERENCED SENSE AMPLIFIER FOR SPIN TORQUE MRAM - Circuitry and a method provide a plurality of timed control and bias voltages to sense amplifiers and write drivers of a spin-torque magnetoresistive random access memory array for improved power supply noise rejection, increased sensing speed with immunity for bank-to-bank noise coupling, and reduced leakage from off word line select devices in an active column. | 10-17-2013 |
| 20130272061 | SPIN CURRENT GENERATOR FOR STT-MRAM OR OTHER SPINTRONICS APPLICATIONS - Spin current generators and systems and methods for employing spin current generators. A spin current generator may be configured to generate a spin current polarized in one direction, or a spin current selectively polarized in two directions. The spin current generator may by employed in spintronics applications, wherein a spin current is desired. | 10-17-2013 |
| 20130272062 | Method and Apparatus for Programming a Spin-Transfer Torque Magnetic Random Access Memory (STTMRAM) Array - A spin-transfer torque memory random access memory (STTMRAM) cell is disclosed comprising a selected magnetic tunnel junction (MTJ) identified to be programmed; a first transistor having a first port, a second port and a gate, the first port of the first transistor coupled to the selected MTJ; a first neighboring MTJ coupled to the selected MTJ through the second port of the first transistor; a second transistor having a first port, a second port, and a gate, the first port of the second transistor coupled to the selected MTJ; a second neighboring MTJ coupled to the selected MTJ through the second port of the second transistor; a first bit/source line coupled to the second end of the selected MTJ; and a second bit/source line coupled to the second end of the first neighboring MTJ and the second end of the second neighboring MTJ. | 10-17-2013 |
| 20130279243 | METHOD TO REDUCE READ ERROR RATE FOR SEMICONDUCTOR RESISTIVE MEMORY - During Magnetic Random Access Memory (MRAM) write operation with opposite electrical current direction through the Magnetic tunnel junction (MTJ), two different resistance of the MTJ can be stored at the MRAM cell as logic data “1” (data_1) and logic data “0” (data_0). The data_1 and data_0 can be read out by sensing the difference in resistance of the MTJ. However, due to the process uniformity, the distribution of resistance value for data_1 (R1) and the distribution of resistance value for data_0 (R0) can be overlapped. Those cells with the distribution of resistance value located in the overlapped region will produce a read error. An additional read and/or write cycle is added to the normal read or write operation to reduce read error rate. Multiple electrical reference current for read operation is added in order to widen the process window and manufacturing margin. | 10-24-2013 |
| 20130279244 | HIERARCHICAL MEMORY MAGNETORESISTIVE RANDOM-ACCESS MEMORY (MRAM) ARCHITECTURE - A hierarchical memory magnetoresistive random-access memory architecture is disclosed. In a particular embodiment, an apparatus includes a first magnetoresistive random-access memory (MRAM) device corresponding to a first level in a hierarchical memory system. The apparatus includes a second MRAM device corresponding to a second level in the hierarchical memory system. The first MRAM device has a first access latency and includes a first magnetic tunnel junction (MTJ) device having a first physical configuration. The second MRAM device has a second access latency and includes a second WI device having a second physical configuration. The first access latency is less than the second access latency. | 10-24-2013 |
| 20130286721 | LOW SENSING CURRENT NON-VOLATILE FLIP-FLOP - A low sensing current non volatile flip flop includes a first stage to sense a resistance difference between two magnetic tunnel junctions (MTJs) and a second stage having circuitry to amplify the output of the first stage. The output of the first stage is initially pre-charged and determined by the resistance difference of the two MTJs when the sensing operation starts. The first stage does not have a pull-up path to a source voltage (VDD), and therefore does not have a DC path from VDD to ground during the sensing operation. A slow sense enable (SE) signal slope reduces peak sensing current in the first stage. A secondary current path reduces the sensing current duration of the first stage. | 10-31-2013 |
| 20130286722 | SPIN TORQUE TRANSFER MEMORY CELL STRUCTURES AND METHODS - Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures include a tunneling barrier material positioned between a ferromagnetic storage material and a pinned ferromagnetic material in contact with an antiferromagnetic material. The tunneling barrier material is a multiferroic material and the antiferromagnetic material, the ferromagnetic storage material, and the pinned ferromagnetic material are positioned between a first electrode and a second electrode. | 10-31-2013 |
| 20130286723 | MAGNETIC RANDOM ACCESS MEMORY WITH FIELD COMPENSATING LAYER AND MULTI-LEVEL CELL - A spin toque transfer magnetic random access memory (STTMRAM) element comprises a reference layer, which can be a single layer structure or a synthetic multi-layer structure, formed on a substrate, with a fixed perpendicular magnetic component. A junction layer is formed on top of the reference layer and a free layer is formed on top of the junction layer with a perpendicular magnetic orientation, at substantially its center of the free layer and switchable. A spacer layer is formed on top of the free layer and a fixed layer is formed on top of the spacer layer, the fixed layer has a fixed perpendicular magnetic component opposite to that of the reference layer. The magnetic orientation of the free layer switches relative to that of the fixed layer. The perpendicular magnetic components of the fixed layer and the reference layer substantially cancel each other and the free layer has an in-plane edge magnetization field. | 10-31-2013 |
| 20130294150 | METHOD AND APPARATUS FOR TESTING A RESISTIVE MEMORY ELEMENT - Methods and apparatus for testing a resistive memory element are provided. In an example, an initial test resistor in a resistance network coupled to a first input of a sense amplifier is selected, where the resistive memory element is coupled. to a second input of the sense amplifier and an output of the sense amplifier is measured. Another test resistor is selected based on the output of the sense amplifier and both the measuring the output step and the selecting another test resistor step are repeated until the output of the sense amplifier changes. A resistance of the resistive memory element is estimated based on the last test resistor selected, where the selected test resistors and the resistive memory element pass respective currents having substantially similar amplitudes and are coupled to respective access transistors having substantially similar properties. | 11-07-2013 |
| 20130294151 | MAGNETIC MEMORY DEVICES AND METHODS OF OPERATING THE SAME - A magnetic memory device includes: a free layer for storing information; and a reference layer disposed on a first surface of the free layer. The reference layer includes at least two magnetic domains and a magnetic domain wall between the at least two magnetic domains. The reference layer extends past both ends of the free layer. The magnetic memory device further includes a switching element connected to a second surface of the free layer. Another magnetic memory device includes: a first reference layer having a first magnetic domain wall; a second reference layer having a second magnetic domain wall; and a memory structure between the first and second reference layers. The memory structure includes: a first free layer adjacent to the first reference layer; a second free layer adjacent to the second reference layer; and a switching element between the first and second free layers. | 11-07-2013 |
| 20130301345 | MAGNETIC RANDOM ACCESS MEMORY AND MEMORY SYSTEM - According to one embodiment, a magnetic random access memory includes a write circuit to write s-bit (s is a natural number equal to 2 or greater) write data to magnetoresistive elements, and a read circuit to read s-bit read data from the magnetoresistive elements. The control circuit is configured to select one of first and second modes based on a mode selection signal, read the read data by the read circuit and write one of the write data and inversion data of the write data to the magnetoresistive elements by the write circuit based on the read data and the write data if free space of the buffer memory is equal to a fixed value or more when the second mode is selected. | 11-14-2013 |
| 20130301346 | SELF REFERENCING SENSE AMPLIFIER FOR SPIN TORQUE MRAM - Circuitry and a method provide self-referenced sensing of a resistive memory cell by using its characteristic of resistance variation with applied voltage in one state versus a relatively constant resistance regardless of the applied voltage in its opposite state. Based on an initial bias state with equalized resistances, a current comparison at a second bias state between a mock bit line and a bit line is used to determine the state of the memory cell, since a significant difference in current implies that the memory cell state has a significant voltage coefficient of resistance. An offset current applied to the mock bit line optionally may be used to provide symmetry and greater sensing margin. | 11-14-2013 |
| 20130301347 | Shared Bit Line SMT MRAM Array with Shunting Transistors Between Bit Lines - An array of rows and columns of SMT MRAM cells has each of the columns associated with one of its adjacent columns. Each of the SMT MRAM cells of the column is connected to a true data bit line and each of the SMT MRAM cells of the associated pair of columns is connected to a shared complement data bit line. A shunting switch device is connected between each of the true data bit lines and the shared complement data bit line for selectively connecting one of the true data bit lines to the shared complement data bit line to effectively reduce the resistance of the complement data bit line and to eliminate program disturb effects in adjacent non-selected columns of the SMT MRAM cells. | 11-14-2013 |
| 20130308373 | Nonvolatile Latch Circuit - One embodiment of a nonvolatile latch circuit comprises a latch circuitry configurated to temporarily hold data and comprising a first output terminal, the latch circuitry is coupled to a high voltage source at a first source terminal and to a low voltage source at a second source terminal, and a first nonvolatile memory element configurated to store said data and comprising a low resistance and a high resistance. The first memory element is connected in-series with a first transistor and coupled between the first output terminal and an intermediate voltage source. The resistance of the first memory element is changed by a bidirectional current running between the first output terminal and the intermediate voltage source, wherein an electrical potential of the intermediate voltage source is higher than that of the low voltage source but lower than that of the high voltage source. Other embodiments are described and shown. | 11-21-2013 |
| 20130308374 | CIRCUIT AND METHOD FOR CONTROLLING MRAM CELL BIAS VOLTAGES - A cell bias control circuit maximizes the performance of devices in the read/write path of memory cells (magnetic tunnel junction device+transistor) without exceeding leakage current or reliability limits by automatically adjusting multiple control inputs of the read/write path at the memory array according to predefined profiles over supply voltage, temperature, and process corner variations by applying any specific reference parameter profiles to the memory array. | 11-21-2013 |
| 20130308375 | Semiconductor Integrated Circuit for Low and High Voltage Operations - A semiconductor integrated circuit comprising a first circuit area for a low voltage operation and a second circuit area for a high voltage operation. The circuit areas comprise two vertically stacked backend patterned metal layers that are separated by an inter-metallic dielectric (IMD). The two metal layers and the IMD form a combination that is operable at the low voltage. The first circuit area uses a first portion of the combination for operating at the low voltage and the second circuit area uses a second portion of the combination for routing at the high voltage, the two metal layers in the second portion being interconnected through the IMD by via hole, for withstanding the high voltage. The first portion may comprise an array of magnetic random access memory (MRAM) devices and the second circuit area may comprise a display drive circuit. | 11-21-2013 |
| 20130314978 | LOW ENERGY MAGNETIC DOMAIN WALL LOGIC DEVICE - A logic gate device is disclosed. The logic gate device structure can include a magnetic tunnel junction on a soft ferromagnetic wire to provide a readout. One input contact can be at one end of the soft ferromagnetic wire and a second input contact can be at the other end of the soft ferromagnetic wire to control domain wall position in the soft ferromagnetic wire. | 11-28-2013 |
| 20130314979 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell unit including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines, and configured to provide a read value in response to an activated word line, a reference value generating unit including a plurality of reference value generating cells coupled between the plurality of word lines and a reference bit line, and configured to provide a single reference value in response to the activated word line, and a sense circuit configured to provide a sense output signal based on the single reference value and the read value. | 11-28-2013 |
| 20130314980 | ROW-DECODER CIRCUIT AND METHOD WITH DUAL POWER SYSTEMS - A Spin-Transfer-Torque Magnetic Random Access Memory includes a dual-voltage row decoder with charge sharing for read operations. The dual-voltage row decoder with charge sharing for read operations reduces read-disturbance failure rates and provides a robust macro design with improved yields. Voltage from one of the power supplies can be applied during a write operation. | 11-28-2013 |
| 20130314981 | MAGNETIC SHIFT REGISTER MEMORY DEVICE - In one embodiment, the invention is a magnetic shift register memory device. One embodiment of a memory cell includes a magnetic column including a plurality of magnetic domains, a reader coupled to the magnetic column, for reading data from the magnetic domains, a temporary memory for storing data read from the magnetic domains, and a writer coupled to the magnetic column, for writing data in the temporary memory to the magnetic domains. | 11-28-2013 |
| 20130314982 | Method for Magnetic Screening of Arrays of Magnetic Memories - A testing method is described that applies a sequence external magnetic fields of varying strength to MRAM cells (such as those with MTJ memory elements) in chips or wafers to selectively screen out cells with low or high thermal stability factor. The coercivity (Hc) is used as a proxy for thermal stability factor (delta). In the various embodiments the sequence, direction and strength of the external magnetic fields is used to determine the high coercivity cells that are not switched by a normal field and the low coercivity cells that are switched by a selected low field. In some embodiments the MRAM's standard internal electric current can be used to switch the cells. Standard circuit-based resistance read operations can be used to determine the response of each cell to these magnetic fields and identify the abnormal high and low coercivity cells. | 11-28-2013 |
| 20130322161 | MAGNETIC RANDOM ACCESS MEMORY - According to one embodiment, a magnetic random access memory includes a write circuit to write complementary data to first and second magnetoresistive elements, and a read circuit to read the complementary data from the first and second magnetoresistive elements. The control circuit is configured to change the first and second bit lines to a floating state after setting the first and second bit lines to a first potential, and change a potential of the first bit line in the floating state to a first value in accordance with a resistance value of the first magnetoresistive element and a potential of the second bit line in the floating state to a second value in accordance with a resistance value of the second magnetoresistive element by setting the common source line to a second potential higher than the first potential. | 12-05-2013 |
| 20130322162 | SEMICONDUCTOR MEMORY DEVICES AND RELATED METHODS OF OPERATION - A semiconductor memory device includes a cell array including one or more bank groups, where each of the one or more bank groups includes a plurality of banks and each of the plurality of banks includes a plurality of spin transfer torque magneto resistive random access memory (STT-MRAM) cells. The semiconductor memory device further includes a source voltage generating unit for applying a voltage to a source line connected to the each of the plurality of STT-MRAM cells, and a command decoder for decoding a command from an external source in order to perform read and write operations on the plurality of STT-MRAM cells. The command includes a combination of at least one signal of a row address strobe (RAS), a column address strobe (CAS), a chip selecting signal (CS), a write enable signal (WE), and a clock enable signal (CKE) | 12-05-2013 |
| 20130322163 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a first cell array includes memory cells and reference cells, a second cell array located adjacent to the first cell array in a first direction, a third cell array located adjacent to the first cell array in a second direction crossing the first direction, a fourth cell array located adjacent to the second cell array in the second direction, and a sense amplifier connected to the first to fourth cell array and configured to compare a current through a memory cell with a current through a reference cell to determine the data of the memory cell. A reference cell is selected from a cell array which is diagonally opposite to a cell array as a read target. | 12-05-2013 |
| 20130329488 | METHOD OF SENSING DATA OF A MAGNETIC RANDOM ACCESS MEMORIES (MRAM) - A MTJ is sensed by applying a first reference current, first programming the MTJ to a first value using the first reference current, detecting the resistance of the first programmed MTJ, and if the detected resistance is above a first reference resistance, declaring the MTJ to be at a first state. Otherwise, upon determining if the detected resistance is below a second reference resistance, declaring the MTJ to be at a second state. In some cases, applying a second reference current through the MTJ and second programming the MTJ to a second value using the second reference current. Detecting the resistance of the second programmed MTJ and in some cases, declaring the MTJ to be at the second state, and in other cases, declaring the MTJ to be at the first state and programming the MTJ to the second state. | 12-12-2013 |
| 20130329489 | MAGNETO-RESISTIVE MEMORY DEVICE INCLUDING SOURCE LINE VOLTAGE GENERATOR - A MRAM includes a memory cell array of spin-transfer torque magnetic random access memory (STT-MRAM) cells and a source line commonly connected to the plurality of STT-MRAM cells. A source line voltage generator generates a source line driving voltage in response to an external power supply voltage and provides the source line driving voltage to the source line. | 12-12-2013 |
| 20130329490 | METHOD OF SWITCHING OUT-OF-PLANE MAGNETIC TUNNEL JUNCTION CELLS - A method of switching the magnetization orientation of a ferromagnetic free layer of an out-of-plane magnetic tunnel junction cell, the method including: passing an AC switching current through the out-of-plane magnetic tunnel junction cell, wherein the AC switching current switches the magnetization orientation of the ferromagnetic free layer. | 12-12-2013 |
| 20130336045 | SPIN TRANSFER TORQUE MEMORY (STTM) DEVICE WITH HALF-METAL AND METHOD TO WRITE AND READ THE DEVICE - Spin transfer torque memory (STTM) devices with half-metals and methods to write and read the devices are described. For example, a magnetic tunneling junction includes a free magnetic layer, a fixed magnetic layer, and a dielectric layer disposed between the free magnetic layer and the fixed magnetic layer. One or both of the free magnetic layer and the fixed magnetic layer includes a half-metal material at an interface with the dielectric layer. | 12-19-2013 |
| 20130343116 | WRITING CIRCUIT FOR A MAGNETORESISTIVE MEMORY CELL, MEMORY CELL ARRANGEMENT AND METHOD OF WRITING INTO A MAGNETORESISTIVE MEMORY CELL OF A MEMORY CELL ARRANGEMENT - A writing circuit for a magnetoresistive memory cell is provided. The writing circuit includes a first electrical connecting terminal, a second electrical connecting terminal, a third electrical connecting terminal, a fourth electrical connecting terminal, a first reference potential terminal, a second reference potential terminal, a first switch configured to couple one of the first electrical connecting terminal, the second electrical connecting terminal, the third electrical connecting terminal and the fourth electrical connecting terminal to the magnetoresistive memory cell, and a second switch configured to couple the first reference potential terminal to the magnetoresistive memory cell if the first electrical connecting terminal or the second electrical connecting terminal is coupled to the magnetoresistive memory cell, and to couple the second reference potential terminal to the magnetoresistive memory cell if the third electrical connecting terminal or the fourth electrical connecting terminal is coupled to the magnetoresistive memory cell. | 12-26-2013 |
| 20130343117 | WRITING CIRCUIT FOR A MAGNETORESISTIVE MEMORY CELL - According to embodiments of the present invention, a writing circuit for a magnetoresistive memory cell is provided. The writing circuit includes a first connecting terminal configured to provide a first electrical signal to switch a variable magnetization orientation of the free magnetic layer from a first magnetization orientation to a second magnetization orientation; a second connecting terminal configured to provide a second electrical signal to switch the magnetization orientation from the second magnetization orientation to the first magnetization orientation; and a sourcing switch configured to provide for a write operation a connection of the first or second connecting terminal to a node coupleable to the magnetoresistive memory cell. The first and second electrical signals have different amplitudes, and the first and second electrical signals are of the same polarity. Further embodiments relate to a memory cell arrangement and a method of writing into a target magnetoresistive memory cell. | 12-26-2013 |
| 20130343118 | MAGNETIC MEMORY DEVICES AND METHODS OF OPERATING THE SAME - Magnetic memory devices, and methods of operating the same, include a magnetoresistive element including a free layer, a pinned layer, and a separation layer between the free layer and the pinned layer. The devices, and methods, further include a first conductive line connected to the free layer and configured to apply a Rashba field to, or induce the Rashba field in, the free layer, and a second conductive line spaced apart from the free layer and configured to apply an external magnetic field to the free layer. A magnetization direction of the free layer is switchable by application of the Rashba field and the external magnetic field to the free layer. | 12-26-2013 |
| 20140003137 | DETERMINING DEVICE AND DETERMINING METHOD | 01-02-2014 |
| 20140003138 | UNIPOLAR SPIN-TRANSFER SWITCHING MEMORY UNIT | 01-02-2014 |
| 20140010004 | MAGNETIC MEMORY - A magnetic memory includes: a base layer; a magnetization free layer; a barrier layer; and a magnetization reference layer. The magnetization free layer, with which the base layer is covered, has invertible magnetization and is magnetized approximately uniformly. The barrier layer, with which the magnetization free layer is covered, is composed of material different from material of the base layer. The magnetization reference layer is arranged on the barrier layer and has a fixed magnetization. When the magnetization of the magnetization free layer is inverted, a first writing current is made to flow from one end to the other end of the magnetization free layer in an in-plane direction without through the magnetization reference layer. | 01-09-2014 |
| 20140016404 | MAGNETIC RANDOM ACCESS MEMORY - A magnetic memory device such as a magnetic random access memory (MRAM), and a memory module and a memory system on which the magnetic memory device is mounted are disclosed. The MRAM includes magnetic memory cells each of which varies between at least two states according to a magnetization direction and an interface unit that provides various interface functions. The memory module includes a module board and at least one MRAM chip mounted on the module board, and further includes a buffer chip that manages an operation of the at least one MRAM chip. The memory system includes the MRAM and a memory controller that communicates with the MRAM, and may communicate an electric-to-optical conversion signal or an optical-to-electric conversion signal by using an optical link that is connected between the MRAM and the memory controller. | 01-16-2014 |
| 20140016405 | THERMALLY ASSISTED MAGNETIC WRITING DEVICE - A magnetic thermally-assisted switching device includes a reference layer, a storage layer magnetised along a variable direction, a spacer that separates the reference layer and the storage layer, and magnetically decouples them, a device for heating the pinning layer so that, during heating, the temperature of the pinning layer exceeds its blocking temperature such that the direction of magnetisation of the storage layer is no longer pinned, a device for applying a writing magnetic torque tending to align the magnetisation of the storage layer along one of two stable magnetisation directions once the blocking temperature is reached. The device also includes a device for applying a magnetic polarisation field at least during the heating phase before the blocking temperature is reached such that the direction of magnetisation of the storage layer is always along the direction of the magnetic polarisation field at the moment that the blocking temperature is reached. | 01-16-2014 |
| 20140022836 | SEMICONDUCTOR MEMORY DEVICE HAVING RESISTIVE MEMORY CELLS AND METHOD OF TESTING THE SAME - A semiconductor memory device includes a memory cell array, a mode register set and a test circuit. The memory cell array includes a plurality of wordlines, a plurality of bitlines, and a plurality of spin-transfer torque magneto-resistive random access memory (STT-MRAM) cells, and each STT-MRAM cell disposed in a cross area of each wordline and bitline, and the STT-MRAM cell includes a magnetic tunnel junction (MTJ) element and a cell transistor. The MTJ element includes a free layer, a barrier layer and a pinned layer. A gate of the cell transistor is coupled to a wordline, a first electrode of the cell transistor is coupled to a bitline via the MTJ element, and a second electrode of the cell transistor is coupled to a source line. The mode register set is configured to set a test mode, and the test circuit is configured to perform a test operation by using the mode register set. | 01-23-2014 |
| 20140022837 | RANDOM BIT GENERATOR WITH MAGNETIC TUNNEL JUNCTION - Devices and methods for generating a random number that utilizes a magnetic tunnel junction are disclosed. An AC current source can be in electrical connection to a magnetic tunnel junction to provide an AC current to the magnetic tunnel junction. A read circuit can be used to determine a bit based on a state of the magnetic tunnel junction. A rate of production of the bits can be adjusted, such as by adjusting a frequency or amplitude of the AC current. A probability of obtaining a “0” or “1” bit can be managed, such as by an addition of DC biasing to the AC current. | 01-23-2014 |
| 20140022838 | MAGNENTIC RESISTANCE MEMORY APPARATUS HAVING MULTI LEVELS AND METHOD OF DRIVING THE SAME - A magnetic resistance memory apparatus capable of implementing various levels and a method of driving the same are provided. The magnetic resistance memory apparatus includes a first magnetic device that includes a fixed layer having a fixed magnetization direction, a tunnel layer disposed on the fixed layer, and a first free layer disposed on the tunnel layer having a variable magnetization direction, and a second magnetic device disposed on the first magnetic device including a plurality of free layers insulated with a spacer layer interposed. | 01-23-2014 |
| 20140029334 | MAGNETIC FIELD SENSING USING MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM) CELLS - A magnetic field sensing system includes one or more magnetoresistive random access memory (MRAM) cells, and may be configured to determine one or more of a presence, a magnitude, and a polarity of an external magnetic field incident upon an MRAM cell. In some examples, a control module of the system controls a write current source, or another device, to provide a write current through a write line associated with the MRAM cell to induce a magnetic field proximate to the MRAM cell. The magnetic field may be less than a magnetic switching threshold of the MRAM cell. After initiating the provision of the write current through the write line, the control module may determine a magnetic state of the MRAM cell, and determine a presence of an external magnetic field incident upon the MRAM cell based at least in part on the magnetic state of the MRAM cell. | 01-30-2014 |
| 20140036582 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device comprises a memory cell configured to store or output data in a magneto-resistance device in response to a write current applied to a bit line and a source line. A voltage detector is configured to sense potentials loaded in the bit line and the source line. A write current controller configured to control activation of a write control signal in response to an output of the voltage detector, and a write driver configured to control amounts of write current applied to the memory cell according to the activation of the write control signal. | 02-06-2014 |
| 20140043890 | MONOLITHIC MULTI-CHANNEL ADAPTABLE STT-MRAM - A monolithic multi-channel resistive memory includes at least one first bank associated with a first channel and tuned according to first device attributes and/or first circuit attributes. The memory also includes at least one second bank associated with a second channel and tuned according to second device attributes and/or second circuit attributes. | 02-13-2014 |
| 20140043891 | NONVOLATILE CORRUPTION RESISTENT MAGNETIC MEMORY AND METHOD THEREOF - A method and system for storing information in a nonvolatile memory comprising: a substrate comprising magnetic material operatively associated therewith, the magnetic material having at least one first portion of low permeability and at least one second portion of high permeability; a reader comprising a sensor for reading information by measuring the magnetic permeability for the at least one first portion and the at least one second portion; whereby the at least one first and second portions are subjected to a magnetic probe field from one of an external source, the sensor, or a combination of an external source and the sensor. | 02-13-2014 |
| 20140043892 | SEMICONDUCTOR MEMORY DEVICE HAVING VARIABLE RESISTANCE MEMORY AND OPERATING METHOD - A semiconductor memory device includes a memory cell array of nonvolatile memory cells having a variable resistance element, and a conductor line array capable of generating a compensation magnetic field for the nonvolatile memory cells. A current driver selectively supplies current to conductive lines, a magnetic field sensor senses an applied external magnetic field and generates external magnetic field information, and a controller controls generation of the compensation magnetic field in response to the external magnetic field information. | 02-13-2014 |
| 20140050019 | MULTI-LEVEL MEMORY CELL USING MULTIPLE MAGNETIC TUNNEL JUNCTIONS WITH VARYING MGO THICKNESS - A Multi-Level Memory Cell (MLC) using multiple Magnetic Tunnel Junction (MTJ) structures having one or more layers with varying thickness is disclosed. The multiple MTJ structures, which are vertically stacked and arranged in series, may have substantially identical area dimensions to minimize fabrication costs because one mask can be used to pattern the multiple MTJ structures. Further, varying the thicknesses associated with the one or more layers may provide the multiple MTJ structures with different switching current densities and thereby increase memory density and improve read and write operations. In one embodiment, the layers with the varying thicknesses may include tunnel barriers or magnesium oxide layers associated with the multiple MTJ structures and/or free layers associated with the multiple MTJ structures. | 02-20-2014 |
| 20140050020 | ARCHITECTURE OF MAGNETO-RESISTIVE MEMORY DEVICE - Provided is a semiconductor memory device including a column decoder, a plurality of sub-cell blocks, and a bit line selection circuit. The column decoder is configured to decode column addresses and drive column selection signals. Each of the sub-cell blocks includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells connected to the plurality of bit lines and the plurality of word lines. The bit line selection circuit includes a plurality of bit line connection controllers, and is configured to select one or more bit lines in response to the column selection signals. Each of the bit line connection controllers electrically couples a respective first bit line to corresponding first and second local input/output (I/O) lines in response to first and second column selection signals of the column selection signals, respectively. | 02-20-2014 |
| 20140056058 | Differential Sensing Method and System for STT MRAM - The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In accordance with one aspect of the invention, a system for reading a memory cell includes a read path and a precharge path. The reference current is provided through the read path and is sampled via a sampling element in the read path. Subsequently, a current from the memory cell is provided through the same sampling element and read path. The output level is then determined by the cell current working against the sampled reference current. | 02-27-2014 |
| 20140056059 | Symmetrical Differential Sensing Method and System for STT MRAM - The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In one example, a system for reading a memory cell includes a sense path and an inverse path. A reference current is provided through the sense path and is sampled via a first sampling element in the sense path, and a cell current from the memory cell is provided through the inverse sense path and is sampled via a second sampling element in the inverse sense path. Subsequently, the memory cell is disconnected from the inverse sense path, the cell current is provided through the sense path, the reference source is disconnected from the sense path, and the reference current is provided through the inverse sense path. The output levels are then determined by the cell and reference currents working against the sampled reference and sampled cell currents. | 02-27-2014 |
| 20140056060 | METHOD AND SYSTEM FOR PROVIDING A MAGNETIC TUNNELING JUNCTION USING SPIN-ORBIT INTERACTION BASED SWITCHING AND MEMORIES UTILIZING THE MAGNETIC TUNNELING JUNCTION - A magnetic memory is described. The magnetic memory includes magnetic junctions and at least one spin-orbit interaction (SO) active layer. Each of the magnetic junctions includes a data storage layer that is magnetic. The SO active layer(s) are adjacent to the data storage layer of the magnetic junction. The at SO active layer(s) are configured to exert a SO torque on the data storage layer due to a current passing through the at least one SO active layer in a direction substantially perpendicular to a direction between the at least one SO active layer and the data storage layer of a magnetic junction of the plurality of magnetic junctions closest to the at least one SO active layer. The data storage layer is configured to be switchable using at least the SO torque. | 02-27-2014 |
| 20140056061 | METHOD AND SYSTEM FOR PROVIDING DUAL MAGNETIC TUNNELING JUNCTIONS USING SPIN-ORBIT INTERACTION-BASED SWITCHING AND MEMORIES UTILIZING THE DUAL MAGNETIC TUNNELING JUNCTIONS - A magnetic memory is described. The magnetic memory includes dual magnetic junctions and spin-orbit interaction (SO) active layer(s). Each dual magnetic junction includes first and second reference layers, first and second nonmagnetic spacer layers and a free layer. The free layer is magnetic and between the nonmagnetic spacer layers. The nonmagnetic spacer layers are between the corresponding reference layers and the free layer. The SO active layer(s) are adjacent to the first reference layer of each dual magnetic junction. The SO active layer(s) exert a SO torque on the first reference layer due to a current passing through the SO active layer(s) substantially perpendicular to a direction between the SO active layer(s) and the first reference layer. The first reference layer has a magnetic moment changeable by at least the SO torque. The free layer is switchable using a spin transfer write current driven through the dual magnetic junction. | 02-27-2014 |
| 20140063921 | METHOD AND SYSTEM FOR PROVIDING INVERTED DUAL MAGNETIC TUNNELING JUNCTION ELEMENTS - A method and system for providing a magnetic junction residing on a substrate and usable in a magnetic device are described. The magnetic junction includes a first pinned layer, a first nonmagnetic spacer layer having a first thickness, a free layer, a second nonmagnetic spacer layer having a second thickness greater than the first thickness, and a second pinned layer. The first nonmagnetic spacer layer resides between the pinned layer and the free layer. The first pinned layer resides between the free layer and the substrate. The second nonmagnetic spacer layer is between the free layer and the second pinned layer. Further, the magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. | 03-06-2014 |
| 20140063922 | MRAM WORD LINE POWER CONTROL SCHEME - Systems, circuits and methods for controlling word line (WL) power levels at a WL of a Magnetoresistive Random Access Memory (MRAM). The disclosed power control scheme uses existing read/write commands and an existing power generation module associated, with the MRAM to supply and control WL power levels, thereby eliminating the cost and increased die-size of schemes that control WL power through relatively large and expensive power control switches and control circuitry on the MRAM macro. | 03-06-2014 |
| 20140063923 | Mismatch Error Reduction Method and System for STT MRAM - The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In accordance with one aspect of the invention, a method for reading a memory cell includes combining a cell current from a memory cell with a reference current from a reference source to create an average current, enabling the average current to flow through a first mirror transistor in a sense path and a second mirror transistor in a reference path, storing the current mismatch on a capacitor coupled to the gates of the first mirror transistor and the second mirror transistor, disconnecting the memory cell from the reference path and disconnecting the reference source from the sense path, enabling the cell current only to flow through the sense path, and determining the output level of the memory cell. | 03-06-2014 |
| 20140063924 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD OF THE SAME - According to one embodiment, a nonvolatile semiconductor memory device comprises a semiconductor substrate, and a memory cell which is arranged on the semiconductor substrate and comprises a variable resistance element. The variable resistance element comprises a laminated structure including a phase-change element which has at least two different crystalline resistance states by varying a crystalline state, and a magnetoresistive element which has at least two different magnetization resistance states by varying a magnetization state, and applies or does not apply a magnetic field to the phase-change element in accordance with the magnetization state. | 03-06-2014 |
| 20140071738 | REFERENCE CELL REPAIR SCHEME - In a magnetic random access memory (MRAM), numerous arrays of reference bit cells are coupled together by coupling their respective bit lines to a merged reference node. Pass gate circuitry coupled between the respective reference bit lines and the merged reference node is configured for selectively coupling or decoupling one or more of the reference bit lines to and from the merged reference node. The pass gate circuitry is controllable by programming one-time programmable devices coupled to the pass gate circuitry. The one-time programmable devices can be programmed to decouple flawed arrays of reference bit cells from the merged reference node or to select between redundant arrays of reference bit cells for coupling to the reference node. | 03-13-2014 |
| 20140071739 | REFERENCE LEVEL ADJUSTMENT SCHEME - A tunable reference cell scheme for magnetic random access memory (MRAM) circuitry selectively couples reference cells and data cells to shared write driver circuitry. Magnetic tunnel junctions (MTJs) in the reference cells can be programmed to a selected magnetic orientation using the shared write driver circuitry. The programmed reference cells can be merged with other programmed reference cells and/or with fixed reference cells to produce a tunable reference level for comparison with MTJ data cells during a read operation. Sharing write driver circuitry between data cells and reference cells allows programming of reference cells without consuming increased area on a chip or macro. | 03-13-2014 |
| 20140071740 | OTP SCHEME WITH MULTIPLE MAGNETIC TUNNEL JUNCTION DEVICES IN A CELL - A one time programming (OTP) apparatus unit cell includes multiple magnetic tunnel junctions (MTJs) and a shared access transistor coupled between the multiple MTJs and a fixed potential. Each of the multiple MTJs in a unit cell can be coupled to separate programming circuitry and/or separate sense amplifier circuitry so that they can be individually programmed and/or individually sensed. A logical combination from the separate sense amplifiers can be generated as an output of the unit cell. | 03-13-2014 |
| 20140071741 | OTP CELL WITH REVERSED MTJ CONNECTION - A one time programming (OTP) apparatus unit cell includes magnetic tunnel junctions (MTJs) with reversed connections for placing the MTJ in an anti-parallel resistance state during programming. Increased MTJ resistance in its anti-parallel resistance state causes a higher programming voltage which reduces programming time and programming current. | 03-13-2014 |
| 20140071742 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - According to one embodiment, a semiconductor memory device comprises a magnetoresistive element including a memory layer having a variable magnetization direction and made of a material which changes from ferromagnetism to paramagnetism when a voltage is applied, a reference layer having an invariable magnetization direction, and a tunnel barrier layer formed between the memory layer and the reference layer, a first interconnection electrically connected to one terminal of the magnetoresistive element, and a second interconnection electrically connected to the other terminal of the magnetoresistive element, and a third interconnection electrically insulated from the magnetoresistive element. | 03-13-2014 |
| 20140071743 | MEMORY SYSTEM INCLUDING NONVOLATILE MEMORY DEVICE AND CONTROL METHOD THEREOF - A memory system is provided including a host configured to generate data bit inversion (DBI) information of data according to a major bit of the data, and a nonvolatile memory device configured to invert one or more bits of the data according to the DBI information, and to program the DBI information and the data. A control method of a memory system comprises generating DBI information according to the number of “1” bits of data relative to the number of “0” bits of the data, transferring the data and the DBI information, and inverting bits of the data according to the DBI information, the inverted bits of the data being programmed at the nonvolatile memory device. | 03-13-2014 |
| 20140071744 | NONVOLATILE MEMORY MODULE, MEMORY SYSTEM INCLUDING NONVOLATILE MEMORY MODULE, AND CONTROLLING METHOD OF NONVOLATILE MEMORY MODULE - A memory system is provided, which includes a nonvolatile memory module including a plurality of nonvolatile memory devices, and a memory module controller configured to control the nonvolatile memory module. At least two nonvolatile memory devices of the plurality of nonvolatile memory devices are configured to store serial presence detect (SPD) information. The memory module controller is configured to read the SPD information from the nonvolatile memory module and to set a communication mode with the nonvolatile memory module based on the read SPD information. | 03-13-2014 |
| 20140071745 | MAGNETORESISTIVE MEMORY DEVICE - According to one embodiment, a magnetoresistive memory device includes first and second bit lines, a memory cell, a power supply line, first and second transistors, and third and fourth transistors. The memory cell has first and second magnetoresistive elements and is connected between the first and second bit lines. The power supply line is connected between the first and second magnetoresistive elements. The first and second transistors have current paths inserted in the first and second bit lines, respectively, and have gate electrodes connected, respectively to the second and first bit lines provided on a side opposite to the memory cell. The third and fourth transistors are inserted in the first and second bit lines. Gate electrodes of the third and fourth transistors are cross-coupled, and the third and fourth transistors are controlled by current from the memory cell. | 03-13-2014 |
| 20140085968 | NONVOLATILE MEMORY DEVICE - According to one embodiment, a nonvolatile memory device includes: a magnetic memory element and a control unit. The magnetic memory element includes a stacked body, and a first and a second stacked units. The first stacked unit includes a first and second ferromagnetic layers and a first nonmagnetic layer provided between the first and the second ferromagnetic layers. The second stacked unit includes a third ferromagnetic layer and a nonmagnetic tunneling barrier layer stacked with the third ferromagnetic layer. The control unit is configured to implement a first operation of setting the magnetic memory element to be in a first state. The first operation includes a first preliminary operation of applying a first pulse voltage; and a first setting operation of applying a second pulse voltage having a second rising time to the magnetic memory element after the first preliminary operation. | 03-27-2014 |
| 20140085969 | NONVOLATILE MEMORY DEVICE - According to one embodiment, a nonvolatile memory device includes a memory unit and a control unit. The memory unit includes a magnetic memory element which includes: a first and second ferromagnetic layers; and a first nonmagnetic layer provided between the first and the second ferromagnetic layers. The memory unit includes a magnetic field application unit configured to apply a magnetic field to the second ferromagnetic layer, the magnetic field having a component in a first in-plane direction perpendicular to a stacking direction. The control unit is electrically connected to the magnetic memory element, and is configured to implement a setting operation of changing a voltage between the first and the second ferromagnetic layers from a first set voltage to a second set voltage. The magnetic field applied by the magnetic field application unit satisfies the condition of | 03-27-2014 |
| 20140085970 | MAGNETIC MEMORY - A magnetic memory includes a magnetic wire, a first insulating layer, first electrodes a second electrode, a current supplying module, and a voltage applying module. The magnetic wire includes a first portion and a second portion, has a first electric resistance value, and is configured to form magnetic domains. The first electrodes are formed on the first insulating layer, arranged along the magnetic wire, and spaced from each other. The second electrode includes a third portion and a fourth portion. The second electrode is electrically connected to the first electrodes between the third portion and the fourth portion and has a second electric resistance value being larger than the first electric resistance value. The current supplying module is configured to supply the magnetic wire with a pulse current. The voltage applying module is configured to apply a voltage that decreases with time. | 03-27-2014 |
| 20140085971 | MAGNETORESISTIVE EFFECT ELEMENT - According to one embodiment, a magnetoresistive effect element includes the following structure. A first ferromagnetic layer has a variable magnetization direction. A second ferromagnetic layer has an invariable magnetization direction. A tunnel barrier layer is formed between the first and second ferromagnetic layers. An energy barrier between the first ferromagnetic layer and the tunnel barrier layer is higher than an energy barrier between the second ferromagnetic layer and the tunnel barrier layer. The second ferromagnetic layer contains a main component and an additive element. The main component contains at least one of Fe, Co, and Ni. The additive element contains at least one of Mg, Al, Ca, Sc, Ti, V, Mn, Zn, As, Sr, Y, Zr, Nb, Cd, In, Ba, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, and W. | 03-27-2014 |
| 20140085972 | SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM AND ACCESS METHOD TO SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a block array having an m number of memory blocks in a row direction and an n number of memory blocks in a column direction (m being an integer of 2 or more and n being an integer of 1 or more), a page selection circuit configured to select a row in the block array as a page to be selected, and a page buffer configured to store data to be written in a page selected by the page selection circuit or data read from the page. Each of the memory blocks includes a memory cell array having a plurality of memory cells, a row selection circuit configured to select a row of the memory cell array, and a column selection circuit configured to select a column of the memory cell array. | 03-27-2014 |
| 20140092677 | DECREASED SWITCHING CURRENT IN SPIN-TRANSFER TORQUE MEMORY - Switching current in Spin-Transfer Torque Memory (STTM) can be decreased. A magnetic memory cell is driven with a first pulse on a write line of the memory cell to heat the cell. The cell is then driven with a second pulse on the write line to set the state of the cell. | 04-03-2014 |
| 20140098599 | SEMICONDUCTOR MEMORY DEVICE WITH DATA PATH OPTION FUNCTION - A semiconductor memory device may include a memory cell, a bit line connected to the memory cell, a bit line data latch circuit configured to sense-amplify data stored in the memory cell connected to the bit line and to store write data in the memory cell via the bit line; an input/output driver configured to output read data on the bit line to an external device or to drive the write data provided from the external device; and a selection unit configured to select whether the read data and the write data are communicated between the input/output driver and the memory cell with or without use of the bit line data latch circuit. | 04-10-2014 |
| 20140098600 | SEMICONDUCTOR MEMORY DEVICE HAVING DISCRIMINARY READ AND WRITE OPERATIONS ACCORDING TO TEMPERATURE - A semiconductor memory device is provided which includes a memory cell array including magnetic memory cells arranged in a matrix form of rows and columns and connected with bit lines and a source line; and a temperature sensing unit configured to generate a temperature sensing signal by sensing a temperature of the memory cell array. A memory controller, constituting a memory system together with the semiconductor memory device, may control read and write operations of the semiconductor memory device differently according to the temperature sensing signal of the temperature sensing unit. | 04-10-2014 |
| 20140098601 | MAIN MEMORY SYSTEM STORING OPERATING SYSTEM PROGRAM AND COMPUTER SYSTEM INCLUDING THE SAME - A main memory system is provided which includes a nonvolatile memory including a first memory area designated to store an operating system program and a second memory area designated to store user data; and a memory controller configured to control the nonvolatile memory such that the operating system program is loaded onto the second memory area from the first memory area. The nonvolatile memory may be one of a phase change RAM, a resistive RAM, and a magnetic RAM. | 04-10-2014 |
| 20140098602 | METHOD AND APPARATUS OF PROBABILISTIC PROGRAMMING MULTI-LEVEL MEMORY IN CLUSTER STATES OF BI-STABLE ELEMENTS - A probabilistic programming current is injected into a cluster of bi-stable probabilistic switching elements, the probabilistic programming current having parameters set to result in a less than unity probability of any given bi-stable switching element switching, and a resistance of the cluster of bi-stable switching elements is detected. The probabilistic programming current is injected and the resistance of the cluster state detected until a termination condition is met. Optionally the termination condition is detecting the resistance of the cluster of bi-stable switching elements at a value representing a multi-bit data. | 04-10-2014 |
| 20140104937 | MEMORY DEVICE WITH TIMING OVERLAP MODE - In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes. | 04-17-2014 |
| 20140112066 | Circuit Arrangement and Method of Forming the Same - In various embodiments, a circuit arrangement may be provided including a data cell. The circuit arrangement may further include a first transistor and a second transistor. The first controlled electrode of the first transistor and the first controlled electrode of the second transistor may be coupled to the first electrode of the data cell. The second controlled electrode of the first transistor may be configured to electrically connect to a first reference voltage such that the first electrode of the data cell is electrically connected to the first reference voltage when the first transistor is activated. The second controlled electrode of the second transistor may be configured to electrically connect to a second reference voltage, such that the first electrode of the data cell is electrically connected to the second reference voltage when the second transistor is activated. | 04-24-2014 |
| 20140119105 | Adaptive Reference Scheme for Magnetic Memory Applications - A structure and method is described for an adaptive reference used in reading magnetic tunneling memory cells. A collection of magnetic tunneling memory cells are used to form a reference circuit and are coupled in parallel between circuit ground and a reference input to a sense amplifier. Each of the magnetic memory cells used to form the reference circuit are programmed to a magnetic parallel state or a magnetic anti-parallel state, wherein each different state produces a different resistance. By varying the number of parallel states in comparison to the anti-parallel states, where each of the two sates produce a different resistance, the value of the reference circuit resistance can be adjusted to adapt to the resistance characteristics of a magnetic memory data cell to produce a more reliable read of the data programmed into the magnetic memory data cell. | 05-01-2014 |
| 20140119106 | MAGNETIC MEMORY DEVICES AND METHODS OF OPERATING THE SAME - Magnetic memory devices, and methods of operating the same, include a magnetoresistive element, a current apply element for applying a spin transfer torque switching current to the magnetoresistive element, and a magnetic field apply element for applying a non-perpendicular magnetic field to the magnetoresistive element. The magnetic memory device writes data in the magnetoresistive element by using the spin transfer torque switching current and the non-perpendicular magnetic field. The magnetoresistive element includes a free layer and a pinned layer each having a perpendicular magnetic anisotropy. | 05-01-2014 |
| 20140119107 | MAGNETIC MEMORY DEVICE HAVING BIDIRECTIONAL READ SCHEME - A data reading method of a magnetic memory device includes generating read commands, supplying a read current to a selected magnetic memory element in a first direction and in turn in a second direction under different ones of the read commands, respectively, and sensing the magnitude of the read current flowing through the selected magnetic memory element to read data stored at the selected magnetic memory element. | 05-01-2014 |
| 20140119108 | MEMORY SYSTEM INCLUDING NONVOLATILE MEMORY AND METHOD OF OPERATING NONVOLATILE MEMORY - A memory system, and an operation method of a nonvolatile memory, include programming memory cells using a normal program pulse, reading out a first set of data from the memory cells, detecting failed cells based on the first set of data, storing information about the failed cells in a buffer, and reprogramming the failed cells using a reinforced program pulse in an idle state based on the information stored in the buffer. | 05-01-2014 |
| 20140119109 | MAGNETORESISTIVE ELEMENT, MAGNETIC MEMORY, AND METHOD OF MANUFACTURING MAGNETORESISTIVE ELEMENT - According to one embodiment, a magnetoresistive element includes first and second magnetic layers, a first nonmagnetic layer, a conductive layer. The first and second magnetic layers have axes of easy magnetization perpendicular to a film plane. The first and second magnetic layers have variable and invariable magnetization directions, respectively. The first nonmagnetic layer is between the first and second magnetic layers. The conductive layer is on a surface of the first magnetic layer opposite to a surface on which the first nonmagnetic layer is formed. The first magnetic layer has a structure obtained by alternately laminating magnetic and nonmagnetic materials. The nonmagnetic material includes at least one of Ta, W, Nb, Mo, Zr, Hf. The magnetic material includes Co and Fe. One of the magnetic materials contacts the first nonmagnetic layer. One of the nonmagnetic materials contacts the conductive layer. | 05-01-2014 |
| 20140126279 | MAGNETORESISTIVE RANDOM ACCESS MEMORY - A magnetoresistive random access memory (MRAM) apparatus includes a first conductive line and a second conductive line. A magnetic tunnel junction is in electrical communication with the first conductive line and the second conductive line. The magnetic tunnel junction includes at least one programmable magnetic layer. The MRAM apparatus also includes an insulating layer radially surrounding the magnetic tunnel junction, and the insulating layer has a cavity adjacent to the magnetic tunnel junction. | 05-08-2014 |
| 20140126280 | MULTIPLE BIT NONVOLATILE MEMORY BASED ON CURRENT INDUCED DOMAIN WALL MOTION IN A NANOWIRE MAGNETIC TUNNEL JUNCTION - A mechanism is provided for storing multiple bits in a domain wall nanowire magnetic junction device. The multiple bits are encoded based on a resistance of the domain wall nanowire magnetic junction device using a single domain wall. The single domain wall is shifted to change the resistance of the domain wall nanowire magnetic junction device to encode a selected bit. The resistance is checked to ensure that it corresponds to a preselected resistance for the selected bit. Responsive to the resistance corresponding to the preselected resistance for the selected bit, he selected bit is stored. Responsive to the resistance not being the preselected resistance for the selected bit, the single domain wall is shifted until the resistance corresponds to the preselected resistance. | 05-08-2014 |
| 20140126281 | MULTIPLE BIT NONVOLATILE MEMORY BASED ON CURRENT INDUCED DOMAIN WALL MOTION IN A NANOWIRE MAGNETIC TUNNEL JUNCTION - A mechanism is provided for storing multiple bits in a domain wall nanowire magnetic junction device. The multiple bits are encoded based on a resistance of the domain wall nanowire magnetic junction device using a single domain wall. The single domain wall is shifted to change the resistance of the domain wall nanowire magnetic junction device to encode a selected bit. The resistance is checked to ensure that it corresponds to a preselected resistance for the selected bit. Responsive to the resistance corresponding to the preselected resistance for the selected bit, he selected bit is stored. Responsive to the resistance not being the preselected resistance for the selected bit, the single domain wall is shifted until the resistance corresponds to the preselected resistance. | 05-08-2014 |
| 20140126282 | READING A CROSS POINT CELL ARRAY - A mechanism is provided for reading a cross point cell array. Voltage biasing is applied to the cross point cell array to determine a state of a target cell on a selected bit line. A negative magnetic field is generated for a selected write bit line corresponding to the target cell. A first current is measured through a selected word line responsive to the negative magnetic field. A positive magnetic field is generated for the selected write bit line corresponding to the target cell. A second current is measured through the selected word line responsive to the positive magnetic field. The state of the target cell is determined based on the first current relative to the second current. | 05-08-2014 |
| 20140126283 | MULTILEVEL MAGNETIC ELEMENT - The present disclosure concerns a multilevel magnetic element comprising a first tunnel barrier layer between a soft ferromagnetic layer having a magnetization that can be freely aligned and a first hard ferromagnetic layer having a magnetization that is fixed at a first high temperature threshold and freely alignable at a first low temperature threshold. The magnetic element further comprises a second tunnel barrier layer and a second hard ferromagnetic layer having a magnetization that is fixed at a second high temperature threshold and freely alignable at a first low temperature threshold; the soft ferromagnetic layer being comprised between the first and second tunnel barrier layers. The magnetic element disclosed herein allows for writing four distinct levels using only a single current line. | 05-08-2014 |
| 20140126284 | MRAM SENSING WITH MAGNETICALLY ANNEALED REFERENCE CELL - Systems and method for reading/sensing data stored in magnetoresistive random access memory (MRAM) cells using magnetically annealed reference cells. A MRAM includes a reference circuit comprising at least one magnetic storage cell, wherein each magnetic storage cell in the MRAM is programmed to the same state. The reference circuit includes a load element coupled to the magnetic storage cell, wherein the load element is configured to establish a reference voltage during a read operation. | 05-08-2014 |
| 20140133220 | METHODS AND DEVICES FOR AVOIDING LOWER PAGE CORRUPTION IN DATA STORAGE DEVICES - A data storage device may comprise a plurality of Multi-Level Cell (MLC) non-volatile memory devices comprising a plurality of lower pages and a corresponding plurality of higher-order pages. A controller may be configured to write data to and read data from the plurality of lower pages and the corresponding plurality of higher-order pages. A buffer may be coupled to the controller, which may be configured to accumulate data to be written to the MLC non-volatile memory devices, allocate space in the buffer and write the accumulated data to the allocated space. At least a portion of the accumulated data may be written in a lower page of the MLC non-volatile memory devices and the space in the buffer that stores data written to the lower page may be de-allocated when all higher-order pages corresponding to the lower page have been written in the MLC non-volatile memory devices. | 05-15-2014 |
| 20140133221 | Magnectic Structure - A method of shifting information between magnetic layers in a thin film structure. The method can comprising applying a magnetic field to the thin film structure, the field having a magnitude sufficient to switch the magnetisation direction of a predetermined one of a pair of layers within the thin film structure when that pair of layers holds a frustration between two regions of different magnetisation direction order parameter within the thin film structure. | 05-15-2014 |
| 20140140126 | MAGNETIC STORAGE ELEMENT, MAGNETIC STORAGE DEVICE, MAGNETIC MEMORY, AND DRIVING METHOD - A magnetic storage element includes a magnetic nanowire. A cross-section of the magnetic nanowire has first and second visible outlines, the first visible outline has a first minimal point at which a distance from a virtual straight line becomes minimal, a second minimal point at which the distance from the virtual straight line becomes minimal, and a first maximal point at which the distance from the virtual straight line becomes longest between the first minimal point and the second minimal point, and an angle between a first straight line connecting the first minimal point and the second minimal point, and one of a second straight line connecting the first minimal point and the first maximal point and a third straight line connecting the second minimal point and the first maximal point is not smaller than four degrees and not larger than 30 degrees. | 05-22-2014 |
| 20140140127 | MAGNETIC RANDOM ACCESS MEMORY APPARATUS, METHODS FOR PROGRAMMING AND VERIFYING REFERENCE CELLS THEREFOR - A magnetic random access memory apparatus includes a memory cell array including a plurality of magnetic memory cells; a reference cell array including a pair of reference magnetic memory cells; a write driver configured to program data in the memory cell array and the reference cell array; and a first switching unit configured to form a current path which extends from a bit line connected to the write driver via the reference cell array including the pair of reference magnetic memory cells to a source line connected to the write driver or a current path which extends from a source line connected to the write driver via the reference cell array including the pair of reference magnetic memory cells to a bit line connected to the write driver. | 05-22-2014 |
| 20140146599 | MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM) DIFFERENTIAL BIT CELL AND METHOD OF USE - A MRAM bit cell including a first magnetic tunnel junction (MTJ) connected to a first data line and a second MTJ connected to a second data line. The MRAM bit cell further includes a first transistor having a first terminal connected to the first MTJ and a second terminal connected to the second MTJ. The MRAM bit cell further includes a second transistor having a first terminal connected to a driving line and a second terminal connected to the first MTJ. The MRAM bit cell further includes a third transistor having a first terminal connected to the driving line and a second terminal connected to the second MTJ. A method of using the MRAM bit cell is also described. | 05-29-2014 |
| 20140146600 | MEMORY SYSTEM HAVING VARIABLE OPERATING VOLTAGE AND RELATED METHOD OF OPERATION - A magneto-resistive random access memory (MRAM) comprising an MRAM cell array having an MRAM cell, and a control and voltage generation unit configured to generate a back bias voltage for the MRAM cell. The control and voltage generation unit comprising a command decoder configured to generate a decoding signal in response to a command output from a memory controller, and a voltage controller and generator configured to generate the back bias voltage with a magnitude based on the decoding signal and a reset signal output from the memory controller. | 05-29-2014 |
| 20140153324 | Magnetic Tunnel Junction Memory Device - A magnetic-assist, spin-torque transfer magnetic tunnel junction device and a method for performing a magnetic-assist, spin-torque-transfer write to the device are disclosed. In an exemplary embodiment, the magnetic tunnel junction device includes a first electrode, a pinned layer disposed on the first electrode, a free layer disposed on the pinned layer, and a barrier layer disposed between the pinned layer and the free layer. The device further includes a second electrode electrically coupled to the free layer, the second electrode containing a magnetic assist region. In some embodiments, the magnetic assist region is configured to produce a net magnetic field when supplied with a write current. The net magnetic field is aligned to assist a spin-torque transfer of the write current on the free layer. | 06-05-2014 |
| 20140153325 | BODY VOLTAGE SENSING BASED SHORT PULSE READING CIRCUIT - As memory geometries continue to scale down, current density of magnetic tunnel junctions (MTJs) make conventional low current reading scheme problematic with regard to performance and reliability. A body-voltage sense circuit (BVSC) short pulse reading (SPR) circuit is described using body connected load transistors and a novel sensing circuit with second stage amplifier which allows for very short read pulses providing much higher read margins, less sensing time, and shorter sensing current pulses. Simulation results (using 65-nm CMOS model SPICE simulations) show that our technique can achieve 550 mV of read margin at 1 ns performance under a 1V supply voltage, which is greater than reference designs achieve at 5 ns performance. | 06-05-2014 |
| 20140160834 | Frequency Resistance Access Magnetic Memory - The invention provides a multibit magnetic memory structure comprising a stack of two or more magnetic plaquettes, each of which has at least three distinct magnetic states. The invention provides for a new type of vertical memory where each layer encodes information in two degrees of freedom, which has the potential to increase the theoretical storage capacity by factor 4 | 06-12-2014 |
| 20140160835 | SPIN TRANSFER TORQUE MAGNETIC MEMORY DEVICE - A spin transfer torque magnetic memory device is disclosed. In one aspect, the spin transfer torque magnetic memory device comprises a first layered structure stacked in a vertical direction and comprising alternating topological insulator layers and insulator layers. The memory device additionally includes a second layered structure stacked in the vertical direction and comprising alternating topological insulator layers and insulator layers. The memory device further includes a magnetic material interposing the first and second layered structures in a horizontal direction different from the vertical direction such that the magnetic material is in contact with a first side surface of the first layered structure and in contact with a first side surface of the second layered structure. Additionally, the magnetic material is configured to have a magnetization direction that can change in response to a current flowing through the magnetic material. | 06-12-2014 |
| 20140169079 | METHOD AND APPARATUS FOR SENSING THE STATE OF A MAGNETIC TUNNEL JUNCTION (MTJ) - A method of measuring the resistance of a magnetic tunnel junction (MTJ) is performed by selecting the MTJ to be measured, the MTJ having a resistance associated therewith and coupled to an access transistor. Further, measuring a voltage at an end of the MTJ that is coupled to the access transistor and measuring voltage, V0, at the coupling of the selected MTJ and the associated access transistor, turning off a decoder that is coupled to the MTJ, and after applying current, measuring the applied current and using the measured applied current to determine the resistance of the MTJ. | 06-19-2014 |
| 20140169080 | THERMAL SPIN TORQURE TRANSFER MAGNETORESISTIVE RANDOM ACCESS MEMORY - A thermal spin torque transfer magnetoresistive random access memory (MRAM) apparatus includes a magnetic tunnel junction and a tunnel junction programming circuit. The magnetic tunnel junction includes a reference layer having a fixed magnetic polarity, a tunnel barrier layer, and a free layer on an opposite side of the tunnel barrier layer from the reference layer. The free layer includes a first layer having a first Curie temperature and a second layer having a second Curie temperature different from the first Curie temperature. The tunnel junction programming circuit is configured to apply a current through the magnetic tunnel junction to generate a write temperature in the magnetic tunnel junction and to write to the free layer of the magnetic tunnel junction. | 06-19-2014 |
| 20140169081 | Flexible Memory and its Fabrication Process - This invention describes the structure and the fabrication method of a flexible memory. The flexible memory includes eight layers. The three function layers are a flexible layer of hall unit, a flexible layer of horizontal lines, and a flexible layer of vertical lines. The main fabrication process of the flexible memory includes the following: the function layers are made on the hard substrates by the traditional nano-micro methods, and then the function layers are transferred on the flexible substrates, finally the whole layers are packaged to form the flexible memory. | 06-19-2014 |
| 20140169082 | THERMAL SPIN TORQURE TRANSFER MAGNETORESISTIVE RANDOM ACCESS MEMORY - A thermal spin torque transfer magnetoresistive random access memory (MRAM) apparatus includes a magnetic tunnel junction and a tunnel junction programming circuit. The magnetic tunnel junction includes a reference layer having a fixed magnetic polarity, a tunnel barrier layer, and a free layer on an opposite side of the tunnel barrier layer from the reference layer. The free layer includes a first layer having a first Curie temperature and a second layer having a second Curie temperature different from the first Curie temperature. The tunnel junction programming circuit is configured to apply a current through the magnetic tunnel junction to generate a write temperature in the magnetic tunnel junction and to write to the free layer of the magnetic tunnel junction. | 06-19-2014 |
| 20140169083 | MAGNETORESISTIVE LAYER STRUCTURE WITH VOLTAGE-INDUCED SWITCHING AND LOGIC CELL APPLICATION - Embodiments of the invention include a voltage-switching MTJ cell structure that includes two sub-MTJs in series. Each free layer can be switched independently from the other. Each sub-MTJ has a high and a low resistance state and the MTJ cell structure can have three or four discrete resistance states. By taking advantage of the electrical field induced anisotropy combining with the spin torque effect, free layer-1 and free layer-2 can be controlled individually by voltage pulses having selected sign (polarity) and amplitude characteristics. The MTJ cell structure can be used as a fully functional logic cell with two input bit values corresponding to the high or low resistance of the two sub-MTJ structures and the output of a logical operation, e.g. an XOR function, determined by the resistance state of each MTJ cell. | 06-19-2014 |
| 20140169084 | Memory device - A memory device is described. The memory device comprises an antiferromagnet. The device may comprise an insulator and an electrode arranged in a tunnel junction configuration. Alternatively, the device may comprise first and second contacts to the antiferromagnet for measuring ohmic resistance of the antiferromagnet. The antiferromagnet is not coupled to any ferromagnet. The state of the antiferromagnet can be set by heating the junction to a temperature at or above a critical temperature at which is possible to re-orientate magnetic moments in the antiferromagnet, applying an external magnetic field and then cooling the antiferromagnet to a temperature below the critical temperature. | 06-19-2014 |
| 20140169085 | VOLTAGE-CONTROLLED MAGNETIC MEMORY ELEMENT WITH CANTED MAGNETIZATION - A memory cell including information that is stored in the state of a magnetic bit (i.e. in a free layer, FL), where the FL magnetization has two stable states that may be canted (form an angle) with respect to the horizontal and vertical directions of the device is presented. The FL magnetization may be switched between the two canted states by the application of a voltage (i.e. electric field), which modifies the perpendicular magnetic anisotropy of the free layer. | 06-19-2014 |
| 20140169086 | COMMON SOURCE SEMICONDUCTOR MEMORY DEVICE - A memory device includes a cell array and a common source line compensation circuit. The cell array includes a plurality of normal cell units connected between a plurality of bit lines and one common source line, respectively. The common source line compensation circuit supplies a plurality of compensation write currents to the common source line to compensate for a plurality of write currents concurrently input into or output from the common source line through the normal cell units. | 06-19-2014 |
| 20140169087 | MEMORY ELEMENT AND MEMORY APPARATUS - A memory element has a layered structure, including a memory layer that has magnetization perpendicular to a film face in which a magnetization direction is changed depending on information, and includes a Co—Fe—B magnetic layer, the magnetization direction being changed by applying a current in a lamination direction of the layered structure to record the information in the memory layer, a magnetization-fixed layer having magnetization perpendicular to a film face that becomes a base of the information stored in the memory layer, and an intermediate layer that is formed of a non-magnetic material and is provided between the memory layer and the magnetization-fixed layer, a first oxide layer and a second oxide layer. | 06-19-2014 |
| 20140169088 | SPIN HALL EFFECT MAGNETIC APPARATUS, METHOD AND APPLICATIONS - An ST-MRAM structure, a method for fabricating the ST-MRAM structure and a method for operating an ST-MRAM device that results from the ST-MRAM structure each utilize a spin Hall effect base layer that contacts a magnetic free layer and effects a magnetic moment switching within the magnetic free layer as a result of a lateral switching current within the spin Hall effect base layer. This resulting ST-MRAM device uses an independent sense current and sense voltage through a magnetoresistive stack that includes a pinned layer, a non-magnetic spacer layer and the magnetic free layer which contacts the spin Hall effect base layer. Desirable non-magnetic conductor materials for the spin Hall effect base layer include certain types of tantalum materials and tungsten materials that have a spin diffusion length no greater than about five times the thickness of the spin Hall effect base layer and a spin Hall angle at least about 0.05. | 06-19-2014 |
| 20140177325 | INTEGRATED MRAM MODULE - Systems and methods for integrated magnetoresistive random access memory (MRAM) modules. An integrated circuit includes a processor without a last level cache integrated on a first chip a MRAM module comprising a MRAM last level cache and a MRAM main memory integrated on a second chip, wherein the MRAM module is a unified structure fabricated as monolithic package or a plurality of packages. The second package further includes memory controller logic. A simplified interface structure is configured to couple the first and the second package. The MRAM module is designed for high speed, high data retention, aggressive prefetching between the MRAM last level cache and the MRAM main memory, improved page handling, and improved seal ability. | 06-26-2014 |
| 20140177326 | ELECTRIC FIELD ENHANCED SPIN TRANSFER TORQUE MEMORY (STTM) DEVICE - Spin transfer torque memory (STTM) devices incorporating a field plate for application of an electric field to reduce a critical current required for transfer torque induced magnetization switching. Embodiments utilize not only current-induced magnetic filed or spin transfer torque, but also electric field induced manipulation of magnetic dipole orientation to set states in a magnetic device element (e.g., to write to a memory element). An electric field generated by a voltage differential between an MTJ electrode and the field plate applies an electric field to a free magnetic layer of a magnetic tunneling junction (MTJ) to modulate one or more magnetic properties over at least a portion of the free magnetic layer. | 06-26-2014 |
| 20140177327 | VOLTAGE-CONTROLLED MAGNETIC ANISOTROPY (VCMA) SWITCH AND MAGNETO-ELECTRIC MEMORY (MERAM) - Voltage controlled magnetic tunnel junctions and memory devices are described which provide efficient high speed switching of non-volatile magnetic devices at high cell densities. Implementations are described which provide a wide range of voltage control alternatives with in-plane and perpendicular magnetization, bidirectionally switched magnetization, and control of domain wall dynamics. | 06-26-2014 |
| 20140177328 | Multi-Bit Magnetic Memory Cell | 06-26-2014 |
| 20140185370 | NONVOLATILE MEMORY APPARATUS HAVING MAGNETORESISTIVE MEMORY ELEMENTS AND METHOD FOR DRIVING THE SAME - A semiconductor memory apparatus includes a source line, a first bit line disposed over the source line, a second bit line disposed under the source line, a first memory cell between the source line and the first bit line, and a second memory cell between the source line and the second bit line. | 07-03-2014 |
| 20140185371 | ANTIFERROMAGNETIC STORAGE DEVICE - An atomic-scale structure according to one embodiment has a net magnetic moment of zero or about zero, two or more stable magnetic states, and an array of atoms that has magnetic moments that alternate between adjacent magnetic atoms along one or more directions. Such structures may be used to store data at ultra-high densities. An antiferromagnetic nanostructure according to another embodiment includes multiple arrays each corresponding to a bit. Each array has at least eight antiferromagnetically coupled magnetic atoms. Each array has at least two readable magnetic states that are stable for at least one picosecond. Each array has a net magnetic moment of zero or about zero. No external stabilizing structure exerts influence over the arrays for stabilizing the arrays. Each array has 100 atoms or less along a longest dimension thereof. | 07-03-2014 |
| 20140185372 | MEMORY SENSING CIRCUIT - A sensing circuit includes a sense amplifier circuit having a first and second nodes through which a magnetic memory element is sensed. A first current source is coupled to the first node a second current source is coupled to the second node. A reference magnetic memory element has a resistance associated therewith and is coupled to the first node, the reference magnetic memory element receives current from the first current source. At least one memory element, having a resistance associated therewith, is coupled to the second node and receives current from the second current source. Current from the first current source and current from the second current source are substantially the same. The logic state of the at least one memory element is sensed by a comparison of the resistance of the at least one memory element to the resistance of the reference magnetic memory element. | 07-03-2014 |
| 20140192590 | MULTI-PORT MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A memory array is organized into rows and columns of resistive elements and is disclosed to include a resistive element to be read or to be written thereto. Further, a first access transistor is coupled to the resistive element and to a first source line and a second access transistor is coupled to the resistive element and to a second source line, the resistive element being coupled at one end to the first and second access transistors and at an opposite end to a bit line. The memory array further has other resistive elements that are each coupled to the bit line. The resistive element is written to while one or more of the other resistive elements are being read. | 07-10-2014 |
| 20140192591 | HIGH CAPACITY LOW COST MULTI-STATE MAGNETIC MEMORY - A multi-state current-switching magnetic memory element includes a stack of magnetic tunneling junction (MTJ) separated by a non-magnetic layer for storing more than one bit of information, wherein different levels of current applied to the memory element cause switching to different states. | 07-10-2014 |
| 20140198563 | MAGNETIC TUNNELING JUNCTION NON-VOLATILE REGISTER WITH FEEDBACK FOR ROBUST READ AND WRITE OPERATIONS - A magnetic tunneling junction non-volatile register with feedback for robust read and write operations. In an embodiment, two MTJ devices are configured to store a logical 0 or a logical 1, and are coupled to drive an output node to a voltage indicative of the stored logical 0 or a logical 1. The output of a D flip-flop is fed to the two MTJ devices so that the state of the D flip-flop may be stored in the two MTJ devices during a store operation. During a read operation, the D flip-flop outputs the state of the two MTJ devices. Read disturbances are mitigated with the use of an edge detector coupled to the output node, so that a LOW voltage is provided to the D flip-flop if a rising voltage at the output node is detected. | 07-17-2014 |
| 20140198564 | MAGNETORESISTIVE ELEMENT AND METHOD OF MANUFACTURING THE SAME - A planar STT-MRAM comprises apparatus, a method of operating and a method of manufacturing a spin-torque magnetoresistive memory and a plurality of magnetoresistive memory element having a ferromagnetic recording layer forming a flux closure with a self-aligned ferromagnetic soft adjacent layer which has an electric field enhanced perpendicular anisotropy through an interface interaction with a dielectric functional layer. The energy switch barrier of the soft adjacent layer is reduced under an electric field along a perpendicular direction with a proper voltage on a digital line from a control circuitry; accordingly, the in-plane magnetization of the recording layer is readily reversible in a low spin-transfer switching current. | 07-17-2014 |
| 20140204661 | MEMORY WITH ELEMENTS HAVING TWO STACKED MAGNETIC TUNNELING JUNCTION (MTJ) DEVICES - A magnetic memory having memory elements each with two magnetic tunneling junction (MTJ) devices is disclosed. The devices in each element are differentially programmed with complementary data. The devices for each element are stacked one above the other so that the element requires no more substrate area than a single MTJ device. | 07-24-2014 |
| 20140204662 | APPARATUS FOR INITIALIZING PERPENDICULAR MRAM DEVICE - The present invention is directed to an apparatus for initializing perpendicular magnetic tunnel junction. The apparatus comprises a permanent magnet for generating a magnetic flux; a flux concentrator made of a soft ferromagnetic material and having a base area in contact with the permanent magnet and an tip area that is smaller than the base area, thereby funneling and concentrating the magnetic flux to the tip area for emitting a magnetic field therefrom; and a means for supporting and conveying a substrate with an arrays of magnetic tunnel junctions formed therein to traverse the magnetic field in close proximity to the tip area. The apparatus may further include at least one of the following: a substrate heater, a flux containment structure coupled to the permanent magnet, and a magnetic imaging plate disposed in proximity to the substrate on the opposite side from the flux concentrator. | 07-24-2014 |
| 20140211549 | ACCOMMODATING BALANCE OF BIT LINE AND SOURCE LINE RESISTANCES IN MAGNETORESISTIVE RANDOM ACCESS MEMORY - A memory has magnetic tunnel junction elements with different resistances in different logic states, for bit positions in memory words accessed by a word line signal coupling each bit cell in the addressed word between a bit line and source line for that bit position. The bit lines and source lines are longer and shorter at different word line locations, causing a resistance body effect. A clamping transistor couples the bit line to a sensing circuit when reading, applying a current through the bit cell and producing a read voltage compared by the sensing circuit to a reference such as a comparable voltage from a reference bit cell circuit having a similar structure. A drive control varies an input to the switching transistor as a function of the word line location, e.g., by word line address, to offset the different bit and source line resistances. | 07-31-2014 |
| 20140211550 | READ CIRCUIT FOR MEMORY - Embodiments are directed to detecting a state of a memory element in a memory device, comprising: applying a pulse of a predetermined magnitude and duration to the memory element to induce a transition in the state of the memory element when a polarity of the pulse is opposite to the state, monitoring, by a device, a signal associated with the memory element to detect a presence or absence of a transition in the signal in an amount greater than a threshold, and determining the state of the memory element based on said monitoring. | 07-31-2014 |
| 20140211551 | MRAM SELF-REPAIR WITH BIST LOGIC - Memory self-repair circuitry includes a memory cell array on a chip, and built-in self test (BIST) circuitry on the chip coupled to the memory cell array. The BIST circuitry is configured to perform a magnetic random access memory (MRAM) write operation to write addresses of failed memory cells in the memory cell array to a failed address sector also in the memory cell array. The memory self-repair circuitry also includes first select circuitry coupled between the BIST circuitry and the memory cell array. The first select circuitry is configured to selectively couple an output of the BIST circuitry and an input to the memory cell array. | 07-31-2014 |
| 20140211552 | MEMORY DEVICE USING SPIN HALL EFFECT AND METHODS OF MANUFACTURING AND OPERATING THE MEMORY DEVICE - A memory device using a spin hall effect, and methods of manufacturing and operating the memory device, include applying a first operational current to a bit line of the memory device such that a spin current is applied to a magnetic tunnel junction (MTJ) cell coupled to the bit line due to a material in the bit line, wherein the bit line is electrically connected to a word line via the MTJ cell, and the word line intersects the bit line. | 07-31-2014 |
| 20140219012 | MAGNETIC STATE ELEMENT AND CIRCUITS - Described is an apparatus, for spin state element device, which comprises: a variable resistive magnetic (VRM) device to receive a magnetic control signal to adjust resistance of the VRM device; and a magnetic logic gating (MLG) device, coupled to the VRM device, to receive a magnetic logic input and perform logic operation on the magnetic logic input and to drive an output magnetic signal based on the resistance of the VRM device. Described is a magnetic demultiplexer which comprises: a first VRM device to receive a magnetic control signal to adjust resistance of the first VRM; a second VRM device to receive the magnetic control signal to adjust resistance of the second VRM device; and an MLG device, coupled to the first and second VRM devices, the MLG device having at least two output magnets to output magnetic signals based on the resistances of the first and second VRM devices. | 08-07-2014 |
| 20140219013 | METHOD AND APPARATUS FOR READING A MAGNETIC TUNNEL JUNCTION USING A SEQUENCE OF SHORT PULSES - A magnetic random access memory (MRAM) array having a magnetic tunnel junction (MTJ) to be read using a magnetic state of the MTJ, the MTJ being read by applying a current there through. Further, the MRAM array has a reference MTJ, a sense amplifier coupled to the MTJ and the reference MTJ, the sense amplifier operable to compare the voltage of the MTJ to the reference MTJ in determining the state of the MTJ; a first capacitor coupled to the sense amplifier at a first end and to ground at a second end; and a second capacitor coupled to the sense amplifier at a first end and to ground at a second end, the first capacitor storing the, wherein short voltage pulses are applied to the first end of each of the first and second capacitors when reading the MTJ thereby makes the current flowing through the MTJ there through for small time intervals thereby avoiding read disturbance to the MTJ. | 08-07-2014 |
| 20140233305 | MAGNETIC RANDOM ACCESS MEMORY HAVING INCREASED ON/OFF RATIO AND METHODS OF MANUFACTURING AND OPERATING THE SAME - A magnetic random access memory (MRAM), and methods of manufacturing and operating the MRAM, include a switching element and a storage node connected to the switching element, and a magnetic node configured to simultaneously store two opposite bits. | 08-21-2014 |
| 20140233306 | BIPOLAR SPIN-TRANSFER SWITCHING - A magnetic device includes a magnetized polarizing layer, a free magnetic layer, and a reference layer. The free magnetic layer forms a first electrode and is separated from the magnetized polarizing layer by a first non-magnetic metal layer. The free magnetic layer has a magnetization vector having a first and second stable state. The reference layer forms a second electrode and is separated from the free-magnetic layer by a second non-magnetic layer. Unipolar current is sourced through the polarizing, free magnetic and reference layers. Switching of the magnetization vector of the free magnetic layer from the first stable state to the second state is initiated by application of a first unipolar current pulse, and switching of the magnetization vector of the free magnetic layer from the second stable state to the first stable state is initiated by application of a second unipolar current pulse. | 08-21-2014 |
| 20140241047 | SELF-ALIGNED PROCESS FOR FABRICATING VOLTAGE-GATED MRAM - A STT-MRAM comprises apparatus and a method of manufacturing a spin-torque magnetoresistive memory and a plurality of a three-terminal magnetoresistive memory element having a voltage-gated recording. A bit line is coupled to the memory element through an upper electrode provided on the top surface of a reference layer, a select CMOS is coupled to the recording layer of the memory element through a middle second electrode and a VIA and a digital line is coupled to a voltage gate which is insulated from the recording layer by a dielectric layer and is used to adjust the switching write current. The fabrication includes formation of bottom digital line, formation of memory cell & VIA connection, formation of top bit line. Dual photolithography patterning and hard mask etch are used to form a small memory pillar. Ion implantation is used to convert a buried dielectric VIA into an electrical conducting path between middle memory cell and underneath CMOS device. | 08-28-2014 |
| 20140247653 | ELECTRIC FIELD ASSISTED MRAM AND METHOD FOR USING THE SAME - The present invention is directed to a spin transfer torque magnetic random access memory (STT-MRAM) device having a plurality of memory elements. Each of the plurality of memory elements comprises a magnetic reference layer with a first invariable magnetization direction substantially perpendicular to layer plane thereof; a magnetic free layer separated from the magnetic reference layer by an insulating tunnel junction layer with the magnetic free layer having a variable magnetization direction substantially perpendicular to layer plane thereof; a dielectric layer formed in contact with the magnetic free layer opposite the insulating tunnel junction layer; and a first conductive layer formed in contact with the dielectric layer opposite the magnetic free layer. | 09-04-2014 |
| 20140254250 | MAGNETIC MEMORY CIRCUIT WITH STRESS INDUCING LAYER - Memory circuit comprising an addressable magnetic tunnel junction (MTJ) stack, forming a magnetic storage element in the circuit. The MTJ stack comprises a tunnel oxide layer between a free layer and a fixed layer. A stress inducing layer is disposed adjacent to the free layer to provide tensile or compressive stress to the free layer, in order to manipulate a magnetic field that is required to write a bit into the MTJ stack. Method of using the memory circuit is also proposed. | 09-11-2014 |
| 20140254251 | MAGNETIC AUTOMATIC TEST EQUIPMENT (ATE) MEMORY TESTER DEVICE AND METHOD EMPLOYING TEMPERATURE CONTROL - In a particular embodiment, a method includes controlling a temperature within a chamber while applying a magnetic field. A device including a memory array is located in the chamber. The method includes applying a magnetic field to the memory array and testing the memory array during application of the magnetic field to the memory array at a target temperature. | 09-11-2014 |
| 20140254252 | MAGNETORESISTIVE ELEMENT - A STT-MRAM comprises apparatus, and method of operating a double-MTJ magnetoresistive memory and a plurality of magnetoresistive memory element having a first recording layer which has an interface interaction with an underneath dielectric functional layer and having a second recording layer which has no interface interaction with an underneath dielectric functional layer. The energy switch barrier of the first recording layer is reduced under an electric field applying along a perpendicular direction of the functional with a proper voltage on a digital line from a control circuitry; accordingly, the magnetization of the first recording layer is readily reversible in a low spin-transfer switching current while the magnetization of the second recording layer is readily reversible in a high spin-transfer switching current, enabling two separate bits recording in a double MTJ stack. | 09-11-2014 |
| 20140254253 | MEMORY ELEMENT AND MEMORY DEVICE - There is disclosed a memory element including a memory layer that has a magnetization and a magnetization direction thereof varies corresponding to information; a magnetization-fixed layer that has a magnetization; and an insulating layer that is provided between the memory layer and the magnetization-fixed layer, wherein an electron that is spin-polarized is injected in a lamination direction of a layered structure, and thereby the magnetization direction of the memory layer varies and a recording of information is performed with respect to the memory layer, and a Ta film in contact with a face of the magnetization-fixed layer, the face of the magnetization-fixed layer is opposite to the insulating layer side. | 09-11-2014 |
| 20140254254 | SEMICONDUCTOR STORAGE DEVICE AND DRIVING METHOD THEREOF - A memory includes a cell array including nonvolatile memory cells. A power generator generates a power supply voltage for driving the cell array. A receiver receives a command and an address. A controller controls an active state of the cell array, the power generator, and the receiver. In an activation mode, the cell array, the power generator, and the receiver are turned into the active states. In a first power saving mode, the cell array, the power generator, and the receiver are turned into inactive states. In a second power saving mode, the cell array and the power generator are turned into the active states, and the receiver is turned into the inactive state. In a third power saving mode, at least a part of the power generator is turned into the active state, and the cell array and the receiver are turned into the inactive states. | 09-11-2014 |
| 20140254255 | MRAM WTIH METAL GATE WRITE CONDUCTORS - In one embodiment of the invention, there is provided a magnetic random access (MRAM) device. The device comprises a plurality of MRAM cells, wherein each MRAM cell comprises a magnetic bit, and write conductors defined by conductors patterned in a second metal layer above the magnetic bit; and a gate formed below the magnetic bit between a source and a drain; and addressing circuits to address the MRAM cells. | 09-11-2014 |
| 20140269028 | Thermally-Assisted Mram with Ferromagnetic Layers with Temperature Dependent Magnetization - A technique is provided for a thermally assisted magnetoresistive random access memory device. The device has a synthetic antiferromagnetic layer disposed on an antiferromagnetic layer. The synthetic antiferromagnetic layer has a first ferromagnetic storage layer, a non-magnetic coupling layer disposed on the first ferromagnetic storage layer, and a second ferromagnetic storage layer disposed on the non-magnetic coupling layer. A non-magnetic tunnel barrier is disposed on the second ferromagnetic storage layer, and a ferromagnetic sense layer is disposed on the non-magnetic tunnel barrier. A first ferromagnetic critical temperature of the first ferromagnetic storage layer is higher than an antiferromagnetic critical temperature of the antiferromagnetic layer, is higher than a second ferromagnetic critical temperature of the second ferromagnetic storage layer, and is higher than a third ferromagnetic critical temperature of the ferromagnetic sense layer. | 09-18-2014 |
| 20140269029 | SELECTIVE SELF-REFERENCE READ - This disclosure relates to selectively performing a read with increased accuracy, such as a self-reference read, from a memory. In one aspect, data is read from memory cells, such as magnetoresitive random access memory (MRAM) cells, of a memory array. In response to detecting a condition associated with reading from the memory cells, a self-reference read can be performed from at least one of the memory cells. For instance, the condition can indicate that data read from the memory cells is uncorrectable via decoding of error correction codes (ECC). Selectively performing self-reference reads can reduce power consumption and/or latency associated with reading from the memory compared to always performing self-reference reads. | 09-18-2014 |
| 20140269030 | METHOD AND APPARATUS FOR MRAM SENSE REFERENCE TRIMMING - A trimming process for setting a reference current used in operating an MRAM module comprising an operational MRAM cell coupled to a bit line, multiple reference MRAM cells coupled to a reference bit line, and a sense amplifier coupled to the bit line and the reference bit line is disclosed in some embodiments. The process includes applying a bit line reference voltage to the reference bit line to provide a reference cell current formed by a sum of respective currents through the plurality of reference MRAM cells. The reference cell current is detected. A determination is made as to whether the detected reference cell current differs from a target reference cell current. The bit line reference voltage is varied, or a sensing ratio of the sense amplifier is varied, if it is determined that the detected reference cell current differs from the target reference cell current. | 09-18-2014 |
| 20140269031 | SYSTEM AND METHOD OF SENSING A MEMORY CELL - A method includes sensing a state of a data cell to generate a data voltage. The state of the data cell corresponds to a state of a programmable resistance based memory element of the data cell. The method further includes sensing a state of a reference cell to generate a reference voltage. The state of the data cell and the state of the reference cell are sensed via a common sensing path. The method further includes determining a logic value of the data cell based on the data voltage and the reference voltage. | 09-18-2014 |
| 20140269032 | ARCHITECTURE FOR MAGNETIC MEMORIES INCLUDING MAGNETIC TUNNELING JUNCTIONS USING SPIN-ORBIT INTERACTION BASED SWITCHING - A magnetic memory includes memory array tiles (MATs), intermediate circuitry, global bit lines and global circuitry. Each MAT includes bit lines, word lines, and magnetic storage cells having magnetic junction(s), selection device(s) and at least part of a spin-orbit interaction (SO) active layer adjacent to the magnetic junction(s). The SO active layer exerts a SO torque on the magnetic junction(s) due to a preconditioning current passing through the SO active layer. The magnetic junction(s) are programmable using write current(s) driven through the magnetic junction(s) and the preconditioning current. The bit and word lines correspond to the magnetic storage cells. The intermediate circuitry controls read and write operations within the MATs. Each global bit line corresponds to a portion of the MATs. The global circuitry selects and drives portions of the global bit lines for read operations and write operations. | 09-18-2014 |
| 20140269033 | MAGNETIC MEMORY - According to one embodiment, a magnetic memory includes magnetoresistive effect elements each including a first magnetic layer, a tunnel barrier layer, and a second magnetic layer which are successively stacked, and a ferroelectric capacitor provided above the magnetoresistive effect elements via an insulating layer, and including a lower electrode, a ferroelectric film, and an upper electrode which are successively stacked. | 09-18-2014 |
| 20140269034 | INTEGRATED CAPACITOR BASED POWER DISTRIBUTION - An embodiment provides power (having low voltage, high current, and high current density) to ultra low voltage non-CMOS based devices using a distributed capacitor that is integrated onto the same chip as the non-CMOS devices. For example, an embodiment provides a spin logic gate adjacent dielectric material and first and second plates of a capacitor. The capacitor discharges low voltage/high current to the spin logic gate using a step down switched mode power supply that charges numerous capacitors during one clock cycle (using a switching element configured in a first orientation) and discharges power from the capacitors during the opposite clock cycle (using the switching element configured in a second orientation). The capacitors discharge the current out of plane and to the spin logic devices without having to traverse long power dissipating interconnect paths. Other embodiments are described herein. | 09-18-2014 |
| 20140269035 | CROSS POINT ARRAY MRAM HAVING SPIN HALL MTJ DEVICES - Cross point array magnetoresistive random access memory (MRAM) implementing spin hall magnetic tunnel junction (MTJ)-based devices and methods of operation of such arrays are described. For example, a bit cell for a non-volatile memory includes a magnetic tunnel junction (MTJ) stack disposed above a substrate and having a free magnetic layer disposed above a dielectric layer disposed above a fixed magnetic layer. The bit cell also includes a spin hall metal electrode disposed above the free magnetic layer of the MTJ stack. | 09-18-2014 |
| 20140269036 | MAGNETIC MEMORY DEVICES AND METHODS OF WRITING DATA TO THE SAME - Magnetic memory devices include a magnetoresistive cell including a free layer having a variable magnetization direction and a pinned layer having a fixed magnetization direction, a bit line on the magnetoresistive cell and including a spin Hall effect material layer exhibiting a spin Hall effect and contacting the free layer; and a lower electrode under the magnetoresistive cell. A voltage is applied between the bit line and the lower electrode so that current passes through the magnetoresistive cell. | 09-18-2014 |
| 20140269037 | MAGNETIC MEMORY ELEMENT AND NONVOLATILE MEMORY DEVICE - A magnetic memory element includes a first stacked unit and a second stacked unit. The first stacked unit includes a first ferromagnetic layer, a second ferromagnetic layer, and a first nonmagnetic layer. The second ferromagnetic layer is stacked with the first ferromagnetic layer. The second ferromagnetic layer has a first and second portion. The first and second portion has a changeable direction of magnetization. The second portion is stacked with the first portion in a stacking direction of the first ferromagnetic layer and the second ferromagnetic layer. A magnetic resonance frequency of the second portion is lower than a magnetic resonance frequency of the first portion. The first nonmagnetic layer is provided between the first ferromagnetic layer and the second ferromagnetic layer. The second stacked unit is stacked with the first stacked unit in the stacking direction. The second stacked unit includes a third ferromagnetic layer. | 09-18-2014 |
| 20140269038 | MAGNETIC MEMORY - A magnetic memory according to an embodiment includes at least one MTJ element, the MTJ element including: a magnetic multilayer structure including a first magnetic layer in which a direction of magnetization is fixed, a second magnetic layer in which a direction of magnetization is changeable, and a tunnel barrier layer located between the first and second magnetic layers; a first electrode provided on a first surface of the magnetic multilayer structure; a second electrode provided on a second surface of the magnetic multilayer structure; an insulating film provided on a side surface of the magnetic multilayer structure; and a control electrode provided on the side surface of the magnetic multilayer structure with the insulating film located therebetween, a voltage being applied to the control electrode in a read operation, which increases an energy barrier for changing the magnetization of the second magnetic layer. | 09-18-2014 |
| 20140269039 | ELECTRONIC DEVICE AND VARIABLE RESISTANCE ELEMENT - A variable resistance element includes: first and second magnetic layers having a lanthanide series element alloyed in a nickel-iron compound; and a tunnel barrier layer interposed between the first and second magnetic layers. | 09-18-2014 |
| 20140269040 | PULSE PROGRAMMING TECHNIQUES FOR VOLTAGE-CONTROLLED MAGNETORESISTIVE TUNNEL JUNCTION (MTJ) - A method of programming a voltage-controlled magnetoresistive tunnel junction (MTJ) includes applying a programming voltage pulse (Vp), reading the voltage-controlled MTJ, and determining if the voltage-controlled MTJ is programmed to a desired state and if not, changing the Vp and repeating the applying and reading steps until the voltage-controlled MTJ is programmed to the desired state. | 09-18-2014 |
| 20140269041 | EMULATION OF STATIC RANDOM ACCESS MEMORY (SRAM) BY MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A magnetic memory system includes a magnetic random access memory (MRAM) including a plurality of magnetic memory banks and operative to store data during a write operation initiated by a write command. The magnetic memory system further includes a first-in-first-out (FIFO) interface device coupled to the MRAM and including a plurality of FIFOs Each of the magnetic memory banks is coupled to a respective one of the plurality of FIFOs, the FIFO being operative to queue write commands on a per magnetic memory bank basis and further operative to issue the queued write commands at a time when the MRAM is not in use, wherein concurrent write operations are performed to at least two of the plurality of magnetic memory banks. | 09-18-2014 |
| 20140269042 | Self-referenced Magnetic Random Access Memory - The present disclosure concerns a magnetic random access memory cell containing a magnetic tunnel junction formed from an insulating layer comprised between a sense layer and a storage layer. The present disclosure also concerns a method for writing and reading the memory cell comprising, during a write operation, switching a magnetization direction of said storage layer to write data to said storage layer and, during a read operation, aligning magnetization direction of said sense layer in a first aligned direction and comparing said write data with said first aligned direction by measuring a first resistance value of said magnetic tunnel junction. The disclosed memory cell and method allow for performing the write and read operations with low power consumption and an increased speed. | 09-18-2014 |
| 20140286084 | MAGNETORESISTIVE ELEMENT - According to one embodiment, a magnetoresistive element comprises a storage layer having perpendicular magnetic anisotropy with respect to a film plane and having a variable direction of magnetization, a reference layer having perpendicular magnetic anisotropy with respect to the film plane and having an invariable direction of magnetization, a tunnel barrier layer formed between the storage layer and the reference layer and containing O, and an underlayer formed on a side of the storage layer opposite to the tunnel barrier layer. The reference layer comprises a first reference layer formed on the tunnel barrier layer side and a second reference layer formed opposite the tunnel barrier layer. The second reference layer has a higher standard electrode potential than the underlayer. | 09-25-2014 |
| 20140286085 | POWER SUPPLY CIRCUIT AND PROTECTION CIRCUIT - According to one embodiment, a power supply circuit includes a first circuit connected to a first line, to which a power supply voltage is applied, and a second line, and a power supply clamp circuit connected to the first and second lines. The power supply clamp circuit includes a current path circuit which connects the first and the second lines to each other, and a control circuit which outputs a control signal to the current path circuit. The current path circuit includes a transistor and a diode group. The power supply clamp circuit is driven during a period in which a first voltage is applied to the first line and controls a potential of the first line so as to become a potential lower than the first voltage. | 09-25-2014 |
| 20140286086 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes first word lines connected to a memory cell array, second word lines connected to a redundancy area, a first row decoder configured to perform selecting from the first word lines based on a row address, a judgment circuit configured to determine whether or not a replacement operation with the redundancy area is needed based on a redundancy address included in the row address, and a second row decoder configured to perform selecting from the second word lines. The row address includes a first row address and a second row address input in order in a time-sharing method. The first row address includes all of the redundancy address. | 09-25-2014 |
| 20140286087 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory cell array, a buffer configured to hold data input to an input/output circuit and to hold data read from the memory cell array, and a controller configured to receive a first command and an address from the outside and to read data, in response to the first command, from a memory cell group coupled to a selected word line designated by the address to the buffer. The controller receives a second command which is input after the first command and indicates a last command of a group of commands including write commands and/or read commands, and starts a write operation from the buffer to the memory cell array in response to the second command. | 09-25-2014 |
| 20140286088 | MEMORY DEVICE - According to one embodiment, a memory device includes a memory cell, a sense amplifier, unit structures and a reference signal generator. Each structure includes a first end, a first transistor, a first local line, a variable resistance element, a second transistor, a second local line, and a third transistor coupled in series. The reference signal generator includes first to fourth global lines, and first and second ones of the unit structures. The first unit structure is coupled at the first end to the first global line and coupled at the second end to the third global line. The second unit structure is coupled at the first end to the fourth global line and coupled at the second end to the second global line. | 09-25-2014 |
| 20140293683 | MAGNETO-RESISTIVE EFFECT ELEMENT | 10-02-2014 |
| 20140293684 | NONVOLATILE MEMORY APPARATUS - A nonvolatile memory apparatus includes: a memory cell coupled to a bit line and a source line; a word line configured to select the memory cell; and a local switch block configured to apply a write voltage, a read voltage, and a source line voltage to the bit line and the source line in response to a local switch select signal. In a write or read operation of the nonvolatile memory apparatus, the word line has a first voltage level, and the local switch select signal has a second voltage level higher than the first voltage level. | 10-02-2014 |
| 20140293685 | MAGNETIC MEMORY - A magnetic memory according to an embodiment includes: a plurality of memory cells, each memory cell including a first MTJ element and a first selection unit; a pair of a first and second bit lines provided to each column of the memory cells; a word line provided to each row of the memory cells; an equalizer circuit provided to each column of the memory cells, and to connect between the first and second bit lines; and a control circuit that sets the first and second bit lines connected to a selected memory cell to be a first and second potentials to conduct a write operation, and after the write operation, transmits a control signal to the equalizer circuit between the first and second bit lines to activate the equalizer circuit to equalize potentials of the first bit line and the second bit line, thereby bringing into floating states. | 10-02-2014 |
| 20140293686 | SEMICONDUCTOR INTERGRATED CIRCUIT AND OPERATING METHOD THEREOF - A semiconductor integrated circuit includes a variable resistive element, a current supply unit and a control signal generating unit. The resistance of the variable resistive element is changed depending on current flowing therethrough. The current supply unit controls the current in response to a control signal. The control signal generating unit generates the control signal by sensing the change in the resistance of the variable resistive element. | 10-02-2014 |
| 20140301135 | MRAM HAVING NOVELSELF-REFERENCED READ METHOD - A STT-MRAM comprises apparatus, a method of operating and a method of manufacturing a self-referenced magnetoresistive memory and a plurality of magnetoresistive memory element including a self-referenced read scheme through a write/read circuitry coupled to the bit line positioned adjacent to selected ones of the plurality of magnetoresistive memory elements to supply bi-directional spin-transfer recording and reading currents across the MTJ stack. Thus magnetization of a recording layer can be readily switched or reversed to the direction in accordance with a direction of a current across the MTJ stack by applying a spin transfer current, and the magnetization of a reference layer can be readily rotated to two reading directions subsequently in accordance with directions of currents across the MTJ stack by applying low spin transfer currents. | 10-09-2014 |
| 20140301136 | MAGNETIC MEMORY, SPIN ELEMENT, AND SPIN MOS TRANSISTOR - A magnetic memory according to an embodiment includes: a multilayer structure including a semiconductor layer and a first ferromagnetic layer; a first wiring line electrically connected to the semiconductor layer; a second wiring line electrically connected to the first ferromagnetic layer; and a voltage applying unit electrically connected between the first wiring line and the second wiring line to apply a first voltage between the semiconductor layer and the first ferromagnetic layer during a write operation, a magnetization direction of the first ferromagnetic layer being switchable by applying the first voltage. | 10-09-2014 |
| 20140313820 | FIELD PROGRAMMING METHOD FOR MAGNETIC MEMORY DEVICES - In one embodiment of the invention, there is provided a method for operating a magnetic memory device. The method comprises selecting a subset of magnetic memory cells of the magnetic memory device; applying a first programming voltage to the selected subset of cells for a predetermined amount of time, wherein the programming voltage is selected to exceed a threshold operating voltage thereby to cause irreversible breakdown of the subset of cells; and reading selected cells of the magnetic memory device by passing a read current through a diode connected in series with each magnetic memory cell. | 10-23-2014 |
| 20140321199 | Nano Multilayer Film, Field Effect Tube, Sensor, Random Accessory Memory and Preparation Method - Disclosed are nano multilayer film of electrical field modulation type, a field effect transistor of electrical field modulation type, an electrical field sensor of switch type, and a random access memory of electrical field drive type, for obtaining an electro-resistance effect in an electrical field modulation multilayer film at room temperature. The nano multilayer film comprises in succession from bottom to top a bottom layer ( | 10-30-2014 |
| 20140328116 | MAGNETIC MEMORY DEVICES - A STT-MRAM comprises apparatus and a method of manufacturing a plurality of magnetoresistive memory element having a dielectric thermal buffer layer between a thin top electrode of the MTJ element and a bit line, and a bit-line VIA electrically connecting the top electrode and the bit line having a vertical distance away from the location of the MTJ stack. In a laser thermal annealing, a short wavelength of a laser has a shallow thermal penetration depth and a high thermal resistance from the bit line to the MTJ stack only causes a temperature rise of the MTJ stack being much smaller than that of the bit line. As the temperature of the MTJ element during the laser thermal annealing of bit line copper layer is controlled under 300-degree C., possible damages on MTJ and magnetic property can be avoided. | 11-06-2014 |
| 20140328117 | INITIALIZATION METHOD OF A PERPENDICULAR MAGNETIC RANDOM ACCESS MEMORY (MRAM) DEVICE WITH A STABLE REFERENCE CELL - A method of initializing a magnetic random access memory (MRAM) element that is configured to store a state when electric current flows therethrough is disclosed. The MRAM element includes a first magnetic tunnel junction (MTJ) for storing a data bit and a second MTJ for storing a reference bit. Each MTJ further includes a magnetic reference layer (RL) having a magnetization with a direction that is perpendicular to the film plane, and a magnetic pinned layer (PL) having a magnetization with a direction that is perpendicular to the film plane. The direction of magnetization of the RL and the PL are anti-parallel relative to each other in the first MTJ. The direction of magnetization of the FL, the RL and the PL are parallel relative to each other in the second MTJ for storing reference bit. | 11-06-2014 |
| 20140328118 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device according to the present embodiment includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells corresponding to intersections between the bit lines and the word lines, respectively, and including magnetic tunnel junction elements capable of storing data. A plurality of sense amplifiers respectively correspond to the bit lines and are configured to detect data stored in the memory cells via a bit line selected from among the corresponding bit lines. A plurality of read latch parts correspond to the sense amplifiers, respectively, and are configured to latch data detected by the corresponding sense amplifiers. A plurality of read global data buses are connected to the read latch parts, respectively, and are configured to consecutively transmit data latched by the read latch parts at a time of a data read operation. | 11-06-2014 |
| 20140328119 | STORAGE ELEMENT AND MEMORY - A storage element includes a magnetization fixed layer, and a magnetization free layer. The magnetization fixed layer includes a plurality of ferromagnetic layers laminated together with a coupling layer formed between each pair of adjacent ferromagnetic layers. The magnetization directions of the ferromagnetic layers are inclined with respect to a magnetization direction of the magnetization fixed layer. | 11-06-2014 |
| 20140340957 | NON-VOLATILE LATCH USING SPIN-TRANSFER TORQUE MEMORY DEVICE - Described is an apparatus of a non-volatile logic (NVL), the apparatus comprises: a sensing circuit to sense differential resistance; a first magnetic-tunneling-junction (MTJ) device coupled to the sensing circuit; a second MTJ device coupled to the sensing circuit, the first and second MTJ devices operable to provide differential resistance; and a buffer to drive complementary signals to the first and second MTJ devices respectively. | 11-20-2014 |
| 20140340958 | RELIABILITY OF MAGNETORESISTIVE RANDOM-ACCESS MEMORY - A memory cell comprises a dual-gate fin field effect transistor (FinFET) and first and second serially connected magnetic tunnel junction (MTJ) devices for improving reliability of memory operations. The FinFET represents an access transistor and includes a first gate and a second gate. The second gate is configured to be electrically independent from the first gate and to adjust threshold voltage of the FinFET. Each of the first and second MTJ devices represent a magnetic storage element and includes at least two ferromagnetic (FM) layers separated by a thin insulating layer forming a tunneling junction. Based on the relative magnetization of the two FM layers, each MTJ device has high and low resistance states. Higher reliability of memory write operation is primarily achieved with the help of FinFET and higher reliability of memory read operation is primarily achieved with increased read margin. | 11-20-2014 |
| 20140340959 | NONVOLATILE MEMORY DEVICE AND DATA PROCESSING METHOD THEREOF - A nonvolatile memory device is provided comprising a memory cell array including first and second memory cells. Data is stored at the first memory cell. The device further comprises an access control circuit configured to read the data stored at the first memory cell and to subsequently perform a data processing operation on the second memory cell contemporaneously with a reprogramming operation performed on the first memory cell. The reprogramming operation on the first memory cell is selectively performed based on a determination whether a state of the first memory cell is changed while the data stored at the first memory cell is read. | 11-20-2014 |
| 20140340960 | MEMORY DEVICE - A memory device includes: a memory element which includes three or more resistance states by using plural magneto-resistive elements each having a first resistance state or a second resistance state; and a comparison and determination circuit which compares the resistance states of the memory element before and after one first magneto-resistive element from among the plural magneto-resistive elements in the memory element is rewritten into the first resistance state, and determines the resistance state of the memory element in accordance with the comparison result. | 11-20-2014 |
| 20140340961 | TUNNEL MAGNETORESISTIVE EFFECT ELEMENT AND RANDOM ACCESS MEMORY USING SAME - Provided is a tunnel magnetoresistive effect element such that a high TMR ratio and a low write current can be realized, and the thermal stability factor (E/k | 11-20-2014 |
| 20140347918 | MRAM Write Pulses to Dissipate Intermediate State Domains - A write method for a STT-RAM MTJ is disclosed that substantially reduces the bit error rate caused by intermediate domain states generated during write pulses. The method includes a plurality of “n” write periods or pulses and “n−1” domain dissipation periods where a domain dissipation period separates successive write periods. During each pulse, a write current is applied in a first direction across the MTJ and during each domain dissipation period, a second current with a magnitude equal to or less than the read current is applied in an opposite direction across the MTJ. Alternatively, no current is applied during one or more domain dissipation periods. Each domain dissipation period has a duration of 1 to 10 ns that is equal to or greater than the precession period of free layer magnetization in the absence of spin torque transfer current. | 11-27-2014 |
| 20140347919 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes: a memory cell array in which a plurality of pairs of bit lines and source lines, a plurality of word lines, and a plurality of resistance change memory cells are arranged; a write driver, a sense amplifier, a global bit line and a global source line provided on a first end side; a plurality of bit line switches provided between the plurality of bit lines and the global bit line; a plurality of source line switches provided between the plurality of source lines and the global source line; a column decoder; a row decoder; a plurality of bit line ground switches provided between the plurality of bit lines and a ground line on a second end side; and a plurality of source line ground switches provided between the plurality of source lines and a ground line on the second end side. | 11-27-2014 |
| 20140355336 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, the semiconductor memory device includes a first memory cell, first, second, third and fourth interconnect lines and first, second and third write circuits. The first memory cell includes a first magnetic tunnel junction (MTJ) element. The first interconnect line is connected to one end of the first memory cell. The first write circuit drives the first interconnect line. The second interconnect line is connected to the other end of the first memory cell. The second write circuit drives the second interconnect line. The third and fourth interconnect lines are adjacent to the first memory cell. The third write circuit drives the third and fourth interconnect lines. | 12-04-2014 |
| 20140355337 | METHOD OF PINNING DOMAIN WALLS IN A NANOWIRE MAGNETIC MEMORY DEVICE - There is provided a method of pinning domain walls in a magnetic memory device ( | 12-04-2014 |
| 20150016184 | MAGNETIC FIELD SENSING USING MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM) CELLS - A magnetic field sensing system includes one or more magnetoresistive random access memory (MRAM) cells, and may be configured to determine one or more of a presence, a magnitude, and a polarity of an external magnetic field incident upon an MRAM cell. In some examples, a control module of the system controls a write current source. Of another device, to provide a write current through a write line associated with the MRAM cell to induce a magnetic field proximate to the MRAM cell. The magnetic field may be less than a magnetic switching threshold of the MRAM cell. After initiating the provision of the write current through the write line, the control module may determine a magnetic state of the MRAM cell, and determine a presence of an external magnetic field incident upon the MRAM cell based at least in part on the magnetic state of the MRAM cell. | 01-15-2015 |
| 20150023092 | RING-SHAPED MAGNETORESISTIVE MEMORY DEVICE AND WRITING METHOD THEREOF - A ring-shaped magnetoresistive memory device includes a ring-shaped magnetoresistive memory cell, a first conductor, and a second conductor. The first conductor is positioned on a first surface of the ring-shaped magnetoresistive memory cell for generating a first magnetic field pulse. The second conductor is positioned on a second surface of the ring-shaped magnetoresistive memory cell for generating a second magnetic field pulse. The first surface is opposite to the second surface. An extension direction of the first conductor is perpendicular to an extension direction of the second conductor. A time delay is between the first magnetic field pulse and the second magnetic field pulse. | 01-22-2015 |
| 20150023093 | METHOD OF WRITING TO A SPIN TORQUE MAGNETIC RANDOM ACCESS MEMORY - Circuitry and a method provide an increased tunnel barrier endurance (lifetime) previously shortened by dielectric breakdown by providing a pulse of opposite polarity associated with a write pulse. The pulse of opposite polarity may comprise equal or less width and amplitude than that of the write pulse, may be applied with each write pulse or a series of write pulses, and may be applied prior to or subsequent to the write pulse. | 01-22-2015 |
| 20150029786 | SELF-REFERENCED SENSE AMPLIFIER FOR SPIN TORQUE MRAM - Circuitry and a method provide a plurality of timed control and bias voltages to sense amplifiers and write drivers of a spin-torque magnetoresistive random access memory array for improved power supply noise rejection, increased sensing speed with immunity for bank-to-bank noise coupling, and reduced leakage from off word line select devices in an active column. | 01-29-2015 |
| 20150036421 | CURRENT SENSE AMPLIFYING CIRCUIT IN SEMICONDUCTOR MEMORY DEVICE - Disclosed is a current sense amplifier suitable for a nonvolatile memory device such as a magnetic random access memory. In the current sense amplifier, a reference memory cell for sensing is implemented by a memory cell equal to a normal memory cell without fabricating different reference memory cells. The current sense amplifier is formed of first and second cross coupled differential amplifiers being covalent bonded. The current sense amplifier compares a current flowing to a sensing node of a memory cell directly with currents flowing to reference sensing nodes. | 02-05-2015 |
| 20150036422 | MAGNETIC STORAGE ELEMENT, MAGNETIC STORAGE DEVICE, MAGNETIC MEMORY, AND METHOD OF DRIVING MAGNETIC STORAGE ELEMENT - A magnetic storage element according to an embodiment includes: a magnetic nanowire having a cross-sectional area varying in a first direction, the magnetic nanowire having at least two positions where the cross-sectional area is minimal; first and second electrode groups having the magnetic nanowire interposed in between, the magnetic nanowire including at least one of a first region where the first electrodes overlap the second electrodes with the magnetic nanowire interposed in between and a second region where neither the first electrodes nor the second electrodes exist with the magnetic nanowire interposed in between, the magnetic nanowire including at least one of a third region where the first electrodes exist and the second electrodes do not exist with the magnetic nanowire interposed in between and a fourth region where the first electrodes do not exist and the second electrodes exist with the magnetic nanowire interposed in between. | 02-05-2015 |
| 20150036423 | SEMICONDUCTOR DEVICE - An array configuration capable of supplying a necessary and sufficient current in a small area is achieved and a reference cell configuration suitable to temperature characteristics of a TMR element is achieved. In a memory using inversion of spin transfer switching, a plurality of program drivers are arranged separately along one global bit line, and one sense amplifier is provided to one global bit line. A reference cell to which “1” and “0” are programmed is shared by two arrays and a sense amplifier. | 02-05-2015 |
| 20150036424 | SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM AND ACCESS METHOD TO SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a block array having an m number of memory blocks in a row direction and an n number of memory blocks in a column direction (m being an integer of 2 or more and n being an integer of 1 or more), a page selection circuit configured to select a row in the block array as a page to be selected, and a page buffer configured to store data to be written in a page selected by the page selection circuit or data read from the page. Each of the memory blocks includes a memory cell array having a plurality of memory cells, a row selection circuit configured to select a row of the memory cell array, and a column selection circuit configured to select a column of the memory cell array. | 02-05-2015 |
| 20150043271 | ADAPTIVE DUAL VOLTAGE WRITE DRIVER WITH DUMMY RESISTIVE PATH TRACKING - An adaptive dual voltage memory write driver system can include an adaptive write voltage generator circuit to provide a first adjustable write voltage and to provide a second adjustable write voltage. The adaptive dual voltage memory write driver system can include an array of dummy memory cells coupled to the adaptive write voltage generator circuit and configured to provide resistive path tracking information to the adaptive write voltage generator circuit. The adjustable write voltages can be automatically increased or decreased responsive to the resistive path tracking information. A tri-state write driver circuit can provide a first adjustable write voltage source for writing “0”s and a second adjustable write voltage source for writing “1”s. A method for generating adjustable memory write voltages using dummy resistive path tracking may include receiving resistive path tracking information from a dummy section, and generating adjustable write voltages based on the resistive path tracking information. | 02-12-2015 |
| 20150043272 | Spin-Transfer Torque Magnetic Random Access Memory (STTMRAM) With Enhanced Write Current - A spin-transfer torque magnetic random access memory (STTMRAM) cell is disclosed. The memory cell comprises a selected magnetic tunnel junction (MTJ) identified to be programmed; a first transistor having a first port, a second port and a gate, the first port of the first transistor coupled to the selected MTJ; a first neighboring MTJ coupled to the selected MTJ through the second port of the first transistor; a second transistor having a first port, a second port, and a gate, the first port of the second transistor coupled to the selected MTJ; a second neighboring MTJ coupled to the selected MTJ through the second port of the second transistor; a first bit/source line coupled to the second end of the selected MTJ; and a second bit/source line coupled to the second end of the first neighboring MTJ and the second end of the second neighboring MTJ. | 02-12-2015 |
| 20150049542 | MEMORY AND LOGIC DEVICE AND METHODS FOR PERFORMING THEREOF - In accordance with one exemplary embodiment of the present technique, there is disclosed a spins selective device, including a first layer comprising a ferromagnetic material. The spin selective device further includes a second layer coupled to the first layer. The second layer includes at least one molecule having a specified chirality, such that when an electrical current flows between the first layer and the second layer one or more regions of the ferromagnetic material become magnetically polarized along a certain direction. | 02-19-2015 |
| 20150055403 | MEMORY DEVICE AND MEMORY SYSTEM WITH SENSOR - According to one embodiment, a memory device includes: a nonvolatile memory that stores data according to a write access; an address memory that stores a first address described with a gray code; a first counter that counts up the first address for each write access, generates a second address as the count-up result, and supplies the second address to the nonvolatile memory; a rounding circuit configured to calculate a third address that is equal to or larger than a final output of the first counter and larger than the first address by one or a power of two after a series of write accesses is completed; and a controller that rewrites the third address in the address memory. | 02-26-2015 |
| 20150055404 | MAGNETIC MEMORY DEVICE AND METHOD OF MAGNETIC DOMAIN WALL MOTION - A magnetic memory device comprises a first electrode, a second electrode, a laminated structure comprising plural first magnetic layers being provided between the first electrode and the second electrode, a second magnetic layer comprising different composition elements from that of the first magnetic layer and being provided between plural first magnetic layers, a piezoelectric body provided on a opposite side to a side where the first electrode is provided in the laminated structure, and a third electrode applying voltage to the piezoelectric body and provided on a different position from a position where the first electrode is provided in the piezoelectric body. | 02-26-2015 |
| 20150055405 | MEMORY DEVICE AND MEMORY SYSTEM WITH SENSOR - According to one embodiment, a memory device includes a first address memory storing a first address; a controller which is based on a first interface which transmits a signal serially and outputs a first command in accordance with the first interface; and a memory which stores data in a nonvolatile manner, is based on the first interface, and stores received write data in an address based on the first address when the memory receives the first command. | 02-26-2015 |
| 20150055406 | NON-DESTRUCTIVE WRITE/READ LEVELING - In some examples, a memory device is configured with non-volatile memory array(s) having one or more associated volatile memory arrays. The memory device may include a non-destructive write mode configured to prevent access to the non-volatile memory array(s) during an initiation or calibration sequence performed by the memory device or an electronic device associated with the memory device to calibrate read and write access timing associated with the memory device. | 02-26-2015 |
| 20150063011 | Method for improving the stabillity, write-ability and manufacturability of magneto-resistive random access memory - This invention provides the method to overcome 4 backwards which limit the manufacturability or production yield rate of Magneto-resistive random access memory (MRAM). The key points of this invention are: (1) providing method to improve the manufacturability through reducing bias variation, by using a compensation module to correct the bias point of extreme cells; (2) providing method to improve the manufacturability through removing outlier cells (called bad cells), by using “writing jump-over” and “reading exclusion” to exclude bad-cells; (3) providing method to reduce the bias point, amplitude and asymmetry variation, using shared fixed-magnetic-reference-layer and proper shape anisotropy; (4) providing method to improve the write-ability, using flipping-assistant-field to speed up STT flipping process by large current, and using heating resistance and heating cells by the same current (including global heating, row heating, column heating, or local cell heating, i.e. heating with conventional thermal nature or heating with thermagnonic spin-transfer torque). | 03-05-2015 |
| 20150063012 | OFFSET CANCELING DUAL STAGE SENSING CIRCUIT - An offset canceling dual stage sensing method includes sensing a data value of a resistive memory data cell using a first load PMOS gate voltage generated by a reference value of a resistive memory reference cell in a first stage operation. The method also includes sensing the reference value of the resistive memory reference cell using a second load PMOS gate voltage generated by the data value of the resistive memory data cell in a second stage operation of the resistive memory sensing circuit. By adjusting the operating point of the reference cell sensing, an offset canceling dual stage sensing circuit increases the sense margin significantly compared to that of a conventional sensing circuit. | 03-05-2015 |
| 20150063013 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a bank including a normal area including normal columns, and a redundancy area including redundancy columns and to be replaced with a failure column of the normal area; sense amplifiers connected to the normal area; and a redundancy sense amplifier connected to the redundancy area. A normal replacement unit is formed of normal columns allocated to each of the sense amplifiers. A redundancy replacement unit is formed of redundancy columns allocated to the redundancy sense amplifier. The redundancy replacement unit is smaller than the normal replacement unit. | 03-05-2015 |
| 20150063014 | MAGNETIC MEMORY AND CONTROLLING METHOD THEREOF - According to one embodiment, a magnetic memory includes a cell array includes a plurality of memory cells, each memory cell including a magnetoresistive effect element; and a read circuit to read data from a memory cell selected based on an address signal from among the memory cells. The read circuit selects one determination level from among a plurality of determination levels corresponding to a position of a magnetoresistive effect element in the cell array and uses the selected determination level to perform reading of the data. | 03-05-2015 |
| 20150063015 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: banks each including a memory cell array; word lines connected to rows of each of the banks; an address latch circuit configured to latch a full address for specifying one of the word lines, the full address including a first address and a second address; and a control circuit configured to ignore a reset operation for the first address as a target of a set operation, and overwrite the first address in accordance with the set operation when receiving a first command for specifying a reset operation for a bank and a set operation for the first address. | 03-05-2015 |
| 20150063016 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: banks each including a memory cell array; word lines connected to rows in each of the banks; and an address latch circuit configured to latch a full address specifying one of the word lines, the full address including a first address and a second address. The address latch circuit receives a first command and a second command to latch the first address and the second address in accordance with the first command and the second command, respectively. Paths for the first address and the second address are configured to be separate from each other. | 03-05-2015 |
| 20150063017 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is capable of executing a first mode having a first latency and a second mode having a second latency longer than the first latency. The semiconductor memory device includes: a pad unit configured to receive an address and a command from an outside; a first delay circuit configured to delay the address by a time corresponding to the first latency; a second delay circuit including shift registers connected in series and configured to delay the address by a time corresponding to a difference between the first latency and the second latency; and a controller configured to use the first delay circuit and the second delay circuit when executing the second mode. | 03-05-2015 |
| 20150063018 | METHODS OF OPERATING A MAGNETIC MEMORY DEVICE - Provided is a data writing method of a magnetic memory device. The method may include flowing first and second currents near left and right sides, respectively, of a selected memory cell to apply an ambient magnetic field to the selected memory cell. Here, directions of the first and second currents may be anti-parallel to each other. | 03-05-2015 |
| 20150063019 | THERMALLY-ASSISTED MAGNETIC WRITING DEVICE - A thermally-assisted magnetic writing device includes at least one magnetic element including: a reference layer having a stable vortex magnetisation configuration; a device to create a magnetic field to reversibly move the vortex core in the plane of the reference layer; a storage layer having a variable magnetisation configuration; a non-magnetic spacer that separates and magnetically decouples the reference layer and the storage layer; an antiferromagnetic pinning layer in contact with the storage layer, the antiferromagnetic layer being capable of pinning the magnetisation configuration of the storage layer, the storage layer having at least two storage levels corresponding to two pinned magnetisation configurations; a device to heat the antiferromagnetic pinning layer such that when heated, the temperature of the antiferromagnetic pinning layer exceeds its blocking temperature such that the magnetisation configuration of the storage layer is no longer pinned when warm. | 03-05-2015 |
| 20150063020 | SEMICONDUCTOR DEVICE - A method includes measuring a first pulse width of a resistance variable memory cell coupled between a first terminal and a second terminal, the first pulse width including a period from starting a first data writing of the resistance variable memory cell by applying a voltage between the first and second terminals to ending the first data writing of the resistance variable memory cell, and measuring a second pulse width of the resistance variable memory cell coupled between the first and the second terminal. The method includes setting longer one of the first and second pulse widths in a first storage area as a pulse width to be used in program. | 03-05-2015 |
| 20150070978 | SYSTEM AND METHOD TO PROVIDE A REFERENCE CELL - An apparatus includes a group of data cells and a reference cell coupled to the group of data cells. The reference cell includes four magnetic tunnel junction (MTJ) cells. Each of the four MTJ cells is coupled to a distinct word line. Each of the four MTJ cells includes an MTJ element and a single transistor. The single transistor of each particular MTJ cell is configured to enable read access to the MTJ element of the particular MTJ cell. | 03-12-2015 |
| 20150070979 | PHYSICALLY UNCLONABLE FUNCTION BASED ON PROGRAMMING VOLTAGE OF MAGNETORESISTIVE RANDOM-ACCESS MEMORY - One feature pertains to a method of implementing a physically unclonable function. The method includes initializing an array of magnetoresistive random-access memory (MRAM) cells to a first logical state, where each of the MRAM cells have a random transition voltage that is greater than a first voltage and less than a second voltage. The transition voltage represents a voltage level that causes the MRAM cells to transition from the first logical state to a second logical state. The method further includes applying a programming signal voltage to each of the MRAM cells of the array to cause at least a portion of the MRAM cells of the array to randomly change state from the first logical state to the second logical state, where the programming signal voltage is greater than the first voltage and less than the second voltage. | 03-12-2015 |
| 20150070980 | MAGNETIC MEMORY DEVICE UTILIZING MAGNETIC DOMAIN WALL MOTION - A magnetic memory device includes a magnetic thin wire including magnetic domains along a direction in which the magnetic thin wire extends. Magnetization directions of the magnetic domains are variable. A magnetic tunnel junction (MTJ) structure includes a pinned layer with a fixed magnetization direction and an insulator, and makes an MTJ including the pinned layer and insulator and a magnetic domain in the magnetic thin wire in a first position to sandwich the insulator with pinned layer. First and second electrodes are at both ends of the magnetic thin wire. At least one third electrode is coupled to the magnetic thin wire between the first and second electrodes. | 03-12-2015 |
| 20150070981 | MAGNETORESISTANCE ELEMENT AND MAGNETORESISTIVE MEMORY - According to one embodiment, a magnetoresistance element includes a spin valve structure portion formed on a substrate and a tunnel magnetic junction structure portion formed on a part of the spin valve structure portion. The spin valve structure portion is formed by having a nonmagnetic layer sandwiched between first and second ferromagnetic layers. Further, the tunnel magnetic junction structure portion includes the second ferromagnetic layer, a tunnel barrier layer formed on a part of the second ferromagnetic layer and a third ferromagnetic layer formed on the tunnel barrier layer. | 03-12-2015 |
| 20150070982 | SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a semiconductor storage device includes a cell array including resistance change elements formed above a semiconductor substrate; first cell transistors formed on the semiconductor substrate and provided in association with the resistance change elements; first gate electrodes included in the first cell transistor and extending in a first direction; a first bit lines electrically connected to the resistance change elements respectively and extending in a second direction perpendicular to the first direction; a second bit lines electrically connected to one end of a current path of the first cell transistors respectively and extending in the second direction; and first active areas in which the first cell transistors are formed, and which extend in a direction crossing the first direction at a first angle. | 03-12-2015 |
| 20150070983 | MAGNETIC MEMORY DEVICE - According to one embodiment, a magnetic memory device includes a bit line, a source line, a magnetoresistance effect element between the bit line and the source line, and a nonlinear element provided between the bit line and the source line and connected in series to the magnetoresistance effect element. The nonlinear element has a voltage-current characteristic in which current increases until a voltage to be applied becomes a predetermined applied voltage, when current flowing through the nonlinear element is within a range not exceeding a predetermined current, and current increases within an applied voltage range lower than the predetermined applied voltage, when current flowing through the nonlinear element is within a range exceeding the predetermined current. | 03-12-2015 |
| 20150070984 | SPIN VALVE - A spin valve includes two layers, a reference layer and a free layer, magnetised perpendicularly to a layer plane and an intermediate layer disposed between the magnetic layers. The reference layer predetermines a preferred orientation of a direction of the magnetisation, is formed from a ferrimagnetic material, and has a higher coercive field strength than the free layer. The free layer is formed from a ferromagnetic or ferrimagnetic material. The intermediate layer is electrically conductive or non-conductive. The reference layer and the free layer have a single-domain magnetisation. The reference layer is formed from an alloy comprising a rare earth element and a transition metal. The coercive field strength of the reference layer is set via its composition and is more than 0.8 kA/m. An anisotropy and layer thickness of the reference layer and a coupling constant define an exchange bias field between 0.8 and 80 kA/m. | 03-12-2015 |
| 20150078070 | MAGNETIC MEMORY DEVICE AND DRIVING METHOD FOR THE SAME - According to one embodiment, a magnetic memory device includes a magnetic unit, a switching part, and a reading part. The magnetic unit includes a magnetic wire, and first and second magnetic parts. The magnetic wire includes magnetic domains and has one end and one other end. The first magnetic part is connected with the one end and has a first magnetization. The second magnetic part is connected with the one end, and has a second magnetization. The switching part includes first and second switches. The first switch is connected with the first magnetic part and flows a first current between the first magnetic part and the magnetic wire. The second switch is connected with the second magnetic part and flows a second current between the second magnetic part and the magnetic wire. The reading part is configured to read a magnetization of the magnetic domains. | 03-19-2015 |
| 20150078071 | MAGENTIC DOMAIN WALL MOTION MEMORY AND WRITE METHOD FOR THE SAME - A magnetic domain wall motion memory according to an embodiment includes: a magnetic memory nanowire; a write magnetic wire intersecting with the magnetic memory nanowire; an intermediate joining portion provided in an intersection region between the write magnetic wire and the magnetic memory nanowire; adjacent pinning portions placed on one of the same side and the opposite side of the write magnetic wire as and from the magnetic memory nanowire; a read unit attached to the magnetic memory nanowire; a pair of first electrodes that applies a write current to the write magnetic wire; and a pair of second electrodes that applies a current for causing the magnetic memory nanowire to move a magnetic domain wall, wherein contact faces of the write magnetic wire in contact with the adjacent pinning portions have magnetization configurations antiparallel to each other. | 03-19-2015 |
| 20150078072 | METHOD AND APPARATUS FOR INCREASING THE RELIABILITY OF AN ACCESS TRANSITOR COUPLED TO A MAGNETIC TUNNEL JUNCTION (MTJ) - A method of writing to a magnetic tunnel junction (MTJ) of a magnetic memory array includes an access transistor coupled to the MTJ for reading of and writing to the MTJ, where when the MTJ is written to, at times, by switching its magnetic orientation from an anti-parallel to a parallel magnetic orientation, a bit line that is coupled to one end of the MTJ is raised to Vcc and a voltage that is the sum of Vcc and Vx is applied to the gate of the access transistor, with Vx being approximately the voltage at an opposite end of the MTJ. Further, the voltage of a Source Line (SL), which is coupled to the MTJ using a first transistor of a write driver that is also coupled to the SL, is regulated such that SL remains sufficiently above 0 volts to avoid violation of Vgs exceeding Vcc where Vgs is the gate to source voltage of the access transistor. | 03-19-2015 |
| 20150078073 | UNIDIRECTIONAL SPIN TORQUE TRANSFER MAGNETIC MEMORY CELL STRUCTURE - Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells having two pinned layers and a free layer therebetween. By utilizing two pinned layers, the spin torque effect on the free layer from each of the two pinned layers, respectively, allows the memory cells to be programmed with unidirectional currents. | 03-19-2015 |
| 20150078074 | THREE-DIMENSIONAL MAGNETIC MEMORY WITH MULTI-LAYER DATA STORAGE LAYERS - Magnetic memories and methods are disclosed. A magnetic memory as described herein includes a plurality of stacked data storage layers to form a three-dimensional magnetic memory. The data storage layers are each formed from a multi-layer structure. At ambient temperatures, the multi-layer structures exhibit an antiparallel coupling state with a near zero net magnetic moment. At higher transition temperatures, the multi-layer structures transition from the antiparallel coupling state to a parallel coupling state with a net magnetic moment. At yet higher temperatures, the multi-layer structure transitions from the antiparallel coupling state to a receiving state where the coercivity of the multi-layer structures drops below a particular level so that magnetic fields from write elements or neighboring data storage layers may imprint data into the data storage layer. | 03-19-2015 |
| 20150085569 | ELECTRIC FIELD FERROMAGNETIC RESONANCE EXCITATION METHOD AND MAGNETIC FUNCTION ELEMENT EMPLOYING SAME - To realize an electric field-driven type ferromagnetic resonance excitation method of low power consumption using an electric field as drive power, and provide a spin wave signal generation element and a spin current signal generation element using the method, a logic element using the elements, and a magnetic function element such as a high-frequency detection element and a magnetic recording device using the method. A magnetic field having a specific magnetic field application angle and magnetic field strength is applied to a laminate structure in which an ultrathin ferromagnetic layer sufficiently thin so that an electric field shield effect by conduction electrons does not occur and a magnetic anisotropy control layer are directly stacked on each other and an insulation barrier layer and an electrode layer are arranged in order on an ultrathin ferromagnetic layer side. An electric field having a high-frequency component of a magnetic resonance frequency is then applied between the magnetic anisotropy control layer and the electrode layer, thereby efficiently exciting ferromagnetic resonance in the ultrathin ferromagnetic layer. | 03-26-2015 |
| 20150092478 | DISTRIBUTED CURRENT CLOCK FOR NANO-MAGNETIC ELEMENT ARRAY - A nano-magnetic element array having a conductive line adjacent to a group of nano-magnetic elements and a multi-level current driver connected to an input node on the conductive line. The current driver is controlled by a pair of voltage clock signals and a voltage reference so as to selectively change the current amount at the input node between a first level that erases the state of the elements, a second level that switches the state of the elements and a third level that maintains the state of the elements. The current driver is further configured so that the transition from the second to the third level is gradual. Optionally, a bias generator can selectively adjust the voltage reference and thereby, the current amount at the input node. Also, optionally, the same voltage clock signal and voltage reference lines can be used to control multiple multi-level current drivers within the array. | 04-02-2015 |
| 20150092479 | RESISTANCE-BASED MEMORY CELLS WITH MULTIPLE SOURCE LINES - In a particular embodiment, a device includes a resistance-based memory cell having multiple source lines and multiple access transistors. A coupling configuration of the multiple access transistors to multiple source lines encodes a data value. | 04-02-2015 |
| 20150092480 | ELECTRONIC DEVICE AND METHOD OF FABRICATING THE SAME - An electronic device includes a semiconductor memory, wherein the semiconductor memory includes: a seed layer including conductive hafnium silicate; a first magnetic layer formed over the seed layer; a tunnel barrier layer formed over the first magnetic layer; and a second magnetic layer formed over the tunnel barrier layer. | 04-02-2015 |
| 20150092481 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - An electronic device includes a semiconductor memory, wherein the semiconductor memory includes: a variable resistance element having a stacked structure of a first magnetic layer, a tunnel barrier layer, and a second magnetic layer; and a protection layer including a pillar-shaped magnetic compensation layer and a non-magnetic layer, which are formed on the sidewall of the variable resistance element. | 04-02-2015 |
| 20150103586 | WRITE DRIVER AND PROGRAM DRIVER FOR OTP (ONE-TIME PROGRAMMABLE) MEMORY WITH MAGNETIC TUNNELING JUNCTION CELLS - A one-time programmable (OTP) memory having a plurality of cells, each cell having a magnetic tunnel junction (MTJ) device; and the OTP memory further including a write driver to drive each MTJ device to an anti-parallel state, and a program driver to drive a subset of the MTJ devices to a blown state depending upon the information to be stored. | 04-16-2015 |
| 20150103587 | ELECTRONIC DEVICE AND METHOD FOR DRIVING THE SAME - In an electronic device including a semiconductor memory, the semiconductor memory may include a unit storage cell including a variable resistor having a resistance value that is changed according to current flowing through both terminals of the variable resistor and a selection element that is electrically coupled to one terminal of the variable resistor, a unit current generation section that generates the current flowing through both terminals by using predetermined voltage according to a polarity of current data as compared with existing data, and a pad that receives the predetermined voltage from an exterior and allows the current flowing through both terminals to be measured from an exterior. | 04-16-2015 |
| 20150109853 | MAGNETORESISTANCE EFFECT ELEMENT AND MAGNETIC MEMORY - A magnetoresistance effect element including a recording layer of high thermal stability to perform perpendicular magnetic recording within a film surface, and a magnetic memory using the element. The element includes: a first ferromagnetic layer of an invariable magnetization direction; a second ferromagnetic layer of a variable magnetization direction; a first non-magnetic layer between the first and second ferromagnetic layers; current supply terminals connected to the first and second ferromagnetic layers; a non-magnetic coupling layer on a surface of the second ferromagnetic layer opposite the first non-magnetic layer; a third ferromagnetic layer of a variable magnetization direction on a surface of the non-magnetic coupling layer opposite the second ferromagnetic layer; and a second non-magnetic layer on a surface of the third ferromagnetic layer opposite the non-magnetic coupling layer. The second and third ferromagnetic layers have the same magnetization direction and are reversed in magnetization by spin injection with a current. | 04-23-2015 |
| 20150109854 | METHOD FOR WRITING TO A MAGNETIC TUNNEL JUNCTION DEVICE - A method of applying a write current to a magnetic tunnel junction device minimizes sub-threshold leakage. NMOS- and PMOS-follower circuits are used in applying the write current, and bias signals for the follower circuits are isolated from global bias signals before the write current is applied. | 04-23-2015 |
| 20150109855 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory cell array, a buffer configured to hold data input to an input/output circuit and to hold data read from the memory cell array, and a controller configured to receive a first command and an address from the outside and to read data, in response to the first command, from a memory cell group coupled to a selected word line designated by the address to the buffer. The controller receives a second command which is input after the first command and indicates a last command of a group of commands including write commands and/or read commands, and starts a write operation from the buffer to the memory cell array in response to the second command. | 04-23-2015 |
| 20150117095 | LOW RESISTANCE BITLINE AND SOURCELINE APPARATUS FOR IMPROVING READ AND WRITE OPERATIONS OF A NONVOLATILE MEMORY - Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells. | 04-30-2015 |
| 20150124523 | INITIALIZATION METHOD OF A PERPENDICULAR MAGNETIC RANDOM ACCESS MEMORY (MRAM) DEVICE - Methods using a sequence of externally generated magnetic fields to initialize the magnetization directions of each of the layers in perpendicular MTJ MRAM elements for data and reference bits when the required magnetization directions are anti-parallel are described. The coercivity of the fixed pinned and reference layers can be made unequal so that one of them can be switched by a magnetic field that will reliably leave the other one unswitched. Embodiments of the invention utilize the different effective coercivity fields of the pinned, reference and free layers to selectively switch the magnetization directions using a sequence of magnetic fields of decreasing strength. Optionally the chip or wafer can be heated to reduce the required field magnitude. It is possible that the first magnetic field in the sequence can be applied during an annealing step in the MRAM manufacture process. | 05-07-2015 |
| 20150124524 | MEMORY DEVICE WITH TIMING OVERLAP MODE - In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes. | 05-07-2015 |
| 20150131369 | PULSE PROGRAMMING TECHNIQUES FOR VOLTAGE-CONTROLLED MAGNETORESISTIVE TUNNEL JUNCTION (MTJ) - A method of programming a voltage-controlled magnetoresistive tunnel junction (MTJ) includes applying a programming voltage pulse (Vp), reading the voltage-controlled MTJ, and determining if the voltage-controlled MTJ is programmed to a desired state and if not, changing the Vp and repeating the applying and reading steps until the voltage-controlled MTJ is programmed to the desired state. | 05-14-2015 |
| 20150131370 | MULTI-LEVEL CELLS AND METHOD FOR USING THE SAME - The present invention is directed to a method for reading and writing an STT-MRAM multi-level cell (MLC), which includes a plurality of memory elements coupled in series. The method detects the resistance states of individual memory elements in an MLC by sequentially writing at least one of the plurality of memory element to the low resistance state in order of ascending write current threshold. If a written element switches the resistance state thereof after the write step, then the written element was in the high resistance state prior to the write step. Otherwise, the written element was in the low resistance state prior to the write step. The switching of the resistance state can be ascertained by comparing the resistance or voltage values of the plurality of memory elements before and after writing each of the plurality of memory elements in accordance with the embodiments of the present invention. | 05-14-2015 |
| 20150131371 | MAGNETIC RESISTANCE STRUCTURE, METHOD OF MANUFACTURING THE MAGNETIC RESISTANCE STRUCTURE, AND ELECTRONIC DEVICE INCLUDING THE MAGNETIC RESISTANCE STRUCTURE - Provided are a magnetic resistance structure, a method of manufacturing the magnetic resistance structure, and an electronic device including the magnetic resistance structure. The method of manufacturing the magnetic resistance structure includes forming a hexagonal boron nitride layer, forming a graphene layer on the boron nitride layer, forming a first magnetic material layer between the boron nitride layer and the graphene layer according to an intercalation process; and forming a second magnetic material layer on the graphene layer. | 05-14-2015 |
| 20150138877 | NONVOLATILE LOGIC GATE DEVICE - A nonvolatile logic gate device is configured to include a resistive network of a memory structure in which at least three nonvolatile resistive elements are connected, a reference resistive network as a reference resistance providing a tolerance of the memory structure to a resistance value of the resistive network of the memory structure, a writing part operable to selectively write or rewrite a value of each of the nonvolatile resistive elements in the resistive network into a maximum or a minimum corresponding to a logical value to be read when data are stored into the resistive network, and a logic circuit structure operable to use, as a logical value of the memory structure, a value obtained by comparison between the resistance value of the resistive network and the resistance value of the reference resistive network. | 05-21-2015 |
| 20150138878 | ELECTRONIC APPARATUS - This invention makes is possible to protect programs and shorten the activation time of an electronic apparatus even if a non-volatile memory such as an MRAM stores the programs including a boot program, and is used as a main memory. Upon power-on or receiving a reset signal, a program stored in bank | 05-21-2015 |
| 20150138879 | READ CIRCUIT FOR MEMORY - Embodiments are directed to detecting a state of a memory element in a memory device, comprising: applying a pulse of a predetermined magnitude and duration to the memory element to induce a transition in the state of the memory element when a polarity of the pulse is opposite to the state, monitoring, by a device, a signal associated with the memory element to detect a presence or absence of a transition in the signal in an amount greater than a threshold, and determining the state of the memory element based on said monitoring. | 05-21-2015 |
| 20150146481 | METHOD AND APPARATUS FOR SENSING TUNNEL MAGNETO-RESISTANCE - In one embodiment, an apparatus comprises: an MRAM (magnetic random access memory) cell array comprising a plurality of MRAM cells including a calibration cell and a plurality of data cells; a reference MRAM cell controlled by a control signal; and a sensing-amplifier/latch; wherein: said plurality of data cells are used for storing user data; the calibration cell is used for a calibration purpose; the reference MRAM cell serves as a reference for comparison with a MRAM cell selected within the MRAM cell array; the sensing-amplifier/latch outputs a logical signal based on comparing a resistance of the MRAM cell selected within the MRAM cell array and a resistance of the reference MRAM cell; and the control signal is established in a calibration process by comparing a resistance of the calibration cell with the resistance of the reference MRAM cell. | 05-28-2015 |
| 20150146482 | METHOD AND APPARATUS FOR READING A MAGNETIC TUNNEL JUNCTION USING A SEQUENCE OF SHORT PULSES - A magnetic random access memory (MRAM) array having a magnetic tunnel junction (MTJ) to be read using a magnetic state of the MTJ, the MTJ being read by applying a current there through. Further, the MRAM array has a reference MTJ, a sense amplifier coupled to the MTJ and the reference MTJ, the sense amplifier operable to compare the voltage of the MTJ to the reference MTJ in determining the state of the MTJ; a first capacitor coupled to the sense amplifier at a first end and to ground at a second end; and a second capacitor coupled to the sense amplifier at a first end and to ground at a second end, the first capacitor storing the, wherein short voltage pulses are applied to the first end of each of the first and second capacitors when reading the MTJ thereby makes the current flowing through the MTJ there through for small time intervals thereby avoiding read disturbance to the MTJ. | 05-28-2015 |
| 20150146483 | DIFFERENTIAL CURRENT SENSING SCHEME FOR MAGNETIC RANDOM ACCESS MEMORY - A circuit includes a cell segment, first and second reference cells, and a current sense amplifier. The first and second reference cells are configured to store opposite logic values, respectively. The current sense amplifier is configured with a first node and a second node for currents therethrough to be compared with each other. The current sense amplifier includes a multiplexer configured to couple the first reference cell or the second reference cell to the first node of the current sense amplifier, and couple the second reference cell or the first reference cell to the second node of the current sense amplifier in a first mode, and couple a cell of the cell segment to the first node of the current sense amplifier, and couple the first and second reference cells to the second node of the current sense amplifier in a second mode. | 05-28-2015 |
| 20150294695 | SEMICONDUCTOR RESISTIVE MEMORY DEVICES INCLUDING SEPARATELY CONTROLLABLE SOURCE LINES - A magnetic memory device can include a plurality of separately controllable magnetic memory segments configured to store data. A plurality of separately controllable source lines can each be coupled to a respective one of the plurality of separately controllable magnetic memory segments. | 10-15-2015 |
| 20150294703 | METHOD AND SYSTEM FOR PROVIDING A THERMALLY ASSISTED SPIN TRANSFER TORQUE MAGNETIC DEVICE INCLUDING SMART THERMAL BARRIERS - A magnetic device usable in electronic devices is described. The magnetic device includes a magnetic junction and at least one smart thermal barrier that is thermally coupled with the magnetic junction. The magnetic junction includes at least one reference layer, at least one nonmagnetic spacer layer and a free layer. The nonmagnetic spacer layer(s) are between the reference layer(s) and the free layer. The free layer is switchable between stable magnetic states when a write current passed through the magnetic junction. The smart thermal barrier has a low heat conductance below a transition temperature range, and a high heat conductance above the transition temperature range. | 10-15-2015 |
| 20150294706 | Offset-Cancelling Self-Reference STT-MRAM Sense Amplifier - Embodiments are directed to a self-reference STT-MRAM sensing scheme that uses offset-cancellation to reduce the impact of FET mismatch and thereby allow the sensing of lower read voltages. In some embodiments, the sensing scheme includes a differential amplifier having a first input connected to a memory cell. In some embodiments, a second input of the differential amplifier may be connected to ground, a common mode voltage of the system or a mid-level supply voltage. The present disclosure provides flexibility with respect to the voltage level at which the sensing is performed (e.g., ground, Voc, Vmid, etc.). The present disclosure provides further flexibility with respect to the sense voltage polarity. | 10-15-2015 |
| 20150294707 | METHOD AND SYSTEM FOR PROVIDING THERMALLY ASSISTED MAGNETIC JUNCTIONS HAVING A MULTI-PHASE OPERATION - A magnetic junction usable in magnetic devices is described. The magnetic junction includes at least one reference layer, at least one nonmagnetic spacer layer and a free layer. The nonmagnetic spacer layer(s) are between the reference layer(s) and the free layer. The free layer has a magnetic thermal stability coefficient having a plurality of magnetic thermal stability coefficient phases. A first phase magnetic thermal stability coefficient has a first slope below a first temperature. A second phase magnetic thermal stability coefficient has a second slope above the first temperature and below a second temperature greater than the first temperature. The first and second slopes are unequal at the first temperature. The magnetic thermal stability coefficient is zero only above the second temperature. The free layer is switchable between stable magnetic states when a write current passed through the magnetic junction. | 10-15-2015 |
| 20150294708 | MULTIBIT SELF-REFERENCE THERMALLY ASSISTED MRAM - A mechanism is provided for a thermally assisted magnetoresistive random access memory device (TAS-MRAM). A storage layer has an anisotropic axis, in which the storage layer is configured to store a state in off axis positions and on axis positions. The off axis positions are not aligned with the anisotropic axis. A tunnel barrier is disposed on top of the storage layer. A ferromagnetic sense layer is disposed on top of the tunnel barrier. | 10-15-2015 |
| 20150302910 | MAGNETIC MEMORY - A magnetic memory according to an embodiment includes: a magnetic layer including a plurality of magnetic domains and a plurality of domain walls, and extending in a direction; a pinning layer formed with nonmagnetic phases and magnetic phases, extending in an extending direction of the magnetic layer and being located adjacent to the magnetic layer; an electrode layer located on the opposite side of the pinning layer from the magnetic layer; an insulating layer located between the pinning layer and the electrode layer; a current introducing unit flowing a shift current to the magnetic layer, the shift current causing the domain walls to shift; a write unit writing information into the magnetic layer; a read unit reading information from the magnetic layer; and a voltage generating unit generating a voltage to be applied between the pinning layer and the electrode layer. | 10-22-2015 |
| 20150302911 | MAGNETIC RANDOM ACCESS MEMORY (MRAM) CELL WITH LOW POWER CONSUMPTION - A magnetic random access memory (MRAM) cell including a magnetic tunnel junction containing: a storage layer including at least one storage ferromagnetic layer, each storage ferromagnetic layer having a storage magnetization; an antiferromagnetic storage layer pinning the storage magnetization at a low threshold temperature and freeing them at a high temperature threshold; a reference layer; and a tunnel barrier layer between the reference layer and the storage layer. The magnetic tunnel junction also includes a free ferromagnetic layer having a free magnetization adapted to induce a magnetic stray field magnetically coupling the free ferromagnetic layer with the storage layer; such that the storage magnetization can be switched by the magnetic stray field when the magnetic tunnel junction is at the high temperature threshold. The disclosed MRAM cell has low power consumption. | 10-22-2015 |
| 20150302912 | METHOD AND APPARATUS FOR GENERATING A REFERENCE FOR USE WITH A MAGNETIC TUNNEL JUNCTION - Methods and apparatus for generating a reference for use with a magnetic tunnel junction are provided. In an example, provided is a magnetoresistive read only memory including a magnetic tunnel junction (MTJ) storage element, a sense amplifier having a first input coupled to the MTJ storage element, and a reference resistance device coupled to a second input of the sense amplifier. The reference resistance device includes a plurality of groups of at least two reference MTJ devices. Each reference MTJ device in a respective group is coupled in parallel with each other reference MTJ device in the respective group. Each group is coupled in series with the other groups. This arrangement advantageously mitigates read disturbances and reference level variations, while saving power, reducing reference resistance device area, and increasing read speed. | 10-22-2015 |
| 20150310904 | SYSTEM AND METHOD OF CONCURRENT READ/WRITE MAGNETO-RESISTIVE MEMORY - In a memory having a first memory cell array, a second memory cell array, an address is received on an address port. Based on the address, an internal address is transmitted, and it is latched and held for a first interval as a first array address. The first memory cell array is accessed over the first interval, based on the first array address. Another address is received at the address port, during the first interval, and another internal address is transmitted, and latched and held for a second interval that overlaps the first interval, as a second array address. The second memory cell array is accessed during the second interval, based on the second array address. | 10-29-2015 |
| 20150318061 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes first word lines connected to a memory cell array, second word lines connected to a redundancy area, a first row decoder configured to perform selecting from the first word lines based on a row address, a judgment circuit configured to determine whether or not a replacement operation with the redundancy area is needed based on a redundancy address included in the row address, and a second row decoder configured to perform selecting from the second word lines. The row address includes a first row address and a second row address input in order in a time-sharing method. The first row address includes all of the redundancy address. | 11-05-2015 |
| 20150325278 | VOLTAGE-CONTROLLED SOLID-STATE MAGNETIC DEVICES - Systems, methods, and apparatus are provided for tuning a functional property of a device. The device includes a layer of a dielectric material disposed over and forming an interface with a layer of an electrically conductive material. The dielectric material layer includes at least one ionic species having a high ion mobility. The electrically conductive material is configured such that a potential difference applied to the device can cause the at least one ionic species to migrate reversibly across the interface into or out of the electrically conductive material layer. | 11-12-2015 |
| 20150325279 | High-Speed Compare Operation Using Magnetic Tunnel Junction Elements Including Two Different Anti-Ferromagnetic Layers - A match-in-place-type compare operation utilizes a string of Magnetic Tunnel Junction (MTJ) elements including storage layers and sense layers having different anti-ferromagnetic structures respectively having higher and lower blocking temperatures. Confidential data is written into the storage layers of the MTJ elements by heating the elements above the higher blocking temperature, and then orienting the storage and sense layers in first storage magnetization directions using field lines. The elements are then cooled to an intermediate temperature between the higher and lower blocking temperatures, and the field lines are turned off, setting the sense layers to preliminary storage magnetization directions opposite to the first directions. During a pre-compare phase, an input logic pattern is written into the sense layers by heating to the intermediate temperature. During a compare operation, with the field lines turned off, resistance of the MTJ string is detected by passing a read current through the string. | 11-12-2015 |
| 20150325280 | NON-VOLATILE MEMORY VALIDITY - An embodiment provides a method, including: reading validity timing information written to a non-volatile memory device; and determining validity of the non-volatile memory device using the validity timing information read from the non-volatile memory device. Other aspects are described and claimed. | 11-12-2015 |
| 20150332748 | VOLTAGE-SWITCHED MAGNETIC RANDOM ACCESS MEMORY (MRAM) AND METHOD FOR USING THE SAME - The present invention is directed to a magnetic random access memory comprising a first magnetic tunnel junction (MTJ) including a first magnetic reference layer and a first magnetic free layer with a first insulating tunnel junction layer interposed therebetween; a second MTJ including a second magnetic reference layer and a second magnetic free layer with a second insulating tunnel junction layer interposed therebetween; and an anti-ferromagnetic coupling layer formed between the first and second variable magnetic free layers. The first and second magnetic free layers have a first and second magnetization directions, respectively, that are perpendicular to the layer planes thereof. The first magnetic reference layer has a first pseudo-fixed magnetization direction substantially perpendicular to the layer plane thereof. The second magnetic reference layer has a second pseudo-fixed magnetization direction that is substantially perpendicular to the layer plane thereof and is substantially opposite to the first pseudo-fixed magnetization direction. | 11-19-2015 |
| 20150332749 | VOLTAGE-CONTROLLED MAGNETIC ANISOTROPY (VCMA) SWITCH AND MAGNETO-ELECTRIC MEMORY (MERAM) - Voltage controlled magnetic tunnel junctions and memory devices are described which provide efficient high speed switching of non-volatile magnetic devices at high cell densities. Implementations are described which provide a wide range of voltage control alternatives with in-plane and perpendicular magnetization, bidirectionally switched magnetization, and control of domain wall dynamics. | 11-19-2015 |
| 20150332750 | HYBRID MAGNETORESISTIVE READ ONLY MEMORY (MRAM) CACHE MIXING SINGLE-ENDED AND DIFFERENTIAL SENSING - A hybrid cache architecture uses magnetoresistive random-access memory (MRAM) caches but has two different types of bit cell sensing. One type of bit cell sensing is single-ended and the other type of bit cell sensing is differential. The result is a uniform bit cell array but a non-uniform sense amplifier configuration. | 11-19-2015 |
| 20150348606 | SPIN HALL EFFECT MAGNETIC APPARATUS, METHOD AND APPLICATIONS - An ST-MRAM structure, a method for fabricating the ST-MRAM structure and a method for operating an ST-MRAM device that results from the ST-MRAM structure each utilize a spin Hall effect base layer that contacts a magnetic free layer and effects a magnetic moment switching within the magnetic free layer as a result of a lateral switching current within the spin Hall effect base layer. This resulting ST-MRAM device uses an independent sense current and sense voltage through a magnetoresistive stack that includes a pinned layer, a non-magnetic spacer layer and the magnetic free layer which contacts the spin Hall effect base layer. Desirable non-magnetic conductor materials for the spin Hall effect base layer include certain types of tantalum materials and tungsten materials that have a spin diffusion length no greater than about five times the thickness of the spin Hall effect base layer and a spin Hall angle at least about 0.05. | 12-03-2015 |
| 20150348607 | SELF-REFERENCED MAGNETIC RANDOM ACCESS MEMORY (MRAM) AND METHOD FOR WRITING TO THE MRAM CELL WITH INCREASED RELIABILITY AND REDUCED POWER CONSUMPTION - MRAM cell including a magnetic tunnel junction including a sense layer, a storage layer, a tunnel barrier layer and an antiferromagnetic layer exchange-coupling the storage layer such that the storage magnetization can be pinned when the antiferromagnetic layer is below a critical temperature and freely varied when the antiferromagnetic layer is heated at or above the critical temperature. The sense layer is arranged such that the sense magnetization can be switched from a first stable direction to another stable direction opposed to the first direction. The switched sense magnetization generates a sense stray field being large enough for switching the storage magnetization according to the switched sense magnetization, when the magnetic tunnel junction is heated at the writing temperature. The disclosure also relates to a method for writing to the MRAM cell with increased reliability and reduced power consumption. | 12-03-2015 |
| 20150357014 | MRAM ELEMENT WITH LOW WRITING TEMPERATURE - MRAM element having a magnetic tunnel junction including a reference layer, a storage layer, a tunnel barrier layer between the reference and storage layers, and a storage antiferromagnetic layer. The storage antiferromagnetic layer has a first function of exchange-coupling a storage magnetization of the storage layer and a second function of heating the magnetic tunnel junction when a heating current in passed in the magnetic tunnel junction. The MRAM element has better data retention and low writing temperature. | 12-10-2015 |
| 20150357015 | Current Induced Spin-Momentum Transfer Stack With Dual Insulating Layers - A high speed, low power method to control and switch the magnetization direction of a magnetic region in a magnetic device for memory cells using spin polarized electrical current. The magnetic device comprises a pinned magnetic layer, a reference magnetic layer with a fixed magnetization direction and a free magnetic layer with a changeable magnetization direction. The magnetic layers are separated by insulating non-magnetic layers. A current can be applied to the device to induce a torque that alters the magnetic state of the device so that it can act as a magnetic memory for writing information. The resistance, which depends on the magnetic state of the device, can be measured to read out the information stored in the device. | 12-10-2015 |
| 20150357016 | RESISTIVE CHANGE MEMORY - A resistive change memory according to an embodiment includes: a memory cell including a resistive change element comprising a first and second terminals, and a semiconductor element, the semiconductor element including a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type, and a third semiconductor layer of a second conductivity type that is different from the first conductivity type, the third semiconductor layer being disposed between the first semiconductor layer and the second semiconductor layer, the first semiconductor layer being connected to the second terminal of the resistive change element; and a read unit configured to perform a read operation by applying a first read voltage between the first terminal and the second semiconductor layer, and then applying a second read voltage that is lower than the first read voltage between the first terminal and the second semiconductor layer. | 12-10-2015 |
| 20150371695 | ELECTRONIC MEMORY INCLUDING ROM AND RAM - An electronic data-storage apparatus having ROM embedded in an STT-MRAM. The apparatus comprises at least two bit lines, a plurality of bit cells, each including, connected to a source line (SL), a series connection (in any order) of a selection element (e.g., transistor gated by word line WL), a resistive storage element (e.g., MTJ), and a permanent connection to one of the bit lines (e.g., BL | 12-24-2015 |
| 20150371697 | Magnetoresistive Device and a Writing Method for a Magnetoresistive Device - According to embodiments of the present invention, a magnetoresistive device is provided. The magnetoresistive device includes at least two ferromagnetic soft layers, wherein the at least two ferromagnetic soft layers have different ranges of magnetization switching frequencies. Further embodiments provide a magnetoresistive device including at least two oscillating ferromagnetic structures, wherein ranges of operating current amplitudes at which oscillations are induced for the at least two oscillating ferromagnetic structures are different. According to further embodiments of the present invention, writing methods for the magnetoresistive devices are provided. | 12-24-2015 |
| 20160005450 | DATA HOLDING CIRCUIT AND DATA RECOVERY METHOD - A data holding circuit includes: a latch circuit having a first terminal and a second terminal, a logical value held at the first terminal being changed according to a value to be held by the data holding circuit, and the second terminal holding an inverted logical value of the logical value held at the first terminal; and a storing circuit which stores the logical values held at the first terminal and the second terminal in response to a write signal, and sets the logical values held at the first terminal and the second terminal to the stored logical values in response to a read signal, wherein the storing circuit includes two Magnetic Tunnel Junction elements which are connected in series between the first terminal and the second terminal and in reverse directions to each other. | 01-07-2016 |
| 20160012874 | SELF-REFERENCED MRAM CELL THAT CAN BE READ WITH REDUCED POWER CONSUMPTION | 01-14-2016 |
| 20160012875 | SEMICONDUCTOR MEMORY DEVICE | 01-14-2016 |
| 20160013793 | ELECTRONIC DEVICE | 01-14-2016 |
| 20160019941 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: banks each including a memory cell array; word lines connected to rows of each of the banks; an address latch circuit configured to latch a full address for specifying one of the word lines, the full address including a first address and a second address; and a control circuit configured to ignore a reset operation for the first address as a target of a set operation, and overwrite the first address in accordance with the set operation when receiving a first command for specifying a reset operation for a bank and a set operation for the first address. | 01-21-2016 |
| 20160019942 | MAGNETIC RANDOM ACCESS MEMORY - According to one embodiment, a magnetic random access memory includes a write circuit to write complementary data to first and second magnetoresistive elements, and a read circuit to read the complementary data from the first and second magnetoresistive elements. The control circuit is configured to change the first and second bit lines to a floating state after setting the first and second bit lines to a first potential, and change a potential of the first bit line in the floating state to a first value in accordance with a resistance value of the first magnetoresistive element and a potential of the second bit line in the floating state to a second value in accordance with a resistance value of the second magnetoresistive element by setting the common source line to a second potential higher than the first potential. | 01-21-2016 |
| 20160019943 | METHOD AND APPARATUS FOR MRAM SENSE REFERENCE TRIMMING - A trimming process for setting a reference current used in operating an MRAM module comprising an operational MRAM cell coupled to a bit line, multiple reference MRAM cells coupled to a reference bit line, and a sense amplifier coupled to the bit line and the reference bit line is disclosed in some embodiments. The process includes applying a bit line reference voltage to the reference bit line to provide a reference cell current formed by a sum of respective currents through the plurality of reference MRAM cells. The reference cell current is detected. A determination is made as to whether the detected reference cell current differs from a target reference cell current. The bit line reference voltage is varied, or a sensing ratio of the sense amplifier is varied, if it is determined that the detected reference cell current differs from the target reference cell current. | 01-21-2016 |
| 20160020250 | SWITCHING FILM STRUCTURE FOR MAGNETIC RANDOM ACCESS MEMORY (MRAM) CELL - An MRAM cell may include a magnetic tunneling junction (MTJ). The MTJ includes a pin layer, a barrier layer, a free layer, and a capping layer. The MRAM cell further includes a bidirectional diode selector, directly coupled to an electrode of the MTJ, to enable access to the MTJ. | 01-21-2016 |
| 20160027489 | HYBRID READ SCHEME FOR SPIN TORQUE MRAM - A method of reading data from a plurality of bits in a spin-torque magnetoresistive memory array includes performing one or more referenced read operations of the bits, and performing a self-referenced read operation, for example, a destructive self-referenced read operation, of any of the bits not successfully read by the referenced read operation. The referenced read operations can be initiated at the same time or prior to that of the destructive self-referenced read operation. | 01-28-2016 |
| 20160035401 | PRECESSIONAL MAGNETIZATION REVERSAL IN A MAGNETIC TUNNEL JUNCTION WITH A PERPENDICULAR POLARIZER - A magnetic device that includes a perpendicular magnetized polarizing layer configured to provide a first spin-torque and an in-plane magnetized free layer having a magnetization vector having at least a first stable state and a second stable state. The magnetic device also includes a reference layer configured to provide a second spin-torque. The first spin-torque and the second spin-torque can combine. The in-plane magnetized free layer and the reference layer form a magnetic tunnel junction and the combined first spin-torque and second spin-torque influences the magnetic state of the in-plane magnetized free layer. An application of a voltage pulse, having either positive or negative polarity and a selected amplitude and duration, through the magnetic device causes the magnetization vector to oscillate between the first stable state and the second stable state for a portion of the duration regardless of an initial state of the magnetization vector. | 02-04-2016 |
| 20160035403 | VOLTAGE GENERATOR AND MEMORY DEVICE INCLUDING THE SAME - A voltage generator comprises a reference voltage providing unit, a comparison voltage providing unit and a comparison unit. The reference voltage providing unit comprises a reference element and a current source series-connected between a power supply voltage and a ground voltage, and outputs a reference voltage through a reference voltage node, which couples the reference element to the current source. The comparison voltage providing unit comprises a magnetic tunnel junction unit coupled between the power supply voltage and a comparison voltage node, and a transistor switch unit coupled between the ground voltage and the comparison voltage node. The comparison unit provides a write voltage to the transistor switch unit by comparing the reference voltage and the comparison voltage. The voltage generator according to example embodiments may increase the performance of the memory device by performing the write operation using stable multi voltages that are applied to a word line. | 02-04-2016 |
| 20160035404 | MAGNETIC RAM ARRAY ARCHITECTURE - A magnetic random access memory (MRAM) array including: a plurality of MRAM cells arranged in an array configuration, each comprising a first type nTron and a magnetic memory element; a wordline select circuit comprising of a second type nTron to drive a plurality of parallel wordlines; and a plurality of bitline select circuits, each comprising of said second type nTron for writing to and reading from a column of memory cells in the array and each capable of selecting a single MRAM cell for a memory read or write operation, wherein the second nTron has a higher current drive than the first nTron. | 02-04-2016 |
| 20160042780 | CIRCUIT AND METHOD FOR CONTROLLING MRAM CELL BIAS VOLTAGES - A cell bias control circuit maximizes the performance of devices in the read/write path of memory cells (magnetic tunnel junction device+transistor) without exceeding leakage current or reliability limits by automatically adjusting multiple control inputs of the read/write path at the memory array according to predefined profiles over supply voltage, temperature, and process corner variations by applying any specific reference parameter profiles to the memory array. | 02-11-2016 |
| 20160049184 | HIGH CAPACIY LOW COST MULTI-STATE MAGNETIC MEMORY - One embodiment of the present invention includes a multi-state current-switching magnetic memory element includes a stack of two or more magnetic tunneling junctions (MTJs), each MTJ having a free layer and being separated from other MTJs in the stack by a seeding layer formed upon an isolation layer, the stack for storing more than one bit of information, wherein different levels of current applied to the memory element causes switching to different states. | 02-18-2016 |
| 20160049185 | DIFFERENTIAL MAGNETIC TUNNEL JUNCTION PAIR INCLUDING A SENSE LAYER WITH A HIGH COERCIVITY PORTION - An apparatus includes a first magnetic tunnel junction (MTJ) device of a differential MTJ pair. The apparatus further includes a second MTJ device of the differential MTJ pair. The first MTJ device includes a sense layer having a high coercivity portion. | 02-18-2016 |
| 20160049186 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, nonvolatile semiconductor memory device comprises: a memory mat including a memory cell having a variable resistance element; a write driver which applies a write current to the memory cell in one of a first direction and a second direction opposite to the first direction in write; and a read driver which applies a verify read current to the memory cell in one of the first direction and the second direction in verify read after write. | 02-18-2016 |
| 20160055891 | MAGNETIC MEMORY - According to one embodiment, a magnetic memory includes a memory cell array including magnetoresistive elements, a heater and a temperature sensor provided in the memory cell array, a heater driver which drives the heater, a temperature detector which detects a first temperature sensed by the temperature sensor, and a control circuit which controls the heater driver based on the first temperature. | 02-25-2016 |
| 20160055894 | REDUNDANT MAGNETIC TUNNEL JUNCTIONS IN MAGNETORESISTIVE MEMORY - Memory cells in a spin-torque magnetic random access memory (MRAM) include at least two magnetic tunnel junctions within each memory cell, where each memory cell only stores a single data bit of information. Access circuitry coupled to the memory cells are able to read from and write to a memory cell even when one of the magnetic tunnel junctions within the memory cell is defective and is no longer functional. Self-referenced and referenced reads can be used in conjunction with the multiple magnetic tunnel junction memory cells. In some embodiments, writing to the memory cell forces all magnetic tunnel junctions into a known state, whereas in other embodiments, a subset of the magnetic tunnel junctions are forced to a known state. | 02-25-2016 |
| 20160055895 | SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a semiconductor storage device includes a first storage area including a plurality of memory cells each including a resistance change element which stores data; a second storage area including a plurality of memory cells each including a resistance change element which stores data; a sub memory cell array including the first storage area and the second storage area: a memory cell array including a plurality of sub memory cell arrays arranged along a column direction and a row direction; a third storage area which stores redundancy information and to supply the redundancy information to the sub memory cell array; and a control circuit which controls an access operation to the memory cell array. | 02-25-2016 |
| 20160055951 | ELECTROMAGNET, TESTER AND METHOD OF MANUFACTURING MAGNETIC MEMORY - According to one embodiment, an electromagnet includes a first electromagnet coil having a first portion and a second portion. The first portion of the first electromagnet coil extends in a direction in parallel with a first plane. The second portion of the first electromagnet coil extends in a direction in parallel with a second plane. The first and second planes intersect at a predetermined angle. | 02-25-2016 |
| 20160064059 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device comprises a memory cell including a variable resistance element, a sense amplifier connected to one side of the memory cell, and a write driver connected to the other side of the memory cell. A write current flows between the sense amplifier and the write driver in a write operation. | 03-03-2016 |
| 20160064060 | METHOD OF FORMING A MAGNETIC DOMAIN WALL IN A NANOWIRE - A method of forming a domain wall in a nanowire, the method comprising the steps of: a) providing a conductive strip orthogonally to a nanowire adjacent a free end of the nanowire, the nanowire having an original magnetization direction; b) pulsing a current through the conductive strip to generate an Oersted field having a direction opposite to the original magnetization direction such that magnetization direction of a portion of the nanowire transversed by the conductive strip becomes opposite to the original magnetization direction, the domain wall being generated in the nanowire at a location defined between the portion of the nanowire transversed by the conductive strip and a second end of the nanowire, wherein no external magnetic field is provided during formation of the domain wall. | 03-03-2016 |
| 20160064061 | SEMICONDUCTOR MEMORY, MEMORY SYSTEM AND METHOD OF CONTROLLING SEMICONDUCTOR MEMORY - According to one embodiment, a semiconductor memory includes a memory area; an error detection circuit which detect an error of first data output from the memory area; and a control circuit which control the memory area and the error detection circuit. When the error is detected in the first data, the control circuit starts precharge of a bit line at a timing when a first period has elapsed from a start of a first operation of the memory area for output of the first data. When the error is not detected in the first data, the control circuit starts the precharge at a timing when a second period has elapsed from the start of the first operation, the second period is shorter than the first period. | 03-03-2016 |
| 20160071568 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first pad which outputs data to the outside; an output driver coupled to the first pad; a calibration circuit which adjusts impedance of the output driver; and a controller. The controller controls a calibration operation by the calibration circuit, in response to a first command received from the outside, and performs a write operation on a mode resister, in response to a second command received from the outside, the second command being different from the first command. | 03-10-2016 |
| 20160071587 | C-ELEMENT WITH NON-VOLATILE BACK-UP - The invention concerns a circuit comprising: a C-element having first and second input nodes and first and second inverters ( | 03-10-2016 |
| 20160078912 | STT-MRAM CELL STRUCTURE INCORPORATING PIEZOELECTRIC STRESS MATERIAL - A magnetic memory cell including a piezoelectric material, and methods of operating the memory cell are provided. The memory cell includes a stack, and the piezoelectric material may be formed as a layer in the stack or adjacent the layers of the cell stack. The piezoelectric material may be used to induce a transient stress during programming of the memory cell to reduce the critical switching current of the memory cell. | 03-17-2016 |
| 20160078914 | STT-MRAM SENSING TECHNIQUE - Embodiments are directed to a system for sensing a data state of a selected memory cell. The system includes a first reference cell, a sample-and-hold sense amplifier and a switching system. During a first sensing phase the switching system is configured to open a first series communication path that places the selected memory cell in series with the first reference cell, thereby creating a first series voltage divider. During the first sensing phase, the switching system is further configured to open a first branch communication path that taps an input of the sample-and-hold sense amplifier into a first divided voltage between the selected memory cell and the first reference cell. | 03-17-2016 |
| 20160078915 | RESISTANCE CHANGE MEMORY - According to one embodiment, according to one embodiment, a resistance change memory includes a memory cell, a sense amplifier, a control circuit and a storage unit. The memory cell includes a resistance change element. The sense amplifier compares a reference current with a cell current flowing through the memory cell. The control circuit calculates offset information of the reference current. The storage unit is provided for the sense amplifier and stores the offset information. The storage unit corresponds to the sense amplifier one to one. | 03-17-2016 |
| 20160078916 | FAST PROGRAMMING OF MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A method of programming a MTJ includes selecting a MTJ that is coupled to an access transistor at the drain of the access transistor. The gate of the access transistor is coupled to a selected word line (WL), the selected WL is substantially at a first voltage, Vdd; whereas the WLs that are not coupled to the MTJ are left to float. A second voltage, Vx, is applied to the unselected bit lines (BLs) and further applied to a source line (SL), the SL being coupled to the source of the access transistor. A third voltage, Vdd or 0 Volts, is applied to a selected BL, the selected BL is coupled the MTJ. The first voltage is applied to a SL, the SL is coupled to the source of the access transistor thereby causing the WL to boot above the first voltage. | 03-17-2016 |
| 20160086646 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device according to the present embodiment includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells corresponding to intersections between the bit lines and the word lines, respectively, and including magnetic tunnel junction elements capable of storing data. A plurality of sense amplifiers respectively correspond to the bit lines and are configured to detect data stored in the memory cells via a bit line selected from among the corresponding bit lines. A plurality of read latch parts correspond to the sense amplifiers, respectively, and are configured to latch data detected by the corresponding sense amplifiers. A plurality of read global data buses are connected to the read latch parts, respectively, and are configured to consecutively transmit data latched by the read latch parts at a time of a data read operation. | 03-24-2016 |
| 20160087631 | MAGNETIC LOGIC DEVICE, MAGNETIC LOGIC CIRCUIT, AND MAGNETIC MEMORY - One embodiment provides a magnetic logic device including: a first conductive thin wire; a second conductive thin wire; and a third conductive thin wire that electrically connects the first conductive thin wire and the second conductive thin wire. The first to third conductive thin wires commonly includes: a first non-magnetic metal layer; a second non-magnetic metal layer; and a magnetic metal layer sandwiched between the first non-magnetic metal layer and the second non-magnetic metal layer. | 03-24-2016 |
| 20160093349 | WRITE VERIFY PROGRAMMING OF A MEMORY DEVICE - A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state. | 03-31-2016 |
| 20160093350 | LATCH OFFSET CANCELATION SENSE AMPLIFIER - Systems and methods relate to operations on a magnetoresistive random access memory (MRAM) bit cell using a circuit configured in multiple phases. In a sensing circuit phase, the circuit configured to determine a first differential voltage between a data voltage across the bit cell and a reference voltage. In a pre-amplifying phase, the circuit is configured to pre-amplify the first differential voltage to generate a pre-amplified differential voltage, which does not have offset voltages that may arise due to process variations. In a sense amplifier phase, the circuit is configured to amplify the pre-amplified differential voltage in a latch. Generation of the pre-amplified differential voltage cancels offset voltages which may arise in the latch. In a write phase, the circuit is further configured to write a write data value to the MRAM bit cell. | 03-31-2016 |
| 20160093351 | CONSTANT SENSING CURRENT FOR READING RESISTIVE MEMORY - Systems and methods relate to providing a constant sensing current for reading a resistive memory element. A load voltage generator provides a load voltage based on a current mirror configured to supply a constant current that is invariant with process-voltage-temperature variations. A data voltage is generated based on the generated load voltage, by passing a sensing current mirrored from the constant current, through the resistive memory element. A reference voltage is generated, also based on the generated load voltage and by passing reference current mirrored from the constant current, through reference cells. A logical value stored in the resistive memory element is determined based on a comparison of the data voltage and the reference voltage, where the determination is free from effects of process-voltage-temperature variations. | 03-31-2016 |
| 20160093352 | REFERENCE VOLTAGE GENERATION FOR SENSING RESISTIVE MEMORY - Systems and methods relate to providing a correct reference voltage for reading a resistive memory element such as a magnetoresistive random access memory (MRAM) bit cell. Two or more reference voltages are provided for each MRAM bit cell and a correct reference voltage is selected from the two or more reference voltages for reading the MRAM bit cell. The correct reference voltage meets sensing margin requirements for reading the MRAM bit cell and overcomes non-idealities and offset voltages in read circuitry for reading the MRAM bit cell. An indication of the correct reference voltage is stored in a non-volatile latch or other non-volatile programmable memory and provided to the read circuitry. | 03-31-2016 |
| 20160093353 | DUAL STAGE SENSING CURRENT WITH REDUCED PULSE WIDTH FOR READING RESISTIVE MEMORY - Systems and methods for reducing a probability of read disturbance during a read operation on a resistive memory bit cell include a dual stage sensing scheme, which is used to reduce pulse widths of sensing currents for reading the resistive memory bit cell. During a first stage of the read operation on the resistive memory bit cell, a first sensing current is passed in a first direction through the resistive memory bit cell, and during a second stage of the read operation, a second sensing current is passed in an opposite, second direction through the resistive memory bit cell. Durations of the first and second stages are each equal to half of the duration of the read operation, which reduces pulse width of the first and second sensing currents. Probability of read disturbance occurring is limited to at most one of the first or second stages. | 03-31-2016 |
| 20160093355 | MAGNETIC FIELD-ASSISTED MEMORY OPERATION - In one embodiment, a magnetoresistance random access memory (MRAM) such as a spin transfer torque (STT) random access memory (RAM), for example, has a subarray of bitcells and an electro-magnet positioned adjacent the subarray. A magnetic field is directed through a ferromagnetic device of bitcells of the first subarray to assist in the changing of states of bitcells of the subarray from a first state to a second state in which the ferromagnetic device of the bitcell is changed from one of parallel and anti-parallel polarization to the other of parallel and anti-parallel polarization. Accordingly, the content of the subarray may be readily preset or erased to one of the parallel or anti-parallel state with assistance from an electro-magnet. | 03-31-2016 |
| 20160099036 | Magnetic Tunnel Junction Memory Device - A magnetic-assist, spin-torque transfer magnetic tunnel junction device and a method for performing a magnetic-assist, spin-torque-transfer write to the device are disclosed. In an exemplary embodiment, the magnetic tunnel junction device includes a first electrode, a pinned layer disposed on the first electrode, a free layer disposed on the pinned layer, and a barrier layer disposed between the pinned layer and the free layer. The device further includes a second electrode electrically coupled to the free layer, the second electrode containing a magnetic assist region. In some embodiments, the magnetic assist region is configured to produce a net magnetic field when supplied with a write current. The net magnetic field is aligned to assist a spin-torque transfer of the write current on the free layer. | 04-07-2016 |
| 20160099037 | MEMORY DEVICE WITH DIFFERENTIAL BIT CELLS - In some examples, a memory device may be configured to utilize differential bit cells formed from two or more tunnel junctions. In some cases, the tunnel junctions forming the differential bit cell may be arranged to utilize shared read circuitry to reduce device mismatch. For instance, the read operations associated with both tunnel junction may be time multiplexed such that the same preamplifier circuitry may sense voltages representative of the tunnel junctions. | 04-07-2016 |
| 20160099038 | MEMORY DEVICE WITH SHARED READ/WRITE CIRCUITRY - In some examples, a memory device may be configured to read or write multiple bit cells as part of the same operation. In some cases, the tunnel junctions forming the bit cells may be arranged to utilize shared read/write circuitry. For instance, the tunnel junctions may be arranged such that both tunnel junctions may be written using the same write voltages. In some cases, the bit cells may be configured such that each bit cell is driven to the same state, while in other cases, select bit cells may be driven high, while others are driven low. | 04-07-2016 |
| 20160099039 | METHOD OF WRITING TO A SPIN TORQUE MAGNETIC RANDOM ACCESS MEMORY - A spin-torque magnetoresistive memory includes array read circuits and array write circuits coupled to an array of magnetic bits. The array read circuits sample magnetic bits in the array, apply a write current pulse to the magnetic bits to set them to a first logic state, resample the magnetic bits, and comparing the results of sampling and resampling to determine the bit state for each magnetic bit. For each of the magnetic bits in the page having the second logic state, the array write circuits initiate a write-back, wherein the write-back includes applying a second write current pulse having opposite polarity in comparison with the first write current pulse to set the magnetic bit to the second state. A read or write operation may be received after initiation of the write-back where the write-back can be aborted for a portion of the bits in the case of a write operation. The write-back may be performed such that different portions of the magnetic bits are written back at different times, thereby staggering the write-back current pulses in time. An offset current may also be used during resampling. | 04-07-2016 |
| 20160099040 | SELF-REFERENCED SENSE AMPLIFIER FOR SPIN TORQUE MRAM - Circuitry and a method provide a plurality of timed control and bias voltages to sense amplifiers and write drivers of a spin-torque magnetoresistive random access memory array for improved power supply noise rejection, increased sensing speed with immunity for bank-to-bank noise coupling, and reduced leakage from off word line select devices in an active column. | 04-07-2016 |
| 20160104519 | HIGH TEMPERATURE DATA RETENTION IN MAGNETORESISTIVE RANDOM ACCESS MEMORY - Techniques and circuits for storing and retrieving data using spin-torque magnetic memory cells as anti-fuses are presented. Circuits are included to allow higher-magnitude voltages and currents to be applied to magnetic memory cells to intentionally break down the dielectric layer included the magnetic tunnel junction. Magnetic memory cells having a normal-resistance magnetic tunnel junction with an intact dielectric layer are used to store a first data state, and magnetic memory cells having a magnetic tunnel junction with a broken-down dielectric layer are used to store a second data state. Data can be stored in such a manner during wafer probe and then later read out directly or copied into other magnetic or non-magnetic memory on the device for use in operations after the device is included in a system. | 04-14-2016 |
| 20160118098 | MAGNETIC MEMORY - A magnetic memory according to an embodiment includes at least one MTJ element, the MTJ element including: a magnetic multilayer structure including a first magnetic layer in which a direction of magnetization is fixed, a second magnetic layer in which a direction of magnetization is changeable, and a tunnel barrier layer located between the first and second magnetic layers; a first electrode provided on a first surface of the magnetic multilayer structure; a second electrode provided on a second surface of the magnetic multilayer structure; an insulating film provided on a side surface of the magnetic multilayer structure; and a control electrode provided on the side surface of the magnetic multilayer structure with the insulating film located therebetween, a voltage being applied to the control electrode in a read operation, which increases an energy barrier for changing the magnetization of the second magnetic layer. | 04-28-2016 |
| 20160118099 | MAGNONIC HOLOGRAPHIC MEMORY AND METHODS - An electronic device using an array of magnetic wave guides is shown. In one example a memory device is shown that utilizes spin waves and a magnet storage element that interacts with the spin waves. In one example, an electronic device is shown that utilizes both a complementary metal oxide device and a magnonic device coupled together. | 04-28-2016 |
| 20160118100 | DIFFERENTIAL CURRENT SENSING SCHEME FOR MAGNETIC RANDOM ACCESS MEMORY - A circuit includes first and second reference cells and a current sense amplifier. The first and second reference cells are configured to store opposite logic values, respectively. The current sense amplifier is configured with a first node and a second node for currents therethrough to be compared with each other. The current sense amplifier includes a multiplexer configured to couple the first reference cell or the second reference cell to the first node of the current sense amplifier, and couple the second reference cell or the first reference cell to the second node of the current sense amplifier for reading bits stored in the first reference cell and the second reference cell. | 04-28-2016 |
| 20160118101 | APPARATUSES AND METHODS FOR SETTING A SIGNAL IN VARIABLE RESISTANCE MEMORY - An example of a method reads a spin torque transfer (STT) memory cell, and writes the STT memory cell using information obtained during the reading of the STT memory cell to set a pulse to write the STT memory cell. An example of an apparatus includes a STT memory cell and read/write circuitry coupled to the STT memory cell to determine a read current (I | 04-28-2016 |
| 20160118102 | METHOD AND APPARATUS FOR WRITING TO A MAGNETIC TUNNEL JUNCTION (MTJ) BY APPLYING INCREMENTALLY INCREASING VOLTAGE LEVEL - A method of writing to magnetic tunnel junctions (MTJs) of a magnetic memory array includes storing in-coming data in a cache register, reading the present logic state of a first one of a set of at least two MTJs, the set of at least two MTJs including the first MTJ and a second MTJ. The in-coming data is to be written into the second MTJ. Further steps are storing the read logic state into a data register, swapping the contents of the data register and the cache register so that the cache register stores the read logic state and the data register stores the in-coming data, applying a first predetermined voltage level to the set of MTJs thereby causing the first MTJ to be over-written, applying a second predetermined voltage level to the set of MTJs, and storing the in-coming data into the second MTJ. | 04-28-2016 |
| 20160125924 | MAGNETO-RESISTIVE DEVICES - Magneto-resistive devices with lower power consumption and higher stability are provided. The magneto-resistive devices may include a pinned layer, a free layer and an insulating layer between the pinned layer and the free layer. The pinned layer, the free layer and the insulating layer may constitute a magnetic tunnel junction. The free layer may include a first magnetic layer and a second magnetic layer that has a Curie temperature lower than a Curie temperature of the first magnetic layer. | 05-05-2016 |
| 20160125925 | ENERGY EFFICIENT THREE-TERMINAL VOLTAGE CONTROLLED MEMORY CELL - Memory cell, method for operating the memory cell and method for fabricating the memory cell are disclosed. The memory cell includes at least three terminals, a first magnetic tunnel junction (MTJ) structure and a second MTJ structure. The first MTJ is coupled between a first terminal (FT) and a third terminal. A portion of the first MTJ is configured to include a first barrier layer disposed between a first fixed layer and a free layer (FL). A magnetization direction of the FL is used to store data, the magnetization direction being controlled by an electric field. The second MTJ is coupled between the FT and a second terminal, where a portion of the second MTJ is configured to include a second barrier layer disposed between a second fixed layer and the FL, where a tunnel magnetoresistance of the second barrier layer is used to read the data. | 05-05-2016 |
| 20160125926 | SYSTEM AND METHOD TO TRIM REFERENCE LEVELS IN A RESISTIVE MEMORY - A method includes, at a resistive memory device, determining an average effective reference resistance level based on a first effective reference resistance and a second effective reference resistance. The first effective reference resistance is based on a first set of reference cells of the resistive memory device and the second effective reference resistance is based on a second set of reference cells of the resistive memory device. The method includes trimming a reference resistance at least partially based on the average effective reference resistance level. Trimming the reference resistance includes, in response to determining that the first effective reference resistance is not substantially equal to the average effective reference resistance level, modifying one or more states of one or more magnetic tunnel junction devices associated with the first effective reference resistance. | 05-05-2016 |
| 20160125928 | BITCELL WTH MAGNETIC SWITCHING ELEMENTS - A method includes receiving a data bit value at a buffer in a bitcell based on a first state of a write bitline connected to the buffer, and transferring the data bit value from the buffer to a first magnetic switching cell in the bitcell for a later read operation at least by holding the write bitline to a reference value different from the first state, and asserting first and second predetermined voltage levels on respective first and second write wordlines connected to the buffer. | 05-05-2016 |
| 20160133308 | RESISTANCE CHANGE MEMORY - A resistance change memory includes a memory cell array comprising memory cells including magnetic tunnel junction (MTJ) elements; a write and read circuit which performs a write operation and a read operation for the memory cells; a temperature sensor which outputs temperature information corresponding to a temperature of the memory cell array; and a memory controller which controls the write operation and the read operation by the write and read circuit in response to the temperature information, such that a first time period from a write command input to a pre-charge command input is variable according to the temperature information, while a second time period from an active command input to the pre-charge command input is fixed constant regardless of the temperature information. | 05-12-2016 |
| 20160141333 | MAGNETO-ELASTIC NON-VOLATILE MULTIFERROIC LOGIC AND MEMORY WITH ULTRALOW ENERGY DISSIPATION - Memory cells, non-volatile logic gates, and combinations thereof have magneto-tunneling junctions (MTJs) which are switched using potential differences across a piezoelectric layer in elastic contact with a magnetostrictive nanomagnet of an MTJ. One or more pairs of electrodes are arranged about the MTJ for supplying voltage across the piezoelectric layer for switching. A permanent magnetic field may be employed to change the positions of the stable magnetic orientations of the magnetostrictive nanomagnet. Exemplary memory cells and universal non-volatile logic gates show dramatically improved performance characteristics, particularly with respect to energy dissipation and error-resilience, over existing methods and architectures for switching MTJs such as spin transfer torque (STT) techniques. | 05-19-2016 |
| 20160148665 | FERROMAGNETIC DEVICE PROVIDING HIGH DOMAIN WALL VELOCITIES - The invention is directed to a method of manufacturing a ferromagnetic device ( | 05-26-2016 |
| 20160148666 | MAGNETIC TUNNEL JUNCTION RESISTANCE COMPARISON BASED PHYSICAL UNCLONABLE FUNCTION - A method includes coupling a first magnetic tunnel junction (MTJ) element and a second MTJ element to a comparison circuit. The method also includes comparing, at the comparison circuit, a first resistance of the first MTJ element to a second resistance of the second MTJ element. The method further includes generating a first physical unclonable function (PUF) output bit based on a result of comparing the first resistance to the second resistance. | 05-26-2016 |
| 20160148667 | MAGNETIC RANDOM ACCESS MEMORY WITH DYNAMIC RANDOM ACCESS MEMORY (DRAM)-LIKE INTERFACE - A memory device includes a magnetic memory unit for storing a burst of data during a burst write operation. Each burst of data includes sequential data units with each data unit being received at a clock cycle, and written during the burst write operation, wherein the burst write operation is performed during multiple clock cycles. Further, the memory device includes a mask register coupled to the magnetic memory unit that generates a write mask during the burst write operation to inhibit or enable data units of write data. Furthermore, the memory device allows a next burst write operation to begin while receiving data units of the burst of data to be written or providing read data. | 05-26-2016 |
| 20160155485 | MAGNETIC DEVICE WITH SPIN POLARISATION | 06-02-2016 |
| 20160163371 | NON-DESTRUCTIVE WRITE/READ LEVELING - In some examples, a memory device is configured with non-volatile memory array(s) having one or more associated volatile memory arrays. The memory device may include a non-destructive write mode configured to prevent access to the non-volatile memory array(s) during an initiation or calibration sequence performed by the memory device or an electronic device associated with the memory device to calibrate read and write access timing associated with the memory device. | 06-09-2016 |
| 20160163966 | Spin Torque MRAM Based on Co, Ir Synthetic Antiferromagnetic Multilayer - Magnetic memory devices having an antiferromagnetic reference layer based on Co and Ir are provided. In one aspect, a magnetic memory device includes a reference magnetic layer having multiple Co-containing layers oriented in a stack, wherein adjacent Co-containing layers in the stack are separated by an Ir-containing layer such that the adjacent Co-containing layers in the stack are anti-parallel coupled by the Ir-containing layer therebetween; and a free magnetic layer separated from the reference magnetic layer by a barrier layer. A method of writing data to a magnetic random access memory device having at least one of the present magnetic memory cells is also provided. | 06-09-2016 |
| 20160172019 | BOOSTED SUPPLY VOLTAGE GENERATOR FOR A MEMORY DEVICE AND METHOD THEREFORE | 06-16-2016 |
| 20160180906 | MAGNETIC RECORDING APPARATUS | 06-23-2016 |
| 20160180907 | METHOD FOR COMPUTING WITH COMPLEMENTARY NETWORKS OF MAGNETIC TUNNEL JUNCTIONS | 06-23-2016 |
| 20160180909 | WRITE OPERATIONS IN SPIN TRANSFER TORQUE MEMORY | 06-23-2016 |
| 20160180910 | WORD LINE AUTO-BOOTING IN A SPIN-TORQUE MAGNETIC MEMORY HAVING LOCAL SOURCE LINES | 06-23-2016 |
| 20160180911 | METHOD OF WRITING TO A SPIN TORQUE MAGNETIC RANDOM ACCESS MEMORY | 06-23-2016 |
| 20160189761 | MEMORY CONTROL CIRCUIT AND CACHE MEMORY - A memory control circuit to control a first memory comprising a plurality of MRAM cells, each MRAM cell including of a magnetoresistive element to store data, has a second memory, when there is a read request to a first address of the first memory, to read data of a second address different from the first address, from the first memory and store the read data, a controller to control access to the first memory and the second memory, a capacitor connected in series to the magnetoresistive element, and a sense amplifier to sense a logic of the data from a voltage between both electrodes of the capacitor, the voltage varying in accordance with a current flowing through the magnetoresistive element. | 06-30-2016 |
| 20160196859 | METHOD AND SYSTEM FOR PROGRAMMING MAGNETIC JUNCTIONS UTILIZING HIGH FREQUENCY MAGNETIC OSCILLATIONS | 07-07-2016 |
| 20160196860 | ELECTRICALLY GATED THREE-TERMINAL CIRCUITS AND DEVICES BASED ON SPIN HALLTORQUE EFFECTS IN MAGNETIC NANOSTRUCTURES APPARATUS, METHODS ANDAPPLICATIONS | 07-07-2016 |
| 20160197263 | Systems and Methods for Implementing Efficient Magnetoelectric Junctions | 07-07-2016 |
| 20160203851 | ANTIFERROMAGNETIC STORAGE DEVICE | 07-14-2016 |
| 20160254040 | BOOSTED SUPPLY VOLTAGE GENERATOR AND METHOD THEREFORE | 09-01-2016 |
| 20160254042 | Method and Apparatus for Increasing the Reliability of an Access Transistor Coupled to a Magnetic Tunnel Junction (MTJ) | 09-01-2016 |
| 20160379698 | MAGNETIC MEMORY ELEMENT AND MEMORY DEVICE - According to one embodiment, a magnetic memory element includes a stacked structure. The stacked structure includes a first and a second stacked member. The first stacked member includes a first and second ferromagnetic layer. A magnetic resonance frequency of the second ferromagnetic layer is a first frequency. A direction of a magnetization of the second ferromagnetic layer is settable to a direction of a first current when a magnetic field of the first frequency is applied to the first stacked member and the first current flows in the first stacked member. The direction of the magnetization of the second ferromagnetic layer does not change when the second current smaller than the first current flows in the first stacked member. The second stacked member includes a third ferromagnetic layer. A magnetization of the third ferromagnetic layer can generate a magnetic field of the first frequency by the second current. | 12-29-2016 |
| 20160379699 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a first memory cell array including a first memory cell having a variable resistive element, a second memory cell array including a second memory cell having the variable resistive element, a reference signal generation circuit which generates a reference signal, a sense amplifier having a first input terminal and a second input terminal, and a read enable control circuit which generates a read enable signal in accordance with a command from outside and control switching between a single cell read mode and a twin cell read mode. | 12-29-2016 |
| 20160379700 | MAGNETIC STORAGE CELL MEMORY WITH BACK HOP-PREVENTION - An apparatus is described that includes a semiconductor chip memory array having resistive storage cells. The apparatus also includes a comparator to compare a first word to be written into the array against a second word stored in the array at the location targeted by a write operation that will write the first word into the array. The apparatus also includes circuitry to iteratively write to one or more bit locations where a difference exists between the first word and the second word with increasing write current intensity with each successive iteration. | 12-29-2016 |
| 20170236570 | CURRENT INDUCED SPIN-MOMENTUM TRANSFER STACK WITH DUAL INSULATING LAYERS | 08-17-2017 |
| 20170236867 | SEMICONDUCTOR DEVICE | 08-17-2017 |
| 20180025764 | MAGNETIC FIELD-ASSISTED MEMORY OPERATION | 01-25-2018 |
| 20180025765 | SEMICONDUCTOR DEVICE | 01-25-2018 |
| 20180026177 | ELECTROMAGNETIC CONVERSION DEVICE AND INFORMATION MEMORY COMPRISING THE SAME | 01-25-2018 |
| 20190147929 | SPIN CURRENT ASSISTED MAGNETORESISTANCE EFFECT DEVICE | 05-16-2019 |
| 20190147931 | SEMICONDUCTOR STORAGE DEVICE, DRIVING METHOD, AND ELECTRONIC DEVICE | 05-16-2019 |
| 20190147971 | SHORT DETECTION AND INVERSION | 05-16-2019 |
| 20190148625 | MAGNETIC RANDOM ACCESS MEMORY | 05-16-2019 |
