| Entries |
| Document | Title | Date |
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| 20080211560 | CLOCK GENERATOR AND ASSOCIATED SELF-TEST AND SWITCHING-CONTROL METHOD - A clock generator with extended tuning range and associated method is provided. The associated self-test and switching-control method includes steps of generating a primary clock signal by a phase-locked loop circuit; determining a frequency limit of the primary clock signal; and determining a frequency-dividing condition of the frequency-dividing module according to the frequency limit and the target frequency. | 09-04-2008 |
| 20080211561 | Clock Signal Generation Circuit and Semiconductor Device - The semiconductor device is provided with a clock signal generation circuit that includes a reference clock signal generation circuit which generates a first reference clock signal, a first counter circuit which counts the number of rising edges of the first reference clock signal by using the first reference clock signal and a synchronizing signal, a second counter circuit which counts the number of rising edges of the first reference clock signal by using an enumerated value of the first counter circuit, a first divider circuit which divides a frequency of the first reference clock signal by using the enumerated value of the first counter circuit and generates a second reference clock signal, and a second divider circuit which divides a frequency of the second reference clock signal and generates a clock signal. | 09-04-2008 |
| 20080231337 | Compact subnanosecond high voltage pulse generation system for cell electro-manipulation - Disclosed are methods and systems for subnanosecond rise time high voltage (HV) electric pulse delivery to biological loads. The system includes an imaging device and monitoring apparatus used for bio-photonic studies of pulse induced intracellular effects. The system further features custom fabricated microscope slide having micro-machined electrodes. A printed circuit board to interface the pulse generator to the micro-machined glass slide having the cell solution. An low-parasitic electronic setup to interface with avalanche transistor-switched pulse generation system. The pc-board and the slide are configured to match the output impedance of the pulse generator which minimizes reflection back into the pulse generator, and minimizes distortion of the pulse shape and pulse parameters. The pc-board further includes a high bandwidth voltage divider for real-time monitoring of pulses delivered to the cell solutions. | 09-25-2008 |
| 20080238517 | Oscillator Circuit and Semiconductor Device - An oscillator circuit includes a capacitance element; an inverter outputting an inverted voltage at a first terminal of the capacitance element; a voltage source including a resistor and an NMOS transistor connected in series between a first high-potential power supply and a ground power supply and outputting a voltage from a node to which the resistor and the NMOS transistor are connected; a switch circuit connecting a second terminal of the capacitance element to the voltage source or the ground power supply in accordance with the voltage output from the inverter; and a constant-current source connected to a second high-potential power supply and allowing, regardless of changes in the voltage and temperature of the second high-potential power supply within certain ranges, flow of a constant current into or out of the first terminal of the capacitance element in accordance with the voltage output from the inverter. | 10-02-2008 |
| 20080258792 | Digital Single Event Transient Hardened Register Using Adaptive Hold - By adjusting a register's capturing clock edge timing so that the register captures data when the data returns to a correct state, the register may be protected against DSET upsets. If a data glitch occurs near the clock edge, the valid time at the register output is increased (CLK to Q). This valid time increase occurs when the presence of a DSET transient is detected near the clock edge. | 10-23-2008 |
| 20080284482 | SEMICONDUCTOR CIRCUIT - A semiconductor circuit for an inverter device, comprising a pulse generator for generating a pulse signal upon receiving the input signal for controlling the high-voltage switching device of the inverter device, a driver circuit for driving the high-voltage switching device, and a signal transfer circuit for transferring the pulse signal generated by the pulse generator to the driver circuit, wherein a wide band-gap semiconductor device is used in the signal transfer circuit | 11-20-2008 |
| 20080297222 | Waveform generation apparatus, setup cycle correction method and semiconductor test apparatus - Spurious noise that occurs in the vicinity of a carrier can be removed even when a high-resolution cycle is set, thereby realizing low jitters in a high-precision variable clock signal. | 12-04-2008 |
| 20090009227 | High-Power Electric Pulse Generator - A high power electric pulse generator includes a charge storage device, a high voltage source for charging the charge storage device, a first photoconductor element connected to the reference potential and to the storage device, a second photoconductor element connected to the storage device and to a useful load, a first light source for delivering a pulse of light to the first photoconductor, a second light source for delivering a pulse of light to the second photoconductor and a synchronization device for synchronizing the emission delay between the first light source and the second light source. The first photoconductor and the second photoconductor are passive semiconductor elements with a linear regime forming photosensitive switches, with the first and second photoconductors being doped silicon photoconductors. | 01-08-2009 |
| 20090015309 | DATA OUTPUT CLOCK SIGNAL GENERATING APPARATUS AND SEMICONDUCTOR INTEGRATED CIRCUIT WITH THE SAME - A data clock control apparatus includes a bias voltage generator configured to receive a plurality of test mode signals and a plurality of fuse signals and to generate a bias voltage to secure a predetermined potential difference from an external driving power supply, and a clock signal controller configured to receive the bias voltage and to buffer an external clock signal and outputs a data output clock signal. | 01-15-2009 |
| 20090015310 | SEMICONDUCTOR DEVICE - A semiconductor device transfers first data to a circuit block. The semiconductor device is provided with a storage circuit configured to store the first data, a shift register configured to set the first data, a transfer circuit configured to transfer the first data from the shift register to the circuit block, a first input terminal configured to receive a first signal indicating the end of a transfer operation, a resetting signal-generating circuit configured to generate a resetting signal for resetting the shift register based on the first signal, a setting signal-generating circuit configured to generate a setting signal for setting the first data in the shift register again after the shift register is reset, and an output circuit configured to externally output the first data that has been set again. | 01-15-2009 |
| 20090051400 | SYSTEM AND METHOD FOR FULLY DIGITAL CLOCK DIVIDER WITH NON-INTEGER DIVISOR SUPPORT - A system and method that use a first clock to digitally generate a second clock, wherein the ratio of the frequency of the first clock to the frequency of the second clock is a non-integer. Circuitry may be used to ensure that the first clock, or input clock, has a frequency at least equal to the highest of the desired output frequencies. The input clock may be used to generate several output clocks with different frequencies. If one of the output clocks has the same frequency as the input clock, the circuitry can be bypassed. The different clocks may be used to drive parts of a system, each of which may require a different frequency. | 02-26-2009 |
| 20090058489 | Spread spectrum clock generator - A spread spectrum clock generator for sequentially modulating a source clock of a fixed frequency with a predetermined frequency range, including: a plurality of first loading units configured to delay clock edges of the source clock by a delay time corresponding to the number of unit delay steps determined by delay step control signals, wherein each of the first loading units comprises a plurality of second loading units each of which is configured to vary a delay value of each unit delay step by changing an inner interconnection configuration thereof in response to unit delay step control signals. | 03-05-2009 |
| 20090058490 | PULSE GENERATING CIRCUIT, ELECTRONIC DEVICE USING THIS PULSE GENERATING CIRCUIT, CELLULAR PHONE SET, PERSONAL COMPUTER, AND INFORMATION TRANSMITTING METHOD USING THIS CIRCUIT - A pulse generating circuit includes a plurality of delay elements cascaded so as to constitute a predetermined loop, wherein when a predetermined input pulse is supplied to a leading end of the series connection, an effective frequency multiplication is applied to signals which appear at a plurality of portions out of the node portions among the plurality of delay elements and the terminal end portion of the series connection by a logical circuit to obtain an output pulse having a higher frequency than the input pulse. | 03-05-2009 |
| 20090066391 | High voltage, high speed, high pulse repetition rate pulse generator - A high voltage, high speed, and high repetition rate pulse generator solves the high pulse repetition rate limitations associated with RF power amplifiers. The pulse generator employs resonant techniques to provide current limiting features that allow for continued high voltage, high speed, and high repetition pulse rate operation of the pulse generator without impairment of the pulse generator during both short circuit and open circuit load conditions. | 03-12-2009 |
| 20090072875 | Green Technologies: The Killer Application of EMI-Free On-Chip Inductor - The EMI-free planar inductor is the core technology of the green technology. The EMI-free planar inductor adopts the structure of the closed magnetic field flux IC inductor (CMFFICI). All the magnetic field being confined in a small volume. The magnetic field is parallel to the surface of the chip. The EMI-free planar inductor makes the on-chip LC tank having very high Q and saves a lot of energy. Combining with the gain-boost-Q technology, it makes the high performance Tales clock chip have the performance being comparable to the xtalchip. The xtalchip is the inductor being replaced with the crystal in the gain-boost Q resonator. Furthermore, the EMI-free planar inductor makes the highest power efficiency boost-buck converter and the on-chip spinning motor. It makes the PC laser TV projector being implementable. The PC laser TV projector is RGB full color for each pixel and having the fast object movement sensitivity and wide dynamic range for the light contrast. The PC laser TV projector can use any wall to be the display screen. | 03-19-2009 |
| 20090121766 | EXTERNALLY ASYNCHRONOUS INTERNALLY CLOCKED SYSTEM - An Externally Asynchronous-Internally Clocked (EAIC) system that generates an internal clock signal includes a clock signal control block. The clock signal control block includes a pull-up unit that is activated in response to an input signal used to generate an internal clock signal; a pull-down unit that is activated in response to the input signal used to generate an internal clock signal, and a bypass unit that is provided between the pull-up unit and the pull-down unit, and selectively provides a signal path to the pull-down unit if the pull-down unit is activated and a signal path from the pull-up unit if the pull-up unit is activated. | 05-14-2009 |
| 20090128212 | Charge pump systems with adjustable frequency control - An electronic system includes a charge pump driver for generating an output to control an electronic element. The electronic system further includes a clock generator coupled to the charge pump driver. The clock generator can generate a clock signal to control the charge pump driver and adjust a frequency of the clock signal according to a status of the electronic element. | 05-21-2009 |
| 20090146719 | Control Voltage Generator for a Clock, Frequency Reference, and Other Reference Signal Generator - Exemplary embodiments of the invention provide a reference signal generator, system and method. An exemplary apparatus to generate a harmonic reference signal includes a reference resonator, such as an LC-tank, a control voltage generator adapted to provide a temperature-dependent control voltage; and a plurality of variable reactance modules. The reference resonator generates a first reference signal having a resonant frequency, and each reactance module is adapted to modify a corresponding reactance in response to the control voltage to maintain the resonant frequency substantially constant or within a predetermined variance over a predetermined temperature range. A frequency controller may also be included to maintain substantially constant a magnitude of a peak amplitude of the first reference signal and maintains substantially constant a common mode voltage level of the reference resonator. | 06-11-2009 |
| 20090160521 | LOW VT DEPENDENCY RC OSCILLATOR - An oscillator utilizes two current sources that have the same temperature and VDD dependency so they generate the same current in changing conditions. Therefore, there is very low VT dependency. The resistor and fringe capacitor temperature coefficient are very low and opposite so they compensate for each other. A comparator with a short period of operation also minimizes VT dependency. | 06-25-2009 |
| 20090174454 | CLOCK CIRCUIT FOR A MICROPROCESSOR - A wireless communication device is described having a transmitter that generates electromagnetic interference when operating in a transmit mode. The wireless communication device comprises a clock circuit including a first clock element configured to generate a first clock output, and a second clock element configured to generate a second clock output. Also included is a controller configured to switch between the first clock output and the second clock output when the transmitter is operating in the transmit mode. | 07-09-2009 |
| 20090251188 | Clock driver and charge pump incluing the same - A clock driver capable of minimizing the ripple of an output signal of a charge pump, and the charge pump including the clock driver are disclosed. The clock driver that generates at least one control clock signal for controlling a pumping circuit, the clock driver includes: a first driver generating a first control clock signal by pulling up a first node, in response to a first reference clock signal and pulling down the first node in response to a second reference clock signal; and a second driver generating a second control clock signal by pulling up a second node in response to the second reference clock signal and pulling down the second node in response to the first reference clock signal; wherein the first driver comprises a first hysteresis controller that generates a first output signal having a time delay in response to the rising transition or the falling transition of the second reference clock signal so that the timing for a pulling down operation of the first node is delayed as compared to the timing for a pulling up operation of the second node. | 10-08-2009 |
| 20090256613 | PULSE SIGNAL GENERATING DEVICE, TRANSPORT DEVICE, IMAGE FORMING APPARATUS, AND PULSE GENERATING METHOD - A pulse signal generating device includes: an encoder that outputs a pulse with a period corresponding to the speed of an object to be detected; a measurement unit that measures a period of the pulse; a storage unit that stores the measured period; an operation unit that calculates a reasonable period, which is estimated to be statistically reasonable, on the basis of a result of period measurement of a plurality of pulses; a detection unit that detects period abnormalities when the measured period of the measurement unit satisfies a period abnormality condition specified from the reasonable period; and a pulse generating unit that generates a pulse on the basis of the measured period when the period abnormalities are not detected and generates a pulse on the basis of the reasonable period when the period abnormalities are detected. | 10-15-2009 |
| 20090256614 | Apparatus and Method for Generating Clock Signal - The invention is related to an apparatus and a method for generating an output clock. The method comprises: receiving a transmitted signal comprising at least one data signal and at least one synchronized signal; producing a reference signal according to the synchronization signal; counting the first reference signal according to a free-run clock outputted by a free-run clock generator to produce a counter signal; and generating the output clock according to the counter signal and the free-run clock. | 10-15-2009 |
| 20090267673 | SIGNAL GENERATION CIRCUIT - A signal generation circuit that uses a waveform generation mechanism to generate predetermined waveform(s) when triggered. A triggering mechanism is configured to repeatedly trigger the waveform generation mechanism at times that are dependent on data provided by a data source. The predetermined waveform may be a bandwidth-limited pulse, but might also be a rising edge or a falling edge of a pulse. Various consecutive waveforms may be summed together to thereby formulate a continuous signal. The waveform may have particular characteristics by design. | 10-29-2009 |
| 20090284297 | CLOCK GENERATION CIRCUIT - A multiphase clock generation circuit ( | 11-19-2009 |
| 20090302920 | CIRCUIT, METHOD FOR RECEIVING A SIGNAL, AND USE OF A RANDOM EVENT GENERATOR - A circuit is provided that includes an input for a clock signal, a random event generator for outputting a random signal, in particular random numbers, a settable delay device that is connected to the input for the clock signal and is connected to the random event generator for the purpose of setting a delay of an edge of the clock signal (clk) by means of the random signal. | 12-10-2009 |
| 20090315606 | OUTPUT CIRCUIT - The present invention is aimed at providing an output circuit that is of relatively small scale and may perform adjustment to make the output-signal rise slew rate and the fall slew rate equal to each other. An output circuit includes a signal output unit configured to produce at a signal output node a signal that makes transition between a first potential and a second potential, a load circuit having a variable load, and a first switch circuit configured to select one of electrical conduction and non-conduction between the signal output node and the load circuit. | 12-24-2009 |
| 20100019821 | METHOD FOR GENERATING A OUTPUT CLOCK SIGNAL HAVING A OUTPUT CYCLE AND A DEVICE HAVING A CLOCK SIGNAL GENERATING CAPABILITIES - A device and a method for generating a output clock signal having a output cycle, the method includes: (i) adjusting a delay of an adjustable ring oscillator to provide a high frequency clock signal having a short cycle so that the output cycle substantially equals a sum of integer multiples of a sleep cycle and integer multiplies of the short cycle; wherein the output cycle differs from any integer multiples of the sleep cycle; wherein the sleep cycle characterizes a sleep clock signal that is generated by a low frequency sleep clock; wherein the short cycle is shorter than the sleep cycle; (ii) counting short cycles and sleep cycles; and (iii) generating, during a sleep mode, in response to the counting and to a predefined counting pattern, the first clock signal; wherein the generating includes activating the adjustable ring oscillator only during a portion of a single sleep cycle per each output cycle. | 01-28-2010 |
| 20100019822 | DELAY LINE SYNCHRONIZER APPARATUS AND METHOD - A synchronizer system and method that can be used with a conventional adjustable delay circuit to preserve a pseudo-synchronous phase relationship between clock signals of different clock domains when the time delay of the adjustable delay circuit from which one of the clock signals is output is changed. | 01-28-2010 |
| 20100039156 | CLOCKLESS TRANSMISSION SYSTEM AND CLOCKLESS TRANSMISSION METHOD - A clockless transmission system includes display controller | 02-18-2010 |
| 20100045354 | DELAY-LOCK LOOP AND METHOD ADAPTING ITSELF TO OPERATE OVER A WIDE FREQUENCY RANGE - A delay-lock loop receives an input clock signal from the output of a programmable divider that receives a reference clock signal. The delay-lock loop includes a voltage-controlled delay line generating a plurality of delayed clock signals having different phases. A plurality of the delayed clock signals are combined to generate a plurality of output signals. During an initialization period, an initialization circuit sets the delay of the delay line to a minimum delay value and then compares this delay value to the period of the input clock signal. Based on this comparison, the initialization circuit programs the programmable divider and adjusts the number of delayed clock signals combined to generate the output signals. More specifically, as the frequency of the reference clock signal increases, the divider is programmed to divide by a greater number, and a larger number of delay clock signals are combined to generate the output signals. | 02-25-2010 |
| 20100045355 | CLOCK SIGNAL GENERATION CIRCUIT AND SEMICONDUCTOR DEVICE - In a semiconductor device capable of radio communication, a stable clock signal is generated even if a reference clock signal for generating a clock signal has varied frequencies in each cycle. A clock signal generation circuit includes an edge detection circuit that detects an edge of an input signal and generates a synchronization signal, a reference clock signal generation circuit that generates a clock signal which functions as reference, a counter circuit that counts the number of edges of rise of the reference clock signal in accordance with the synchronization signal, a duty ratio selection circuit that selects a duty ratio of a clock signal from a count value, and a frequency division circuit that generates the clock signal having the selected duty ratio. | 02-25-2010 |
| 20100052759 | PULSE GENERATOR - A pulse generator includes a pulse command register and a digital differential analyzer (DDA). The pulse command register includes a first register, a second register, and an adder. The first register receives and stores a pulse command from a CPU in an operating cycle. The second register receives and stores the pulse command shifted from the first register when the first register receives a second pulse command from the CPU in the operating cycle. The adder sums the pulse commands of the first register and the second register and the result is transmitted to the DDA. The DDA determines whether a pulse is to be generated after calculation according to the result from the adder of the pulse command register. | 03-04-2010 |
| 20100052760 | Pulse signal generator, and method of generating pulse signal - A pulse signal generator includes a period setting unit that receives a period set signal including an information indicative of a pulse period, and that outputs a period control signal controlling the pulse period, a duty ratio setting unit that receives a duty ratio set signal including an information indicative of a duty ratio of a pulse, that receives a signal including the pulse period set in the period setting unit, and that generates a duty ratio control signal controlling the duty ratio of the pulse on a basis of the pulse period and the duty ratio set signal, and a pulse generation unit that generates a pulse signal including the pulse period and the duty ratio of the pulse on a basis of the period control signal and the duty ratio control signal. | 03-04-2010 |
| 20100073061 | INVERTER CIRCUIT - An inverter circuit using FETs which do not cause a fluctuation in gate threshold voltage Vth is provided. The inverter circuit has a load transistor and a driving transistor which is serially connected to the load transistor and supplies a load current to the load transistor in accordance with an input signal. The load transistor has at least two FETs which are connected in parallel and have controlled terminals. A driving part alternately turns on the FETs through the controlled terminals. | 03-25-2010 |
| 20100073062 | Voltage Control Oscillator Without Being Affected by Variations of Process and Bias Source - A VCO includes a reference current module and a clock signal generating module. The reference current module generates a reference current according to a reference voltage. The clock signal generating module generates a clock signal according to the reference current. The reference current module utilizes the negative feed-back mechanism to keep the generated reference current at the predetermined size without being changed with the variation of the process and the bias source. | 03-25-2010 |
| 20100102868 | Hardware and Method to Test Phase Linearity of Phase Synthesizer - A circuit to test phase linearity of a phase synthesizer, which synthesizes an output clock having a phase corresponding to a digital phase value input to the phase synthesizer. A digital counter provides the digital phase value to the phase synthesizer. The digital counter receives a counter clock synchronized with an input clock. The digital phase value is stepped by the digital counter, thereby shifting the frequency of the output clock. The output clock is analyzed with respect to phase linearity of the phase synthesizer to produce a phase linearity analysis output. | 04-29-2010 |
| 20100109736 | ELECTRONIC DEVICE AND SQUARE WAVE GENERATOR THEREOF - A square wave generator includes a sawtooth wave generator and a convertor. The sawtooth wave generator generates a sawtooth wave. The convertor generates a square wave based on the sawtooth wave. The sawtooth wave generator includes a capacitor and a switching unit connected parallel to each other. A first terminal of the capacitor is electrically coupled to a power source and the convertor, and a second terminal of the capacitor is grounded. When a voltage drop on the capacitor equals to or is greater than a first threshold voltage, the switching unit closes and grounds the first terminal of the capacitor, so that the capacitor discharges rapidly. | 05-06-2010 |
| 20100148840 | PULSE MODULATED CHARGE PUMP CIRCUIT - A circuit for increasing a gate voltage of a transmission gate in a high-speed switch to a level higher than a level of a supply voltage is provided. The circuit includes an oscillator generating a clock signal and a charge pump circuit operatively coupled to the oscillator. The charge pump circuit receives the supply voltage and the clock signal as inputs, and outputs the gate voltage. The circuit also includes a comparator circuit coupled to the oscillator circuit and the charge pump circuit and a pulse signal generator circuit operatively coupled to the oscillator, the pulse signal generator circuit generating a pulse signal which enables the oscillator. | 06-17-2010 |
| 20100219871 | GENERATION OF A LOW JITTER CLOCK SIGNAL - Systems and methods for generation of a low jitter clock signal for wireless circuits are disclosed. In an implementation, the system includes a wireless circuit powered by a first power supply and a low jitter clock (LJC) generator powered by a second power supply. The LJC generator provides at least one clock signal to the wireless circuit. The system further includes an LJC driver circuit including a clock buffer powered by the first power supply and a receive buffer powered by the second power supply. | 09-02-2010 |
| 20100231281 | SELF-TEST DESIGN METHODOLOGY AND TECHNIQUE FOR ROOT-GATED CLOCKING STRUCTURE - In a method of generating clock signals for a level-sensitive scan design latch, at least one test input signal is transmitted to a plurality of splitter leaves. Once the test input signal is stabilized at each of the splitter leaves, generating a shaped oscillator clock signal having a predetermined pattern of pulses from a central root is generated. At the plurality of splitter leaves, the test input signal is logically combined with the shaped oscillator clock signal, thereby generating a first latch clock signal and a second latch clock signal. The logically combining action includes applying a delay of less than one clock cycle to the shaped oscillator clock signal to generate a delayed oscillator clock signal; logically combining the delayed oscillator clock signal with a second signal so as to generate the first latch clock signal; and logically combining the shaped oscillator clock signal with a third signal so as to generate the second latch clock signal. | 09-16-2010 |
| 20100244922 | CLOCK SUPPLY APPARATUS AND CLOCK SUPPLY METHOD - According to one embodiment, a clock supply apparatus according to one embodiment of the invention includes a first transmission line connected to a clock generator that generates clock signals, a second transmission line connected to a clock supply destination having input impedance different from output impedance of the clock generator, a capacitor that capacitively couples the first and second transmission lines, a pull-up resistor that is provided on the first transmission line to suppress reflection of the clock signal, and a pair of voltage divider resistors that apply potential obtained by voltage division to the second transmission line as a reference potential of the clock signal. The impedance of the pair of voltage divider resistors on the second transmission line is set to match the input impedance of the clock supply destination. | 09-30-2010 |
| 20100264973 | ECONOMY PRECISION PULSE GENERATOR - A system includes an input device, an output device, a mechanical chassis, a printed circuit board, and a semiconductor device. The semiconductor device includes a mechanical package, and a semiconductor die. The semiconductor die includes a semiconductor layer, a plurality of metal layers, a clock distribution network that distributes a clock signal within the die, and an economy precision pulse generating circuit. The economy precision pulse generating circuit includes a pre-charge circuit, a gate-to-the-partial-jam-latch-keeper circuit, a partial-jam-latch-keeper circuit, and a pull-down-against-the-up-keeper circuit. A source clock signal is derived from the clock signal. The source clock signal is provided to a first input of a logical AND circuit, the pre-charge circuit, and the gate-to-the-partial-jam-latch-keeper circuit. A common storage node is connected to a second input of the logical AND circuit. The logical AND circuit outputs an output pulse. The output pulse is fed back to the pull-down-against-the-up-keeper circuit. | 10-21-2010 |
| 20100308883 | BURST ORDER CONTROL CIRCUIT AND METHOD THEREOF - A burst order control circuit includes a burst signal generating unit configured to receive a seed column address and to generate a first rising burst signal, a second rising burst signal, a first falling burst signal and a second falling burst signal in response to the seed column address, and a repeater unit configured to transfer the first rising burst signal, the second rising burst signal, the first falling burst signal and the second failing burst signal to a pipe latch. | 12-09-2010 |
| 20100315146 | EXTERNAL FREQUENCY ADJUSTMENT METHODS AND SYSTEMS - External frequency adjustment methods and systems are provided. First, an external frequency of an electronic device is increased from an initial frequency until a processing unit fails to properly operate, and a maximum first frequency value at which the processing unit can properly operate is recorded as the external frequency. The electronic device is enabled to reboot, and at least one peripheral device is initiated and operated according to the first frequency value. It is determined whether the peripheral device is properly operating at the first frequency value. When the peripheral device can not properly operate at the first frequency value, the electronic device is enabled to reboot, the first frequency value is subtracted by a predefined value to obtain a second frequency value, and the second frequency value is set as the external frequency, wherein the second frequency value is the maximum frequency value at which the processing unit can properly operate. | 12-16-2010 |
| 20100327936 | METHOD AND APPARATUS FOR DETERMINING WITHIN-DIE AND ACROSS-DIE VARIATION OF ANALOG CIRCUITS - Described herein is the method and apparatus for determining frequency of an oscillator coupled with one or more analog devices, and for determining within-die or across-die variations in an analog property associated with the one or more analog devices, the determining based on the oscillator frequency. The analog property includes output signal swing, bandwidth, offset, gain, and delay line linearity and range. The one or more analog devices include input-output (I/O) buffer, analog amplifier, and delay line. The method further comprises updating a simulation model file based on the determining of the within-die and/or across-die variations of the analog property. | 12-30-2010 |
| 20100327937 | CONFIGURABLE PULSE GENERATOR - The described embodiments provide a circuit that can be configured as a pulse generator or as an oscillator. The circuit includes a pulse generator circuit and a test circuit that is coupled to the pulse generator circuit. In the described embodiments, an disable signal is coupled to the test circuit. When the disable signal is asserted, the test circuit is disabled, and the pulse generator circuit outputs pulses of a predetermined duration. In contrast, when the disable signal is deasserted, the test circuit is enabled, and the pulse generator circuit outputs an oscillating signal. | 12-30-2010 |
| 20110018603 | SPURIOUS PULSE GENERATOR - According to a spurious pulse generator of this invention, integrating circuits are provided at a plurality of stages for carrying out integrating operations about time and outputting a spurious pulse, the integrating circuits being constructed to input a voltage value for controlling a crest value which is a peak swing of the spurious pulse to an amplifier forming an integrating circuit at a most upstream stage when a switching element is ON, and to input a constant voltage value when the switching element is OFF. As a result, the voltage value before ON-state and after ON-state of the switching element does not change but remains a constant voltage value, thereby obtaining a desired spurious pulse. | 01-27-2011 |
| 20110095803 | Adaptive control of power supply for integrated circuits - The present invention relates to a circuit arrangement and method for controlling power supply in an integrated circuit wherein at least one working parameter of at least one electrically isolated circuit region ( | 04-28-2011 |
| 20110140752 | Adaptive Clock Generators, Systems, and Methods - Adaptive clock generators, systems, and related methods than can be used to generate a clock signal for a functional circuit to avoid or reduce performance margin are disclosed. In certain embodiments, a clock generator autonomously and adaptively generates a clock signal according to a delay path(s) provided in a delay circuit(s) relating to a selected delay path(s) in the functional circuit(s). The clock generator includes a delay circuit(s) adapted to receive an input signal and delay the input signal by an amount relating to a delay path(s) of a functional circuit(s) to produce an output signal. A feedback circuit is coupled to the delay circuit(s) and responsive to the output signal, wherein the feedback circuit is adapted to generate the input signal back to the delay circuit(s) in an oscillation loop configuration. The input signal can be used to provide a clock signal to the functional circuit(s). | 06-16-2011 |
| 20110140753 | RESONANT CLOCK DISTRIBUTION NETWORK ARCHITECTURE WITH PROGRAMMABLE DRIVERS - A resonant clock distribution network architecture is proposed that uses clock drivers of programmable size and reference clocks of programmable duty cycle to achieve a target clock rise time and clock amplitude with low energy consumption when operating in any one of multiple clock frequencies in resonant or non-resonant mode. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. | 06-16-2011 |
| 20110221500 | DELAY-LOCK LOOP AND METHOD ADAPTING ITSELF TO OPERATE OVER A WIDE FREQUENCY RANGE - A delay-lock loop receives an input clock signal from the output of a programmable divider that receives a reference clock signal. The delay-lock loop includes a voltage-controlled delay line generating a plurality of delayed clock signals having different phases. A plurality of the delayed clock signals are combined to generate a plurality of output signals. During an initialization period, an initialization circuit sets the delay of the delay line to a minimum delay value and then compares this delay value to the period of the input clock signal. Based on this comparison, the initialization circuit programs the programmable divider and adjusts the number of delayed clock signals combined to generate the output signals. More specifically, as the frequency of the reference clock signal increases, the divider is programmed to divide by a greater number, and a larger number of delay clock signals are combined to generate the output signals. | 09-15-2011 |
| 20110234284 | SEMICONDUCTOR BOOST CIRCUIT AND METHOD OF CONTROLLING THE SAME - According to one embodiment, provided is a semiconductor boost circuit including a pump circuit, a switch signal generating circuit and a clock signal generating circuit. The pump circuit receives a clock signal and performs charge pump operation on the basis of the clock signal to boost an input potential to a set potential. The switch signal generating circuit outputs CLK cycle switch signal when a potential output by the pump circuit reaches a first potential greater than the input potential and less than the set potential. The clock signal generating circuit outputs the clock signal having a first frequency if not receiving the CLK cycle switch signal, and, on the other hand, outputs the clock signal having a second frequency greater than the first frequency if receiving the CLK cycle switch signal. | 09-29-2011 |
| 20110241747 | APPARATUS AND METHOD FOR REDUCING INTERFERENCE SIGNALS IN AN INTEGRATED CIRCUIT USING MULTIPHASE CLOCKS - An apparatus and method for reducing interference signals using multiphase clocks. An integrated circuit includes a digital circuit and an analog circuit. The digital circuit includes a derived clock circuit configured to receive a root clock having a frequency D*f, D being a divide factor, to divide the root clock by D, and generate multiphase clocks having N phases. N circuits of the digital circuit are configured to receive a corresponding one of the N phases, with edges of the multiphase clocks being spread over the N phases. The multiphase clocks cause a frequency shift in interference signals generated by reduced periodic peak currents drawn by the N circuits from f to N*f and harmonics thereof. The analog circuit receives an in-band range of signals. A value of N is configured to shift the interference signals outside the in-band range of signals. | 10-06-2011 |
| 20110241748 | METHODS AND SYSTEMS FOR GENERATING LOCAL OSCILLATOR SIGNALS - A method is provided for generating local oscillator signals for a mixer. The method includes providing a reference frequency signal and generating a differential in-phase signal and a differential quadrature signal from the reference frequency signal. The method further includes re-clocking each of the differential in-phase and differential quadrature signals using the reference frequency signal. The re-clocked differential in-phase and differential quadrature signals are then provided as the local oscillator signals for the mixer. | 10-06-2011 |
| 20110254607 | Method And Apparatus For Digital Synthesis Of Long Multi-Cycle Microwave Pulses - Conductive segments (transmission line conductors) are positioned within a transmission line structure in order to generate multi-cycle microwave pulses. The conductor segments are switchably coupled to one or the other conductor of the transmission lines, inside the transmission line structure. Microwave pulses may be induced in the transmission line by closing the switches in a controlled manner to discharge successive segments, or successive groups of segments, into the transmission lines. The induced pulses travel uninterrupted along the transmission lines in a desired direction to the load. Efficiency of systems and energy delivered to the load in multi-section transmission lines is increased and/or maximized by adjusting the ratio of characteristic impedances associated with the transmission line conductor segments according to an optimum ratio. | 10-20-2011 |
| 20110273213 | METHOD AND APPARATUS TO DYNAMICALLY ADJUST A CLOCK RATE IN A MOBILE DEVICE - In a particular embodiment, a method includes dynamically adjusting a clock rate to one or more hardware components within a mobile device during a silence period. During the silence period of a video telephony call, when a user of the mobile device is not speaking, the mobile device monitors the background noise and compares detected background noise data to previously detected background noise data to determine changes in the background noise. If the comparison shows that the change in background noise does not result in a change in background noise conditions or does not exceed a difference threshold, the clock rate to certain hardware components may be reduced and portions of certain hardware components may be powered down. The mobile device may send previously stored background noise update packets. | 11-10-2011 |
| 20110273214 | CLOCK GENERATING CIRCUIT - According to one embodiment, a clock generating circuit includes first and second current generating circuits, first and second voltage generating circuits, first and second comparing circuits, a clock output circuit, a control circuit. The first current generating circuit is configured to generate a first current. The first voltage generating circuit is configured to generate a first voltage which increases or decreases according to a phase of a clock signal as time advances by the first current. The first comparing circuit is configured to compare the first voltage with a first threshold voltage to generate a first comparison result. The second current generating circuit is configured to generate a second current. The second comparing circuit is configured to compare the second voltage with a second threshold voltage to generate a second comparison result. The clock output circuit is configured to generate the clock signal whose phase inverts in synchronization with timing when the first and the second comparison results change. The control circuit is configured to generate a random number and configured to variably control at least one of the first current, the second current, the first threshold voltage and the second threshold voltage according to the random number. | 11-10-2011 |
| 20110304373 | LOW VOLTAGE HIGH-SPEED WAVE SHAPING CIRCUITRY - Within hard disk drives (HDDs), for example, a preamplifier or preamp is generally used to perform read and write operations with a magnetic head. Typically, for write operations, the preamplifier generates a current waveform that uses a DC current to polarize magnetic elements within the disk and overshoot components to compensate for frequency dependent attenuation in the interconnect between the head and preamp. Conventional pulse-shaping circuitry used for this application uses high voltage to accomplish this task. Here, however, pulse-shaping circuitry is provided which can generate a similar waveform using lower voltage (i.e., about 5V) for this application and others. | 12-15-2011 |
| 20120001670 | Clock Routing in Mulitiple Channel Modules and Bus Systems - The terminating module includes integrated circuits and a termination circuit which receive clock signals from the integrated circuit. The integrated circuit includes at least one memory integrated circuit mounted on a printed circuit board. An electrical connector is configured to couple the terminating module to a motherboard. Additionally, the termination circuit includes a resistor. In another embodiment, the terminating module provides a printed circuit board, a memory integrated circuit mounted on the circuit board, a terminator circuit which includes a resistor, and an electrical connector. The electrical connector couples the terminating module to a motherboard. | 01-05-2012 |
| 20120025887 | CLOCK DRIVER FOR A CAPACITANCE CLOCK INPUT - A circuit that produces a clocking signal for a low to medium capacitance input of a device includes a drive gate connected to a common-base bi-polar driver circuit. The output of the drive gate is connected to an emitter of an NPN bi-polar transistor through one coupling capacitor and to an emitter of a PNP bi-polar transistor through another coupling capacitor. The transistors are connected in a common-base configuration with the collectors of the transistors connected together. One voltage is connected to the base of the PNP transistor. Another voltage is connected to the base of the NPN transistor. A diode is connected in parallel with the base-emitter of the PNP transistor. Another diode is connected in parallel with the base-emitter of the NPN transistor. A damping resistor is connected between the collectors of the transistors and the low to medium capacitance clock input of the device. | 02-02-2012 |
| 20120086490 | INTEGRATED CIRCUIT DEVICES USING POWER SUPPLY CIRCUITS WITH FEEDBACK FROM A REPLICA LOAD - An integrated circuit device includes an external power supply input configured to be coupled to an external power supply and a digital circuit, such as a clock signal generator circuit, that generates noise at a power supply input thereof. The device further includes a replica load circuit and a power supply circuit coupled to the external power supply input, to a power supply input of the digital circuit and to a power supply input of the replica load circuit. The power supply circuit is configured to selectively couple the external power supply node to the power supply input of the digital circuit responsive to a voltage at the power supply input of the replica load circuit. The replica load circuit may be configured to provide a load that varies responsive to a voltage at the power supply input of the digital circuit. | 04-12-2012 |
| 20120126871 | METHOD AND APPARATUS OF ALTERNATING SERVICE MODES OF AN SOI PROCESS CIRCUIT - A method and apparatus of alternating service modes of a silicon on insulator (SOI) process circuit includes determining whether the SOI process circuit is in a first or second service mode. A first clock or a second clock is selected for transmission along a buswire of the SOI process circuit based upon the determination. A receiving device of the signal is notified whether the SOI process circuit is operating in the first service mode or the second service mode. | 05-24-2012 |
| 20120169394 | METHOD FOR BUFFERING CLOCK SKEW BY USING A LOGICAL EFFORT - A method buffers clock skew by using a logical effort, and is applicable to a clock tree that stays in a strong-inversion region, a moderate-inversion region, or a weak-inversion region. The method includes establishing in the clock tree a temperature sensor and a tunable-width buffer, and establishing width and temperature comparative lists according to a logical effort equation, for the tunable-width buffer to be individually applied to the strong-inversion region, the moderate-inversion region, and the weak-inversion region; selecting one from the width and temperature comparative lists that corresponds to one of the inversion regions in which the clock tree stays, enabling the temperature sensor to sense a temperature, and searching the selected width and temperature comparative list for a width that corresponds to the temperature sensed by the temperature sensor; and enabling the tunable-width buffer to perform a width modulation process according to the searched width. | 07-05-2012 |
| 20120206183 | RESPONSE TO WEAROUT IN AN ELECTRONIC DEVICE - An electronic device comprises a first component susceptible to a wearout effect, operation of which first component depends on an operating parameter, and a second component having an on-state and an off-state. The electronic device further comprises a time estimator for updating an estimate of an accumulated time the second component was in the on-state; and a controller for controlling the operating parameter on the basis of the accumulated time estimate so as to respond to the expected wearout effect. The first component and the second component may be the same, or the first component may have an on-state correlated to the on-state of the second component. The operating parameter may, for example, be a level or amplitude or correction value of one of the following: a voltage applied at the first component, an electric current fed to the first component, and a power provided to the first component. A method of operating such an electronic device is also disclosed. | 08-16-2012 |
| 20120229188 | SEMICONDUCTOR DEVICE AND OPERATION MODE SWITCH METHOD - A semiconductor device including an internal terminal, a first transistor of a first conductivity type that is coupled between a first reference potential and the internal terminal, and that includes a first control terminal, a second transistor of a second conductivity type that is coupled between a second reference potential and the internal terminal, and that includes a second control terminal, an oscillator that includes an output terminal to output a clock signal, and a comparator that is coupled to the internal terminal, and that compares a potential of the internal terminal when the internal terminal is coupled to the first reference potential with a potential of the internal terminal when the internal terminal is coupled to the second reference potential. Each control terminals is coupled to the output terminal to commonly receive the clock signal, and the first and second transistors exclusively operate in response to the clock signal. | 09-13-2012 |
| 20120262214 | RF SIGNAL GENERATION CIRCUIT AND WIRELESS TRANSMITTER - A wireless transmitter includes an RF signal generation circuit, a driver amplifier, and a class-D amplifier. The RF signal generation circuit detects an amplitude signal and a phase signal based on a digital baseband signal subjected to orthogonal modulation, thus generating a pulse phase signal which is High in response to the phase ranging from 0° to 180° but is Low in response to the phase ranging from 180° to 360°. The amplitude signal is subjected to sigma-delta modulation in synchronism with the pulse phase signal and further mixed with the pulse phase signal, thus producing an RF pulse signal. The RF pulse signal is input to the class-D amplifier via the driver amplifier, thus outputting a pulse voltage signal based on a reference voltage. Thus, it is possible to achieve a small-size wireless transmitter with good noise/distortion characteristics and high power efficiency. | 10-18-2012 |
| 20120286841 | PULSE GENERATOR HAVING AN EFFICIENT FRACTIONAL VOLTAGE CONVERTER AND METHOD OF USE - Disclosed are systems and methods which provide voltage conversion in increments less than integer multiples of a power supply (e.g., battery) voltage. A representative embodiment provides power supply voltage multipliers in a binary ladder distribution to provide a desired number of output voltage steps using a relatively uncomplicated circuit design. By using different sources in various combinations and/or by “stacking” different sources in various ways, the voltage multiplier circuit may be used to provide desired voltages. In order to minimize the number of components used in a voltage converter of an embodiment, a capacitive voltage converter circuit uses one or more storage capacitors in place of pump capacitors in a voltage generation cycle. Also, certain embodiments do not operate to generate an output voltage until the time that voltage is needed. | 11-15-2012 |
| 20120326761 | PROCESSOR FREQUENCY ADJUSTMENT CIRCUIT - A processor frequency adjustment circuit for adjusting a frequency of a processor includes a voltage converting module, a first reference voltage generating module, a clock chip, a voltage comparing module. The voltage converting module converts a pulse voltage into a constant voltage. The first reference voltage generating module generates a first reference voltage. The voltage comparing module is connected with the voltage converting module, the first reference voltage generating module, and the clock chip to compare the constant voltage with the first reference voltage, and generates a first voltage level signal to a first terminal of the clock chip; the clock chip adjusts the frequency of the processor in response to obtaining the first voltage level signal. | 12-27-2012 |
| 20120326762 | OSCILLATOR CIRCUIT - An oscillator circuit includes an oscillator output signal generating circuit configured to generate an oscillator output signal using an oscillator as a resonator, an amplitude detection circuit configured to detect the amplitude of the oscillator output signal and compare the detected amplitude with a threshold; and a boost circuit configured to boost the oscillator output signal according to the result of the comparison at the amplitude detection circuit. The amplitude detection circuit includes an absolute value circuit configured to obtain an absolute value signal of the oscillator output signal, a low-pass filter configured to convert the absolute value signal into a low-frequency signal, and a comparator configured to compare the low-frequency signal with the threshold. | 12-27-2012 |
| 20130076426 | APPARATUS FOR SUPPLYING CLOCK AND METHOD THEREOF - An apparatus for providing clock and a method thereof are provided. The provided apparatus includes a frequency generation unit and a control unit. The frequency generation unit decides amplitude of a clock signal to be a first amplitude or a second amplitude in response to a mode signal. The frequency generation unit converts an external oscillation signal into the clock signal. The control unit receives the clock signal, and outputs the mode signal in response to a system status signal. The control unit outputs the clock signal to external when determining that the clock signal has a stable oscillation. When the system status signal is a power on signal, the first amplitude is used as the amplitude of the clock signal, and when the system status signal is a power off signal, the second amplitude smaller than the first amplitude is used as the amplitude of the clock signal. | 03-28-2013 |
| 20130127509 | EMI SHIELDING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME - An electromagnetic interference (EMI) shielding circuit and a semiconductor integrated circuit including the same are provided. The EMI shielding circuit includes a data level comparison unit, a control signal generation unit, and a driver for EMI cancellation. The data level comparison unit generates a data comparison signal by comparing a number of high-level data transmitted through a plurality of data lines and a number of low-level data transmitted through the plurality of data lines. The control signal generation unit generates a driving control signal in response to the data comparison signal. The driver for EMI cancellation outputs an EMI cancellation signal in response to the driving control signal. | 05-23-2013 |
| 20130127510 | ISOLATION INTERFACE CIRCUIT FOR POWER MANAGEMENT - An isolation interface circuit is disclosed. The isolation interface circuit comprising a transmitting circuit and a receiving circuit. The transmitting circuit configured to receive a first serial interface signal and a second serial interface signal for generating a differential polarity pulse signal. The receiving circuit configured to receive the differential polarity pulse signal for generating the first serial interface signal and the second serial interface signal. The differential polarity pulse signal are generated in response to the first serial interface signal and the second serial interface signal. The first serial interface signal and the second serial interface signal are generated in accordance with the differential polarity pulse signal. In a period, only one of the transmitting circuit and the receiving circuit can be enabled. | 05-23-2013 |
| 20130169338 | CLOCK GENERATOR AND METHOD OF GENERATING CLOCK SIGNAL - A clock generator utilized for providing a clock signal includes: a first oscillator and a switching circuit. The switching circuit is coupled to the first oscillator and a second oscillator, and utilized for receiving a first oscillating signal generated from the first oscillator and a second oscillating signal generated from the second oscillator, and selecting one of the first oscillating signal and the second oscillating signal as the clock signal according to a status signal. | 07-04-2013 |
| 20130194018 | Method for Selecting Natural Frequency in Resonant Clock Distribution Networks with no Inductor Overhead - An inductor architecture for resonant clock distribution networks is described. This architecture allows for the adjustment of the natural frequency of a resonant clock distribution network, so that it achieves energy-efficient operation at multiple clock frequencies. The proposed architecture exhibits no inductor overheads. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to the binning of semiconductor devices according to achievable performance levels. | 08-01-2013 |
| 20130257503 | LAYER-ID DETECTOR FOR MULTILAYER 3D-IC AND METHOD OF THE SAME - A layer-ID detector for multilayer 3D-IC, including a random generator to generate a random signal, a layer-ID designation mechanism circuit coupled to the random generator to generate a layer-ID designating signal, and a counter coupled to the layer-ID designating signal to output a layer-ID signal. | 10-03-2013 |
| 20130271198 | CLOCK GENERATION METHOD AND SYSTEM - The clock generation method contains the following steps. In a pulse recognition step, an input pulse signal is first filtered to remove a shorter signal. Then, a width digitization calculation is conducted on the remaining pulse signal. Based on the width digitization calculation, a signal is recorded and a period of the recorded signal is determined. The value of the period is delivered to a gain module. In a step for verifying the input value to D/A converter, two values are input to a D/A converter from the gain module, and the output from the D/A converter is delivered to an oscillator. The gain module determines a desired input value from the gain module to the D/A converter. In a pulse generation step, the gain module inputs the desired input value to the D/A converter which in turn delivers to the oscillator for the generation of a corresponding clock. | 10-17-2013 |
| 20130307604 | PULSE OUTPUT CIRCUIT, SHIFT REGISTER, AND DISPLAY DEVICE - An object is to suppress change of a threshold voltage of a transistor in a shift register and to prevent the transistor from malfunctioning during a non-selection period. A pulse output circuit provided in the shift register regularly supplies a potential to a gate electrode of a transistor which is in a floating state so that the gate electrode is turned on during a non-selection period when a pulse is not outputted. In addition, supply of a potential to the gate electrode of the transistor is performed by turning on or off another transistor regularly. | 11-21-2013 |
| 20140015585 | Resonant Clock Distribution Network Architecture for Tracking Parameter Variations in Conventional Clock Distribution Networks - A resonant clock distribution network architecture is proposed that enables a resonant clock network to track the impact of parameter variations on the insertion delay of a conventional clock distribution network, thus limiting clock skew between the two networks and yielding increased performance. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. | 01-16-2014 |
| 20140043082 | CLOCK GENERATION METHOD AND SYSTEM - The clock generation method contains the following steps. In a pulse recognition step, an input pulse signal is first filtered to remove a shorter signal. Then, a width digitization calculation is conducted on the remaining pulse signal. Based on the width digitization calculation, a signal is recorded and a period of the recorded signal is determined. The value of the period is delivered to a gain module. In a step for verifying the input value to D/A converter, two values are input to a D/A converter from the gain module, and the output from the D/A converter is delivered to an oscillator. The gain module determines a desired input value from the gain module to the D/A converter. In a pulse generation step, the gain module inputs the desired input value to the D/A converter which in turn delivers to the oscillator for the generation of a corresponding clock. | 02-13-2014 |
| 20140077859 | CLOCK SIGNAL GENERATING CIRCUIT AND POWER SUPPLY INCLUDING THE SAME - The present invention relates to a clock signal generating circuit and a power supply including the same. The present invention includes: a counter for counting one period of an input clock signal by using a reference clock signal, and generating a count signal; and a clock signal generator for receiving the count signal and the reference clock signal, dividing the count signal to generate a quotient and a remainder, setting the quotient as a reference period of an output clock signal, and distributing and disposing the remainder to the output clock signal with a plurality of periods occurring for one period of the input clock signal. | 03-20-2014 |
| 20140167831 | CLOCK DISTRIBUTION USING MTJ SENSING - Clock signals are distributed on a chip by applying an oscillating magnetic field to the chip. Local clock generation circuits including magnetic field sensors are distributed around the chip and are coupled to local clocked circuitry on the chip. The magnetic field sensors may include clock magnetic tunnel junctions (MTJs) in which a magnetic orientation of the free layer is free to rotate in the free layer plane in response to the applied magnetic field. The MTJ resistance alternates between a high resistance value and a low resistance value as the free layer magnetization rotates. Clock generation circuitry coupled to the clock MTJs senses voltage oscillations caused by the alternating resistance of the clock MTJs. The clock generation circuitry includes amplifiers, which convert the sensed voltage into local clock signals. | 06-19-2014 |
| 20140167832 | CHANGING RESONANT CLOCK MODES - Described is an integrated circuit having a clock distribution network capable of transitioning from a non-resonant clock mode to a first resonant clock mode Transitions between clock modes or between various resonant clock frequencies are done gradually over a series of clock cycles. In example, when transitioning from a non-resonant clock mode to a first resonant clock mode, a strength of a clock sector driver is reduced over a series of clock cycles, and individual ones of a plurality of resonant switches associated with resonant circuits are modified in coordination with reducing the strength of the clock sector driver. | 06-19-2014 |
| 20140232444 | SELF-POWERED TIMER APPARATUS - A method is provided for implementing a timer using a floating-gate transistor. The method includes: injecting a charge into a floating-gate transistor at an initial time, where a gate terminal of the floating-gate transistor is comprised of polysilicon encased by an insulating material; creating lattice imperfections at boundary of the polysilicon to cause leakage from the floating-gate transistor; measuring current read out from the floating-gate transistor at a time subsequent to the initial time; and determining an amount of time between the initial time and the subsequent time using the measured current. | 08-21-2014 |
| 20140247079 | Pulse Generator Circuit - A pulse generator circuit is disclosed that is optimized for printed, solution-processed thin film transistor processing. In certain embodiments, the circuit comprises dual thin film transistors that operate as a diode and resistor, respectively. Optionally, a third thin film transistor may be provided to operate as a pass transistor in response to an enable signal. The elements of the circuit are configured such that a rising pulse on an input node triggers an output pulse on an output node in the manner of a monostable multivibrator. | 09-04-2014 |
| 20140253201 | PULSE GENERATION IN DUAL SUPPLY SYSTEMS - Various apparatuses and methods are disclosed. The system describes a pulse generator comprising a first stage configured to be powered by a first voltage; and a second stage configured to be powered by a second voltage different from the first voltage, wherein the second stage is further configured to generate a pulse in response to an input to the first stage comprising a trigger and feedback from the second stage. | 09-11-2014 |
| 20140266375 | Integrated Circuitry for Generating a Clock Signal in an Implantable Medical Device - Timer circuitry completely formable in an integrated circuit (IC) for generating a clock signal in an implantable medical device is disclosed. The timer circuitry can be formed on the same Application Specific Integrated Circuit typically used in the implant, and requires no external components. The timer circuitry comprises modification to a traditional astable timer circuit. A resistance in the disclosed timer circuit can be trimmed to adjust the frequency of the clock signal produced, thus allowing that frequency to be set to a precise value during manufacturing. Precision components are not needed in the RC circuit, which instead are used to set the rough value of the frequency of the clock signal. A regulator produces a power supply for the timer circuitry from a main power supply (Vcc), producing a clock signal with a frequency that is generally independent of temperature and Vcc fluctuations. | 09-18-2014 |
| 20140306746 | DYNAMIC CLOCK SKEW CONTROL - A device includes a dock generator operable to generate a clock signal. A first module includes a first clock network coupled to the clock generator for distributing the clock signal. A second module includes a second clock network coupled to the clock generator for distributing the clock signal. A clock skew control circuit is operable to receive a first instance of the clock signal from the first clock network and a second instance of the clock signal from the second clock network and to control skew between the first and second instances of the clock signal. | 10-16-2014 |
| 20140354339 | SEMICONDUCTOR DEVICES - The semiconductor device includes an internal clock generator, a shift signal generator and a first control signal generator. The internal clock generator generates a first internal clock signal and a second internal clock signal in response to an external clock signal. The shift signal generator shifts a clock enable signal in response to the first internal clock signal to generate first and second shift signals, and the shift signal generator shifts the clock enable signal in response to the second internal clock signal to generate third and fourth shift signals. The first control signal generator generates a first control signal in response to the first and third shift signals. | 12-04-2014 |
| 20150008970 | PERIOD SIGNAL GENERATION CIRCUIT - A period signal generation circuit includes a first buffer unit suitable for buffering a buffer signal and output an output signal; and a second buffer unit suitable for buffering the output signal and output a period signal, wherein each of the first and second buffer units includes a resistor element coupled between a body of a metal oxide semiconductor (MOS) transistor and a source. | 01-08-2015 |
| 20150145582 | PULSE GENERATING CIRCUIT FOR AUDIO-FREQUENCY AMPLIFIERS AND REGULATED POWER SUPPLIES - A circuit for generating a series of pulses in response to a first signal, the circuit comprising: a lossy integrator which receives a second signal as its input; and a comparator which: receives the output of the lossy integrator at one of its inputs; and receives the first signal at the other of its inputs. This circuit can be incorporated into, for example, audio-frequency amplifiers and regulated power supplies. | 05-28-2015 |
| 20150293556 | CONFIGURABLE CLOCK INTERFACE DEVICE - A configurable clock circuit on an integrated circuit, such as an integrated circuit memory, can be configured to utilize external multiple phase clocks and external single phase clocks to produce an internal clock signal in a form compatible with the integrated circuit. | 10-15-2015 |
| 20150316950 | DUAL-EDGE GATED CLOCK SIGNAL GENERATOR - A clock signal generator provides a gated clock signal GCLK to trigger operation of dual-edge triggered circuits. A first detector generates, while a clock gating signal /EN is asserted, a first detector output signal that is asserted or de-asserted as a function of disjunction or conjunction respectively of the values that an input clock signal CLK and the gated clock signal GCLK had when the clock gating signal /EN transitioned. A second detector generates, while the clock gating signal /EN is de-asserted, as the value of the gated clock signal GCLK, the value CLK or its complement /CLK as a function of the first detector output signal. When the clock gating signal /EN is asserted, the second detector maintains the value that the gated clock signal GCLK had when the clock gating signal /EN transitioned from de-asserted to asserted. | 11-05-2015 |
| 20150316952 | CLOCK SOURCE, METHOD FOR DISTRIBUTING A CLOCK SIGNAL AND INTEGRATED CIRCUIT - The present invention provides a clock source for an integrated circuit, comprising a primary oscillator adapted to generate a primary clock signal based on a reference control signal, at least one secondary oscillator each secondary oscillator being adapted to generate a secondary clock signal based on the reference control signal, wherein for each secondary oscillator a frequency correction unit is provided and adapted to adjust the reference control signal for the associated secondary oscillator based on the primary clock signal and the secondary clock signal of the associated secondary oscillator such that the clock frequency of the secondary clock signal of the associated secondary oscillator essentially equals the clock frequency of the primary clock signal. The present invention furthermore provides a method for providing a clock signal, and an integrated circuit. | 11-05-2015 |
| 20150333736 | METHOD AND CIRCUIT FOR TEMPERATURE DEPENDENCE REDUCTION OF A RC CLOCK CIRCUIT - A method and a circuit for generating a clock signal from a clock integrated circuit are introduced herein. A compensation voltage is generated according to a temperature coefficient of a resistor and a clock period of a clock circuit, where the compensation voltage is resistor-corner independent. The clock period of the clock circuit is determined by the resistor and at least one capacitor of the clock circuit. The temperature dependence of the clock period of the clock circuit is reduced according to the compensation voltage. | 11-19-2015 |
| 20150357997 | CORRECTION ARITHMETIC CIRCUIT AND A SIGNAL PROCESSOR - A correction arithmetic circuit disclosed herein includes an offset temperature characteristic correction unit that corrects an offset temperature characteristic of an input signal according to an input signal characteristic at a specific temperature and a temperature characteristic at a specific input signal. A signal processor disclosed herein includes a pulse count number setting circuit that generates a pulse count number setting signal in accordance with an input signal and a pulse generation unit that generates a pulse signal by counting a pulse number of a reference clock signal according to the pulse count number setting signal. The pulse count number setting circuit corrects the pulse count number setting signal so as to cancel a frequency temperature characteristic of the pulse signal. | 12-10-2015 |
| 20160028379 | CLOCK GENERATOR - A clock generator comprises a voltage controlled oscillator including a ring oscillator which has a plurality of differential inverter circuits connected in a ring shape, and a phase controller to control an output of a differential inverter circuit which belongs to a second group, in a first state or a second state, for a predetermined time period. The differential inverter circuit which belongs to the second group is distinct from a differential inverter circuit which belongs to a first group. The differential inverter circuit which belongs to the second group, in the first state, outputs a first logic signal from a first differential output terminal and outputs a second logic signal from a second differential output terminal. Further, the differential inverter circuit which belongs to the second group, in the second state, outputs the second logic signal from the first differential output terminal and outputs the first logic signal from the second differential output terminal. | 01-28-2016 |
| 20160077544 | CLOCK GATING CIRCUITS AND CIRCUIT ARRANGEMENTS INCLUDING CLOCK GATING CIRCUITS - Clock gating circuits may include: a first inverter; a first switch having a first terminal and a second terminal, the first terminal of the first switch coupled to an output of the first inverter; a feedback circuit having an input-output terminal, the input-output terminal of the feedback circuit coupled to the second terminal of the first switch; and a first logic gate having a first input terminal and a second input terminal, the first input terminal coupled to the input-output terminal of the feedback circuit, the second input terminal electrically connected to receive a master clock signal. | 03-17-2016 |
| 20160105161 | IMPLEMENTING BROADBAND RESONATOR FOR RESONANT CLOCK DISTRIBUTION - A method and circuit for implementing a broadband resonator for resonant clock distribution, and a design structure on which the subject circuit resides are provided. The circuit includes a pair of first inductors, and a second inductor and a capacitor coupled between a respective first end of the respective first inductors. An opposite free end of the respective first inductors is connected to a respective clock transmission line and connected in parallel to a load capacitance. A frequency response of the circuit includes two poles and a zero in a frequency band of the resonant clock distribution system. | 04-14-2016 |
| 20160161978 | SIGNAL COMPARISON APPARATUS AND METHOD OF CONTROLLING SAME - A signal comparison apparatus and a method of controlling the same are provided. The signal comparison apparatus includes a first comparator, a self-timed clock generator and a controller. The first comparator is controlled by a start signal to compare differences of first input signals and generate output signals. The self-timed clock generator receives the output signals to generate a self-timed clock signal. The controller receives the self-timed clock signal and calculates a time interval of the self-timed clock signal which responds to the first input signals of the first comparator, and determines whether the time interval is equal to or larger than a threshold time to generate a metastable detection signal. When the time interval is equal to or larger than the threshold time, the controller outputs the metastable detection signal as the start signal, such that the first comparator continue comparing the next differences of the first input signals. | 06-09-2016 |
| 20160164499 | SIGNAL INPUT CIRCUIT AND OPERATING METHOD THEREOF - An input circuit includes: an input buffering unit suitable for receiving one or more input data, wherein each toggling time is defined according to a value of each input data; and a data transformation unit suitable for transforming the input data into an output data according to a mapping table and the toggling time of the input data during a data input duration. | 06-09-2016 |
| 20160191029 | SPREAD-SPECTRUM CLOCK GENERATION CIRCUIT, INTEGRATED CIRCUIT AND APPARATUS THEREFOR - A spread-spectrum clock generation circuit comprises at least one comparison element; at least one charge storage device arranged to couple an output of the at least one comparison element to an input of the at least one comparison element and arranged to set a first oscillation frequency of the spread-spectrum clock generation circuit; and a switched charge storage arrangement additionally arranged to couple an output of the at least one comparison element to an input of the at least one comparison element and arranged to set a second oscillation frequency of the spread-spectrum clock generation circuit. | 06-30-2016 |
| 20220140820 | SOFTWARE-DEFINED PULSE ORCHESTRATION PLATFORM - A system comprises pulse program compiler circuitry operable to analyze a pulse program that includes a pulse operation statement, and to generate, based on the pulse program, machine code that, if loaded into a pulse generation and measurement circuit, configures the pulse generation and measurement circuit to generate one or more pulses and/or process one or more received pulses. The pulse operation statement may specify a first pulse to be generated, and a target of the first pulse. The pulse operation statement may specify parameters to be used for processing of a return signal resulting from transmission of the first pulse. The pulse operation statement may specify an expression to be used for processing of the first pulse by the pulse generation and measurement circuit before the pulse generation and measurement circuit sends the first pulse to the target. | 05-05-2022 |
