| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 327298000 | Single clock output with multiple inputs | 45 |
| 20080258794 | GLITCH-FREE CLOCK SWITCHING CIRCUIT - A glitch-free clock switching circuit receives a first clock signal and a second clock signal and outputs a third clock signal corresponding to the first clock signal or a fourth clock signal corresponding to the second clock signal according to a clock switching signal. The glitch-free clock switching circuit switches to output clock signals by stopping output of a clock signal, and then waiting for a predetermined period of time before outputting another clock signal. | 10-23-2008 |
| 20080272819 | CLOCK RECEIVERS - A clock receiver is provided. A receiving unit receives a pair of complementary clocks and generates a first clock, and a calibration unit detects whether a cross point of the complementary clocks has shifted, generates a detected result and accordingly adjusts toggling of the first clock. | 11-06-2008 |
| 20080284484 | CLOCK SWITCH FOR GENERATION OF MULTI-FREQUENCY CLOCK SIGNAL - An improved clock switch in an integrated circuit chip that multiplexes two asynchronous clock signals to generate a multi-frequency clock signal in a manner that avoids glitches on the clock output line and meta-stable states within the switch. The clock switch does not include a cross-coupled feedback loop, thus rendering the clock switch test-friendly and avoiding potential race conditions in the switch. The clock switch is useable with asynchronous clock sources having a variety of different clock frequencies and phases. | 11-20-2008 |
| 20080290925 | Clock generator - A multiphase clock with high resolution is generated. A first clock generator circuit ( | 11-27-2008 |
| 20080309393 | CLOCK-GENERATOR ARCHITECTURE FOR A PROGRAMMABLE-LOGIC-BASED SYSTEM ON A CHIP - A programmable system-on-a-chip integrated circuit device comprises at least one of a crystal oscillator circuit, an RC oscillator circuit, and an external oscillator input. A clock conditioning circuit is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A real-time clock is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A programmable logic block is coupled to the clock conditioning circuit and the real-time clock. | 12-18-2008 |
| 20090039940 | APPARATUS AND METHOD FOR PREVENTING GENERATION OF GLITCH IN A CLOCK SWITCHING CIRCUIT - An apparatus and for preventing a glitch in a clock switching circuit includes a select signal manager and a clock gate unit. The select signal manager generates a detect change signal, provides the detect change signal as an input signal for generating a clock gate signal to the clock gate unit, and changes a muxsel signal into a select signal using the clock gate signal to select a clock intending for switching. Upon receiving the detect change signal, the clock gate unit gates a received clock, generates the clock gate signal using a level of the detect change signal as an input signal, and provides the generated clock gate signal to the select signal manager. | 02-12-2009 |
| 20090072878 | Phase Clock Generator - Disclosed is a phase clock generator. The phase clock generator can include transistors and a buffer. The transistors are connected between a power line and a grounding line and are provided in a form of a 4×N matrix to receive a plurality of phase-delayed signals through their gate terminals. Four transistors can form a unit column between the power line and the grounding line. From ground line to power line, the first two transistors of the unit column provide a pair of NMOS transistors, and the second two transistors provide a pair of PMOS transistors. The buffer is connected to a line, which is provided between the pair of the NMOS transistors and the pair of the PMOS transistors forming the unit column, to transmit a clock signal. | 03-19-2009 |
| 20090167400 | DEVICE AND METHOD FOR GENERATING CLOCK SIGNAL - In a device for generating a clock signal having a desired phase from input multi-phase clock signals, an intermediate clock generator generates, by using one of the input multi-phase clock signals as a reference clock signal, multi-phase intermediate clock signals in which one cycle is equal to a plurality of cycles of the reference clock signal. A first phase selector selects one of the multi-phase intermediate clock signals. A second phase selector selects one of the multi-phase clock signals. A latch circuit latches the intermediate clock signal selected by the first phase selector with the clock signal selected by the second phase selector. | 07-02-2009 |
| 20090195287 | APPARATUS AND METHOD FOR EXTERNAL TO INTERNAL CLOCK GENERATION - A phase recombination circuit includes a first phase input and a first one-shot pulse generator adapted to receive the first phase input and produce a first signal to pull a signal to a first state. The phase recombination circuit also includes a second phase input in phase relationship with the first phase input, and a second one-shot pulse generator adapted to receive the second phase input and produce a second signal to pull a signal to a second state. | 08-06-2009 |
| 20090206905 | SELF CLOCK GENERATION - A clock signal may be generated for a receiving circuit without requiring an external oscillator. A first digital circuit may convert a first signal edge at an input into a first clock signal at an output, and a second digital circuit, in feedback connection with the first digital circuit, may generate a second signal edge at the input based on the first clock signal at the output. Then, the first circuit may convert the second signal edge at the input to a second clock signal at the output. Thus, the first circuit and the second circuit, in combination, may generate a continuous stream of signal edges at the input and clock signals at the output. The second circuit may communicate with the controller circuit that may indicate that a subsequent clock signal is needed. The controller circuit may send commands and receive status from the receiving circuit. | 08-20-2009 |
| 20090256615 | PULSE SIGNAL GENERATING DEVICE, TRANSPORT DEVICE, IMAGE FORMING APPARATUS, AND PULSE GENERATING METHOD - A pulse signal generating device includes: the plurality of encoders each of which outputs an encoder signal with a pulse period corresponding to the speed of an object to be detected; delay amount control unit that controls a relative delay amount with respect to a pulse signal for each of the plurality of pulse output signals output from the plurality of encoders; a detection unit that individually detects abnormalities in pulses of the plurality of encoder signals; a switching unit that performs switching to one pulse output signal, in which pulse abnormalities are not detected, of the plurality of pulse output signals; and a pulse generating unit that generates a pulse signal by delaying the one pulse output signal switched by the switching unit by the corresponding relative delay amount. | 10-15-2009 |
| 20100066425 | Synchronization detection circuit, pulse width modulation circuit using the same, and synchronization detection method - Provided is a synchronization detection circuit including: a multiphase clock generation circuit which includes a phase locked loop circuit that generates multiphase clock signals having a plurality of different phases, based on a reference clock signal, and which generates high-speed multiphase clock signals having a frequency obtained by multiplying a frequency of the reference clock signal, and low-speed multiphase clock signals having a frequency obtained by dividing a frequency of the high-speed multiphase clock signal; and a synchronous clock specifying circuit that specifies a clock signal synchronized with a synchronous signal from among the multiphase clock signals, and generates a synchronous position signal indicating a synchronous position of the synchronous signal, based on a comparison result between the synchronous signal and the high-speed multiphase clock signals and a comparison result between the synchronous signal and representative clock signals selected from the low-speed multiphase clock signals. | 03-18-2010 |
| 20100102869 | Apparatus and Method for Generating a Clock Signal - An apparatus and method are disclosed for generating one or more clock signals. A clock signal is generated based on pattern signals and a reference clock signal. When the reference clock signal transitions high, the state of a first pattern signal is output, and when the reference clock signal transitions low, the state of a second pattern signal is output. Successive states of the first and second pattern signals, selected according to the reference clock signal, provide the generated clock signal. | 04-29-2010 |
| 20100231283 | METHOD AND APPARATUS FOR PREVENTING PHASE INTERPOLATION CIRCUIT FROM GLITCH DURING CLOCK SWITCHING - The present invention relates to a method and an apparatus, during a phase switching process, for choosing all of outputted phases upon the clock phases devoid of phase switching so as to avoid glitches during clock switching. Compared with the conventional approach for removing glitches by controlling a clock switching sequence, an improvement of a phase rotator is further disclosed in the present invention, which eliminates the glitches of the outputted phase clock so as to realize a glitch-less phase switching in a phase interpolation circuit. | 09-16-2010 |
| 20100237924 | DIGITAL FREQUENCY SYNTHESIZER DEVICE AND METHOD THEREOF - A first plurality of clock signals including a first clock signal and a second clock signal is received, the first and second clock signal out of phase with each other. A second plurality of clock signals comprising a third clock signal and a fourth clock signal is received, the third and fourth clock signals out of phase with each other. A plurality of enable signals are received. A fifth clock signal is determined based on the first plurality of clock signals and the plurality of enable signals. A sixth clock signal is determined based on the second plurality of clock signals and the plurality of enable signals. A seventh clock signal is determined based on the fifth clock signal and the sixth clock signal. | 09-23-2010 |
| 20100315147 | PHASE MIXER WITH ADJUSTABLE LOAD-TO-DRIVE RATIO - Phase mixers, clock signal generators, memories and methods for providing an output signal having a phase relative to the phase difference of input clock signals are disclosed. One such phase mixer includes a phase mixer circuit having inputs and an output. The phase mixer is configured to receive a plurality of input clock signals and generate an output clock signal at the output having a phase relative to the plurality of input clock signals. The phase mixer further includes an adjustment circuit coupled to the phase mixer circuit. In some phase mixers, a control circuit coupled to the phase mixer circuit and the adjustment circuit is included. The control circuit is configured to generate a control signal based on the input signals to adjust an electrical load-to-drive ratio of the phase mixer. | 12-16-2010 |
| 20100315148 | LOW FREQUENCY OSCILLATOR FOR BURST-MODE DIMMING CONTROL FOR CCFL DRIVER SYSTEM - Oscillator system and method thereof. The oscillator system includes a first voltage-to-current converter configured to receive a first voltage and generate a first current based on at least information associated with the first voltage, and a second voltage-to-current converter configured to receive a second voltage and generate a second current based on at least information associated with the second voltage. Additionally, the oscillator system further includes a current-mode N-bit digital-to-analog converter configured to receive at least the second current and a first clock signal and to generate a third current based on at least information associated with the second current and the first clock signal. N is a first integer. The first clock signal is associated with a first clock frequency corresponding to a first clock period. Moreover, the oscillator system further includes a current comparator coupled to the first voltage-to-current converter and the current-mode N-bit digital-to-analog converter. | 12-16-2010 |
| 20100321081 | CLOCK CIRCUIT FOR A MICROPROCESSOR - A mobile communication device includes an analog clock and a digital clock circuit. The analog clock circuit is configured to generate an oscillating output. The digital clock circuit is configured to generate a digital clock output having a frequency that is substantially equal to the frequency of the oscillating output. | 12-23-2010 |
| 20110025395 | SYSTEM AND METHOD FOR COMPENSATING PULSE GENERATOR FOR PROCESS AND TEMPERATURE VARIATIONS - An apparatus for generating a pulse having a pulse width substantially independent of process variation in resistive and capacitive values. The apparatus includes a PTAT current source to generate a first current to charge a capacitor to produce a first voltage; a ΔVGS current source to generate a second current through a resistor to produce a second voltage V | 02-03-2011 |
| 20110128061 | Phase Generating Apparatus and Method Thereof - A phase generating apparatus generates an output clock having a desired phase according to a digital signal. The apparatus includes a phase selecting unit and a phase generating unit. The phase selecting unit selects one of a plurality of input clocks according to a portion of bits of the digital signal to generate a reference clock. Each of the input clocks respectively has a difference phase. The phase selecting unit divides the frequency of the reference clock, and selectively delays the frequency-divided reference clock according to another portion of bits of the digital signal to generate the output clock. | 06-02-2011 |
| 20110273215 | HIGH JITTER AND FREQUENCY DRIFT TOLERANT CLOCK DATA RECOVERY - In a method for recovery of a clock from a received digital data stream and an apparatus for recovering a clock from a received digital data stream, phase-shifted clock signals are generated from a receiver's clock. After selecting one of the phase-shifted clock signals, two other phase-shifted clock signals are determined. Depending on sample values taken at rising/falling edges of the three selected phase-shifted clock signals, counter values are increased and compared. The selection of phase-shifted clock signals and the steps of sampling the input digital data stream, comparing the values and increasing counter values, if required, are repeatedly performed until the comparison result of the counter values indicates that one of the latter determined phase-shifted clock signals strobes the received digital data stream in the centre of a bit period. | 11-10-2011 |
| 20110279161 | LOW FREQUENCY OSCILLATOR FOR BURST-MODE DIMMING CONTROL FOR CCFL DRIVER SYSTEM - Oscillator system and method thereof. The oscillator system includes a first voltage-to-current converter configured to receive a first voltage and generate a first current based on at least information associated with the first voltage, and a second voltage-to-current converter configured to receive a second voltage and generate a second current based on at least information associated with the second voltage. Additionally, the oscillator system further includes a current-mode N-bit digital-to-analog converter configured to receive at least the second current and a first clock signal and to generate a third current based on at least information associated with the second current and the first clock signal. N is a first integer. The first clock signal is associated with a first clock frequency corresponding to a first clock period. Moreover, the oscillator system further includes a current comparator coupled to the first voltage-to-current converter and the current-mode N-bit digital-to-analog converter. | 11-17-2011 |
| 20110304374 | METHODS AND APPARATUS FOR A GRAY-CODED PHASE ROTATING FREQUENCY DIVIDER - Methods and apparatus for a gray-coded phase rotating frequency divider. A phase selector is provided that includes two or more selectors, each selector configured to receive multiple clock phases and output a respective clock phase based on one or more selection bits that are part of a selection input, and a gray code generator configured to generate a gray coded output that forms the selection input so that when the gray coded output changes state only selection bits associated with a single selector change. A method includes grouping a plurality of clock phases into two or more groups, for each group, selecting a respective clock phase based on one or more selection bits that are part of a selection input, and generating a gray coded output that forms the selection input so that when the gray coded output changes state only selection bits associated with a single group change. | 12-15-2011 |
| 20120133410 | Clock Generation Circuit - A clock generation circuit, includes a first current source, a resistor connected to the first current source, a second current source, a first demux circuit connected to the second current source, a second demux circuit connected to the second current source, a capacitor connected to the first demux circuit and the second demux circuit, a first comparator connected to the first current source and the capacitor, a second comparator connected to the first current source and the capacitor, and a RS trigger connected both to the first comparator and the second comparator. The present invention has simple structure, small process variation, and lower cost, and is able to improve the accuracy of the clock with maximum possibility. | 05-31-2012 |
| 20120146702 | PHASE MIXER WITH ADJUSTABLE LOAD-TO-DRIVE RATIO - Phase mixers, clock signal generators, memories and methods for providing an output signal having a phase relative to the phase difference of input clock signals are disclosed. One such phase mixer includes a phase mixer circuit having inputs and an output. The phase mixer is configured to receive a plurality of input clock signals and generate an output clock signal at the output having a phase relative to the plurality of input clock signals. The phase mixer further includes an adjustment circuit coupled to the phase mixer circuit. In some phase mixers, a control circuit coupled to the phase mixer circuit and the adjustment circuit is included. The control circuit is configured to generate a control signal based on the input signals to adjust an electrical load-to-drive ratio of the phase mixer. | 06-14-2012 |
| 20120194250 | MULTIPLEXER CIRCUIT WITH LOAD BALANCED FANOUT CHARACTERISTICS - A multiplexer (MUX) circuit with balanced select line loading is provided. The MUX circuit includes a plurality of 2:1 MUX units coupled together in a multistage cascading arrangement, along with a selection module coupled to the MUX units. The MUX units are arranged in an initial MUX stage, at least one intermediate MUX stage coupled to and following the initial MUX stage, and a final MUX stage coupled to and following the at least one intermediate MUX stage. Each MUX unit is controlled with a respective select bit input value provided by the selection module. The selection module controls the operation of the MUX units in the initial MUX stage with a first plurality of different select bits, controls the operation of the MUX units in the at least one intermediate MUX stage with a second plurality of different select bits, and controls the operation of the final MUX stage with a devoted select bit. | 08-02-2012 |
| 20120194251 | RECEIVING APPARATUS, TEST APPARATUS, RECEIVING METHOD AND TEST METHOD - Provided is a receiving apparatus that receives a data signal and a clock signal indicating a reference timing to acquire the data signal. The receiving apparatus includes a multi-strobe generating section that generates, based on a pulse of the recovered clock, a plurality of strobes of which phases are different from each other, a first detecting section that detects a position of an edge of the clock signal relative to the strobes based on values of the clock signal that are acquired at respective timings of the strobe, a first adjusting section that adjusts a phase of the recovered clock according to the edge position of the clock signal, and a second adjusting section that adjusts the timing to acquire the data signal according to a phase adjustment amount of the recovered clock made by the first adjusting section. | 08-02-2012 |
| 20120306558 | Control of Digital Voltage and Frequency Scaling Operating Points - A clock signal for electronic circuitry is generated by generating, based on which one of a plurality of application use cases is presently active, a first signal that indicates a first selected one of a plurality of clock signal operating points. Based on the electronic circuitry's present speed requirement, a second signal is generated that indicates a second selected one of the clock signal operating points. For any given one of the application use cases, the speed requirement need not remain constant for the duration of the application use case. Based on whichever one of the first and second signals is associated with a higher clock frequency operating point, a third signal is generated that indicates which clock signal operating point (and possibly what voltage level) should be active. The third signal controls generation of a clock (and possibly also voltage level). | 12-06-2012 |
| 20130038370 | MULTI-PHASE CLOCK GENERATOR - A clock generator includes a first latch configured to output a first intermediate clock phase signal based on a first clock signal and a second intermediate clock phase signal. A first phase interpolation circuit has a first input coupled to a first input of the first latch and a second input coupled to a first output of the first latch. The first phase interpolation circuit is configured to output a first clock phase signal based on the first and second intermediate clock phase signals. | 02-14-2013 |
| 20130063197 | Switching Clock Sources - A clock-switching circuit having at least two inputs for receiving at least two different clock sources, an output for providing a selected one of the clock sources, and a switch for selecting the one of the inputs to provide on the output, the switch including elements that, prevent the providing of a truncated version of any of the clock sources on the output, always provide a clock signal on the output, and always maintain phase alignment and pulse ratio of the clock sources on the output. | 03-14-2013 |
| 20130113539 | CLOCK CIRCUIT FOR A MICROPROCESSOR - A mobile communication device includes an analog clock and a digital clock circuit. The analog clock circuit is configured to generate an oscillating output. The digital clock circuit is configured to generate a digital clock output having a frequency that is substantially equal to the frequency of the oscillating output. | 05-09-2013 |
| 20130187697 | MULTI-LEVEL HIGH VOLTAGE PULSER INTEGRATED CIRCUIT USING LOW VOLTAGE MOSFETS - A multi-level high-voltage pulse generator integrated circuit has a digital logic-level control interface circuit. A pair of complementary MOSFETs is controlled by the digital control interface circuit. A pair of supply voltage rails is provided, wherein one of the pair of supply voltage rails is connected to each of the pair of complementary MOSFETs. A pair of Zener diodes is provided, wherein one of the pair of Zener diodes is connected to each of the pair of complementary MOSFETs. A pair of resistors is provided, wherein one of the pair of resistors is connected in parallel with each of the pair of Zener diodes. A pair of complementary voltage blocking-MOSFETs having predetermined gate bias voltages is provided, wherein each of the pair complementary voltage blocking-MOSFETs is attached to a corresponding one pair of complementary MOSFETs. | 07-25-2013 |
| 20130307605 | Hybrid Dual Mode Frequency Synthesizer Circuit - A dual mode frequency synthesizer circuit including: a DDS or PLL ( | 11-21-2013 |
| 20140159792 | VOLTAGE GENERATION CIRCUIT - A voltage generation circuit includes an oscillator configured to output a first period signal and a second period signal in response to a detection signal; a period signal select unit configured to receive the first and second period signals and output one of the first and second period signals as an additional period signal in response to a control signal; and a charge pump unit configured to charge-pump an input voltage in response to the first period signal and the additional period signal and generate a power supply voltage. | 06-12-2014 |
| 20140176217 | SIGNAL COMPONENT REJECTION - A method includes providing a first local oscillator signal having a first duty cycle to a first mixer unit and providing a second local oscillator signal having a second duty cycle to a second mixer unit. At least one of the first duty cycle or the second duty cycle is greater than fifty percent. A frequency of the first local oscillator signal approximately equals a frequency of the second local oscillator signal. The method may also include generating a modulated output signal based on an output signal of the first mixer unit and based on an output signal of the second mixer unit. | 06-26-2014 |
| 20140176218 | LOW FREQUENCY OSCILLATOR FOR BURST-MODE DIMMING CONTROL FOR CCFL DRIVER SYSTEM - Oscillator system and method thereof. The oscillator system includes a first voltage-to-current converter configured to receive a first voltage and generate a first current based on at least information associated with the first voltage, and a second voltage-to-current converter configured to receive a second voltage and generate a second current based on at least information associated with the second voltage. Additionally, the oscillator system further includes a current-mode N-bit digital-to-analog converter configured to receive at least the second current and a first clock signal and to generate a third current based on at least information associated with the second current and the first clock signal. N is a first integer. The first clock signal is associated with a first clock frequency corresponding to a first clock period. Moreover, the oscillator system further includes a current comparator coupled to the first voltage-to-current converter and the current-mode N-bit digital-to-analog converter. | 06-26-2014 |
| 20140253204 | CLOCK SIGNAL GENERATOR MODULE, INTEGRATED CIRCUIT, ELECTRONIC DEVICE AND METHOD THEREFOR - A clock signal generator module arranged to generate at least one clock signal for at least one functional module is described. The clock signal generator module comprises a first clock source component associated with at least one functional module, at least one further clock source component associated with the at least one functional module, and at least one management unit arranged to controllably enable signal generation by the first and at least one further clock source components in accordance with at least one operating characteristic of the at least one functional module associated therewith. | 09-11-2014 |
| 20140300400 | COMPARATOR AND CLOCK SIGNAL GENERATION CIRCUIT - A comparator used in a clock signal generation circuit has first and second input transistors coupled to input signals of the comparator. First and second hysteresis transistors are coupled between the input transistors and an output stage of the comparator, and apply hysteresis to a comparison of the input signals. First and second hysteresis control transistors are coupled between the input transistors and the hysteresis transistors to isolate the hysteresis transistors from the input transistors under control of a hysteresis enable signal. | 10-09-2014 |
| 20150070068 | INTERNAL VOLTAGE GENERATOR AND METHOD OF GENERATING INTERNAL VOLTAGE - An internal voltage generator includes an internal voltage control unit suitable for generate an enable signal based on a voltage level of an internal voltage, a clock control unit suitable for generate a control clock having a restricted toggling period based on the enable signal and a clock while controlling the toggling number of the control clock, and an internal voltage generation unit suitable for generate the internal voltage based on the control clock. | 03-12-2015 |
| 20150333739 | LOW LATENCY GLITCH-FREE CHIP INTERFACE - A scheme is described that provides for a low latency, glitch free chip interface that does not require a clock. This invention handles input transitions that are skewed and also input transitions that are momentary. A change in an input state initiates a pulse that propagates through the system and samples the new input state after a delay. If there is a difference between the sampled input state and the present input state, then a new pulse is initiated in order to avoid any illegal transitions at the output. | 11-19-2015 |
| 20160116934 | CLOCK CIRCUIT FOR GENERATING CLOCK SIGNAL AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING THE SAME - A clock circuit for generating a clock signal includes a first clock generator configured to generate a first clock signal, a second clock generator configured to generate a second clock signal, and a selector connected to the first clock generator and the second clock generator. The selector is configured to select one of the first and second clock signals as a selected clock signal based on a selection signal. The selector is configured to transmit, if a selection of the selector changes from the second clock signal to the first clock signal, a turn-on request signal to at least one first component to enable the at least one first component. The at least one first component is configured to send a turn-on acknowledgement signal to the selector in response to the turn-on request signal. The first clock generator includes the at least one first component. | 04-28-2016 |
| 20160142045 | ASYNCHRONOUS CLOCK ENABLEMENT - An asynchronous clock enable system includes a clock generation device configured to generate a first clock signal to operate a target resource. The asynchronous clock enable system also includes a clock gating device coupled to the clock generation device to determine when the first clock signal achieves stability. The clock gating device generates a clock gating signal to enable the first clock signal when the first clock signal achieves stability. The clock gating device is asynchronous relative to the clock request signal. | 05-19-2016 |
| 20160204766 | METHOD AND APPARATUS FOR GENERATING A SPREAD-SPECTRUM CLOCK | 07-14-2016 |
| 20160380620 | Signal Generation and Waveform Shaping - Measures, including apparatus, methods and computer program products, for generating an output signal with a defined waveform shape are provided. A plurality of switched inductor arrangements are each connected in parallel to generate a combined output signal. Each of the switched inductor arrangements are selectively enabled, wherein the number of enabled switched inductor arrangements is varied to define a waveform shape of the combined output signal. | 12-29-2016 |
| 20190149180 | CIRCUIT FOR DETERMINING WHETHER AN ACTUAL TRANSMISSION WAS RECEIVED IN A LOW-VOLTAGE DIFFERENTIAL SENSING RECEIVER | 05-16-2019 |
