Class / Patent application number | Description | Number of patent applications / Date published |
327299000 | Single clock output with single clock input or data input | 76 |
20080258795 | LOW POWER OSCILLATOR - A CMOS low frequency oscillator circuit comprising an amplifier ( | 10-23-2008 |
20080265968 | CLOCK FREQUENCY DIFFUSING DEVICE - A clock frequency diffusing device including a multiphase clock signal generator, a random number generator, signal selectors, and a clock signal generator. The multiphase clock signal generator receives an input clock signal and produces a plurality of delayed clock signals that are delayed relative to the input clock signal by various amounts of time. The clock signal selector randomly chooses one of the delayed signals based upon random numbers generated by the random number generator and produces a selector output signal based on its chosen delayed clock signal. A clock signal generator receives the selector output signal and produces an output clock signal. | 10-30-2008 |
20080272820 | Circuit to Reduce Transient Current Swings During Mode Transitions of High Frequency/High Power Chips - A method, an apparatus, and a computer program are provided to reduce transient current swings during mode transitions. Traditionally, transient supply voltage fluctuations on a chip account for a large portion of the power supply. The number of series inductances and resistances are typically minimized, while adding large decoupling capacitances between the supply voltage and ground. However, situations may arise where reduction of series inductances and resistances cannot be accomplished. Therefore, to assist in controlling the transient current swings, reduction of clocking frequencies are performed in a controlled manner. | 11-06-2008 |
20080303576 | Clock Distribution Network Architecture with Resonant Clock Gating - Disclosed herein is a digital system that includes a distribution network to carry a reference clock, and a circuit domain coupled to the distribution network to receive the reference clock for synchronous operation in accordance with the reference clock. The circuit domain includes a clock generator driven by the reference clock to generate a resonant clock signal, an input port to receive a control signal, and a gate coupled to the input port to discontinue application of the resonant clock signal within the circuit domain based on the control signal. | 12-11-2008 |
20090039941 | METHOD AND CIRCUIT FOR GENERATING MEMORY CLOCK SIGNAL - A memory clock signal is generated in response to a reference clock signal and a clock enable signal. The memory clock signal with a frequency identical to that of the reference clock signal is generated during the clock enable signal is in an enabled state; and the memory clock signal with a reduced frequency is generated when the clock enable signal is changed from the enabled state to a disabled state. The generation of a memory clock signal is adaptive so as to save power. | 02-12-2009 |
20090085630 | ARBITRARY CLOCK CIRCUIT AND APPLICATIONS THEREOF - A clock circuit includes a waveform generator, a comparison module, and a clock signal module. The waveform generator is coupled to generate a waveform based on a reference oscillation. The comparison module is coupled to compare the waveform with a plurality of references to produce a plurality of waveform comparisons. The clock signal module is coupled to generate a clock signal from the plurality of waveform comparisons. | 04-02-2009 |
20090085631 | BUS CIRCUIT - Clock control is handed over in a bus circuit from a first circuit ( | 04-02-2009 |
20090121768 | Semiconductor device and operation method thereof - Semiconductor device and operation method thereof includes an aspect of the present invention, there is provided a clock generator configured to receive an external clock signal to generate a first clock signal corresponding to a rising edge of the external clock and a second clock signal corresponding to a falling edge of the external clock, a drive control signal generator configured to restrict an activation period of the first clock signal within a deactivation period of the second clock signal to generate a first drive control signal, and restrict an activation period of the second clock signal within a deactivation period of the first clock signal to generate a second drive control signal and an output driver configured to receive a drive data in response to the first and second drive control signal to drive an output terminal in response to the drive data. | 05-14-2009 |
20090167401 | Timing Signal Generator Providing Synchronized Timing Signals At Non-Integer Clock Multiples Adjustable By More Than One Period - A system for providing a plurality of synchronous timing signals having period values that are not even multiples of the clock period including a plurality of local edge generators receiving the clock signals, each local generator including local programmable means to record an absolute time at which to generate a timing signal in the current or future period and the means to generate that timing signal at a synchronous even sub-division of the clock period resolution. A separate time value is maintained allowing generated timing signals to be delayed by more than one period. An output delay circuit generates the timing signal responsive to a future time value and a phase offset. The phase offset can be provided using a clock multiplier and serial parallel converter to simplify hardware realizations. | 07-02-2009 |
20090179681 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage. | 07-16-2009 |
20090201064 | Phase Interpolator System and Associated Methods - A phase interpolator system is disclosed that may include a clock to provide a clock signal, and a control section in communication with the clock to regulate the strength of the clock signal. The system may also include a generator circuit to produce an alternate clock signal based upon the strength of the clock signal received from the control section. | 08-13-2009 |
20090201065 | Local signal generation circuit - A local signal generation circuit in accordance with one aspect of the present invention includes a phase comparator that detects a phase difference between a reference signal and a feedback signal and outputs a error signal, a charge-pump circuit that receives the error signal and generates a step-up voltage, a loop filter that generates a tuning voltage by changing the shape of the step-up voltage, a voltage control oscillator that generates a first output signal having a predefined frequency based on the tuning voltage, and a prescaler that outputs a second output signal generated by dividing the frequency of the first output signal to a predefined frequency and also outputs a frequency-division signal generated by dividing the frequency of the first output signal to the predefined frequency to a frequency divider that generates the feedback signal. | 08-13-2009 |
20090201066 | Digitally Clock with Selectable Frequency and Duty Cycle - A system and method are provided for controlling the duty cycle and frequency of a digitally generated clock. The method accepts a first clock signal having a fixed first frequency. A frequency control word with a first pattern is loaded into a first plurality of serially-connected registers. A duty cycle control word with a second pattern is loaded into a second plurality of serially-connected registers. A register clock signal is generated in response to the first clock and the first pattern. Then, a digital clock signal is generated having a frequency and duty cycle responsive to the register clock signal and the second pattern. | 08-13-2009 |
20090251190 | SYSTEM AND METHOD FOR GENERATING TWO EFFECTIVE FREQUENCIES USING A SINGLE CLOCK - A method and apparatus are disclosed for generating a second clock signal, having a second effective clock frequency, from a first clock signal, having a first effective clock frequency. Clock pulses of the first clock signal are counted to generate a count value. When the count value reaches a predetermined blanking value, a blanking signal is generated. The blanking signal blanks at least one clock pulse of the first clock signal. The process is repeated multiple times at a predetermined rate corresponding to the predetermined blanking value to generate the second clock signal. | 10-08-2009 |
20090284298 | METHOD FOR AUTOMATICALLY ADJUSTING CLOCK FREQUENCY AND CLOCK FREQUENCY ADJUSTING CIRCUIT - A method for automatically adjusting the clock frequency for a USB interface including the steps of: generating a clock signal with an adjustable frequency; receiving a USB differential signal; counting the clock signal based on each frame time of the USB differential signal and obtaining a count value; and adjusting the frequency of the clock signal when the count value exceeds a predetermined count range. The present invention further provides a clock frequency adjusting circuit. | 11-19-2009 |
20090295450 | Signal Processing Apparatus, Signal Processing System and Signal Processing Method - A signal processing apparatus is provided, which generates a data signal having a signal waveform corresponding to a first bit value of a signal waveform transitioning from a high level to a low level or a signal waveform transitioning from a low level to a high level, a pre-transition signal level corresponding to a second bit value of one of a plurality of high levels and a plurality of low levels, and a post-transition signal level corresponding to a third bit value of the other. | 12-03-2009 |
20090322400 | INTEGRATED CIRCUIT WITH NON-CRYSTAL OSCILLATOR REFERENCE CLOCK - An integrated circuit with a non-crystal reference clock includes: an oscillator adapted to generate and transmit an oscillator output signal, wherein the oscillator includes at least one of an inductor, a resistor, and a capacitor; a comparator adapted to receive the oscillator output signal and a calibration input signal, compare the oscillator output signal characteristics and the calibration input signal characteristics, and generate and transmit a first comparator signal in response to the comparison of the oscillator output signal and the calibration input signal, a state machine adapted to receive the first comparator signal, analyze the first comparator signal and calibrate the oscillator in response to the analysis of the first comparator signal, and a controller adapted to the receive the oscillator output signal, wherein a frequency of the oscillator output signal is utilized by the controller as a clock frequency. | 12-31-2009 |
20100127749 | PRECISION PULSE GENERATOR - A pulse generator circuit. The pulse generator circuit includes a precharge circuit coupled to receive a clock signal alternating between a first logic level and a second logic level, a storage circuit having a storage node, wherein the precharge circuit is configured to precharge the storage node when the clock signal is at the first logic level, a logic circuit having an output, a first input node coupled to receive the clock signal, and a second input node coupled to the storage node and configured to produce a pulse at the second logic level responsive to the clock signal transitioning to the second logic level, and a discharge circuit configured to discharge the storage node at a predetermined delay time subsequent to the clock signal transitioning to the second logic level, wherein the output of the logic circuit transitions to the first logic level responsive to discharging the storage node. | 05-27-2010 |
20100171540 | System and Method of Changing a PWM Power Spectrum - In a particular embodiment, a circuit device includes a pulse edge control circuit to receive at least one pulse-width modulated (PWM) signal from a PWM source. The pulse edge control circuit is adapted to selectively invert and swap the at least one PWM signal with a logic-inverted duty-cycle complement of the at least one PWM signal at discrete time intervals to produce at least one modulated PWM signal having a changed power spectrum. The pulse edge control circuit provides the at least one modulated PWM signal to at least one output of the pulse edge control circuit. | 07-08-2010 |
20100237925 | CLOCK DISTRIBUTION NETWORK - Some embodiments include apparatus and methods having a clock path with a combination of current-mode logic (CML) based and complementary metal-oxide semiconductor (CMOS) components. | 09-23-2010 |
20110012663 | CLOCK SIGNAL GENERATING ARRANGEMENT FOR A COMMUNICATION DEVICE - A clock signal generating arrangement for a communication device generates a system clock signal at an output for use as a timing reference. The clock signal generating arrangement comprises a reference clock generator for generating a reference clock signal, a main clock generator for generating a main clock signal having a greater accuracy than the reference clock signal, a clock adjust circuit coupled to the reference clock generator for generating a compensated reference clock signal to compensate for error in the reference clock signal and a clock signal selector coupled to the reference clock generator the main clock generator and the clock adjust circuit. The clock signal selector selectively provides to the output of the clock signal generating arrangement as the system clock signal the compensated reference clock signal when an error in the reference clock signal reaches a first predetermined threshold and until the error in the reference clock signal has been compensated and otherwise the reference clock signal when the communication device is operating in an idle mode or the main clock signal when the communication device is operating in an active mode. | 01-20-2011 |
20110050314 | DISPLAY LINK CLOCKING METHOD AND APPARATUS - An apparatus includes a clock circuit and a plurality of display interface circuits. The clock circuit provides a common clock signal. The display interface circuits each provide a respective display link clock signal in response to the common clock signal. One of the display link clock signals is at a different clock speed that another of the display link clock signals. | 03-03-2011 |
20110057702 | CHANGING AN OPERATING PERFORMANCE POINT - A method of changing an operating performance point of an integrated circuit including detecting a need to change the operating performance point of the integrated circuit to a new operating performance point. The method also includes changing a voltage of the integrated circuit to correspond with the new operating performance point, changing a maximal receiver clock frequency value to correspond with the new operating performance point, exporting the maximal receiver clock frequency value to a distant integrated circuit, and receiving an acknowledgement of the changed maximal receiver clock frequency value from the distant integrated circuit. | 03-10-2011 |
20110128062 | Low-Noise Fine-Frequency Tuning - Circuits, methods, apparatus, and code that provide low-noise and high-resolution electronic circuit tuning. An exemplary embodiment of the present invention adjusts a capacitance value by pulse-width modulating a control voltage for a switch in series with a capacitor. The pulse-width-modulated control signal can be adjusted using entry values found in a lookup table, by using analog or digital control signals, or by using other appropriate methods. The capacitance value tunes a frequency response or characteristic of an electronic circuit. The response can be made to be insensitive to conditions such as temperature, power supply voltage, or processing. | 06-02-2011 |
20110199142 | DOUBLE CLIPPED RF CLOCK GENERATION WITH SPURIOUS TONE CANCELLATION - A clock generator circuit generates a wanted RF clock signal by using an up-converter, a spurious tone cancellation circuit, a controller, and at least two clock driver/dividers. The spurious tone cancellation circuit includes a tone detection circuit and a tone generation circuit. The up-converter mixes modulation signals with local quadrature RF clock signals to create an up-converted signal having a frequency tone equal to a desired frequency of the wanted RF clock signal. The first clock driver/divider amplifies and clips the up-converted signal into a first-clipped clock signal. The tone detection circuit detects the amplitude and phase of unwanted tones of the first-clipped clock signal in the baseband domain and provides information to the controller, which controls the tone generation circuit to cancel the unwanted tones and create a compensated version of first-clipped clock signal. The second clock driver/divider further amplifies and clips the compensated version of first-clipped clock signal to generate the wanted RF clock signal. | 08-18-2011 |
20110199143 | INTERNAL CLOCK GENERATING CIRCUIT AND METHOD FOR GENERATING INTERNAL CLOCK SIGNAL WITH DATA SIGNAL - An internal clock generating circuit and a method for generating an internal clock signal are disclosed. The internal clock generating circuit includes a transition detecting block for detecting transitions in a data signal and generating data transition information, and an internal clock generating block for generating and storing a period digital data while detecting the unit period of the data signal in a period confirming mode. In the internal clock generating circuit, the internal clock signal can be generated without the external clock signal, so that the internal clock generating circuit can be implemented with a simple constitution. Additionally, an extra locking time is not required for locking the extra clock signal, so that the operating speed of the internal clock generating circuit is improved. The internal clock signal is dependent on the data signal, so that it is easy to control the set-up and hold for data. | 08-18-2011 |
20110234287 | FREQUENCY DETECTION MECHANISM FOR A CLOCK GENERATION CIRCUIT - A frequency detection mechanism for a clock generation unit on an integrated circuit includes a clock generation unit and a detection unit. The clock generation unit may generate an output clock signal at a predetermined frequency that corresponds to a frequency multiple of a reference clock signal provided as an input to the clock generation unit. The detection unit may determine whether the output clock signal is at the predetermined frequency. As such, the detection unit includes a first counter that may generate a first count value based upon the reference clock signal and a second counter that may generate a second count value based upon the output clock signal. The detection unit also includes comparison logic that may perform a plurality of multiplication operations on the first and second count values and generate a final result that indicates whether the output clock signal is at the predetermined frequency. | 09-29-2011 |
20110248764 | Clock Divider System and Method - In a particular embodiment, a single step increment calculation module is responsive to a first ramp control value and a second ramp control value. The single step increment calculation module generates a single step frequency adjustment as an output. The generated single step frequency adjustment is applied to a system clock signal having a first frequency to change the system clock signal to a second clock signal having a second frequency. The first frequency is different from the second frequency and the system clock signal has a first duty cycle that is within a tolerance range of a second duty cycle of the second clock signal. | 10-13-2011 |
20110260769 | ERROR-FREE STARTUP OF LOW PHASE NOISE OSCILLATORS - An isolation switch is used to isolate the output of an oscillator, during startup of the oscillator, from the circuitry that uses the periodic signal generated by the oscillator. In one implementation, a device may include an oscillator to generate a periodic signal and a switch connected to receive an output of the oscillator. The switch may include a control input that controls whether the switch is in an open or closed state. Switch control circuit may control the switch so that the switch is in an open state during startup of the oscillator and the switch is in a closed state thereafter. | 10-27-2011 |
20110285444 | OSCILLATOR CIRCUIT, METHOD FOR MANUFACTURING OSCILLATOR CIRCUIT, INERTIAL SENSOR USING THE OSCILLATOR CIRCUIT, AND ELECTRONIC DEVICE - An oscillator circuit includes an oscillator, a filter that filters a monitoring signal output from the oscillator and outputs the filtered signal, a driver that amplifies the filtered signal to generate a driving signal, and a controller operable to control a passing characteristic of the filter based on the monitoring signal. The oscillator performs a vibration while being driven by the driving signal, and outputs the monitoring signal according to the vibration. This oscillator circuit allows the oscillator to vibrate stably. | 11-24-2011 |
20110291732 | DIGITAL SIGNAL GENERATOR - The invention relates to a digital signal generator for providing one or more phases of a local oscillator signal for use in digital to analogue converters and harmonic rejection mixers. Embodiments disclosed include a local oscillator signal generator ( | 12-01-2011 |
20110309871 | SYSTEM AND DEVICE FOR GENERATING REFERENCE SIGNAL, AND TIMING SIGNAL SUPPLY DEVICE - Provided is a timing signal supply device that can frequently perform a phase comparison on a side of receiving a supply of a timing signal and flexibly achieve various operation modes. A GPS receiver | 12-22-2011 |
20120019301 | FREQUENCY DETECTION MECHANISM FOR A CLOCK GENERATION CIRCUIT - A frequency detection mechanism for a clock generation unit on an integrated circuit includes a clock generation unit and a detection unit. The clock generation unit may generate an output clock signal at a predetermined frequency that corresponds to a frequency multiple of a reference clock signal provided as an input to the clock generation unit. The detection unit may determine whether the output clock signal is at the predetermined frequency. As such, the detection unit includes a first counter that may generate a first count value based upon the reference clock signal and a second counter that may generate a second count value based upon the output clock signal. The detection unit also includes comparison logic that may perform a plurality of multiplication operations on the first and second count values and generate a final result that indicates whether the output clock signal is at the predetermined frequency. | 01-26-2012 |
20120025888 | Drive Strength Control of Phase Rotators - A phase rotator includes a phase selector stage operative to receive a clock signal and output a first phase and a second phase of the clock signal, a slew rate control stage including a first pass gate circuit operative to control a slew rate of the first phase of the clock signal and a second pass gate circuit operative to control a slew rate of the second phase of the clock signal, and a phase blending stage operative to combine the first phase with the second phase of the clock signal and output a phase rotated signal. | 02-02-2012 |
20120044005 | FAIL SAFE ADAPTIVE VOLTAGE/FREQUENCY SYSTEM - A system on chip (SoC) has a digital domain. An adaptive voltage/frequency scaling circuit includes a critical path replica circuit with respect to that digital domain. The critical path replica circuit generates a margin signal, and the adaptive voltage scaling circuit responds to the margin signal by decreasing bias voltage (and/or increasing clock frequency) applied to the digital domain of the system on chip so as to recover available margin. A fail-safe timing sensor is included within the digital domain of the system on chip. The timing sensor generates a flag signal when timing criteria within the digital domain are violated. The adaptive voltage scaling circuit responds to the flag signal by increasing the bias voltage (and/or decreasing the clock frequency) applied to the digital domain of the system on chip so as to implement a recovery operation. | 02-23-2012 |
20120062302 | PROPER FREQUENCY PLANNING IN A SYNTHETIC INSTRUMENT RF SYSTEM - A system and method for clocking in analog-to-digital (ADC) converter in a synthetic instrument unit is presented. A method begins by applying an input clock to an amplifier to produce an amplified clock. The amplified clock is filtered to produce a filtered clock. The ADC of this synthetic instrument unit is clocked with the filtered clock. The input frequency of the ADC corresponds to a second or higher order Nyquist zone that is above the sampling frequency of the ADC. The input data is carried by an intermediate frequency (IF) signal. The filtered clock of ADC is switched off a clock path of the ADC when the ADC is not in use. | 03-15-2012 |
20120081164 | Timing circuit and method of generating an output timing signal - A timing circuit and corresponding method are provided to generate an output timing signal in dependence on an input timing signal. The timing circuit comprises a plurality of circuit components, each circuit component configured to receive an input dependent on the input timing signal and to generate an output in dependence on that input. Each circuit component performs switching operations by switching its output level in response to a transition of its input level. Each circuit component exhibits a delay in switching its output level, the delay comprising a first delay associated with a first switching of its output level and a second delay associated with a second switching of its output level. The first switching is in an opposite direction to the second switching and the first delay and the second delay exhibit a change in magnitude as each circuit component repeatedly performs its switching operations. This change in magnitude is in opposite directions for the first delay and the second delay respectively, and the plurality of circuit components are arranged such that a timing of the output timing signal is dependent on both said first delay and said second delay, such that the effects of each on the timing of the output signal counteract one another. | 04-05-2012 |
20120086492 | FREQUENCY DOMAIN CLOCK RECOVERY - Consistent with an aspect of the present disclosure, an optical signal carrying data or information is supplied to photodetector circuitry that generates a corresponding analog signal. The analog signal may be amplified or otherwise processed and supplied to analog-to-digital conversion (ADC) circuitry, which samples the analog signal to provide a plurality of digital signals or samples. The timing of such sampling is in accordance with a clock signal supplied to the ADC circuitry. A phase detector is provided that detects and adjust the clock signal to have a desired phase based on frequency domain data that is output from a Fast Fourier transform (FFT) circuit that receives the digital samples. Preferably, the phase detector circuit is configured such that it need not receive all the frequency domain data output from the FFT at any given time in order to determine the clock phase. Rather, a subset of such data is supplied to the phase detector circuit, such that the phase detector has a simpler design, operates faster, and is computationally efficient. | 04-12-2012 |
20120086493 | METHOD AND DEVICE FOR MANAGING HANDHELD DEVICE POWER CONSUMPTION - A method and device for managing handheld device power consumption are disclosed. The method includes the following steps of: calculating an operating frequency needed by the function currently operated by the handheld device; and setting the system clock of the handheld device according to the operating frequency. | 04-12-2012 |
20120119809 | CLOCK CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME - An internal clock frequency control circuit of a semiconductor memory apparatus includes a mode register set configured to receive a mode register set control signal and output a mode register set signal; a delay unit configured to generate an enable signal when a predetermined cycle has elapsed after the mode register set signal was activated; a division command decoder configured to receive and decode a synchronization command to generate a division start signal when the enable signal is activated; and a division selection unit configured to receive an input clock having a first frequency and output a selection clock having a second frequency, wherein a value of the second frequency is substantially the same as the first frequency or lower than the first frequency depending on a level of the division start signal. | 05-17-2012 |
20120126872 | Adjusting PLL Clock Source to Reduce Wireless Communication Interference - Adjusting a phase locked loop (PLL) clock source to reduce wireless communication (e.g., radio frequency (RF)) interference within a device. The PLL may be included in a high speed serial interface, e.g., coupled to a display, and may be initially driven by a first clock. Later, when a second clock is available and aligned with the first clock, the PLL may be driven by the second clock. The second clock may be configured to change its frequency over time such that the PLL does not lose lock and also does not interfere (or reduces interference) with wireless communication of the device. For example, the second clock may be programmable or may dynamically vary its operating frequency, thereby reducing its interference with the wireless communication of the device. | 05-24-2012 |
20120154010 | SYSTEMS AND METHOD FOR SPUR SUPRESSION IN A MULTIPLE RADIO SoC - A digital system includes a spur calculator that computes harmonics of a frequency of a digital clock signal and that identities a harmonic that lies in a frequency band of operation of a radio frequency circuit. A duty cycle computation module receives the harmonic and computes a duty cycle for the harmonic. Further, a clock generator that is coupled to the duty cycle computation block generates a digital clock signal of the frequency and with the duty cycle such that amplitude of spur caused due to the harmonic is suppressed. | 06-21-2012 |
20120154011 | METHOD AND APPARATUS FOR PHASE SELECTION ACCELERATION - A method and apparatus for generating a clock that can be switched in phase within a reduced interval of dead time are disclosed. | 06-21-2012 |
20120161842 | CLOCK SIGNAL SUPPLYING METHOD AND CIRCUIT FOR SHIFT REGISTERS - A clock signal supplying method for shift registers includes following steps: receiving a clock signal; and transmitting the clock signal to two first stage signal transmission paths simultaneously, the first stage signal transmission paths determined by a first control signal whether to be conducted, and further conducted at different time. | 06-28-2012 |
20120182059 | SEAMLESS COARSE AND FINE DELAY STRUCTURE FOR HIGH PERFORMANCE DLL - A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at the boundary of the coarse and fine delays. The system may use a delay line configured to generate two intermediate clocks from the input reference clock and having a fixed phase difference therebetween. A phase mixer receives these two intermediate clocks and generates the final output clock having a phase between the phases of the intermediate clocks. The shifting in the delay line at high clock frequencies does not affect the phase relationship between the intermediate clocks fed into the phase mixer. The output clock from the phase mixer is time synchronized with the input reference clock and does not exhibit any jitter or noise even at high clock frequency inputs. Because of the rules governing abstracts, this abstract should not be used to construe the claims. | 07-19-2012 |
20120187997 | CIRCUIT AND METHOD FOR PROVIDING ABSOLUTE INFORMATION FOR FLOATING GROUNDED INTEGRATED CIRCUIT - The present invention discloses a circuit and a method for providing absolute information for floating grounded integrated circuit. The method includes: receiving an absolute information sense signal carrying absolute information; converting the absolute information sense signal to a current signal; and generating an internal reference signal according to the current signal, wherein the internal reference signal or a relationship between the internal reference signal and a floating ground level is related to the absolute information. | 07-26-2012 |
20120235725 | Interface for MEMS inertial sensors - In a high-performance interface circuit for micro-electromechanical (MEMS) inertial sensors, an excitation signal (used to detect capacitance variation) is used to control the value of an actuation signal bit stream to allow the dynamic range of both actuation and detection paths to be maximized and to prevent folding of high frequency components of the actuation bit stream due to mixing with the excitation signal. In another aspect, the effects of coupling between actuation signals and detection signals may be overcome by performing a disable/reset of at least one of and preferably both of the detection circuitry and the MEMS detection electrodes during actuation signal transitions. In a still further aspect, to get a demodulated signal to have a low DC component, fine phase adjustment may be achieved by configuring filters within the sense and drive paths to have slightly different center frequencies and hence slightly different delays. | 09-20-2012 |
20120235726 | Interface for MEMS intertial sensors - In a high-performance interface circuit for micro-electromechanical (MEMS) inertial sensors, an excitation signal (used to detect capacitance variation) is used to control the value of an actuation signal bit stream to allow the dynamic range of both actuation and detection paths to be maximized and to prevent folding of high frequency components of the actuation bit stream due to mixing with the excitation signal. In another aspect, the effects of coupling between actuation signals and detection signals may be overcome by performing a disable/reset of at least one of and preferably both of the detection circuitry and the MEMS detection electrodes during actuation signal transitions. In a still further aspect, to get a demodulated signal to have a low DC component, fine phase adjustment may be achieved by configuring filters within the sense and drive paths to have slightly different center frequencies and hence slightly different delays. | 09-20-2012 |
20120262215 | TIMING GENERATOR AND TEST APPARATUS - A timing generator that outputs a timing signal obtained by delaying an input signal, comprising first and second period delay sections that each output a rate signal obtained by delaying the input signal by a delay amount corresponding to an integer multiple of a period of an operation clock supplied thereto; a first high-accuracy delay section that outputs the timing signal obtained by delaying a signal input thereto by a delay amount that is less than the period of the operation clock; and a mode switching section that switches between a low-speed mode, in which the rate signal output by the first period delay section is input to the first high-accuracy delay section, and a high-speed mode, in which a signal obtained by interleaving the rate signals output by the first period delay section and the second period delay section is input to the first high-accuracy delay section. | 10-18-2012 |
20120280737 | SIGNAL DELAY CIRCUIT, CLOCK TRANSFER CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME - A signal delay circuit including a clock transfer control circuit configured to transmit or block a clock signal, and a pulse signal generation circuit configured to delay a first pulse signal in response to the transmitted clock signal to generate a second pulse signal which has a longer active period than the first pulse signal. | 11-08-2012 |
20130009687 | SEMICONDUCTOR DEVICE, RADIO COMMUNICATION TERMINAL USING SAME, AND CLOCK FREQUENCY CONTROL METHOD - A semiconductor device | 01-10-2013 |
20130021080 | CLOCK DISTRIBUTION NETWORK - Some embodiments include apparatus and methods having a clock path with a combination of current-mode logic (CML) based and complementary metal-oxide semiconductor (CMOS) components. | 01-24-2013 |
20130038371 | SCAN TESTING - An electronic system is configured for scan testing, with a clock distribution network going to a plurality of blocks of the system, and a test capture clock being generated locally at each block. Capture clock pulses may optionally be generated at different times for different blocks, and may optionally be suppressed for some blocks. | 02-14-2013 |
20130127511 | Method, Apparatus and System for Sensing a Signal With Automatic Adjustments for Changing Signal Levels - The present specification provides a method, apparatus and system for sensing a signal with automatic adjustments for changing signal levels. A novel fractional peak discriminator circuit is provided which can be incorporated into a system for measuring periodic signals from moving elements. The circuit can be used regardless of whether the periodic signals are detected using optics, magnetic detector or other methods. | 05-23-2013 |
20130181760 | METHOD AND APPARATUS FOR GENERATING ON-CHIP CLOCK WITH LOW POWER CONSUMPTION - A fully on-chip clock generator on an integrated circuit (“IC”) includes a frequency detector for receiving a reference current and providing a first voltage; an error integrator for receiving the first voltage from the frequency detector, comparing it with a reference voltage, and providing a control voltage; a voltage controlled oscillator (“VCO”) for receiving the control voltage from the error integrator, and providing an output clock; and a logic controller on the IC, coupled between the VCO and the frequency detector, and generating logic control signals for controlling the frequency detector. The fully on-chip clock generator requires no external crystal, but its power consumption is significantly lower than a relaxation oscillator that generates the same clock frequency. | 07-18-2013 |
20130187698 | HIGH FREQUENCY SWITCHING CIRCUIT AND METHOD OF CONTROLLING THE SAME - There is provided a high frequency switching circuit reducing power consumption at the time of signal reception and signal transmission. The high frequency switching circuit includes a pulse generation unit generating a clock selecting pulse signal having a predetermined active period; a clock selection unit selecting a reference clock signal when the clock selecting pulse signal is in an active state and selecting a low-speed clock signal having a frequency lower than that of the reference clock signal when the clock selecting pulse signal is not in an active state; a voltage down unit accumulating negative charges in a capacitor to generate predetermined negative voltage; and a switching unit including at least one switch holding a turned-off state by being applied with the predetermined negative voltage. | 07-25-2013 |
20130222034 | High Speed Pulse Shaping Technology - A circuit adapted to generate a high speed shaped pulse comprising an input adapted to receive a data signal and a control signal. A plurality of logic elements are configures to receive the data signal and the control signal and generate a plurality of output signals representative of the shaped pulse. A digital to analog converter is adapted to receive the plurality of output signals and generate a shaped pulse. | 08-29-2013 |
20130234772 | CLOCK SUPPLY CIRCUIT - A circuit that supplies a clock signal to a load having a clock input section capable of suppressing power consumption is disclosed. A clock generating section generates a clock signal having an amplitude corresponding to an absolute value of an electric potential difference between a lower limit of a high-level input voltage V | 09-12-2013 |
20130265093 | OSCILLATOR CIRCUIT FOR GENERATING CLOCK SIGNAL - An oscillator circuit includes a charge current source and first and second muxes. The first mux has a common node, a discharge node, a control node and a charge node coupled to the charge current source. The control node couples the common node to either the discharge or charge nodes. The second mux has a shared node, a reference node, a control node and a ground node coupled to ground. The second mux control node couples the shared node to either the reference or ground nodes. A capacitor is coupled between the common node and the shared node. A comparator has a non-inverting input coupled to the common node, an inverting input coupled to the reference node, and an output coupled to the first and second control nodes. A discharge current sink couples the discharge node to ground and an oscillator output is provided by the comparator. | 10-10-2013 |
20140002169 | EARLY NOTIFICATION OF POWER LOSS IN THREE PHASE METER | 01-02-2014 |
20140002170 | SAMPLING CLOCK GENERATOR CIRCUIT, AND IMAGE READER AND ELECTRONIC DEVICE INCORPORATING THE SAME | 01-02-2014 |
20140035648 | TIMER MATCH DITHERING - A counter/timer circuit and a method of operating the counter/timer circuit are described. In one embodiment, a method of operating a counter/timer circuit involves determining a match condition by comparing a count value of the counter/timer circuit with a value stored in a match register of the counter/timer circuit and delaying an assertion of the match condition based on a value programmed in a match companion register of the counter/timer circuit. The match companion register is associated with the match register. Other embodiments are also described. | 02-06-2014 |
20140035649 | TUNED RESONANT CLOCK DISTRIBUTION SYSTEM - A tunable clock distribution system that includes a clock network including an inductive circuit and a capacitive circuit where at least one of the capacitive circuit or the inductive circuit is tunable. The tunable clock distribution system may further include a driving circuit and a phase determiner. The driving circuit may be configured to receive a clock signal and to distribute a resonant clock signal based on the clock signal to the clock network. The phase determiner may be configured to receive the clock signal and the resonant clock signal and to determine whether the clock signal and the resonant clock signal have a predetermined phase difference. When the clock signal and the resonant clock signal do not have the predetermined phase difference, the phase determiner may be configured to tune at least one of the capacitive circuit or the inductive circuit. | 02-06-2014 |
20140035650 | LOW-LATENCY, FREQUENCY-AGILE CLOCK MULTIPLIER - In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock. | 02-06-2014 |
20140043083 | PULSE GENERATOR - Provided is a pulse generator that generates a pulse signal with a preferred waveform and offers increased isolation for a period of time when the pulse signal is not output. | 02-13-2014 |
20140118047 | Method and Apparatus for Clock Transmission - Apparatus and methods are provided for an extraction circuit. In one configuration, an apparatus includes: an edge extraction circuit for receiving a first clock signal and outputting a second clock signal, wherein a duty cycle of the second clock is substantially smaller than a duty cycle of the first clock; a transistor for receiving the second clock signal and outputting a current signal; a transmission line for receiving the current signal on a first end and transmitting the current signal to a second end; a termination circuit for receiving the current signal at the second end and converting the current signal into a voltage signal; and an edge detection circuit for outputting a third clock by detecting an edge of the voltage signal. In one embodiment, the edge detection circuit comprises an inverter. In another embodiment, the edge detection circuit comprises a comparator. | 05-01-2014 |
20140145774 | Microcontroller with Digital Clock Source - A microcontroller has a numerical controlled oscillator receiving a primary clock signal and is configured to provide an internal system clock of the microcontroller. A method for operating a microcontroller performs the following steps: Selecting a primary clock signal from a plurality of clock signals; feeding the primary clock signal to a numerical controlled oscillator; configuring the numerical controlled oscillator to generate a numerical controlled clock signal; and providing the numerical controlled clock signal as an internal system clock for the microcontroller. | 05-29-2014 |
20140159793 | SYSTEM CLOCK MATCHING - A method for a control device comprising a processing device, an I/O module and a clock generator for providing a system clock, wherein the processing device and the I/O module are designed to operate with the system clock of the clock generator, comprises the steps of determining that capacity utilization of the processing device is exceeding a predetermined threshold, of determining that the I/O module is in a state in which a change in the system clock is uncritical, and of changing the system clock in order to match the performance capacity of the processing device to the capacity utilization. | 06-12-2014 |
20140218094 | Method and Circuit Arrangement for Converting a Sine Wave Signal into a Square Wave Signal - A method for converting a sine wave signal into a square wave signal includes inputting the sine wave signal at an input of a threshold-value device that generates the square wave signal. The square wave signal is generated by comparing a sine wave signal value to a predefined threshold value, and the square wave signal is output at an output of the threshold-value device. An actuating signal is superposed on the sine wave signal at the input of the threshold-value device. The actuating signal is generated by forming an average-value signal representing an average value of the square wave signal and inputting the average-value signal at an input of a control amplifier device for generating, as the actuating signal, a signal representing a difference between an average-value signal actual value and a predefined average-value signal nominal value. | 08-07-2014 |
20140354340 | FAST SETTLING CHARGE PUMP WITH FREQUENCY HOPPING - Embodiments provide, among other things, a circuit including a frequency generator and a charge pump. In embodiments, the frequency generator may be configured to provide the charge pump with a clock signal at a first frequency for a predefined period of time. Thereafter, the frequency generator may provide the charge pump with a clock signal at one or more other frequencies. In embodiments, the first frequency may enable the charge pump to settle in a reduced period of time when compared with the one or more other frequencies. | 12-04-2014 |
20140354341 | CHIP INSTRUMENTATION FOR IN-SITU CLOCK DOMAIN CHARACTERIZATION - Chip instrumentation determines, in-situ, an allowable increase over product specification in the operating frequency of at least one clock domain in an integrated circuit for a given set of environmental, power supply and/or functionality constraints. Information on the allowable increase in operating frequency for the at least one clock domain is provided to circuits and/or software to effect change in operating frequency. | 12-04-2014 |
20140361822 | FINE PULSE GENERATOR AND METHOD FOR GENERATING FINE PULSE - There are provided a pulse generator capable of securing a maximum transfer rate of an IR-UWB signal, while maintaining low power consumption characteristics of an all-digital scheme, and a method for generating a fine pulse. A bandwidth of a fine pulse is determined by adjusting a difference in delay time between two adjacent pulses and a pulse is generated by selecting only one of a rising edge and a falling edge of an input pulse, and thus there is no need to remove an unnecessary batch of pulses afterwards and a transfer rate is enhanced. | 12-11-2014 |
20150333743 | CURRENT MODE LOGIC CIRCUIT WITH MULTIPLE FREQUENCY MODES - A device comprising a clock circuit, a control circuit, and a current mode logic (CML) circuit is disclosed. The clock circuit provides a first differential clock signal and the control circuit generates a control signal based at least in part on the frequency of the first differential clock signal. The CML circuit generates a second differential clock signal based at least in part on the first differential clock signal. The CML circuit operates in one of a plurality of different frequency modes based at least in part on the control signal and includes a number of variable resistors that are responsive to the control signal. | 11-19-2015 |
20160109899 | Induction-Coupled Clock Distribution for an Integrated Circuit - An integrated circuit package including an induction-coupled clock distribution system is disclosed. An exemplary embodiment of the disclosure includes a transmission module coupled to a main clock line, a clock reception module coupled to the transmission module, the clock reception module including a clock output line, and an electronic circuit coupled to the clock output line of the clock reception module, the electronic circuit including at least one clocked element and configured to operate synchronously with a clocking signal received through the clock output line of the clock reception module. The transmission module may be disposed on the supporting case of the IC package, and the electronic circuit and the clock reception module may be disposed on the semiconductor die of the IC package. | 04-21-2016 |
20160164520 | POWER MANAGEMENT SYSTEM FOR INTEGRATED CIRCUITS - A power management circuit for integrated circuits operating systems where the power supply may be marginal includes a supply voltage characterization circuit and a clock synthesis circuit. The supply voltage characterization circuit determines the strength of the supply voltage applied to the IC and provides information to the synthesis circuit that is used to adjust the clock frequency of the IC to insure the IC does not draw too much current and force the IC into reset. A counter is used to determine the time between when the supply voltage reaches a first level and a second higher level, the time being representative of the slope of the supply voltage. Knowledge of the characteristics of a portion of the circuit under certain operating or benchmark conditions may be used to adjust the characterization. | 06-09-2016 |
20160378133 | CURRENT SENSOR BASED CLOSED LOOP CONTROL APPARATUS - A method and apparatus for performing current control for an integrated circuit are described. In one embodiment the apparatus comprises core logic coupled to receive a first current; a clock generator to generate a first clock signal; and a closed loop current controller coupled to the clock generator and coupled to provide a second clock signal to the core logic based on the first clock signal, the current controller to control an amount of the first current received by the core logic by changing the first clock signal to generate the second clock signal. | 12-29-2016 |