Entries |
Document | Title | Date |
20080246519 | GATE DRIVE CIRCUIT - A gate drive circuit including dead time control circuits delaying on periods of switching elements S | 10-09-2008 |
20080309383 | Semiconductor Integrated Circuit - A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an external clock signal. The internal clock signal is used for a synchronous operation of an internal circuit. Even if an error (undesired variation) occurs in the oscillation characteristic of the oscillator circuit due to process variations, it is possible to cause an internal clock signal frequency to coincide with an external clock signal frequency corresponding to a target frequency without the need for external attachment of a crystal oscillator and the input of an external clock signal. | 12-18-2008 |
20090015301 | CONTROLLING TIMING DEPENDENCIES IN A MIXED SIGNAL SYSTEM-ON-A-CHIP (SOC) - The claimed subject matter provides systems and/or methods that facilitate controlling timing dependencies in a mixed signal circuit. Timing performance associated with a horizontal scanner and an analog to digital converter (ADC) can be monitored. Moreover, data related to the monitored timing performance can be leveraged to modify timing parameter(s) of clocks that coordinate operations of the horizontal scanner and the ADC (e.g., and/or digital component(s) included in the mixed signal circuit). For example, the clocks associated with the horizontal scanner and the ADC can be independently tuned to optimize mixed signal circuit performance. | 01-15-2009 |
20090066377 | PULSE WIDTH MODULATION CIRCUIT AND SWITCHING AMPLIFIER USING THE SAME - A pulse width modulation circuit of the present invention changes a voltage of a charging circuit based on an input signal voltage and in synchronization with a first switching signal; changes, during a predetermined second period following a first period during which the voltage of the charging unit is changed, the voltage of the charging unit in an opposite direction to a direction in which the voltage is changed during the first period, based on a constant bias current; detects time starting from when the second period starts to when the voltage of the charging unit reaches a predetermined reference voltage; and generates, based on the detected time which is repeatedly output each time the first switching signal is output, a pulse signal having a pulse width of the time. | 03-12-2009 |
20090115468 | Integrated Circuit and Method for Operating an Integrated Circuit - An integrated circuit, comprising a first data retention element configured to retain the data, the first data retention element having a first setup time, and a second data retention element configured to retain the data, the second data retention element having a second setup time, the second data retention element further having a data input. The second data retention element is connected in parallel with the first data retention element, and the second data retention element is configurable via the data input such that the second setup time is longer than the first setup time. | 05-07-2009 |
20090153202 | SYNCHRONIZATION CIRCUIT - A synchronization circuit includes a first flip-flop circuit to hold an input signal which is asynchronous to a clock signal by the clock signal, and output an output signal, a second flip-flop circuit to hold the input signal by a signal of an opposite phase to the clock signal and output a signal, a comparing unit to compare the input signal and the output signal of the first flip-flop circuit and output a signal with a high or low level depending on whether the input signal and the output signal of the first flip-flop circuit have the same level, a selection unit to select one of the output signal of the first flip-flop circuit and the output signal of the second flip-flop circuit depending on the level of the signal outputted by the comparing unit, and a third flip-flop circuit to output the output signal selected by the selection unit. | 06-18-2009 |
20090160504 | METHODS AND SYSTEMS FOR SYNCHRONIZING A CONTROL SIGNAL OF A SLAVE FOLLOWER WITH A MASTER SOURCE - A method for synchronizing a slave follower with a master source is provided. The method includes defining a relationship between the master source and the slave follower, inputting a first position of the master source, and inputting a first position of the slave follower. The method also includes defining a second position where the slave follower synchronizes with the master source, and fitting a curve between the first position of the slave follower the second position. The curve is fit based on the relationship between the master source and the slave follower, the first position of the slave follower, the first position of the master source, and the second position. The curve is fit to synchronize the slave follower and the master source without exceeding pre-determined boundaries of the slave follower. | 06-25-2009 |
20090195272 | Data transmission system for exchanging multi-channel signals - A receiver circuit is provided with: a plurality of input terminals; a plurality of hold circuits holding reception signals received by the plurality of input terminals; a detector circuit detecting clock bits from selected one of the reception signals to recover a clock signal in response to the detected clock bits; and a clock circuit connected to the detector circuit and generating one or more internal clock signals from the clock signal. The hold circuits commonly receive the internal clock signal(s) and perform sampling of the reception signals commonly in synchronization with the internal clock signal(s). | 08-06-2009 |
20090224809 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR EVALUATING AN EYE-OPENING MARGIN - An eye-opening margin measurement method for a high-speed serial data reception circuit which uses a circuit for eye-opening margin measurement involving operation of a clock data recovery circuit without fixing the clock phase. In this method, an error acceleration test can also be made on received data by giving an offset pulse signal to phase information to add a jitter component. The method uses a semiconductor integrated circuit device which includes a serializer/deserializer circuit (SerDes) for receiving serial data and a reference serializer/deserializer circuit (Ref_SerDes) for receiving an accompanying clock signal. The SerDes circuit converts received serial data into parallel data through a recovery clock whose phase is controlled using phase control signal P_CS generated by the Ref_SerDes circuit. An offset pulse signal Offset_Pulse from the pulse-forming circuit is applied to the phase control signal P_CS to make eye-opening margin measurement. | 09-10-2009 |
20090261869 | CLOCK DOMAIN DATA TRANSFER DEVICE AND METHODS THEREOF - Two clock domains of a data processing device are each synchronized with a different clock signal. The clock signals are generated by clock generation logic. The clock generation logic also generates a transfer enable signal based on the relative frequency of each clock signal to indicate when data can be transferred between the clock domains. Further, as the relative frequency of the clock signals change, the timing of the transfer enable signal also changes to ensure reliable data transfer. | 10-22-2009 |
20090267657 | METHOD AND APPARATUS FOR DIVIDER UNIT SYNCHRONIZATION - A method an apparatus for synchronizing phases of one or more divider units comprise powering on a master divider unit to provide a reference signal. A phase of a slave divider unit is synchronized to the reference signal from the master divider unit by providing a power on pulse at the slave divider unit, synchronizing the phase of the slave divider unit to the reference signal using a digitally controlled oscillator, and powering on the slave divider unit after a first predetermined delay period following a rising edge of the power on pulse. By synchronizing a slave divider unit to the reference signal from the master divider unit, any number of slave divider units may be powered on and in-phase with each other. | 10-29-2009 |
20090267658 | Synchronizing Frequency and Phase of Multiple Variable Frequency Power Converters - In an embodiment, a power converter system includes a plurality of variable frequency power converters and a plurality of synchronization circuits. Each variable frequency power converter has a switching frequency. Each synchronization circuit is associated with a respective one of the plurality of variable frequency power converters. A control circuit is coupled to and coordinates the plurality of synchronization circuits. The plurality of synchronization circuits and the control circuit are operable to synchronize the switching frequencies of the variable frequency power converters to each other. Each synchronization circuit is operable to: receive a first input signal indicative of the beginning of a switching period for the associated variable frequency power converter; receive a second input signal indicative of the end of the switching period for the associated variable frequency power converter; generate a first output signal for directing a pulse width modulation of the associated variable frequency power converter; and generate a second output signal for coordinating a phase relationship with another variable frequency power converter in the system. | 10-29-2009 |
20090278576 | CRITICAL PATH MONITOR FOR AN INTEGRATED CIRCUIT AND METHOD OF OPERATION THEREOF - A path monitor, a method of monitoring a path, an integrated circuit and a library of standard logic elements. In one embodiment, the path monitor includes: (1) a delay element having an input couplable to an input of a clocked flip-flop associated with a path to be monitored and configured to provide a predetermined delay and (2) a clocked exclusive OR gate having a clock input, a first input coupled to an output of the delay element, a second input couplable to the output of the clocked flip-flop and an output at which the clocked exclusive OR gate is configured to respond to a clock signal to provide an error signal only when logic levels of the first input and the second input differ. | 11-12-2009 |
20090302901 | Command decoder and command signal generating circuit - A command decoder generates a command signal based on first to fourth control signals in response to a second chip select signal generated by delaying a first chip select signal for a predetermined interval. | 12-10-2009 |
20100026350 | CLOCK DATA RECOVERY DEVICE - A clock/data recovery device | 02-04-2010 |
20100039147 | SEMICONDUCTOR DEVICES WITH SIGNAL SYNCHRONIZATION CIRCUITS - Semiconductor devices are disclosed providing synchronization circuits for synchronized signal distribution for a plurality of devices in a semiconductor device. The synchronization apparatus includes an independent synchronization circuit and a dependent synchronization circuit. The independent synchronization circuit may be configured to receive a source signal and to generate a first destination signal substantially synchronized with the source signal. The dependent synchronization circuit may be coupled to the independent synchronization circuit and configured to receive the source signal and to generate a second destination signal substantially synchronized with the source signal. | 02-18-2010 |
20100060329 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a clock input unit configured to receive a system clock and a data clock externally; a phase dividing unit configured to generate a plurality of multi-system clocks in response to the system clock, wherein each of the multi-system clocks has an individual phase difference; a phase detecting unit configured to detect phase differences between the plurality of multi-system clock and the data clock and to generating generate a training information signal in response to the detection result; and a signal transmitting unit configured to transmit the training information signal. | 03-11-2010 |
20100097107 | TWO-PHASE CLOCK-STALLING TECHNIQUE FOR ERROR DETECTION AND ERROR CORRECTION - One embodiment of the present invention provides a system that augments a circuit design with a mechanism for detecting and correcting timing errors. This system first partitions the circuit into a set of blocks that are clocked by an independent clock source, and integrates an error signal propagation circuit between the set of blocks. For a respective block, the system determines a set of internal registers that are to be implemented as double data sampling registers, and replaces the determined set of internal registers with double data sampling registers, wherein a given double data sampling register is configured to generate an error signal when it detects a timing error. Then, the system integrates a two-phase error correction circuit into the respective block, wherein when notified of a timing error by a double data sampling register, the two-phase error correction circuit is configured to stall registers in the respective block. | 04-22-2010 |
20100097108 | SEMICONDUCTOR DEVICE - A semiconductor device having a nonvolatile variable resistor, includes: a resistance value conversion circuit unit configured to convert a resistance value of the nonvolatile variable resistor into a potential or a current and which outputs the converted potential or current; a comparison circuit unit configured to compare the output from the resistance value conversion circuit unit and a potential or current at a node of a portion within the semiconductor device; and a resistance value changing circuit unit configured to change the resistance value of the nonvolatile variable resistor based on the comparison results from the comparison circuit unit. | 04-22-2010 |
20100117691 | OSCILLATOR PRESCALE CALIBRATION FOR HARMONIZING MULTIPLE DEVICES WITH INDEPENDENT OSCILLATORS OVER AN I2C BUS INTERFACE - A system and method for synchronizing otherwise independent oscillators private to I | 05-13-2010 |
20100141308 | METHOD AND DEVICE FOR CLOCK-DATA RECOVERY - A method for the recovery of a clock signal from a data signal is provided where the edges of the signals are each represented as a chronologically-ordered sequence of timing points. In one procedural stage, a plurality of timing points of the data signal are processed in parallel as follows: resolving the timing points of the data signal by a nominal clock pulse; estimating the bit-period deviations for the adjusted timing points; and injecting the nominal clock pulse to the estimated bit-period deviations. | 06-10-2010 |
20100188122 | SYNCHRONIZING AN INVERTER WITH AN ALTERNATING VOLTAGE SOURCE - A method and device are disclosed for synchronizing an inverter with an alternating voltage source. The method includes measuring a current generated by the alternating voltage source and flowing through diodes of the inverter, determining a phase angle and angular velocity relating to the alternating voltage source from the measured current for enabling synchronization between the inverter and the alternating voltage source, and starting modulation of the inverter according to the obtained phase angle and angular velocity. | 07-29-2010 |
20100271084 | SOUCE-SYNCHRONOUS DATA LINK FOR SYSTEM-ON-CHIP DESIGN - A method of producing an integrated circuit ( | 10-28-2010 |
20100277209 | SIGNAL RECEIVER CIRCUIT CAPABLE OF IMPROVING AREA AND POWER EFFICIENCY IN SEMICONDUCTOR INTEGRATED CIRCUITS - A signal receiver circuit includes a first level detector for offset-controlling a first output node in response to a pair of first reference signals. A second level detector offset-controls a second output node in response to a pair of second reference signals. | 11-04-2010 |
20100327921 | CIRCUIT ARCHITECTURE FOR EFFECTIVE COMPENSATING THE TIME SKEW OF CIRCUIT - A circuit architecture for effective compensating the time skew of circuit is disclosed. The circuit architecture comprises a required compensation circuit, two duplicated circuits, and a time skew detection and compensation circuit, wherein these duplicated circuits are the duplicates of the required compensation circuit. A differential of logic 0 and logic 1 signals are simultaneously inputted into two duplicated circuits to output a first detection signal and a second detection signal, then the time skew detection and compensation circuit detects the time skew between a first detection signal and a second detection signal so as to generate a compensation signal to the required compensation circuit. Accordingly, the time skew existed in the required compensation circuit can be reduced or eliminated. | 12-30-2010 |
20100327922 | INTEGRATED CIRCUIT DEVICE AND DATA TRANSMISSION SYSTEM - An integrated circuit device includes: a plurality of I/O cells coupled to an external apparatus; a control signal generator configured to detect a phase relationship among data signals respectively input into the plurality of I/O cells and to generate control signals based on the phase relationship; and a drive controller circuit configured to control the driving of the I/O cells in response to the control signals. | 12-30-2010 |
20110012648 | SYSTEMS AND METHODS FOR REDUCING AVERAGE CURRENT CONSUMPTION IN A LOCAL OSCILLATOR PATH - A method for reducing average current consumption in a local oscillator (LO) path is disclosed. An LO signal is received at a master frequency divider and a slave frequency divider. Output from the master frequency divider is mixed with an input signal to produce a first mixed output. Output from the slave frequency divider is mixed with the input signal to produce a second mixed output. The second mixed output is forced to be in phase with the first mixed output. | 01-20-2011 |
20110050297 | SYSTEM EMPLOYING SYNCHRONIZED CRYSTAL OSCILLATOR-BASED CLOCK - A synchronized clock system, for use with an electronic system with several system nodes requiring a synchronized clock signal. The clock system includes a first synch bus and a second synch bus, isolated from the first synch bus, and at least one pair and preferably several pairs of SXO modules connected to the busses in alternating fashion. Each of the system nodes is connected at a different one of any number of arbitrarily selected connection points anywhere along the first bus. The points along the busses at which the SXO modules are connected are spaced roughly equidistantly apart. The system nodes are connected to the bus by means of signal conditioning circuits, which may include correction circuits, an amplifier, a frequency multiplier, a logic translator and a fan buffer. | 03-03-2011 |
20110050298 | POWER SUPPLY CIRCUIT FOR SOUTH BRIDGE CHIP - A power supply circuit for a south bridge chip includes a voltage sampling circuit, a control circuit, and an I/O controller. The voltage sampling circuit comprises an input terminal capable of receiving a first voltage, and an output terminal capable of outputting a control signal. The control circuit is capable of receiving the control signal from the voltage sampling circuit and outputting a power good signal when a high voltage level control signal is received. The I/O controller is capable of receiving the power good signal from the control circuit, adjusting time sequence for the power good signal to synchronize with the first voltage, and outputting the adjusted power good signal to provide power for the south bridge chip. | 03-03-2011 |
20110057689 | SIGNAL PROCESSING-SYSTEM USING SINGULARITY, AND ITS INFORMATION MEMORY MEDIUM - This invention provides the signal processing-system using singularity which is excellent in determination of the original signal against the degradation environment of an operating condition and robust to the signal degradation of noise, can generate the signal suitable to regeneration of the original signal, and has regeneration means to regenerate the original signal. This is the signal processing-system using singularity and has following configuration and features. | 03-10-2011 |
20110068836 | SPREAD-SPECTRUM CLOCK ACQUISITION AND TRACKING - Apparatus having corresponding methods and computer-readable media comprise: a phase detector configured to generate an error signal representing a phase difference between a recovered spread-spectrum clock signal and a serial data stream that includes a spread-spectrum clock signal; and a phase selector configured to provide the recovered spread-spectrum clock signal based on an error signal from a current spread-spectrum cycle of the spread-spectrum clock signal and an error signal from a previous spread-spectrum cycle of the spread-spectrum clock signal. | 03-24-2011 |
20110080193 | ELECTRONIC DEVICE CONTROL SYSTEM AND METHOD - An exemplary control method includes a step of employing a look-up table to derive first waveform value data for a multi-phase reference waveform. The exemplary method also includes a step of deriving second waveform value data corresponding to modifier data for the multi-phase reference waveform. The modifier data is added into the reference waveform to produce a modified reference waveform. The exemplary method additionally includes a step of generating a plurality of control signals from the modified reference waveform and controlling one or more electronic devices based on the control signals. | 04-07-2011 |
20110181325 | CIRCUIT AND METHOD OF CLOCKING MULITIPLE DIGITAL CIRCUITS IN MULTIPLE PHASES - A circuit includes a power supply terminal and a clock parsing circuit configured to produce multiple clock signals having a common clock period and different phases. The circuit further includes a plurality of digital circuits coupled to the clock parsing circuit and the power supply terminal. Each digital circuit includes an input to receive data and logic to process the data. Each digital circuit is responsive to a phase associated with a respective clock signal of the multiple clock signals to draw current from the regulated power supply terminal to process the data to produce a data output. Additionally, the circuit includes an output timing management circuit coupled to each of the plurality of digital circuits and configured to control data outputs of each of plurality of digital circuits to prevent timing violations at one or more destination circuits. | 07-28-2011 |
20110193598 | EFFICIENT RETIMER FOR CLOCK DIVIDERS - Conventional retimers generally consume too much power, are too noisy, and are too large. Additionally, phase noise and jitter are generally a function of retiming. As a result, a retimer is provided with a smaller footprint that has reduced power consumption and improved noise characteristics over other conventional retimers. | 08-11-2011 |
20110199133 | TEST APPARATUS AND TEST METHOD - Provided is a test apparatus and a test method for substantially synchronizing phases of test signals for each of a plurality of clock domains. The test apparatus tests a device under test including a plurality of clock domains. The test apparatus comprises a period generator that generates a rate signal for determining a test period corresponding to an operation period of the device under test; a pattern generator that generates a test pattern; phase comparing sections that, for each clock domain, receive an operation clock signal of the clock domain acquired from a terminal of the device under test included in the clock domain, and detect a phase difference of the operation clock signal of the clock domain with respect to the rate signal; and a plurality of waveform shaping sections that are provided respectively to the clock domains, and that each shape a test signal based on the test pattern, according to the phase difference of the corresponding clock domain, to substantially synchronize the test signal with the operation clock signal of the corresponding clock domain. | 08-18-2011 |
20110234267 | Semiconductor device and method for controlling flip-flop - A semiconductor device according to one aspect of the present invention includes: a flip-flop; a clock control circuit that controls a clock signal supplied to the flip-flop; and a controller that supplies a data retention signal to the flip-flop and controls the clock control circuit. When the flip-flop is driven by a negative edge of the clock signal and retains data when the clock signal is at a high level, the controller controls the clock control circuit so as to supply a high-level clock signal to the flip-flop after the input clock signal is fixed and before the flip-flop retains data. This prevents the occurrence of unintended latching of data when the flip-flop having a retention function retains data. | 09-29-2011 |
20110241740 | DEVICE, DEVICE BASE, AND SYSTEM FOR DATA SENDING AND RECEIVING PROCESSING - A system and method for data sending and receiving processing using a secondary data transmit channel is disclosed. The system comprises a device and a device base in which a secondary data transmit channel on the device is enabled when the device is coupled to the device base and receives a triggering signal from the device base. The system implements a 2T2R RF design in which the use of an additional data transmit channel increases the uplink transmit gain and coverage and reduces the deployment costs of base stations. | 10-06-2011 |
20120013372 | POWER LAYER GENERATION OF INVERTER GATE DRIVE - Techniques include systems and methods of synchronizing multiple parallel inverters in a power converter system. In one embodiment, control circuitry is connected to a power layer interface circuitry at each of the parallel inverters, via an optical fiber interface. The system is synchronized by transmitting a synchronizing pulse to each of the inverters. Depending on the operational mode of the system, different data exchanges may occur in response to the pulse. In an off mode, power up and power down data may be exchanged between the control circuitry and the inverters. In an initiating mode, identification data may be transmitted from the inverters to the control circuitry. In an active mode, control data may be sent from the control circuitry to the inverters. In some embodiments, the inverters also transmit feedback data and/or acknowledgement signals to the control circuitry. Power layer circuitry of the inverter adjusts a local clock based upon sampled data from the control circuitry to maintain synchronicity of the inverters between synchronization pulses. | 01-19-2012 |
20120013373 | SEMICONDUCTOR DEVICE, CIRCUIT CORRECTION METHOD, DESIGN SUPPORT DEVICE, AND RECORDING MEDIUM STORING DESIGN SUPPORT PROGRAM - There has been a problem in a conventional semiconductor device that a great deal of time is needed for a returning process associated with circuit correction. A semiconductor device according to the present invention includes a plurality of trigger signal driving elements (FFa and FFb) that synchronize with a trigger signal and operate, trigger wiring lines (CW | 01-19-2012 |
20120223748 | CIRCUIT AND METHOD FOR APPLYING A THREE PHASE POWER SOURCE TO A THREE PHASE LOAD - A circuit and method of applying a three phase power source to a load such that each phase is applied to the load in a manner, such as a predetermined sequence, so as to reduce the electromagnetic interference (EMI) and heat generated in the switching devices during the application and removal of each phase to the load. | 09-06-2012 |
20120223749 | CLOCK SYNCHRONIZATION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - A clock synchronization circuit receives a base clock, a first synchronization signal for synchronizing the base clock and a system clock, and a selection signal containing information about the division ratio of the system clock, holds the first synchronization signal over a predetermined time on the basis of the selection signal, and outputs, in synchronization with the base clock, a second synchronization signal for synchronizing the base clock and the system clock. | 09-06-2012 |
20120268172 | OSCILLATION DETECTOR - An oscillation detector having an RF oscillator configured to be synchronized with a first frequency and a comparator for distinguishing the synchronized state from the non-synchronized state of the radiofrequency oscillator on the basis of an oscillating signal produced by the radiofrequency oscillator and indicating the presence of oscillations in a frequency band around the first frequency in response to identifying the synchronized state and, in alternation, indicating the absence of oscillations in this frequency band otherwise. | 10-25-2012 |
20120280726 | CONTROL CIRCUIT ARRANGEMENT FOR PULSE-WIDTH MODULATED DC/DC CONVERTERS AND METHOD FOR CONTROLLING A PULSE-WIDTH MODULATED CONVERTER - A control circuit arrangement for pulse-width modulated DC/DC converters includes a phase generator for a complementary driver which provides respective gate signals to a first and second driver transistor in response to a control signal. A clock control circuit receives a clock signal and a pulse-width modulated signal and provides the control signal in response to a signal edge of the pulse-width modulated signal and the clock signal applied thereto. A mode selection input terminal receives a mode selection signal to select a first mode or a second mode of operation. The phase generator provides in the first mode each of the gate signals the control signal and the respective other gate signal. In the second mode of operation, it provides each gate signal in response to the control signal. | 11-08-2012 |
20120286832 | Data Synchronization Circuit - The invention concerns a circuit comprising: a first circuit block ( | 11-15-2012 |
20120299627 | CLOCK MESH SYNTHESIS WITH GATED LOCAL TREES AND ACTIVITY DRIVEN REGISTER CLUSTERING - A clock mesh network synthesis method is proposed which enables clock gating on the local sub-trees of the clock mesh network in order to reduce the clock power dissipation. Clock gating is performed with a register clustering strategy that considers both i) the similarity of switching activities between registers in a local area and ii) the timing slack on every local data path of the design area. The method encapsulates the efficient implementation of the gated local trees and activity driven register clustering with timing slack awareness for clock mesh synthesis. With gated local tree and activity driven register clustering, the switching capacitance on the mesh network can be reduced by 22% with limited skew degradation. The method has two synthesis modes as low power mode and high performance mode to serve different design purposes. | 11-29-2012 |
20120319746 | ARRAY ANTENNA APPARATUS - An array antenna apparatus in which an SN ratio is improved. Antenna elements having transmission modules, respectively, are arranged in plurality, wherein the plurality of transmission modules respectively have transmission signal generators that each output a transmission intermediate frequency signal, local oscillation signal generators that each output a local oscillation signal, and transmission mixers that each mix the transmission intermediate frequency signal and the local oscillation signal with each other, thereby to carry out frequency conversion to a transmission high frequency signal. A reference signal source inputs a reference signal to the transmission signal generators and the local oscillation signal generators. The transmission intermediate frequency signal and the local oscillation signal are synchronized with each other by the reference signal. | 12-20-2012 |
20130002315 | ASYNCHRONOUS CLOCK ADAPTER - An asynchronous clock adapter is disclosed that transmits multiple data elements from a buffer in a source clock domain to a data register in a destination clock domain. The buffer can be selected by a pointer register in the destination clock domain and a round trip timing path exists from the pointer register to the data register. Data elements from the buffer can be sent on interleaved cycles of the destination clock such that each data element can have a delay constraint of more than one clock period. | 01-03-2013 |
20130038358 | WIRELESS SENSOR NODE AND METHOD - Determining time latency at a sensor node in a mesh network. A beacon time is received at the sensor node from an upstream node, the beacon time offset from global time by the latency. The latency, the global time, and a corresponding local time are determined at the sensor node. | 02-14-2013 |
20130038359 | DIGITAL GLITCH FILTER - A digital glitch filter for filtering glitches in an input signal includes first and second flip-flops and a synchronizer. The synchronizer includes third and fourth flip-flops. A glitch prone input signal is provided to the first and second flip-flops. Additionally, an input clock signal is provided to the first and second flip-flops and the synchronizer. A glitch occurring in the input signal toggles the first and second flip-flops between transmitting and non-transmitting states and first and second intermediate signals are generated. The synchronizer synchronizes the first and second intermediate signals with the input clock signal to generate a filtered output signal. | 02-14-2013 |
20130038360 | TIMING CONTROL DEVICE AND CONTROL METHOD THEREOF - Provided is a timing control device including: a storage unit that stores multiple pieces of timing control information including identification information and expected value data; a first selector that selectively outputs any of the multiple pieces of timing control information; a second selector that selectively outputs any of data items output from data output devices based on the identification information; a reference data generation unit that generates reference data based on expected value data and a data item output from the second selector in synchronization with a switching of the timing control information; a comparator that compares the reference data with the data item output from the second selector and outputs a coincidence signal when the reference data and the data item coincide with each other; and an output control unit that outputs a timing signal according to the coincidence signal. | 02-14-2013 |
20130049824 | 3D CHIP STACK SKEW REDUCTION WITH RESONANT CLOCK AND INDUCTIVE COUPLING - There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. The clock distribution network includes a plurality of clock distribution circuits, each being arranged on a respective one of the two or more strata for providing the global clock signals to various chip locations. Each of the plurality of clock distribution circuits includes a resonant circuit for providing stratum-to-stratum coupling for the clock distribution network. The resonant circuit includes at least one capacitor and at least one inductor. | 02-28-2013 |
20130057322 | DELAY CIRCUIT AND DELAY STAGE THEREOF - A delay circuit includes at least a delay stage. The delay stage includes an inverting receiver, a capacitive element, an output inverter, and a feedback transistor. The inverting receiver includes a resistive element. An input node of the inverting receiver receives an input signal, and the resistive element is coupled to an output node and an internal node of the inverting receiver. A capacitive element is coupled to the output node of the inverting receiver. An input node of the output inverter is coupled to the output node of the inverting receiver, and an output node of the output inverter outputs an output signal of the delay stage. The feedback transistor is coupled between the output node and the input node of output inverter, such that the feedback transistor compensates a delay time of the inverting receiver as at least one of a process, a supply-voltage, and a temperature varies. | 03-07-2013 |
20130076409 | Multiple Channel Distributed System and Method - A complex acquisition system and method for synchronizing components thereof. The complex acquisition system further including a master acquisition module. The master acquisition module further including an analog to digital acquisition signal generator for generating an analog to digital acquisition signal, a memory acquisition signal generator for generating a memory acquisition signal, a delay calibration signal for generating a delay calibration signal, a step source signal generator for generating a step source signal, and a synchronization module. The complex acquisition system further includes a plurality of slave acquisition modules, each also including a synchronization module. The complex acquisition system additionally includes a distribution system for distributing each of the analog to digital acquisition signal, memory acquisition signal, delay calibration signal and step source signal to each of the synchronization modules in the master and plurality of slave acquisition modules. | 03-28-2013 |
20130099835 | CALIBRATION APPARATUS FOR PERFORMING PHASE DETECTION/EDGE DISTANCE DETECTION UPON SIGNALS AND RELATED CALIBRATION METHOD THEREOF - An exemplary calibration apparatus includes a detecting circuit and a calibrating circuit. The detecting circuit is arranged for generating a detection result by detecting relationship between edges of a plurality of signals generated from a plurality of signal sources, wherein at least one of the edges is a falling edge. The calibrating circuit is coupled to the detecting circuit, and arranged for calibrating at least one of the signal sources according to the detection result. An exemplary calibration method includes the following steps: generating a detection result by detecting relationship between edges of a plurality of signals generated from a plurality of signal sources, wherein at least one of the edges is a falling edge; and calibrating at least one of the signal sources according to the detection result. | 04-25-2013 |
20130141142 | Multiphase Electrical Power Assignment at Minimal Loss - In a multiphase electrical power assignment, a processor: receives instructions to connect a bi-directional power device to a multiphase premise power source; determines that the power device is to be coupled to a target phase's phase connection; confirms that the power device is not coupled to any phase connections; and couples the power device to the phase connection, where the power device's power signal is synchronized with the phase connection's power signal. When the power device is in a connected state, the processor: issues a command to place each phase connection switch in an open state; in response to confirming that the phase connection switches are in the open state, issues commands to the power device so that a power signal of the power device will be synchronized with the target phase; and closes the phase connection switch corresponding to the target phase. | 06-06-2013 |
20130141143 | OSCILLATION FREQUENCY ADJUSTING APPARATUS, OSCILLATION FREQUENCY ADJUSTING METHOD, AND WIRELESS COMMUNICATION APPARATUS - A voltage controlled oscillation circuit oscillates at an oscillation frequency corresponding to a control voltage. Injection locked oscillation circuits oscillate at an oscillation frequency corresponding to an output signal from the voltage controlled oscillation circuit. A mixer circuit performs a frequency conversion based on output signals from the injection locked oscillation circuits. A synchronization determiner determines the synchronous status between the injection locked oscillation circuits in accordance with an output signal from the mixer circuit. The injection locked oscillation circuits synchronize with each other at a frequency that is an integral multiple of the oscillation frequency of the voltage controlled oscillation circuit. | 06-06-2013 |
20130147528 | Multiple electrothermal-filter device - During operation of the device, a drive circuit may provide a drive signal having a fundamental frequency to two electrothermal filters (ETFs) having different temperature-dependent time constants. In response to the drive signal, the two ETFs may provide, signals having the fundamental frequency and phases relative to the drive signal corresponding, respectively, to the time constants of the ETFs. Then, phase-shift values of the phases may be measured using a phase detector, and a signal may be output based on the phase-shift values. Note that the signal may correspond to a value that is a function of a temperature of the device. | 06-13-2013 |
20130214827 | METHOD AND SYSTEM FOR SYNCHRONIZING THE PHASE OF A PLURALITY OF DIVIDER CIRCUITS IN A LOCAL-OSCILLATOR SIGNAL PATH - A method and system for synchronizing the output signal phase of a plurality of frequency divider circuits in a local-oscillator (LO) or clock signal path is disclosed. The LO path includes a plurality of frequency divider circuits and a LO buffer for receiving a LO signal coupled to the plurality of frequency divider circuits. The method and system comprise adding offset voltage and setting predetermined state to each of the frequency divider circuits; and enabling the frequency divider circuits. The method and system includes enabling the LO buffer to provide the LO signal to the frequency divider circuits after they have been enabled. When the LO signal drives each of the frequency divider circuits, each of the frequency divider circuits starts an operation. Finally the method and system comprise removing the offset voltage from each of the frequency divider circuits to allow them to effectively drive other circuits. | 08-22-2013 |
20130214828 | METHODS AND APPARATUS FOR SYNCHRONIZING RF PULSES IN A PLASMA PROCESSING SYSTEM - A synchronized pulsing arrangement for providing at least two synchronized pulsing RF signals to a plasma processing chamber of a plasma processing system is provided. The arrangement includes a first RF generator for providing a first RF signal. The first RF signal is provided to the plasma processing chamber to energize a plasma therein, the first RF signal representing a pulsing RF signal. The arrangement also includes a second RF generator for providing a second RF signal to the plasma processing chamber. The second RF generator has a sensor subsystem for detecting values of at least one parameter associated with the plasma processing chamber that reflects whether the first RF signal is pulsed high or pulsed low and a pulse controlling subsystem for pulsing the second RF signal responsive to the detecting the values of at least one parameter. | 08-22-2013 |
20130234764 | PHASE SYNCHRONIZATION CIRCUIT FOR AC VOLTAGE - A phase synchronization circuit for AC voltage includes an optical phase detection unit that outputs a phase detection signal by detecting an externally provided first AC voltage; a power failure detection unit that outputs a power failure signal by detecting the power failure condition of the first AC voltage; a control unit that selectively activates a selection signal according to the control of the power failure detection signal and outputs a phase control signal according to the control of the phase detection signal; a second AC voltage generation unit that generates a second AC voltage to have the same phase of the first AC voltage when outputting a second AC voltage according to the control of the phase control signal; and a selection unit that outputs either the first AC voltage or the second AC voltage according to the control of the selection signal. | 09-12-2013 |
20130241608 | HIGH SPEED, WIDE FREQUENCY-RANGE, DIGITAL PHASE MIXER AND METHODS OF OPERATION - The present disclosure is directed to a unit phase mixer in combination with an input buffer. The unit phase mixer has a pull-up path for pulling an output terminal up to a first voltage. The pull-up path has a first transistor responsive to a first enable signal and a series connected second transistor responsive to a first clock signal. The unit phase mixer has a pull-down path for pulling the output terminal down to a second voltage. The pull-down path has a third transistor responsive to a second clock signal and a series connected fourth transistor responsive to a second enable signal. The input buffer skews the first and second clock signals by different amounts to enable a break-before-make method of operation so that the first voltage is not connected to the second voltage. The unit phase mixer can be used as a building block in more complex mixers which may include the ability to weight the input clocks as well as providing feed-forward paths for certain of the signals. Because of the rules governing abstract, this abstract should not be used to construe the claims. | 09-19-2013 |
20130278305 | SEMICONDUCTOR WAFER AND METHOD FOR AUTO-CALIBRATING INTEGRATED CIRCUIT CHIPS AT WAFER LEVEL - In integrated circuit chips that are used for RFID, a method of calibrating an operation frequency that is generated in an operation frequency generator and a semiconductor wafer including a calibration circuit are provided. The method of calibrating an operation frequency of integrated circuit chips includes: supplying DC power to the integrated circuit chips; selecting an integrated circuit chip to perform calibration of an operation frequency; receiving an operation frequency that is generated in the selected integrated circuit chip; generating a frequency calibration value by comparing the operation frequency with a calibration target frequency; transmitting a control signal including the frequency calibration value to the integrated circuit chip; and releasing a selection of the integrated circuit chip in which calibration of the operation frequency is complete. | 10-24-2013 |
20130278306 | SENSOR DEVICE - A sensor device for monitoring the environment of a vehicle includes at least two sensors, each with a signal generator, a transmitting antenna, and at least two receiving antennas, characterized in that at least one reference clock pulse generator for generating a common reference clock pulse for the signal generators of the at least two sensors is provided. | 10-24-2013 |
20130285716 | POWER SYSTEM DATA ACQUISITION SYSTEMS - A system comprising an interface configured to condition a signal associated with a power system; a clock module configured to generate a synchronization signal; and a module coupled to the interface and configured to digitize the signal from the interface; filter the digitized signal; and generate a time-shifted, digitized signal in response to the filtering and the synchronization signal. | 10-31-2013 |
20130300465 | SYSTEMS AND METHODS OF SIGNAL SYNCHRONIZATION FOR DRIVING LIGHT EMITTING DIODES - System and method for signal synchronization. The system includes a first selection component, a first signal generator, a second signal generator and a first gate drive component. The first selection component is configured to receive a first mode signal and generate a first selection signal based on at least information associated with the first mode signal. The first signal generator is configured to, if the first selection signal satisfies one or more first conditions, receive a first input signal and generate at least a first clock signal based on at least information associated with the first input signal. Furthermore, the first gate drive component is configured to, if the first selection signal satisfies the one or more first conditions, receive at least the first clock signal and output a first drive signal to a first switch. | 11-14-2013 |
20130321042 | DEVICES FOR SYNCHRONIZING A COMMUNICATION END DEVICE WITH A BASE STATION, METHODS FOR SYNCHRONIZING A COMMUNICATION END DEVICE WITH A BASE STATION, DEVICES FOR GENERATING A SECONDARY SYNCHRONIZATION SIGNAL, AND METHODS FOR GENERATING A SECONDARY SYNCHRONIZATION SIGNAL - In an aspect of this disclosure, a device for synchronizing a communication end device with a base station may be provided. The device may include: a primary synchronization determiner configured to determine a first synchronization parameter; and a secondary synchronization signal generator configured to simultaneously generate a plurality of bits of a secondary synchronization signal based on the first synchronization parameter. | 12-05-2013 |
20130321043 | PULSE SYNCHRONIZER CIRCUIT - A pulse synchronizer circuit converts an input data signal generated under a source-clock domain into an output data signal under a destination-clock domain, where the destination clock is independent of the source clock. The pulse synchronizer circuit successfully converts each data pulse in the input data signal into a corresponding data pulse in the output data signal when the source clock is faster than the destination clock, when the source clock is slower than the destination clock, when an input data pulse has a duration of one source-clock cycle, and when an input data pulse has a duration of multiple source-clock cycles. The pulse synchronizer circuit has source-domain circuitry and destination-domain circuitry. The source-domain circuitry detects input data pulses and determines whether they are single- or multi-cycle data pulses. The destination-domain circuitry generates output data pulses based on the processing of the source-domain circuitry. | 12-05-2013 |
20130321044 | SYSTEM FOR REDUCING NOISE IN A CHEMICAL SENSOR ARRAY - A system including a power supply and a clock circuitry to generate a plurality of clock signals. Each clock signal is synchronous with a primary clock signal. First, second, and third clock signals of the plurality of clock signals are asynchronous to each other. The system further includes a plurality of switches. Each switch of the plurality of switches is communicatively coupled to the power supply and the clock circuitry. A first switch of the plurality of switches receives the first clock signal, a second switch of the plurality of switches receives the second clock signal, and a third switch of the plurality of switches receives the third clock signal. | 12-05-2013 |
20140103971 | METHODS AND APPARATUS FOR SOURCE-SYNCHRONOUS CIRCUITS - Source-synchronization between a source module and a responder module generally includes providing, at the source module, an initial determinism reconciliation signal, propagating the initial determinism reconciliation signal from the source module to the responder module and back to the source module to produce a received determinism reconciliation signal, and compensating for an intrinsic delay of the circuit based on the initial determinism reconciliation signal and the received determinism reconciliation signal. | 04-17-2014 |
20140218076 | Synchronization of RF Pulsing With RF Metrology, Processing, and Control - A radio frequency (RF) system is disclosed. The RF system includes an RF sensor, an analog to digital converter (ADC) module, a processing module, and a synchronization module. The RF sensor measures a parameter of an RF output and generates an RF signal based on the parameter. The ADC module converts samples of the RF signal into digital values. The processing module generates processed values based on the digital values. The synchronization module outputs one of the processed values in response to a transition in the RF output. | 08-07-2014 |
20140253189 | Control Circuits for Asynchronous Circuits - The described embodiments include a computing device with one or more asynchronous circuits and control circuits that control the operation of the asynchronous circuits. In some embodiments, the control circuits are arranged in a hierarchy with a top-level control circuit atop the hierarchy and one or more local control circuits lower in the hierarchy. In these embodiments, the top-level control circuit processes operating information for the one or more asynchronous circuits and/or other functional blocks in the computing device to determine an operating state for the computing device. Based on the operating state, the top-level control circuit communicates commands to the local control circuits to cause the local control circuits to operate in corresponding operating modes. Based on a corresponding operating mode command, each local control circuit sets one or more operating parameters for corresponding asynchronous circuits (and/or one or more other functional blocks). | 09-11-2014 |
20140266332 | ISOLATOR-BASED TRANSMISSION SYSTEM WITH SIDE ISOLATOR CHANNEL FOR REFRESH SIGNALS - A multi-channel isolation system has N+1 isolators for N channels of communication data. N of the isolators may transfer data signals across an isolation barrier, one for each of the N channels of data. An N+1 | 09-18-2014 |
20140312940 | SEMICONDUCTOR DEVICE WITH CLOCK-BASED SIGNAL INPUT CIRCUIT - A semiconductor device includes a signal input circuit suitable for synchronizing an input signal with a dock signal and receiving the dock signal as a power source when the input signal has a first phase. | 10-23-2014 |
20140327474 | SYSTEM FOR REDUCING NOISE IN A CHEMICAL SENSOR ARRAY - A system including a power supply and a clock circuitry to generate a plurality of clock signals. Each clock signal is synchronous with a primary clock signal. First, second, and third clock signals of the plurality of clock signals are asynchronous to each other. The system further includes a plurality of switches. Each switch of the plurality of switches is communicatively coupled to the power supply and the clock circuitry. A first switch of the plurality of switches receives the first clock signal, a second switch of the plurality of switches receives the second clock signal, and a third switch of the plurality of switches receives the third clock signal. | 11-06-2014 |
20140375365 | OVERSAMPLING METHOD FOR DATA SIGNAL AND OVERSAMPLING APPARATUS THEREOF - An oversampling method for data signal includes oversampling data strobe signal and data signal according to sampling phases to generate first and second sampling results, performing edge detection on the first and second sampling results to obtain first and second edge positions where edges are detected, calculating and storing first offset according to the first edge position and the corresponding second edge position when the second edge position are obtained, using first offset obtain in a previous sampling cycle as the first offset in a current sampling cycle when the second edge position aren't obtained, calculating first sampling point according to the first edge position; calculating second sampling point according to the first sampling point and the corresponding first offset, and selecting and outputting the corresponding second sampling results according to the second sampling point. | 12-25-2014 |
20150137861 | UNIFIED CONNECTOR FOR MULTIPLE INTERFACES - Circuits, methods, and apparatus that may reduce the number of connector receptacles that are needed on an electronic device. One example may provide a unified connector and circuitry that may be capable of communicating with more than one interface. | 05-21-2015 |
20160028407 | SEMICONDUCTOR APPARATUS AND SYSTEM INCLUDING PLURALITY OF CHANNELS - A semiconductor apparatus includes a direct access section, an interface section, and a through-silicon via region. The direct access section receives a normal clock, a first clock, and a control signal through a direct access pad. The interface section comprises a plurality of channel circuits suitable for aligning the control signal to the first clock, and outputting an aligned control signal. The through-silicon via region transfers the normal clock and the aligned control signal from the interface section to a plurality of channels corresponding to the respective channel circuits. | 01-28-2016 |
20160028408 | PARALLEL INTERFACE AND INTEGRATED CIRCUIT - A parallel interface is disclosed. The parallel interface of the present disclosure includes an input unit configured to input, in parallel, a plurality of predetermined data signals and a clock signal; an output unit configured to output, in parallel, the predetermined data signals in synchronization with the clock signal; and a plurality of transmission lines disposed between the input unit and the output unit and configured to transmit, in parallel, the predetermined data signals and the clock signal, wherein the transmission lines are configured with a wiring pattern in which the transmission lines have different electrical lengths and an equal electrical capacitance. | 01-28-2016 |
20160065200 | INPUT APPARATUS AND INPUT SYSTEM - An input apparatus may include a pulse width control circuit, a reception circuit, and a latch circuit. The pulse width control circuit may be configured to generate a pulse width control signal by performing a logical operation on a pulse width detection signal and a clock signal. The reception circuit may be configured to selectively provide a received input signal as a period signal on the basis of the clock signal and the pulse width control signal. The latch circuit may be configured to provide an output signal by inverting the period signal, and provide the output signal as the pulse width detection signal in response to the clock signal. | 03-03-2016 |
20160099717 | TRANSMISSION CIRCUIT, INTEGRATED CIRCUIT, AND PARALLEL-TO-SERIAL CONVERSION METHOD - A transmission circuit includes: a shift register configured to shift, in synchronization with a first clock signal, input parallel data within a plurality of flip-flop circuits; a control circuit configured to output a second clock signal of a phase in accordance with a phase of the first clock signal; a selector configured to select any one of the input parallel data and pieces of output parallel data of the plurality of flip-flop circuits; and a conversion circuit configured to convert, in synchronization with the second clock signal, the parallel data selected by the selector into pieces of serial data, in which the control circuit outputs a selection signal to the selector, in accordance with a deviation amount of the detected phase of the first clock signal. | 04-07-2016 |