| Entries |
| Document | Title | Date |
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| 20080211551 | Semiconductor memory device - A semiconductor memory device performs a reset operation at a wafer state by using a signal input through an address pin in a test mode. The semiconductor memory device includes a buffer for transferring a reset command in response to a reset-active signal and a test reset signal, a test-reset entry signal generation unit for generating an internal test-reset entry signal in response to the test reset signal, and a rest signal driving unit for driving an active signal of an output signal of the buffer and the internal test-reset entry signal as an internal reset signal for a reset mode entry. | 09-04-2008 |
| 20080218223 | POWER ON DETECTION CIRCUIT - A power on detection circuit for accurately detecting an input voltage with a simple circuit structure and reduced current consumption includes a voltage conversion circuit, which converts input voltage into current, and a latch circuit, which holds the power on detection signal. The voltage conversion circuit supplies output current to a current source and a capacitor via a connection node. The current source generates a flow of current that is proportional to the absolute temperature. When the output current of the voltage conversion circuit becomes greater than the current of the current source, the capacitor is charged and the voltage at the connection node is pulled up. A latching circuit is activated in accordance with the voltage at the connection node to output a power on detection signal. | 09-11-2008 |
| 20090079476 | Reset signal generation circuit - A reset signal generation circuit for generating a reset signal synchronously or asynchronously to a clock signal in accordance with an operation state. An operation detection circuit detects operation of a CPU and generates an operation detection signal. A signal control circuit generates a first reset signal synchronously or asynchronously to an internal clock signal based on the operation detection signal and a system reset signal. The first reset signal is provided to synchronous circuits including the CPU. | 03-26-2009 |
| 20090096495 | Ring oscillator for temperature sensor, temperature sensor circuit, and semiconductor device having the same - A ring oscillator includes an odd number of unit circuits connected in series each of which includes an inverter. Each of the unit circuits includes the inverter and a MOSFET. The MOSFET is an FET which is a temperature sensor, and uses a drain-source leakage current in a state that the FET is normally turned off. | 04-16-2009 |
| 20090108886 | Semiconductor Device - A semiconductor device includes a circuit having a first data holding node and a second data holding node; a first MOS field-effect transistor coupled to the first data holding node; a second MOS field-effect transistor coupled to the second data holding node; and a clock generation circuit coupled to a first gate electrode of the first MOS field-effect transistor for outputting a clock signal, wherein the first gate electrode is coupled to the second data holding node via the second MOS field-effect transistor, and a second gate electrode of the second MOS field-effect transistor is coupled to the first data holding node via the first MOS field-effect transistor. | 04-30-2009 |
| 20090115469 | Variability-Aware Scheme for Asynchronous Circuit Initialization - A system for automatically transforming a given synchronous circuit description into an equivalent and provably correct desynchronized circuit description. Included in the automated transformation are techniques for synthesizing a variability-aware controller using a two-phase protocol, techniques for synthesizing a variability-aware controller using gated clocks and testability circuits, techniques for synthesizing a variability-aware controller optimized for performance, techniques for initializing the synthesized controller, techniques for dynamically minimizing power requirements, and techniques for interfacing the desynchronized circuit with external synchronous circuits. Also disclosed are techniques for implementing a system for automatically transforming a synchronous circuit description into an equivalent and provably correct desynchronized circuit description within the context of an electronic design automation design flow. Exemplary circuits used in the application of the aforementioned techniques are provided. Application of mathematical models and techniques used for proving equivalence between the input description and the resulting desynchronized circuit are presented and explained. | 05-07-2009 |
| 20090167376 | SYSTEM AND METHOD FOR PULSE EDGE SYNCHRONIZATION - A system and method for pulse edge synchronization, According to an embodiment, a first series of PWM signals that may drive a first device wherein each pulse in this series has a rising edge and a falling edge. The system and method further includes a second series of PWM signals that may drive a second device wherein each pulse in the second series of pulses also has a rising edge and a falling edge. These series of pulses are then synchronized such that each rising edge in the first series occurs simultaneous to a falling edge in the second series and vice versa. Such a system and method reduces the level of acoustic noise generated between the two motors. Further, synchronizing the rising and falling edges of the PWM pulses reduces and often eliminates stray EMI. | 07-02-2009 |
| 20090231000 | MOTHERBOARD POWER ON CIRCUIT - A motherboard power on circuit includes a switch connector, an impedance circuit, and a super I/O chip. The impedance circuit includes a first resistor, a second resistor, and a capacitor. A terminal of the first resistor is connected to the power on terminal of the switch connector. The other terminal of the first resistor is connected to the power on terminal of the super I/O chip, a terminal of the second resistor, and a terminal of the capacitor. The other terminals of the second resistor and the capacitor are connected to a power source and ground respectively. | 09-17-2009 |
| 20090237129 | SEMICONDUCTOR DEVICE AND DATA PROCESSOR - Synchronization between command and address signals commonly coupled to a plurality of memory devices to be operated in parallel and a clock signal coupled to the memory devices is achieved, while suppressing an increase in the clock wiring length. A semiconductor device has a data processing device mounted on a wiring substrate and a plurality of memory devices accessed in parallel by the data processing device. The data processing device outputs the command and address signals as a first frequency from command and address terminals, and outputs a clock signal as a second frequency from a clock terminal. The second frequency is set to multiple times of the first frequency, and an output timing equal to or earlier than a cycle starting phase of the clock signal output from the clock terminal can be selected to the command and address signals output from the command and address terminals. | 09-24-2009 |
| 20100013528 | SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM - A semiconductor device or an information processing system comprises a plurality of circuit units, and a control unit for controlling a start timing of large-current operations executed by the respective circuit units within a predetermined period, where the large-current operation involves a relatively large current which flows in a power supply system, as compared with other operations. The control unit controls the start timing of the large-current operation from one circuit unit to another such that the waveform of a current flowing from the power supply system is shaped into the waveform of a half cycle of a sinusoidal wave when the circuit units execute large-current operations within the predetermined period. | 01-21-2010 |
| 20100019810 | CIRCUIT FOR GENERATING NEGATIVE VOLTAGE AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME - A circuit for generating negative voltage of a semiconductor memory apparatus includes a first detecting unit configured to generate a first detecting signal by detecting a first negative voltage level, a first negative voltage generating unit configured to generate the first negative voltage in response to the first detecting signal, a second detecting unit configured to generate a second detecting signal by detecting the second negative voltage level, a timing controlling unit configured to output the second detecting signal as an enable signal when a power up signal is enabled and the first detecting signal is disabled, and a second negative voltage generating unit configured to generate the second negative voltage in response to the enable signal. | 01-28-2010 |
| 20100109720 | SEMICONDUCTOR INTEGRATED CIRCUIT AND CONTROL METHOD OF THE SAME - A semiconductor integrated circuit according to an exemplary embodiment of the present invention includes a power-on-reset circuit that outputs a reset signal based on a detect signal representing that power is applied to the semiconductor integrated circuit; an initialization object circuit for which an initialization is performed based on the reset signal; and a power-on-reset monitor circuit that generates and outputs a power-on-reset monitor signal representing whether or not the initialization is performed normally, based on the reset signal output from the power-on-reset circuit and an output signal of the initialization object circuit for which the initialization is performed. | 05-06-2010 |
| 20100109721 | SYSTEM FOR DETECTING A RESET CONDITION IN AN ELECTRONIC CIRCUIT - There is disclosed a system for detecting the assertion of a reset signal. A plurality of circuit elements is configurable by a reset signal to output a string of data values in a predetermined pattern. A comparator receives the string of data values and determines whether the string of data values matches the predetermined pattern. If so, the comparator generates an output signal indicative of a reset. In one embodiment, the output signal of the comparator can be used to automatically trigger a reset if the reset signal has not been asserted. | 05-06-2010 |
| 20100109722 | INTIALIZATION CIRCUIT FOR DELAY LOCKED LOOP - An initialization circuit in a delay locked loop ensures that after power up or other reset clock edges are received by a phase detector in the appropriate order for proper operation. After reset of the delay locked loop, the initialization circuit assures that at least one edge of a reference clock is received prior to enabling the phase detector to increase (or decrease) the delay in a delay line. After at least one edge of a feedback clock is received, the initialization circuit enables the phase detector to decrease (or increase) the delay in a delay line. | 05-06-2010 |
| 20100141309 | Initialization circuit and bank active circuit using the same - An initialization circuit comprises a section signal generator generating a section signal, of which a prescribed section is enabled in response to a power-up signal, a first oscillator generating a first period signal in response to the section signal, a first period multiplier generating a first multiplied signal by multiplying a period of the first period signal, and a signal selector transferring the first multiplied signal or a second multiplied signal selectively as a self-refresh enable signal in response to the section signal. | 06-10-2010 |
| 20100171532 | PHASE SYNCHRONIZATION LOOP TYPE FREQUENCY SYNTHESIZER OF FRACTIONAL N-TYPE, AND PHASE SHIFT CIRCUIT WITH FREQUENCY CONVERTING FUNCTION - Provided is a phase-locked loop frequency synthesizer, including: a reference oscillator; a voltage controlled oscillator; a variable frequency divider that divides the high frequency signal in frequency to output a feedback signal; a phase comparator that compares the reference signal and the feedback signal with each other to output a phase comparison signal; a loop filter that outputs a control signal of the voltage controlled oscillator based on the phase comparison signal; and a frequency/phase control circuit that generates frequency division number control data in synchronism with any one of the feedback signal and the reference signal based on setting data which is input from an external to give an output frequency and setting data which is input from the external to give a phase to the reference signal, to thereby output the frequency division number control data to the variable frequency divider. | 07-08-2010 |
| 20100194452 | INTEGRATED CIRCUIT DEVICE AND ELECTRONIC APPARATUS - An integrated circuit device includes: an internal circuit; a ground terminal; a first terminal that is provided with a first signal that becomes to be a ground level during at least a portion of a period in which the internal circuit is operating; a detection circuit that compares a voltage on the first terminal and a voltage on the ground terminal, thereby detecting an open state of the ground terminal; and a setting circuit that sets the internal circuit to a reset state or a disabled state when the open state of the ground terminal is detected by the detection circuit. | 08-05-2010 |
| 20100237912 | RESET SIGNAL GENERATING CIRCUIT - A reset signal generating circuit for a processor includes a charging circuit, a discharging circuit, and a triggering circuit. The charging circuit receives timing pulse signals from the processor to supply charging current according to the timing pulse signals when the processor operates normally, and stops supplying the charging current when the processor is at fault. The discharging circuit buffers the charging current supplied by the charging circuit when the processor operates normally, and discharges a low voltage to the triggering circuit when the processor is at fault. The triggering circuit outputs a trigger signal to the processor when the triggering circuit detects the low voltage to reset the processor. | 09-23-2010 |
| 20100271085 | DELAY CHAIN INITIALIZATION - A delay chain initialization circuit that converts a singled-sided signal to a dual sided-signal. The dual-sided delay chain including a data rail and a complement rail. Each of the data rail and data complement rail include inverter chains that are interconnected through cross-coupled inverter pairs. The delay chain initialization circuit being adapted to produce, at an output, a data signal and a data complement signal that are substantially simultaneous. | 10-28-2010 |
| 20100308875 | SWITCHABLE LOAD FOR INITIALIZING AN OUTPUT VOLTAGE OF A POWER SUPPLY - A conductive transistor switch has a collector that applies a reset pulse to an electronic circuit. A pull-up resistor is coupled between the collector of the transistor switch and a power supply voltage developed in a filter capacitor that energizes the electronic circuit. Proper reset operation requires the output supply voltage not to exceed, for example, 0.2 volts, during at least a portion of the reset operation. The user initiates the reset pulse that momentarily disables a power supply for ceasing the generation of the output supply voltage when the reset operation is performed. The value of the resistor is selected to be sufficiently low such that when the transistor switch is conductive, the discharge of the filter capacitor via the pull-up resistor is speeded up for completing the discharge of the filter capacitor in no more than, for example, 2 seconds to provide a maximum level of the output supply voltage that is no more than 5% of its normal operation voltage level. | 12-09-2010 |
| 20100321071 | Semiconductor integrated circuit - A resume signal hold circuit holds an assertion of a resume signal instructed while the circuit block is in a stand-by mode. A resume signal mask circuit is provided between the circuit block and the resume signal hold circuit, and masks the signals while the circuit block is in the stand-by mode so that no signal can be input to the circuit block. A power saving control circuit causes the resume signal hold circuit to hold the assertion of the event signal and causes the resume signal mask circuit to mask the signals while the circuit block is in a stand-by mode. The power saving control circuit also causes the resume signal hold circuit to cancel the holding of the assertion of the resume signal after the completion of the resume setting of the circuit block and cancelling of the signal masking by the resume signal mask circuit. | 12-23-2010 |
| 20100321072 | Device and Method for Signal Detection in a TDMA Network - The present invention is related to a circuit ( | 12-23-2010 |
| 20110012649 | INTERRUPTER, A METHOD OF RESPONDING TO A MONITORED EVENT AND AN INTEGRATED CIRCUIT INCLUDING AN INTERRUPTER - An interrupter, a method of responding to a monitored event and an IC are disclosed. In one embodiment, the interrupter includes: (1) a monitoring circuit configured to monitor for an occurrence of at least one event and generate an external event signal when detecting the occurrence, (2) a microprocessor, having: (2A) at least one functional pin and (2B) a reset input pin, coupled to the monitoring circuit, the microprocessor configured to begin a reset process in response to receiving the external event signal at the reset input pin and thereby set the functional pin to a reset state, and (3) a responding circuit coupled to the functional pin and configured to initiate a predetermined action when the functional pin is set to a reset state. | 01-20-2011 |
| 20110032009 | DELAY LOCKED LOOP CIRCUIT - A delay locked loop circuit comprising a VCDL which outputs a feedback clock by delaying an input clock in accordance with a magnitude of a control voltage, a phase comparator which detects a phase difference between the feedback clock and a reference clock by comparing the feedback clock with the reference clock, and outputs an Up-signal for raising the control voltage and a Down-signal for lowering the control voltage in accordance with the phase difference, a control voltage generation circuit which determines the control voltage in accordance with the Up-signal and the Down-signal, and outputs the control voltage to the VCDL, and a reset circuit which resets the phase comparator based on a logical OR between the reference clock and a first intermediate clock which is a signal obtained by delaying the input clock by the VCDL and is output before the feedback clock. | 02-10-2011 |
| 20110050299 | ELECTRICAL INSTRUMENT HAVING A PROTECTION CIRCUIT - A protection circuit suitable for electrical instruments includes a software detecting circuit, a logic AND circuit, a driver and control circuit for engine operating power components, and a hardware detecting circuit connected with the logic AND circuit. Both the software detecting circuit and the hardware detecting circuit monitor the state of an operating switch and provide signals to the logic AND circuit. Only when the state of the switch changes from opened to closed and both detecting circuits determine that this state is correct will the driver and control circuit signal the engine to operate. Furthermore, by connecting two or more power components in serial at the same time, the engine will not work by accident and the machine will not be out of control when any one of the power components is damaged. A circuit using capacitors of suitable specification can also be provided to isolate the controlling pin of a power component in the form of an SCR to thereby avoid failure and damage of the entire system. | 03-03-2011 |
| 20110062997 | RESET SIGNAL DISTRIBUTION - Methods, circuits and systems may operate to generate a reset signal at an input reset block and synchronously distribute the reset signal, via a number of pipelined reset blocks, to multiple ports of a core circuit. The reset signal may be transmitted successively to each of the pipelined reset blocks to provide delayed reset signals having delay times. The delay times may be based on locations of the pipelined reset blocks in the reset circuit. On or more of the delayed reset signals may be programmably coupled to one or more ports of the core circuit. Additional methods, circuits, and systems are disclosed. | 03-17-2011 |
| 20110102027 | SEMICONDUCTOR INTEGRATED DEVICE AND CONTROL METHOD THEREOF - Provided is a semiconductor integrated device that selects one or more of a plurality of functional blocks and resets the selected functional block, and a control method of the semiconductor integrated device. The semiconductor integrated circuit includes a functional block that is reset when a clock signal and a reset signal are supplied, a reset signal output unit that outputs the reset signal for resetting the functional block, a clock mask circuit that stops the clock signal to be supplied to the functional block, and a clock mask control circuit that controls the clock mask circuit. | 05-05-2011 |
| 20110156766 | DELAY LOCKED LOOP - A delay locked loop includes a replica delay oscillator unit, a division unit, a pulse generation unit, a code value output unit, and a delay line. The replica delay oscillator unit generates a replica oscillation signal having a period corresponding to a replica delay. The division unit receives the replica oscillation signal and a clock signal and divides the replica oscillation signal and the clock signal at a first or second ratio in response to a delay locking detection signal. The pulse generation unit generates a delay pulse having a pulse width corresponding to a delay amount for causing a delay locking. The code value output unit adjusts a code value corresponding to the pulse width of the delay pulse in response to the delay locking detection signal. The delay line delays the clock signal in response to the code value. | 06-30-2011 |
| 20110156767 | DELAY LOCKED LOOP AND METHOD FOR DRIVING THE SAME - A delay locked loop includes a delay pulse generation unit, a coding unit, and a delay line. The delay pulse generation unit is configured to generate a delay pulse having a certain width. The coding unit is configured to code the delay pulse and output a code value. The delay line is configured to delay an input clock by the code value, and generate a delayed locked clock. The delay pulse has a logic high level state during a third period equivalent to a difference between a first period, which corresponds to an integer multiple of the input clock, and a second period, which is a certain replica delay period. | 06-30-2011 |
| 20110156768 | INTERNAL COMMAND GENERATION DEVICE - The initial command generation device includes a first flag signal generation unit configured to generate a reset flag signal setting a reset period in response to a reset command, an initial pulse signal generation unit configured to generate a first initial pulse signal and a second initial pulse signal in response to the reset flag signal, a second flag signal generation unit configured to generate a device auto initialization flag signal setting a device auto initialization period in response to the first initial pulse signal and an internal command generation unit configured to generate an internal refresh command enabled within the device auto initialization period in response to the second initial pulse signal. | 06-30-2011 |
| 20110193599 | PHASE FREQUENCY TO DIGITAL CONVERTER - A circuit arrangement is described comprising a first receiver configured to receive a first input signal, a second receiver configured to receive a second input signal, a first signal generator configured to generate a first pulse signal, a second signal generator configured to generate a second pulse signal, wherein a delay between a rising edge of the first pulse signal and a rising edge of the second pulse signal is proportional to a difference between the first input signal and the second input signal, a first converter configured to convert the first pulse signal to a first digital number proportional to a width of the first pulse signal, a second converter configured to convert the second pulse signal to a second digital number proportional to a width of the second pulse signal, wherein at least one of the first converter and the second converter comprises a cascade of at least two converter stages, wherein each converter stage of the at least two converter stages is configured to propagate and shrink the respective pulse signal. Also a corresponding method is described. | 08-11-2011 |
| 20110210769 | INTEGRATED CIRCUIT - An integrated circuit includes a pad, an input buffer unit, and a supplementary driving unit. The pad is configured to receive a reset signal from an external device. The input buffer unit is configured to buffer a reset signal applied to the pad. The supplementary driving unit is configured to receive an output signal from the input buffer unit and supplementarily drive an input terminal of the input buffer unit to a deactivation level of the reset signal. | 09-01-2011 |
| 20110210770 | SYSTEM FOR DETECTING A RESET CONDITION IN AN ELECTRONIC CIRCUIT - There is disclosed a system for detecting the assertion of a reset signal. A plurality of circuit elements is configurable by a reset signal to output a string of data values in a predetermined pattern. A comparator receives the string of data values and determines whether the string of data values matches the predetermined pattern. If so, the comparator generates an output signal indicative of a reset. In one embodiment, the output signal of the comparator can be used to automatically trigger a reset if the reset signal has not been asserted. | 09-01-2011 |
| 20110215845 | POWER-UP SIGNAL GENERATOR FOR USE IN SEMICONDUCTOR DEVICE - In an apparatus for generating a power-up signal, a mode register set (MRS) and other circuits are prevented from being reset, thereby providing stable circuit operation. A final power-up signal is not disabled even though an internal voltage generating unit is turned off at a test mode. The apparatus includes a power-up signal generator for producing a power-up signal; a multiplexing unit for selectively outputting the power-up signal or a static voltage signal in a test mode; and a power-up signal generator for producing a final power-up signal in response to the power-up signal of the power-up signal generator and an output signal of the multiplexing unit as the final power-up signal. | 09-08-2011 |
| 20110221483 | INTEGRATED CIRCUIT AND STANDBY CONTROLLING METHOD THEREOF - The present invention is applicable to the field of electrics and provides an integrated circuit (IC) and a standby controlling method thereof. The IC comprises a reset device, a standby control device, a functional device and a power supply control device. The functional device at least comprises a functional unit that does not operate in a standby mode. The power supply control device is configured to supply power to the functional device, the standby control device and the reset device. The standby control device is configured to control the power supply control device to control a power supply voltage of the functional unit to be within a preset range below a normal operating voltage when a standby status signal is detected, and restore the power supply voltage into the normal operating voltage when a wake-up signal is detected; and the reset device is configured to reset the functional device when the system standby status signal is detected and release the resetting of the functional device when the wake-up signal is detected. The IC of the present invention reduces the time required by the IC to wake up from the standby mode while ensuring that the whole functional device has low static power consumption. | 09-15-2011 |
| 20110285429 | Microcontroller and method of controlling the same - A microcontroller includes a data input unit that receives input data and outputs a start request signal according to the input data upon receiving the input data; an oscillator that starts according to the start request signal, to generate a clock signal; a clock signal supply control unit that outputs the start request signal supplied from the data input unit to the oscillator, and supplies the clock signal supplied from the oscillator generated after the start as a first clock signal and a second clock signal that are operation clock signals of the data input unit; and a CPU that operates the second clock signal as an operation clock, and performs processing according to the input data when the second clock signal is operated. | 11-24-2011 |
| 20110291710 | CLOCK SUPPLY APPARATUS - A clock supply apparatus for supplying clock signals to a plurality of circuit blocks includes a supply unit configured to supply, to reset the plurality of circuit blocks, a clock signal rising at timing different from one circuit block to another to each of the plurality of circuit blocks. | 12-01-2011 |
| 20110316592 | REFRESH OPERATION DURING LOW POWER MODE CONFIGURATION - A target circuit of an electronic device is placed in a suspended mode by disconnecting the target circuit from one or more voltage sources. A refresh controller periodically initiates a refresh operation during the suspended mode by temporarily reconnecting the target circuit to the one or more voltage sources for a duration sufficient to recharge capacitances of the target circuit. The refresh controller terminates the refresh operation by disconnecting the target circuit from the one or more voltage sources, thereby continuing the suspended mode of the electronic device. The refresh controller can employ a Very Low Frequency Oscillator (VLFO) to time the frequency of refresh operations. The VLFO manages the refresh initialization timing based on the voltage across a capacitor that is selectively charged or discharged so as to implement the refresh operation. The refresh controller further can employ a counter to time the duration of the refresh operation. | 12-29-2011 |
| 20120001668 | DIE AND A PACKAGE COMPRISING A PLURALITY OF DIES - A first die includes a controller configured to select at least one task to be performed by the first die and signal circuitry configured in response to the selection of the at least one task to provide a signal to be sent to a second die for initiating performance of at least one task on the second die which corresponds to (and is to be performed in a time coordinated manner with) the at least one task on the first die. The first die has task circuitry configured to perform the task in response to generation of the signal, and the second die has task circuitry configured to perform the corresponding task in response to receipt of the signal. | 01-05-2012 |
| 20120007639 | SEMICONDUCTOR DEVICE - A semiconductor device includes a reset signal generator configured to change the number of activated signals among a plurality of reset signals according to a frequency of an external clock, a plurality of mixing control signal generators configured to generate a plurality of first and second mixing control signals, and a clock mixer configured to generate a mixing clock by mixing a first driving clock and a second driving clock, wherein the first driving clock is generated by driving a positive clock of the external clock according to the plurality of first mixing control signals, and the second driving clock is generated by driving a negative clock of the external clock according to the plurality of second mixing control signals. | 01-12-2012 |
| 20120032716 | Initializing Components of an Integrated Circuit - Methods, systems, and computer program products for initializing one or more components of a system, the system comprising an integrated circuit that comprises at least one processor, are disclosed. A method includes initializing at least one component of the system, determining a temperature of the integrated circuit using a temperature sensing device embedded on the integrated circuit, comparing the determined temperature to a predetermined suitable temperature operating range of at least one additional component to yield a comparison result, and initializing the at least one additional component based on the comparison result. The at least one additional component may be initialized on the condition that the determined temperature of the integrated circuit is within the predetermined suitable temperature operating range of the at least one additional component. | 02-09-2012 |
| 20120038397 | METHOD AND APPARATUS OF RESETTING MOBILE DEVICE - A method and apparatus of resetting a mobile device including a Power Management Integrated Circuit (PMIC) with no manual reset function are provided. The apparatus includes an input unit for creating a specific input signal for a reset according to a user's input. The apparatus includes a reset unit for creating a manual reset input signal in response to the specific input signal, and for blocking battery power supplied to the PMIC by using the manual reset input signal and a signal created during operations of the mobile device. The reset apparatus includes a power unit for supplying the battery power. | 02-16-2012 |
| 20120043998 | RESET CIRCUIT - A reset circuit includes two voltage dividing circuits, a switching circuit, a selection button, two voltage converters, and a processor. The voltage converters convert a first or second power supply for supplying power to the processor. When the first power supply supplies power to the processor the processor operates normally. When the second power supply supplies power to the processor, one of the voltage dividing circuits outputs a signal to the processor to restore an electronic device to factory settings according to the signal. | 02-23-2012 |
| 20120056650 | METHOD FOR ACTIVATING THE COUNTER OF SECTIONALIZER - The invention relates to a method for activating the counter of a sectionalizer that allows the simultaneous opening of the phases of the sectionalizer since it includes for the radio transmission of the opening. According to the invention, the counter of the sectionalizer is activated upon detection of an increase in current over a given period greater than a pre-determined increase, allowing the sectionalizers to be standardized into a single model, as the counter is not activated using a threshold value, and allowing short-circuit currents to be differentiated from increases in current that are simply due to an increase in consumption. | 03-08-2012 |
| 20120062282 | CLOCK MANAGEMENT UNIT AND METHOD OF MANAGING A CLOCK SIGNAL - A clock management unit includes a delay unit; and an output unit, wherein the delay unit receives a clock signal and a reset signal for resetting an external circuit, and supplies a delayed reset signal to the output unit, wherein the output unit supplies to the external circuit an external clock signal obtained by processing the clock signal and the delayed reset signal, and wherein the external clock signal does not experience any edge transitions during at least two periods of the clock signal after the reset signal transitions to an active state for resetting the external circuit. | 03-15-2012 |
| 20120074991 | RESET SIGNAL DISTRIBUTION - Methods, circuits and systems may operate to generate a reset signal at an input reset block and synchronously distribute the reset signal, via a number of pipelined reset blocks, to multiple ports of a core circuit. The reset signal may be transmitted successively to each of the pipelined reset blocks to provide delayed reset signals having delay times. The delay times may be based on locations of the pipelined reset blocks in the reset circuit. On or more of the delayed reset signals may be programmably coupled to one or more ports of the core circuit. Additional methods, circuits, and systems are disclosed. | 03-29-2012 |
| 20120092044 | CIRCUIT FOR SWAPPING A MEMORY CARD IN AN ELECTRONIC DEVICE - A circuit for hot-swapping a memory card in an electronic device is disclosed. A power-reset unit has a first node electrically coupled to a power supply, and a second node electrically coupled to a power pin of the memory card. The power-reset unit is configured to generate a rising voltage at the second node without rebooting the electronic device when the memory card is hot-plugged into the electronic device. | 04-19-2012 |
| 20120092045 | RSMRST SIGNAL OUTPUT CIRCUIT - A resume and reset (RSMRST) signal output circuit, for outputting a low level voltage RSMRST signal, includes a first switch circuit, a delay circuit, and a second switch circuit. The first switch circuit receives a first voltage signal and converts the first voltage signal to a second voltage signal. The delay circuit is charged by the second voltage signal and outputs the second voltage signal it is when fully charged. The second switch circuit receives the second voltage signal and outputs the low level voltage RSMRST signal. The delay circuit is charged during a first state and discharged during a second state. | 04-19-2012 |
| 20120105112 | Method and Apparatus for Providing System Clock Failover - A method and apparatus for providing system clock failover using a one-shot circuit are disclosed. A process, in one embodiment, is able to detect a clock failure using a one-shot circuit, wherein the clock signals are generated by a first clock circuit. Upon generating a switching signal in response to the clock failure, a system reset signal is asserted for a predefined time period in accordance with the clock failure. After switching a second clock circuit to replace the first clock circuit, the process is capable of resuming the clock signals via the second clock circuit. | 05-03-2012 |
| 20120112803 | PROCESS, TEMPERATURE, PART AND SETTING INDEPENDENT RESET PULSE ENCODING AND DECODING SCHEME - A method of generating a reset signal for an integrated circuit without a dedicated reset pin includes calibrating a first clock pulse from a clock signal, measuring a second clock pulse from the clock signal, measuring a third clock pulse from the clock signal, and generating an internal reset signal if the first clock pulse width is longer than a predetermined minimum clock pulse width, if the second clock pulse is within an expected first value range, and if the third clock pulse is within an expected second value range. | 05-10-2012 |
| 20120112804 | CALIBRATION METHOD AND APPARATUS FOR CLOCK SIGNAL AND ELECTRONIC DEVICE - An embodiment of the invention provides a clock calibration method to calibrate an internal clock signal of a computer. The method comprises: receiving an external clock signal from an external clock source; generating a pulse signal with a first duration according to the external clock signal; counting the internal clock signal according to the pulse signal to get a first count value; and calibrating the internal clock according to the first count value. | 05-10-2012 |
| 20120112805 | PHASE-FREQUENCY DETECTOR - A phase-frequency detector includes an up signal generating unit and a down signal generating unit. The up signal generating unit is configured to evaluate a first node to generate an up signal, precharge the first node in response to a first clock, and reset the first node in response to the first clock, the up signal, and a down signal. The down signal generating unit is configured to evaluate a second node to generate a down signal, precharge the second node in response to a second clock, and reset the second node in response to the second clock, the up signal, and the down signal. | 05-10-2012 |
| 20120119799 | WAKE-UP CIRCUIT AND AN ON BOARD UNIT INCLUDING THE SAME, A FILTER, METHODS FOR FREQUENCY DETECTION AND FILTERING - A wake-up circuit, comprising: a control signal generation circuit comprising: a pulse generator configured to receive a digital signal and generate a pulse sequence signal with a frequency thereof; a first comparison circuit and a second comparison circuit both coupled to the pulse generator and configured to receive the pulse sequence signal; the first comparison circuit is configured to compare the frequency of the pulse sequence signal with a first threshold frequency and generate a first control signal; the second comparison circuit is configured to compare the frequency of the pulse sequence signal with a second threshold frequency and generate a second control signal; the frequency detector further comprises: an indication generation circuit configured to generate a wake-up indication if the frequency of the pulse sequence signal falls within a frequency range defined by the first and second threshold frequencies. | 05-17-2012 |
| 20120119800 | PLL FREQUENCY SYNTHESIZER - In a digital PLL frequency synthesizer, after lock detection, first oscillating signal phase information is switched to second oscillating signal phase information by an estimation section based on previous oscillating signal phase information and a phase difference. As a result, the first oscillating signal phase information which has a risk of an error in the normal state (locked state) is not used. In addition, a conventional high-speed latch circuit for reclocking is not required. As a result, power consumption can be reduced, compared to the conventional art, while reducing or avoiding a degradation in phase-noise characteristics. | 05-17-2012 |
| 20120126863 | ELECTRONIC CIRCUIT, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE - The electronic circuit includes a first comparator and a second comparator in which an induced electromotive force of a coil are compared with each of a first reference potential and a second reference potential and which output a pulse signal in accordance with conditions; the first signal processing circuit which outputs a first receiving rectangular wave signal and a first error signal in accordance with conditions of the pulse signal output from the first comparator and in which data held in accordance with conditions of pulse signal output from the second comparator is reset; and the second signal processing circuit which outputs a second receiving rectangular wave signal and a second error signal in accordance with conditions of the pulse signal output from the second comparator and in which data held in accordance with conditions of pulse signal output from the first comparator is reset. | 05-24-2012 |
| 20120169385 | ELECTRONIC DEVICE WITH RESET CIRCUIT - A reset circuit used for resetting a processing unit of an electronic device includes a switch control unit, a first switch unit, and a reset signal generation unit. The switch control unit controls the on and off state of the first switch unit according to users' operation. The reset signal generation unit outputs a reset signal after the first switch unit has been off for a predetermined time period. The reset signal generation unit stops outputting the reset signal as the first switch unit turns on. The processing unit is reset when receiving the reset signal. | 07-05-2012 |
| 20120169386 | RESETTING CIRCUIT - An exemplary resetting circuit adapted for regulating a voltage on an output terminal of a shift register is disclosed. The resetting circuit includes a reset driving module and a reset module. The reset driving module is received with an enable signal to output a control voltage signal to an output terminal of the reset driving module. The reset module is electrically coupled to the output terminal of the shift register and the output terminal of the reset circuit driving module, and is controlled by the control voltage signal on the output terminal of the reset driving module to determine whether switching on an electrical path between the output terminal of the shift register and a gate-off voltage level. | 07-05-2012 |
| 20120176166 | DRIVER CIRCUIT - A driver circuit drives a pulse width modulation (PWM) controller. The driver circuit includes an enabling circuit, a power supply input control circuit, a stabilizing circuit, and a discharge circuit. The stabilizing circuit is electrically connected to the PWM controller. The power supply input control circuit is electrically connected between the enabling circuit and the stabilizing circuit. The discharge circuit is electrically connected between the stabilizing circuit and the ground. In response to the driver circuit working in normal operation, the enabling circuit enables the power supply input control circuit to output a working voltage to the stabilizing circuit, and in response to the process of the driver circuit restarting, the enabling circuit enables the power supply input to stop outputting power supply to the stabilizing circuit. The discharge circuit leads a residual voltage of the stabilizing circuit to the ground, during the process of the driver circuit being restarted. | 07-12-2012 |
| 20120187984 | PREVENTING METASTABILITY OF A DIVIDE-BY-TWO QUADRATURE DIVIDER - Embodiments of the present invention provide an approach for receiving true and complement clock signals at high or low frequencies into inputs of a divide-by-two quadrature divider, and providing true and complement clock signals, which are one-half the measured frequencies of the clock input signals, at the output of the quadrature divider. A tri-state clock mux coupled with combinatorial reset logic, with pull-up and pull-down devices at the output of the tri-sate clock mux, and/or pull-up and pull-down devices between the quadrature divider latches provide a defined logic state during startup at the input of the quadrature divider. The defined logic state ensures the output of the quadrature divider is metastability-free during high frequency application. Specifically, the quadrature divider has two output clock signals that are true and complement with measured frequencies that are one-half of the measured frequencies of the two clock input signals coming into the quadrature divider. | 07-26-2012 |
| 20120194230 | CONTROL CIRCUIT AND DATA HOLD DEVICE USING THE CONTROL CIRCUIT - A control circuit | 08-02-2012 |
| 20120200322 | CLOCK TREE INSERTION DELAY INDEPENDENT INTERFACE - Disclosed herein is a multi-clock interface, an integrated circuit and a module thereof having the multi-clock interface and a library having cells corresponding to the above noted circuitry. In one embodiment the multi-clock interface includes: (1) a multi-clock reset synchronizer configured to receive a first external clock signal and a second external clock signal that is a multiple of the first clock signal, the reset synchronizer configured to synchronize a reset of both the first and second external clock signals and based thereon generate a reset release signal and (2) a multi-phase clock generator configured to receive the reset release signal and the second clock signal, the multi-phase clock generator configured to generate multiple clock phases from the second clock signal based on the reset release signal. | 08-09-2012 |
| 20120229181 | ASYNCHRONOUS CIRCUIT - The asynchronous circuit includes a plurality of circuit blocks connected in a hierarchical structure, each circuit block including an arithmetic circuit and a control circuit that makes two-phase control on the arithmetic circuit, and a mode control circuit. The mode control circuit controls a circuit block in a first stage to start initialization when the circuit block starts idle phase and start working phase when a circuit block in a lowermost stage starts idle phase, and controls a circuit block in a second stage to start working phase when the circuit block in the first block starts initialization and start initialization when the circuit block in the first stage starts working phase. This improves the processing speed of a two-phase asynchronous circuit and suppresses an increase in circuit size. | 09-13-2012 |
| 20120235715 | RESET CIRCUIT AND METHOD OF PORTABLE TERMINAL - A reset circuit and a reset method of a portable terminal are provided. The reset circuit of a portable terminal includes an input unit for generating a certain input signal for reset according to a user input, a reset unit for generating a manual reset input signal according to an input of the certain input signal, for performing a control operation to cut-off power to be supplied to a Power Management IC (PMIC) using a signal generated during an operation maintenance time interval of the portable terminal and the manual reset input signal, and for performing a control operation to resupply the power to the PMIC according to an input signal from the input unit or completion of a preset timer, and a power supply unit for supplying the power. | 09-20-2012 |
| 20120249193 | MEASUREMENT INITIALIZATION CIRCUITRY - Measurement initialization circuitry is described. Propagation of a start signal through a variable delay line may be stopped by either of two stop signals. One stop signal corresponds to a rising edge of a reference clock signal. A second stop signal corresponds to a falling edge of the reference clock signal. The start signal propagation is stopped responsive to the first to arrive of the first and second stop signals. Accordingly, in some examples, start signal propagation through a variable delay line may be stopped responsive to either a rising or falling edge of the reference clock signal. | 10-04-2012 |
| 20120256662 | POWER-UP SIGNAL GENERATION CIRCUIT - A power-up signal generation circuit includes: a first section signal generation unit configured to sense a level of an external voltage and a level of an internal voltage and generate a first section signal; a second section signal generation unit configured to output a second section signal by buffering the first section signal when the internal voltage is lowered to below a minimum level; and a selective output unit configured to output the first section signal as a power-up signal, wherein the selective output unit outputs the second section signal as the power-up signal when a power-up section is ended and a mode register setting operation is performed. | 10-11-2012 |
| 20120256663 | INITIALIZATION CIRCUIT AND BANK ACTIVE CIRCUIT USING THE SAME - An initialization circuit comprises a section signal generator generating a section signal, of which a prescribed section is enabled in response to a power-up signal, a first oscillator generating a first period signal in response to the section signal, a first period multiplier generating a first multiplied signal by multiplying a period of the first period signal, and a signal selector transferring the first multiplied signal or a second multiplied signal selectively as a self-refresh enable signal in response to the section signal. | 10-11-2012 |
| 20120268173 | SEMICONDUCTOR MODULE INCLUDES SEMICONDUCTOR CHIP INITIALIZED BY RESET SIGNAL - Disclosed herein is a device that includes a plurality of semiconductor chips mounted on a module substrate. Each of the semiconductor chips includes a reset terminal to which a reset signal is supplied, and an internal circuit that is initialized based on the reset signal. The module substrate includes a reset signal line connected commonly to the reset terminals of the semiconductor chips, and an anti-resonance element connected to the reset signal line. | 10-25-2012 |
| 20120268174 | SYSTEM FOR DETECTING A RESET CONDITION IN AN ELECTRONIC CIRCUIT - There is disclosed a system for detecting the assertion of a reset signal. A plurality of circuit elements is configurable by a reset signal to output a string of data values in a predetermined pattern. A comparator receives the string of data values and determines whether the string of data values matches the predetermined pattern. If so, the comparator generates an output signal indicative of a reset. In one embodiment, the output signal of the comparator can be used to automatically trigger a reset if the reset signal has not been asserted. | 10-25-2012 |
| 20120293220 | Reset Control Device, Reset Control Method and Electronic Device - A reset control device for an electronic device having a battery for providing operating power for a system circuit is provided. The reset control device includes a signal generating unit for generating a control signal, and a control module installed in the battery and coupled to the signal generating unit for disconnecting a power supply link between the battery and the system circuit for a predetermined duration and recovering the power supply link, when the control signal conforms to a predefined rule, so as to reset the system circuit. | 11-22-2012 |
| 20120306548 | INITIALIZATION CIRCUIT FOR DELAY LOCKED LOOP - An initialization circuit in a delay locked loop ensures that after power up or other reset clock edges are received by a phase detector in the appropriate order for proper operation. After reset of the delay locked loop, the initialization circuit assures that at least one edge of a reference clock is received prior to enabling the phase detector to increase (or decrease) the delay in a delay line. After at least one edge of a feedback clock is received, the initialization circuit enables the phase detector to decrease (or increase) the delay in a delay line. | 12-06-2012 |
| 20120313675 | TOUCH PANEL SYSTEM WITH DELAY COMPENSATION CAPABILITY AND METHOD FOR COMPENSATING DELAY IN TOUCH PANEL SYSTEM - A touch panel system includes a signal generator configured to generate a reference signal and one or more channels. Each of the channels comprises a sensing unit configured to sense a touch thereon to output a sensing signal indicative of the touch; and a delay unit configured to adjust the reference signal based on a delay compensation value to compensate delay of the reference signal caused by the difference of distance between the signal generator and the channel. Further, each of the channels comprises an operation unit configured to perform an operation on the sensing signal and the reference signal from the delay unit to produce an operation result representing difference between the sensing signal and the adjusted reference signal; and a controller configured to determine the delay compensation value of the delay unit in each channel based on the voltage signal from the operation unit. | 12-13-2012 |
| 20130002316 | RESET PULSE ENCODING AND DECODING SCHEME WITH NO INTERNAL CLOCK - An integrated circuit (IC) provides a reset function. The IC receives a command that is defined by a first sequence of counts of signal transitions of a first signal during windows of a second signal and provides a reset function when it is determined that the command is received. A device including the IC and a system including the device are provided. | 01-03-2013 |
| 20130027095 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR DRIVING THE SAME - A semiconductor integrated circuit includes a command generating unit configured to generate a plurality of second commands in response to a first command, each second command for indicating an operation sections of a corresponding anti-fuse circuit, and a plurality of anti-fuse circuits, each comprising an anti-fuse and configured to receives a corresponding second command and perform a rupture operation of the anti-fuse in response to the received corresponding second command. | 01-31-2013 |
| 20130033292 | CIRCUITS AND METHODS FOR LATCH-TRACKING PULSE GENERATION - Circuits and methods for latch-tracking pulse generation across process, voltage and temperature (PVT) variations are disclosed in one embodiment, the method includes receiving a clock input at a pulse generation circuit and generating a pulse at the pulse generation circuit in response to the clock input. The method further includes distributing the pulse to a mimic latch, which writes a mimic storage node through a mimic storage circuit of the mimic latch in response to the pulse. The method further includes terminating generation of the pulse at the pulse generation circuit in response to a transition of the mimic storage node. The method may include receiving a clock enable input at a pulse control circuit coupled to the pulse generation circuit and either suppressing or allowing generation of a pulse in response to a value of the clock enable input. | 02-07-2013 |
| 20130057323 | INTEGRATED CIRCUIT FOR CONTROLLING A SWITCH OF A CURRENT PATH WITH LEADING EDGE BLANKING DEVICE OF THE CURRENT SIGNAL - An integrated control circuit of a switch is described, which is adapted to open or close a current path; said integrated circuit includes a comparator to compare a first signal with a second signal representative of the current flowing through said current path. The comparator outputs a third variable signal between a low logic level and a high logic level according to whether said second signal is lower than said first signal or vice versa; the integrated circuit has a driver to generate a signal to drive said switch in response to the third signal, and is configured to detect a spike on the leading edge of said second signal and to blank said third signal for a first blanking time period which depends on a turn-on delay of said switch and a second blanking period which depends on the duration of said spike on the leading edge of said second signal. | 03-07-2013 |
| 20130069697 | SYNCHRONIZER WITH HIGH RELIABILITY - A system and method for synchronizing asynchronous input signals with reliability. Each of a first and a second storage element in a synchronizer receives a first clock signal in a first clock domain. The second storage element may also receive a first reset signal generated by a second clock signal in the first clock domain different from the first clock signal. The first storage element receives a combination of an asynchronous data input signal and the first reset signal. The data input signal may be generated from circuitry utilizing a second clock domain different from the first clock domain. The second storage element additionally receives an output of a second combination of a stored output value of the first storage element and a second reset signal generated from the first clock signal. The second storage element stores a stable output value based at least on the asynchronous data input signal. | 03-21-2013 |
| 20130069698 | RESET SIGNAL GENERATING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME - A reset signal generating circuit according to an aspect of the present invention includes: a first signal line that transmits a reference reset signal to a first node; a second signal line that transmits an inverted signal of the reference reset signal to a second node; a first inverting circuit that outputs an inverter signal of the signal transmitted to the second node; and a control circuit that makes a reset signal active regardless of the reference reset signal, when a logical value of the signal transmitted to the first node does not match a logical value of the signal output from the first inverting circuit. | 03-21-2013 |
| 20130082749 | RESET GENERATOR - A reset circuit comprising: a first depletion mode device having a first terminal coupled to a node at a reset voltage and a second terminal for providing a reset signal to at least one device; and a control circuit arranged to switch the first depletion mode device into a high impedance state after a first predetermined period. | 04-04-2013 |
| 20130082750 | Electronic Circuit - An electronic circuit of the present disclosure includes a noise eliminating circuit configured to eliminate noise in a reset signal and output a signal obtained by eliminating the noise in the reset signal; a digital circuit configured to be reset by the signal outputted from the noise eliminating circuit; and an early-initialization circuit configured to fix an output signal of the digital circuit at a predetermined value until a reset status due to the reset signal is released. | 04-04-2013 |
| 20130106473 | POWER-ON RESET CIRCUIT AND METHOD | 05-02-2013 |
| 20130106474 | STARTUP AND PROTECTION CIRCUITRY FOR THIN OXIDE OUTPUT STAGE | 05-02-2013 |
| 20130113530 | Oscillator Based Frequency Locked Loop - A method includes determining a control setting and selectively stopping oscillation of an oscillator after a time period. The oscillator is configured to remain in an active mode after the time period. The method further includes applying the control setting to the oscillator. | 05-09-2013 |
| 20130113531 | ELECTRONIC CIRCUIT, SAFETY CRITICAL SYSTEM, AND METHOD FOR PROVIDING A RESET SIGNAL - An electronic circuit comprises a reset input for receiving an input reset signal, a clock input for receiving a clock signal, and a reset output for providing an output reset signal. And it comprises a synchronous reset signal path comprising a synchronization unit, arranged to receive the input reset signal and provide the input reset signal synchronized with the clock signal to the reset output when the clock signal is available, and an asynchronous reset signal path arranged to provide the input reset signal to the reset output when a current clock availability information in a clock monitoring signal indicates that the clock signal is not available. | 05-09-2013 |
| 20130120032 | Analog Front End Device with Two-Wire Interface - An analog front end (AFE) device has at least one programmable analog-to-digital converter (ADC) and a serial interface switchable to operate in a bidirectional serial interface mode and in a unidirectional two wire serial interface mode, wherein the unidirectional two wire serial interface mode only uses a clock input and a data output signal line, wherein the ADC operates in the unidirectional two wire serial interface mode synchronous with a clock supplied to the clock input. | 05-16-2013 |
| 20130127503 | SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME - A semiconductor device includes a comparison unit configured to compare the phases of a plurality of clocks having different frequencies and output a phase comparison signal, a phase inversion control unit configured to generate a phase inversion control signal, and a start control unit configured to generate a start control signal in response to a clock enable signal, wherein the comparison unit is configured to start an operation in response to the start control signal and invert, in response to the phase inversion control signal, a phase of an internal clock generated from one of the plurality of clocks when the plurality of clocks have different phases. | 05-23-2013 |
| 20130127504 | METHOD FOR RESETTING PHOTOELECTRIC CONVERSION DEVICE, AND PHOTOELECTRIC CONVERSION DEVICE - A reset method of an photoelectric conversion device at least including a phototransistor having a first collector, a first base, and a first emitter, and a first field-effect transistor having a first source, a first drain, and a first gate, includes: connecting the first base, and one of the first source and the first drain of the first field-effect transistor by having a common region, or a continuous region, without a base electrode; supplying a base reset potential to the other of the first source and the first drain; and overlapping a time in which a first emitter potential is supplied to the first emitter and a time in which a first ON-potential that turns on the first field-effect transistor is supplied to the first gate. | 05-23-2013 |
| 20130135017 | SYNCHRONIZER LATCH CIRCUIT THAT FACILITATES RESOLVING METASTABILITY - The disclosed embodiments provide a synchronizer latch circuit that facilitates resolving metastability issues. This synchronizer latch circuit includes a set of lightly loaded, cross-coupled transistors that form a metastable resolving and state-holding element that is coupled to two outputs. An incoming synchronization signal creates a voltage difference between the two outputs, but does not directly force a state change for the outputs. Instead, the data and clock inputs control transistors that allow neighboring power sources and/or ground network connections to weakly influence the outputs. The cross-coupled transistors then amplify the resulting voltage difference to generate valid output voltages, even when the data input and clock signal are received at roughly the same time. Thus, the synchronizer latch circuit facilitates rapidly resolving metastability and improving synchronizer performance. | 05-30-2013 |
| 20130176061 | Delay Locked Loop Circuit and Method - A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached. | 07-11-2013 |
| 20130222017 | RESET DEVICE AND ELECTRONIC SYSTEM HAVING THE SAME - An electronic system is provided. The electronic system comprises a power device and a reset device. The power device provides power to the electronic system. The reset device comprises a wireless signal generator, a wireless signal receiver and a control module. The wireless signal generator generates a wireless signal. The wireless signal receiver receives the wireless signal and generates a control signal in response. The control module is electrically connected to the wireless signal receiver to activate a reset mechanism of the control module or reset the power device upon reception of the control signal from the wireless signal receiver. | 08-29-2013 |
| 20130222018 | ADAPTIVE CLOCK GENERATING APPARATUS AND METHOD THEREOF - An adaptive clock generating apparatus is provided. The apparatus includes a fixed frequency divider, a replica, a counter, a variable frequency divider. The adaptive clock generating apparatus generates a clock whose period varies along with changes in the critical path delay of a synchronous circuit. | 08-29-2013 |
| 20130234765 | VOLTAGE GENERATION CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A voltage generation circuit of a semiconductor memory apparatus includes a plurality of pumping units configured to provide voltages to an output node; a sensing unit configured to sense a voltage level of the output node and generate a pumping enable signal; an oscillator configured to generate an oscillator signal in response to the pumping enable signal; and a control unit configured to selectively output the oscillator signal to the plurality of pumping units in response to an active signal, a power-up signal and a mode register set signal. | 09-12-2013 |
| 20130234766 | INPUT RECEIVER AND OPERATION METHOD THEREOF - An input receiver includes a first input receiving unit, a second input receiving unit, a delay unit, and a first logic unit. The first input receiving unit receives an inverse wake-up signal, an external clock enable signal, a first voltage, and a reference signal, and then generates a first enable signal according to the external clock enable signal and the reference signal. The second input receiving unit receives the external clock enable signal, the first voltage, and an inverse enable voltage, and then generates a second enable signal as its output according to the external clock enable signal. The delay unit generates a wake-up signal according to the second enable signal. The first logic unit receives the wake-up signal and the first enable signal, and then generates an internal clock enable signal according to the wake-up signal and the first enable signal. | 09-12-2013 |
| 20130241609 | SEMICONDUCTOR DEVICE - A semiconductor device for ignition performing a current control function and a self shut down function can include a pulse generating circuit, a switching circuit, and a current source circuit, the three circuits together generating a pulse current that discharges a capacitor in the self shut down process. This construction can serve to suppress oscillation of a collector current Ic of the output stage IGBT in the operating processes of the current control circuit and the self shut down circuit, thus preventing or minimizing the likelihood of the ignition plug from erroneous ignition. In addition, the discharge of the capacitor in a pulsed mode can allow for down-sizing of the capacitor, which can contribute to minimization of the semiconductor device. | 09-19-2013 |
| 20130265088 | OVERCURRENT BASED POWER CONTROL AND CIRCUIT RESET - In one embodiment, a circuit is provided. The circuit includes a load configured to receive power through a power path. The circuit also includes a current monitor configured to sense a current draw on the power path. A switch on the power path is coupled in series between the load and a power rail, and a control circuit is coupled to the current monitor. The control circuit is configured to set the switch to a non-conducting state and to send a reset signal to the load if the current monitor senses an overcurrent on the power path. | 10-10-2013 |
| 20130271189 | CLOCK SUPPLY APPARATUS - A clock supply apparatus for supplying clock signals to a plurality of circuit blocks includes a supply unit configured to supply, to reset the plurality of circuit blocks, a clock signal rising at timing different from one circuit block to another to each of the plurality of circuit blocks. | 10-17-2013 |
| 20130307595 | LATCH CIRCUIT AND FLIP-FLOP CIRCUIT INCLUDING THE SAME - A latch circuit may include a first inverting unit configured to drive a second node in response to a level of a first node, a second inverting unit configured to drive the first node in response to a level of the second node, an initialization unit configured to drive the first node at a first level in response to activation of an initialization signal, and a power breaker configured to break a supply of power of a second level to the second inverting unit when the initialization signal is activated. | 11-21-2013 |
| 20130307596 | PLL DUAL EDGE LOCK DETECTOR - A lock signal indicating that a target signal is in phase with a reference signal includes detecting the reference signal at the rising and falling edges of the target signal. The target signal is detected on the rising and falling edges of the reference signal. An out of phase condition between the target and reference signals is used to place a timing means in a reset state. When the timing means is allowed to time out, a signal is asserted which indicates that the target signal is deemed to be locked to the reference signal. | 11-21-2013 |
| 20130321045 | CHARGE PUMPS WITH IMPROVED LATCHUP CHARACTERISTICS - Some embodiments of the present disclosure relate to improved regulators for charge pumps. Such regulators selectively activate a charge pump based not only on the voltage output of the charge pump, but also on an series of wake-up pulses that are delivered at predetermined time intervals and which are delivered independently of the voltage output of the charge pump. Hence, these wake-up pulses prevent extended periods of time in which the charge pump is inactive, thereby helping to prevent latch-up in some situations. | 12-05-2013 |
| 20130328601 | PULSE LATCHES - A pulse latch includes a pulse generator and a latch circuit. The pulse generator generates first and second pulse signals. The first pulse signal is generated when a test enable signal is in a first state, and the second pulse signal is generated when the test enable signal is in a second state. The latch circuit outputs the latched signal by selectively latching a normal data input signal or a test data input signal. The latch circuit includes first and second tri-state elements. The first tri-state element is controlled by the first pulse signal to enable the test data input signal to be latched when the test enable signal is in the first state. The second tri-state element is controlled by the second pulse signal to enable the normal data input signal to be latched when the test enable signal is in the second state. | 12-12-2013 |
| 20130342245 | RESET SIGNAL GENERATION APPARATUS - A reset signal generation apparatus includes a reset signal generation unit and a reset signal expansion unit. The reset signal generation unit enables a reset signal and an enable signal in response to a reset input signal, and disables the reset signal in response to a pulse width extension signal. The reset signal expansion unit generates the pulse width extension signal that is enabled for a predetermined time, in response to the enable signal. | 12-26-2013 |
| 20140002148 | METHODS, APPARATUSES, AND CIRCUITS FOR BIMODAL DISABLE CIRCUITS | 01-02-2014 |
| 20140015573 | METHOD AND APPARATUS TO AUTOMATICALLY SCALE DLL CODE FOR USE WITH SLAVE DLL OPERATING AT A DIFFERENT FREQUENCY THAN A MASTER DLL - A method and apparatus for scaling a DLL code for a slave DLL operating at a different frequency than a master DLL is disclosed. An apparatus includes a master DLL coupled to receive a first clock signal and a group of series-coupled slave DLLs coupled to receive a second clock signal. The master DLL may provide a specified fraction of a cycle of the first clock signal. Scaling circuitry coupled between the master DLL and the group of slave DLLs may determine a ratio of frequencies of the first clock signal to the second clock signal. Based on the ratio and a delay code from the first DLL, the scaling circuitry may generate an adjusted delay code received by the group of slave DLLs to set a delay for the second clock signal to the specified fraction. | 01-16-2014 |
| 20140035633 | AUTONOMOUS INITIALIZATION METHOD OF FACING PORT OF SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - On a transmission path connecting a first semiconductor integrated circuit that is started by a system management apparatus and a second semiconductor integrated circuit that is not started by the system management apparatus, when connection of the first semiconductor integrated circuit to the second semiconductor integrated circuit is detected, after being turned to a first signal state for detecting a valid lane, each lane on the transmission path is turned to a second signal state corresponding to each bit of initial setting code. In the second semiconductor integrated circuit, the first and second signal states are detected for each lane of the transmission path. Based on the detected signal state, after detecting the first signal state, the second signal state is detected and each bit value of the initial setting code is decoded. Based on the decoded initial setting code, an initialization process is executed. | 02-06-2014 |
| 20140043071 | SELF-INITIALIZING ON-CHIP DATA PROCESSING APPARATUS AND METHOD OF SELF-INITIALIZING AN ON-CHIP DATA PROCESSING APPARATUS - An on-chip data processing apparatus has an operating supply voltage selected from a range of supply voltages and has voltage level detection circuitry configured to determine the level of the operating supply voltage. The voltage level detection circuitry comprises adaptive circuitry responsive to a variation in the reference voltage. Phase lock loop circuitry is configured to generate a source clock signal from the operating supply voltage, to receive the voltage level selection signal, to select a target frequency for the source clock signal in dependence on the voltage level selection signal, and to phase lock the source clock signal on the target frequency. Initialization circuitry is configured to initialize the on-chip data processing apparatus for data processing in dependence on the level of said operating supply voltage after the phase lock loop circuitry has phase locked the source clock signal on the target frequency. | 02-13-2014 |
| 20140055177 | Reset Circuit For Gate Driver On Array, Array Substrate, And Display - A reset circuit for Gate Driver on Array, an array substrate and a display is used for increasing reliability and long-term stability of a GOA circuit and thus improving performance of the GOA circuit. The GOA reset circuit includes a first electronic switch circuit ( | 02-27-2014 |
| 20140062545 | Method and Apparatus for Reducing the Clock Kick-Back of ADC Comparators While Maintaining Transistor Matching Behavior - The core concept of this ADC is the high-speed fully-differential comparators which are clocked at 2.64 GHz and used in a 60 GHz transceiver. The comparator consists of a pre-amplifier stage, a capture stage, a regeneration cell and an output latch. The pre-amplifier stage is not clocked; therefore, the pre-amplifier stage does not suffer initialization and transient behavior effects when the clock signal switches state. The transient response of being enabled and disabled is eliminated. Instead, a capture stage transfers the contents of the pre-amplifier stage into a memory regeneration stage. The capture stage is clocked by pulses that are timed to minimize the clock kick-back generated by the memory regeneration stage. The clock kick-back is reduced even when many comparators are coupled to the PGA. The comparators, instead of having extra dummy fingers, are also aligned right next to each other to minimize the mismatching layout effect. | 03-06-2014 |
| 20140062546 | SEMICONDUCTOR DEVICE AND METHOD OF DRIVING THE SAME - A semiconductor device includes a division unit configured to divide an oscillation signal and to generate a plurality of divided signals having different division ratios each other, a delay amount determination unit configured to combine an source signal, the oscillation signal, and the plurality of divided signals and to generate a delay amount information signal with information on a given delay amount, and an edge-delayed signal output unit configured to generate at least one edge-delayed signal corresponding to the given delay amount in response to the source signal and the delay amount information signal. | 03-06-2014 |
| 20140062547 | CORE VOLTAGE RESET SYSTEMS AND METHODS WITH WIDE NOISE MARGIN - Presented systems and methods facilitate efficient reset operation. In one embodiment, a system comprises a core domain portion an I/O domain portion and a core reset I/O by-pass component. The core domain portion is configured to operate at a nominal core domain voltage level. The I/O domain portion configured to operate at a nominal I/O domain voltage level. The core reset I/O by-pass component configured to forward a reset indication to the core domain independent of the I/O domain. In one exemplary implementation the core reset I/O by-pass component is operable to receive an input reset indication at a high domain voltage level and to convert the input reset indication to a core reset signal that is less than or substantially equal to the nominal core domain voltage, wherein the high domain is voltage higher than the core domain voltage level. | 03-06-2014 |
| 20140103972 | DUTY CYCLE PROTECTION CIRCUIT - A duty cycle protection circuit including a first synchronous device adapted to receive a first clock signal on an input line and to generate a first clock transition of a second clock signal in response to a first clock transition of the first clock signal; and reset circuitry coupled to the input line and adapted to generate a second clock transition of the second clock signal by resetting the first synchronous device a time delay after the first clock transition of the first clock signal. | 04-17-2014 |
| 20140118033 | GLITCHLESS CLOCK SWITCHING THAT HANDLES STOPPED CLOCKS - An integrated circuit receives a first and second clock signal and a select signal that selects one of the clock signals. A glitchless switching circuit supplies an output clock signal according to which of the first and second clocks is selected by the select signal. A reset circuit coupled to the glitchless switching circuit responds to a direction of a transition of the select signal and generates a first reset signal in response to a first direction of the transition and generates a second reset signal in response to a second direction of the transition. The reset pulses are supplied respectively to first and second paths in the glitchless switching circuit to reset the state machine formed by the first and second paths in the event one of the input clocks is absent. | 05-01-2014 |
| 20140125387 | SEMICONDUCTOR DEVICE INCLUDING A DELAY LOCKED LOOP CIRCUIT - A method for initializing a delay locked loop having a delay circuit includes a plurality of serially connected delay elements and a counter circuit for selecting an output of one of the delay elements as an output clock signal. The method includes resetting an initial delay control circuit, generating, with the initial delay control circuit, a pulse based on a period of an input clock signal, determining, with the initial delay control circuit, a number of delay elements required to produce a delay time at least substantially equivalent to a pulse width for a preset signal, initializing the counter circuit based on the preset signal and adjusting the counter circuit in response to phases of the input and output clock signals. | 05-08-2014 |
| 20140132315 | INTEGRATED CIRCUIT WITH DEGRADATION MONITORING - An integrated circuit including a degradation monitoring circuit. The degradation monitoring circuit includes a comparison circuit having a delay element including an input coupled to a data node of a timing path and having an output to provide a delayed signal of a data signal of the data node. The comparison circuit includes a logic comparator that provides a logic comparison between a data signal of the data node and the output of the delay element. The monitoring circuit includes a sampling circuit that provides a sampled signal of the output of the logic comparator that is a sampled with respect to a clock signal of the clock signal line. The monitoring circuit includes a hold circuit that provides a signal indicative of a data signal of the data node transitioning within a predetermined time of an edge transition of a clock signal of the clock signal line. | 05-15-2014 |
| 20140145764 | MULTI-PHASE CLOCK GENERATION CIRCUIT - A multi-phase clock generation circuit includes a first clock buffer unit configured to invert and buffer a first internal clock and a second internal clock in response to an external clock, and to generate a third internal clock and a fourth internal clock, and a second clock buffer unit configured to invert and buffer the third internal clock and the fourth internal clock in response to the external clock, and to generate the first internal clock and the second internal clock. | 05-29-2014 |
| 20140159783 | ELECTRONIC DEVICE AND RESET CIRCUIT - A reset circuit is connected to a processor chip to reset the processor chip. The reset circuit includes a control unit, a standby power, and a voltage converting unit. The standby power provides power to the control unit. The control unit receives external control signals and outputs an enable signal in responds to the external control signal. The voltage converting unit converts an external voltage into a work voltage and generates a reset signal in responds to the enable signal. The voltage converting unit provides the work voltage to the processor chip and transmits the enable signal to control the processor chip to reset. | 06-12-2014 |
| 20140184283 | TIME SEQUENCE CIRCUIT FOR POWER SUPPLY UNIT - A time sequencing circuit for a power supply unit to ensure the correct sequencing of system voltages for a computer from a power supply unit includes first to ninth resistors, first to fifth electronic switches, and a capacitor. Each of the first to fifth electronic switches includes first to third terminals. When the power supply unit outputs all required voltages, the power supply unit outputs a high-voltage level indicating power good and the computer can start up. If any one of the required voltages is not being outputted, the power supply unit outputs a low-voltage level good signal until any non-output of voltage is cured. | 07-03-2014 |
| 20140184284 | SEMICONDUCTOR DEVICE - A method for synchronizing an output clock signal with an input clock signal in a delay locked loop. A first count values decreasing the number of bypassed elements in a differential delay line until an edge of the output clock signal is delayed relative to an edge of the input clock signal or the first count value reaches a first count final value if the first count value reaches the first count final value, a second count value is adjusting to decrease the number of bypassed elements in a single-ended delay line until the edge of the output clock signal is delayed relative to the edge of the input clock signal. A third count value is adjusted to decrease the delay of an interpolator until the edge of the output clock signal is no longer delayed with respect to the edge of the input clock signal. | 07-03-2014 |
| 20140191786 | PHASE FREQUENCY DETECTOR CIRCUIT - A phase-frequency detector (PFD) circuit is disclosed. The PFD circuit includes a PFD portion adapted to detect frequency and phase difference of two input signals and to generate control signals according to the detected frequency and phase difference and a delay and reset portion adapted to delay the generated control signals, to generate reset signals for resetting the PFD portion based on a combination of the control signals and the delayed control signals, and to provide the generated reset signals to the PFD portion. | 07-10-2014 |
| 20140197870 | RESET EXTENDER FOR DIVIDED CLOCK DOMAINS - A clock divider may provide a lower speed clock to a logic block portion, but during reset, the clock divider may not operate properly, causing the logic block portion to be reset at a clock frequency greater than the frequency for which that logic was designed. However, an extended reset may be employed in which the clock divider is reset normally first before the logic block portion, allowing that logic to be reset according to the divided clock (e.g., rather than a higher speed clock). An asynchronous reset may also be employed in which one or more clock dividers first emerge from reset before being provided with a (synchronized) high speed clock signal, causing the clock dividers to be in phase with each other. This may enable communication between different areas of an IC that might not otherwise be in proper phase with each other. | 07-17-2014 |
| 20140218077 | METHODS, APPARATUSES, AND CIRCUITS FOR BIMODAL DISABLE CIRCUITS - Circuits, integrated circuits, and methods are disclosed for bimodal disable circuits. In one such example method, a counter is maintained, with the counter indicating a logic level at which an output signal will be disabled during at least a portion of one of a plurality of disable cycles. The logic level indicated by the counter is transitioned. An input signal is provided as the output signal responsive to the enable signal indicating that the output signal is to be enabled, and the output signal is disabled at the logic level indicated by the counter responsive to the enable signal indicating that the output signal is to be disabled. | 08-07-2014 |
| 20140266333 | GENERATING CLOCK ON DEMAND - A clock generation system for an integrated circuit (IC) chip (e.g., a microcontroller) is disclosed that allows digital blocks and other components in the IC chip to start and stop internal clocks dynamically on demand to reduce power consumption. | 09-18-2014 |
| 20140266334 | FINE GRAIN DATA-BASED CLOCK GATING - Embodiments of a logic path are disclosed that may allow for a reduction in switching power. The logic path may include a storage circuit, a comparison circuit, and a clock gating circuit. The storage circuit may be configured to store received data responsive to a local clock signal. The comparison circuit may be operable to compare the received data to data previously stored in the storage circuit. The clock gating circuit may be configured to generate the local clock signal dependent on a global clock signal, and de-activate the local clock signal dependent upon the results of the comparison performed by the comparison circuit. | 09-18-2014 |
| 20140266335 | INTEGRATED CIRCUIT AND CONTROL METHOD THEREOF - There is provided an integrated circuit having a plurality of circuit blocks. An acquisition unit acquires a request of a reset operation for at least one of the plurality of circuit blocks. A determination unit determines, based on constraining condition information indicating whether or not a reset target circuit block can perform the reset operation simultaneously with another circuit block in which the reset operation is underway, whether or not to instruct the reset target circuit block to perform the reset operation according to the request. An instruction unit instructs the reset target circuit block to start the reset operation according to the request when the determination unit determines to instruct the reset target circuit block to perform the reset operation. | 09-18-2014 |
| 20140300395 | SAFE RESET CONFIGURATION OF FUSES AND FLOPS - Methods, apparatus, and fabrication techniques relating to improved propagation of fuse data through an integrated circuit device during scan shift reset. In some embodiments, the methods comprise loading a first value of at least one fuse bit to an integrated circuit device, during a time period when a clock signal having a first frequency is provided to at least one component of the integrated circuit device; disabling a scan shift after the loading of the first value; inactivating the clock signal after the loading of the first value; propagating the first value of the at least one fuse bit to the at least one component of the integrated circuit device; and reactivating the clock signal after the propagation of the first value. | 10-09-2014 |
| 20140320179 | SIGNAL GENERATING APPARATUS FOR GENERATING POWER-ON-RESET SIGNAL - A signal generating apparatus, for generating a power-on-reset signal, including a bias circuit and a power-on-reset signal generating circuit is disclosed. The bias circuit is for generating an output bias voltage, and includes at least one bipolar junction transistor (BJT), wherein a base terminal of the BJT is coupled to a collector terminal of the BJT, and the output bias voltage is related to an emitter-to-base voltage of the BJT. The power-on-reset signal generating circuit is coupled to the bias circuit, and is for generating a duplicated voltage by duplicating the output bias voltage, wherein the power-on-reset signal is generated according to the duplicated voltage. | 10-30-2014 |
| 20150035571 | WAVEFORM GENERATION - A predetermined waveform is generated using a lower frequency clock signal ( | 02-05-2015 |
| 20150042385 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor device includes a buffer unit suitable for outputting a first signal of differential input signals as a positive signal, and a second signal of differential input signals as a negative signal in response to a setting signal, and a setting control unit suitable for generating the setting signal based on a level state of the positive signal and the negative signal in response to a reset signal. | 02-12-2015 |
| 20150084676 | APPARATUS AND METHODS FOR SYNCHRONIZING PHASE-LOCKED LOOPS - Apparatus and methods for synchronizing phase-locked loops (PLLs) are provided. In certain implementations, a fractional-N synthesizer includes a PLL and a control circuit that controls a division value of the PLL. The control circuit includes an interpolator, a reset phase adjustment calculator, and a synchronization circuit. The interpolator can control a fractional portion of the PLL's division value. The reset phase adjustment calculator can include a counter for counting a number of cycles of the reference clock signal since initialization of the fractional-N synthesizer, and the reset phase adjustment calculator can generate a phase adjustment signal based on the count. The synchronization circuit can synchronize the PLL in response to a synchronization signal, and can correct for a synchronization phase error indicated by the phase adjustment signal. | 03-26-2015 |
| 20150091621 | ADVANCED CLOCK SYNCHONIZATION CIRCUIT - A circuit and method for switching between a system's internal clock and an external synchronization clock when a stable external clock has been detected, and for switching back to operating the system using said internal clock when a predetermined number of sequential external clock pulses exceed a predetermined switching period dropout threshold or are otherwise missing. | 04-02-2015 |
| 20150130518 | AUTO FREQUENCY CALIBRATION FOR A PHASE LOCKED LOOP AND METHOD OF USE - An apparatus comprises a code generator configured to generate a coarse tuning signal and a reset signal based on a reference frequency and a phase difference signal. The apparatus also comprises a digital loop filter configured to generate a fine tuning signal based on the phase difference signal. The apparatus further comprises a voltage control oscillator configured to generate an output signal based on the coarse tuning signal and the fine tuning signal. The apparatus additionally comprises a divider configured to generate a divider frequency based on a divider control signal and the output signal. The phase difference signal is based, at least in part, on the divider frequency, and the divider is configured to be reset based on the reset signal. | 05-14-2015 |
| 20160006418 | RECEIVER CIRCUIT OF SEMICONDUCTOR APPARATUS - A receiver circuit of a semiconductor apparatus may include, a latch comprising differential input terminals and differential output terminals. The receiver circuit may also include a control unit configured to selectively reset first and second intermediate nodes coupled between the differential input terminals and the differential output terminals according to previous data. | 01-07-2016 |
| 20160048155 | RESET CIRCUITRY FOR INTEGRATED CIRCUIT - An on-board reset circuit for a system-on-chip (SOC) addresses the problem of meta-stability in flip-flops on asynchronous reset that arises when different power domains or reset domains receive resets from different sources. To ameliorate the problem, a reset signal is asserted and de-asserted while the clocks are gated. The clocks are re-instated for a minimum period of time following assertion (or de-assertion) so that logic having synchronous reset can also receive the reset. | 02-18-2016 |
| 20160056825 | Fractional-N All Digital Phase Locked Loop Incorporating Look Ahead Time To Digital Converter - A novel and useful look-ahead time to digital converter (TDC) that is applied to an all digital phase locked loop (ADPLL) as the fractional phase error detector. The deterministic nature of the phase error during frequency/phase lock is exploited to achieve a reduction in power consumption of the TDC. The look-ahead TDC circuit is used to construct a cyclic DTC-TDC pair which functions to reduce fractional spurs of the output spectrum in near-integer channels by randomly rotating the cyclic DTC-TDC structure so that it starts from a different point every reference clock thereby averaging out the mismatch of the elements. Associated rotation and dithering methods are also presented. The ADPLL is achieved using the look-ahead TDC and/or cyclic DTC-TDC pair circuit. | 02-25-2016 |
| 20160085279 | METHOD FOR RESETTING AN ELECTRONIC DEVICE HAVING INDEPENDENT DEVICE DOMAINS - A reset state control circuit adapted to reset independent device domains of an electronic device, said reset state control circuit comprising a capturing unit adapted to capture reset events; and a reset shaping logic adapted to change dynamically a reset control flow to reset device domains of said electronic device depending on a sequence of the reset events captured by said capturing unit. | 03-24-2016 |
| 20160156354 | SENSING CIRCUIT | 06-02-2016 |
| 20160156363 | MASKING CIRCUIT AND TIME-TO-DIGITAL CONVERTER COMPRISING THE SAME | 06-02-2016 |
| 20160164532 | CLOCK CONDITIONER CIRCUITRY WITH IMPROVED HOLDOVER EXIT TRANSIENT PERFORMANCE - Disclosed is a circuit, such as a clock conditioner, that provides an improved ability to exit from holdover operations, most notably during conditions where the clock signal inputs to a PLL of the clock conditioner are significantly out of phase. The circuit utilizes the PLL to generate output clocks based on a reference clock and a feedback clock. During holdover mode, the PLL is unlocked. When the reference clock becomes available and holdover mode can be exited, a holdover controller issues a reset signal that triggers a synchronization of the phases of the inputs to the PLL. The reset signal causes the feedback divider component that generates the feedback clock input to reset its phase and adjust its divide ratio for at least the first divide cycle after restart so that its next rising edge will be phase-aligned with the reference clock. Once the two inputs of the PLL phase detector are phase-aligned, the PLL is re-enabled and the PLL smoothly resumes normal operation. | 06-09-2016 |
| 20160191065 | OUTPUT CONTROL CIRCUIT FOR SEMICONDUCTOR APPARATUS AND OUTPUT DRIVING CIRCUIT INCLUDING THE SAME - An output control circuit may include a period setting signal generation unit configured to output a setup signal enabled during a designated period, in response to a delayed locked loop (DLL) locking signal and an output enable reset signal. The output control circuit may also include a clock division unit configured to divide an internal clock at a preset division ratio in response to the setup signal, and output a divided clock. In addition, the output control circuit may include a shift unit configured to shift the setup signal by a preset first time in response to the divided clock, and output a first delayed setup signal. Further, the output control circuit may include an output unit configured to receive and process the first delayed setup signal in response to the divided clock, and output the output enable reset signal. | 06-30-2016 |
| 20160202723 | METHOD FOR CALIBRATING A CLOCK SIGNAL GENERATOR IN A REDUCED POWER STATE | 07-14-2016 |
| 20160204787 | APPARATUS AND METHOD FOR FAST PHASE LOCKING FOR DIGITAL PHASE LOCKED LOOP | 07-14-2016 |
| 20170237442 | CLOCK GENERATION CIRCUIT, INTERFACE CIRCUIT AND SEMICONDUCTOR SYSTEM USING THE SAME | 08-17-2017 |
