| Entries |
| Document | Title | Date |
|---|
| 20090167381 | Time Measurement of Periodic Signals - A system for measuring a time between a first periodic signal and a second periodic signal. The second signal has a frequency higher than a frequency of the first signal. According to one embodiment, the system includes an electronic circuit for determining an approximation of the time based on a period of the second signal and for determining an adjustment to the approximation based on the second signal and a third signal corresponding to the second signal and aligned with the first signal. The length of the adjustment is less than the period of the second signal. | 07-02-2009 |
| 20090179674 | Phase-combining circuit and timing signal generator circuit for carrying out a high-speed signal transmission - A phase-combining circuit for combining cyclic timing waveforms that have been phase-controlled by control signals based on three or more input signals of different phases, has a weight signal generating circuit and a weighting circuit. The weight signal generating circuit generates weights according to the control signals, and the weighting circuit gives the weights to the respective input signals, with a positive or negative polarity for each one signal. | 07-16-2009 |
| 20090322388 | MULTI-PHASE CORRECTION CIRCUIT - A multi-phase correction circuit adjusts the phase relationship among multiple clock signals such that their rising edges are equidistant in time from one another. | 12-31-2009 |
| 20100176852 | SPREAD SPECTRUM CLOCK GENERATOR USING ARRIVAL LOCKED LOOP TECHNOLOGY - A new technique using arrival locked loop technology to produce a spread spectrum clock signal with random frequency modulation and with precise variable frequency spread is presented. The arrival locked loop includes three modules, the arrival comparator with a precise spread control, the loop filter and the VCO. An arrival locked loop is made unstable and oscillates at a certain frequency to produce a low frequency modulation signal on the final error correction output to spread the high frequency output signal from VCO in frequency. The period of frequency spread in each cycle of the low frequency modulation signal also increases by a small random amount of time cycle after cycle until the period of frequency spread becomes so long that cycle-slip is produced to the punctual signal at the input of arrival comparator to reset the period of frequency spread to a small amount. | 07-15-2010 |
| 20100182055 | DEVICE AND METHOD FOR DETECTING AND CORRECTING TIMING ERRORS - A device that includes an error detection circuit that is configured to detect a timing error resulting from a fast voltage drop by comparing a signal from a critical path to a signal from a replica path; and a clock signal provider that is adapted to receive a clock signal and to delay, by a fraction of the clock cycle and in response to a detection of the timing error, the clock signal to provide a delayed clock signal that is provided to a clocked circuit that is coupled to the critical path; and a controller that is configured determine a level of a supply voltage in response to a capability of the error detection circuit and the clock signal provider to manage fast voltage drops; wherein the supply voltage is provided to at least one component of the critical path. | 07-22-2010 |
| 20100182056 | METHODS FOR CALIBRATING GATED OSCILLATOR AND OSCILLATOR CIRCUIT UTILIZING THE SAME - An oscillator circuit is provided. The oscillator circuit includes a gated oscillator and a calibration circuit. The gated oscillator is arranged to generate an oscillator signal according to a control signal, and receive a gating signal to align an edge of the oscillator signal with an edge of the gating signal. The calibration circuit coupled to the gated oscillator is arranged to receive a first clock signal and a second clock signal, detect an alignment operation of the gated oscillator according to the first clock signal and a second clock signal and generate the control signal according to the detected alignment operation. | 07-22-2010 |
| 20100321073 | OSCILLATOR AND PHASE SYNCHRONIZING CIRCUIT - When a direct-current voltage is applied from a power supply, a signal line generates a standing wave having the ¾ wavelength where a starting end of the signal line connected to the power supply is used as a node and a terminating end is used as an antinode. Strips are connected to a ground layer through switches, respectively. The switches switch connection and non-connection of the strips and the ground layer, under the control from a switch controller. By switching the connection and non-connection of the switches, the distance between the signal line and the ground layer is pseudo adjusted and the effective permittivity in a transmission line unit changes. Therefore, the frequency of the standing wave can be adjusted. | 12-23-2010 |
| 20100327924 | WAVEFORM EQUALIZATION CIRCUIT AND WAVEFORM EQUALIZATION METHOD - A waveform equalization circuit includes: a decision feedback equalization unit that feeds back and equalizes an input signal; a clock phase adjustment unit that adjusts a clock phase of a signal equalized by the decision feedback equalization unit based on a signal determined with a prescribed potential as a threshold; and a duo-binary decoder that encodes, into a duo-binary signal, the signal determined with the prescribed potential as a threshold based on a clock adjusted by the clock phase adjustment unit from the signal equalized by the decision feedback equalization unit; wherein the equalized signal is generated by adding the duo-binary signal encoded by the duo-binary decoder to the input signal. A first post-tap of the input signal is equalized by the clock phase adjustment unit without feedback equalization by the decision feedback equalization unit. Second and subsequent post-taps of the input signal are fed back and equalized by the decision feedback equalization unit. | 12-30-2010 |
| 20110043260 | INTEGRATED PULSE-CONTROL AND ENABLE LATCH CIRCUIT - The described embodiments provide a configurable clock circuit. The clock circuit includes a control and enable circuit and a clock distribution circuit. During operation, when a signal on an enable input to the control and enable circuit is asserted and the control and enable circuit is configured in a clock mode, the control and enable circuit generates an enable signal on a control output to enable a signal on a clock input to propagate through the clock distribution circuit to the clock output. Alternatively, when a signal on the enable input to the control and enable circuit is asserted and the control and enable circuit is configured in a pulse mode, the control and enable circuit generates a pulsed control signal on the control output to control a length of a pulse generated from the clock input on a clock output by the clock distribution circuit. | 02-24-2011 |
| 20110057692 | DIGITAL CIRCUITS WITH ADAPTIVE RESISTANCE TO SINGLE EVENT UPSET - A digital circuit with adaptive resistance to single event upset. A novel transient filter is placed within the feedback loop of each latch in the digital circuit to reject pulses having a width less than T, where T is the longest anticipated duration of transients. The transient filter includes a first logic element having a controllable inertial delay and a second logic element coupled to an output of the first logic element. A first controller provides a control voltage VcR to each first logic element to control a rise time of the first logic element to be equal to T. A second controller provides a control voltage VcF to each first logic element to control a fall time of the first logic element to be equal to T. | 03-10-2011 |
| 20110080195 | AUTOMATIC FREQUENCY CONTROL CIRCUIT - The present invention realizes low power consumption at the time of an automatic frequency control circuit operation. An automatic frequency control circuit includes a mixing unit that generates a modulated signal from a reception signal according to a frequency of a local signal, a demodulation unit that demodulates the modulated signal supplied by the mixing unit, an error evaluation unit that generates a frequency error signal according to a duty of the demodulated signal supplied by the demodulation unit, a holding unit that holds a frequency setting of the local signal and updates the frequency setting according to the frequency error signal supplied by the error evaluation unit, and an oscillation unit that controls a frequency of the local signal according to the frequency setting supplied by the holding unit. | 04-07-2011 |
| 20110156772 | INTERFACE APPARATUS FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND INTERFACING METHOD THEREOF - An interface apparatus for a semiconductor integrated circuit and an interfacing method thereof controls the VOX of differential signals to a target level in response to the differential signals being outputted by an output block. The interface apparatus for a semiconductor integrated circuit includes an output block configured to output differential signals output by an internal circuit a detector configured to detect a timing error of the differential signals; and a controller configured to control a timing of the differential signals output by the internal circuit according to a detection result of the detector. | 06-30-2011 |
| 20110204934 | SYSTEM, APPARATUS AND METHOD FOR CALIBRATING A DELAY ALONG A SIGNAL PATH - The present disclosure teaches a calibration system, a calibration apparatus and a method for calibrating a signal path and a method for calibrating a delay. The calibration system comprises an injector, a calibration signal generator, a correlator, a detector unit, a polygon former and a pattern classifier unit. The calibration system is adapted to calculate a fraction of a delay from a set of polygons. The delay is being accumulated along a signal path. The fraction of the delay is indicative of an accuracy of the delay at a fine sampling rate as if the delay was measured at the fine sampling rate being an integer multiple of the coarse sampling rate. The method for calibrating of the signal path uses a calibration signal sampled at a coarse sampling rate. Correlation techniques are used in order to detect a fraction of the delay from a set of polygons. | 08-25-2011 |
| 20110221488 | INTERFACE CIRCUIT WITH DAMPING RESISTOR CIRCUIT - A semiconductor integrated circuit is provided with: a variable resistor section, a variable delay section and a data fetch section. The variable resistor section provides damping for a data signal inputted thereto to thereby generate a damped data signal. The damping resistance of the damping is variable. The variable delay section gives a variable delay to a clock signal to thereby generate a delayed clock signal. The data fetch section fetches data from the damped data signal in synchronization with the delayed clock signal. | 09-15-2011 |
| 20110234269 | METHOD AND APPARATUS FOR QUANTIZATION NOISE REDUCTION IN FRACTIONAL-N PLLS - A first current source supplies a first charge amount responsive to a first pulse signal from the phase frequency detector and a second current source supplies a second charge amount according to a fixed value and a variable value. The variable value corresponds to a phase difference between a first feedback clock signal and a hypothesized feedback clock signal with reduced quantization noise. The first and second charge amounts are of opposite polarity. A single set of first and second current sources perform the functions of charge pump and noise reduction DAC. | 09-29-2011 |
| 20110279155 | Slew rate PWM controlled charge pump for limited in-rush current switch driving - Circuits and methods to limit an in-rush current of a load circuit such as a processor are disclosed. A charge pump is used as driver for switches with pulse modulation width (PWM) control on the duty cycle of a clock. A clock generator generates a ramp signal with variable slope and a reference voltage. The slope of the ramp signal is dependent on the in-rush current of the switch. No dedicated slew rate driver or an external capacitor is required. The main building blocks are: a charge pump used as driver connected to single supply domain, one external (or internal) switch device, a single capacitive feedback between the switch device and the PWM control, and a PWM control comprising a fix frequency voltage triangular pulse generator with variable slope proportional to the in-rush current measurement. | 11-17-2011 |
| 20110291713 | SLAVE DEVICE, SYSTEM INCLUDING MASTER DEVICE AND SLAVE DEVICE, METHOD FOR OPERATING THE SAME, AND CHIP PACKAGE - A slave device communicating with a master device includes a transmission unit configured to transmit a signal to the master device through a communication channel, a calibration unit configured to measure a flight time of a calibration signal which is transmitted to the master device and fed back through a calibration channel coupled to the master device, and a transmission delay unit configured to delay the signal transmitted from an internal circuit of the slave device to the transmission unit by a delay value determined according to the measurement result of the calibration unit. | 12-01-2011 |
| 20110316594 | CHIP INTERFACE - In one aspect, an integrated circuit (IC) system includes a receiver IC configured to receive a first clock signal and includes a feedback circuit to provide a feedback signal to a driver IC. The system also includes the driver IC configured to receive a second clock signal and includes a phase selection circuit configured to provide a phase selection signal to the receiver IC based on the feedback signal. The phase selection signal controls the data received by the receiver IC by adjusting the first clock signal. | 12-29-2011 |
| 20120038399 | ELECTRONIC APPARATUS AND CONTROL METHOD OF THE SAME - According to one embodiment, an electronic apparatus non-masks a clock signal portion used for shift-outputting respective digital signals by first parallel/serial converting device and masks the remaining clock signal portion, in the clock signal supplied to the first and second parallel/serial converting devices, in a first mode. The apparatus non-masks the clock signal supplied to the first and second parallel/serial converting devices, in a second mode. | 02-16-2012 |
| 20120081157 | POWER-SUPPLY NOISE SUPPRESSION USING A FREQUENCY-LOCKED LOOP - An integrated circuit that includes a digitally controlled oscillator (DCO) that adjusts a clock frequency of a critical path of the integrated circuit based on the variations in a power-supply voltage of the DCO and the critical path is described. This DCO may be included in a feedback control loop that includes a frequency-locked loop (FLL), and which determines an average clock frequency of the critical path based on a reference frequency. Furthermore, the DCO may have a selectable delay characteristic that specifies a delay sensitivity of the DCO as a function of the power-supply voltage, thereby approximately matching a manufactured delay characteristic of the critical path. Additionally, for variations in the power-supply voltage having frequencies greater than a resonance frequency associated with a chip package of the integrated circuit, adjustments of the clock frequency may be proportional to the variations in the power-supply voltage and the selectable delay characteristic. | 04-05-2012 |
| 20120161828 | Clock Generating Circuit and Clock Generating Method - A clock generation circuit is provided, having a bandgap reference circuit, a frequency controlled resistor, a comparison circuit and a voltage controlled oscillator. The bandgap reference circuit generates a first voltage. The frequency controlled resistor is coupled to a first node to provide a second voltage. The comparison circuit generates a first current according to a difference between the first voltage and the second voltage. The voltage controlled oscillator outputs first, second and third output clocks according to a third voltage on a second node, wherein the third voltage is generated according to the first current, and the second and third output clocks are fed back to the frequency controlled resistor such that the frequency controlled resistor converts the first current into the second voltage according to the second and third output clocks. | 06-28-2012 |
| 20120194232 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a pre-charge signal generator configured to pre-charge a plurality of oscillation signals to a certain voltage level in a pre-charge mode, wherein the pre-charge signal generator includes: a first storage unit for storing a first pre-charge oscillation signal in response to a reference oscillation signal, a feedback unit for feeding back a second pre-charge oscillation signal, a second storage unit for storing the second pre-charge oscillation signal corresponding to an output signal of the first storage unit in response to the reference oscillation signal, and a pre-charge signal output unit for outputting a pre-charge signal in response to the first pre-charge oscillation signal and the second pre-charge oscillation signal. | 08-02-2012 |
| 20120212265 | DELAY CELL FOR CLOCK SIGNALS - An integrated circuit for delaying a clock signal using a delay cell is described. The integrated circuit includes a current starved inverter. The current starved inverter includes a switched capacitor current source with a first dummy inverter, a first amplifier coupled to the first dummy inverter and a first capacitor coupled to the first amplifier via a first switch. The current starved inverter also includes a first transistor coupled to the current source. The integrated circuit also includes a second capacitor. A delay applied to the clock signal is dependent on a ratio between the first capacitor and the second capacitor. The first capacitor and the second capacitor may be located in proximity such that process, voltage and temperature variations affect the first capacitor and the second capacitor similarly and the delay applied to the clock signal is independent of process, voltage and temperature variations. | 08-23-2012 |
| 20120280728 | POWER SEMICONDUCTOR DEVICE HAVING PLURALITY OF SWITCHING ELEMENTS CONNECTED IN PARALLEL - A power semiconductor device includes first and second power semiconductor elements connected in parallel to each other and a drive control unit. The drive control unit turns on or off each of the first and second power semiconductor elements in response to an ON instruction and an OFF instruction repeatedly received from outside. Specifically, the drive control unit can switch between a case where the first and second power semiconductor elements are simultaneously turned on and a case where one of the first and second power semiconductor elements is turned on first and thereafter the other thereof is turned on, in response to the ON instruction. The drive control unit turns off one of the first and second power semiconductor elements first and thereafter turns off the other thereof, in response to the OFF instruction. | 11-08-2012 |
| 20130076411 | CDR CIRCUIT - A CDR circuit includes a clock recovery circuit that generates, from an external clock, a first clock with which data of a received data signal is to be sampled and a second clock with which an edge of the received data signal is to be sampled and adjusts phases of the first clock and the second clock. The CDR circuit includes a phase detecting circuit that outputs a result of sampling of the received data signal with the first clock as a data sampling result and a result of sampling of the received data signal with the second clock as an edge sampling result. The CDR circuit includes a result comparing circuit that determines that a false lock condition has occurred and outputs a false lock condition detection signal if the edge sampling result matches with the data pattern. | 03-28-2013 |
| 20130082751 | CONTINUOUS SIGNAL GENERATOR - Disclosed herein is a continuous signal generator including: a synchronization circuit generating a synchronized clock signal; a signal source supplying a clock signal to the synchronization circuit; and a switch unit connected between the synchronization circuit and the signal source and selectively switched so as to allow the clock signal output from the signal source to be input to the synchronization circuit or feed back a clock signal output from the synchronization circuit to input the clock signal to the synchronization circuit. | 04-04-2013 |
| 20130093476 | CLOCK DISTRIBUTION CIRCUIT - A clock distribution circuit is provided with a clock generation circuit configured to generate a clock signal, a clock distribution network in which the clock signal is distributed, and a sequential circuit configured to operate on the clock signal distributed through a branch point of the clock distribution network. The clock distribution circuit is further provided with a clock generation circuit configured to input as a feedback signal the clock signal that has branched from the branch point and to output the clock signal to the clock distribution network based on the inputted feedback signal and a reference clock signal. The branch point is provided at a clock driver near the clock generation circuit, among preceding stage clock drivers of the sequential circuit of the clock distribution network. | 04-18-2013 |
| 20130120034 | Voltage Controlled Oscillator Calibration - A mobile communication device is provided that has a transceiver including a voltage controlled oscillator (VCO) and a calibration circuit for calibrating the VCO. The calibration circuit includes a logic block configured to estimate a calibration value for a tuning of the VCO to a desired frequency, and an asynchronous counter configured to execute a counting sequence to identify a frequency of the VCO after the tuning of the VCO using the calibration value, where the calibration circuit is configured to determine a tuned calibration value for producing the desired frequency from the counting sequence. | 05-16-2013 |
| 20130169326 | GATED VOLTAGE-CONTROLLED OSCILLATOR AND CLOCK AND DATA RECOVERY CIRCUIT - A gated voltage-controlled oscillator receives a gating signal and outputs an oscillating signal having a frequency corresponding to the gating signal. The gated voltage-controlled oscillator includes a delay unit, having a first terminal and a second terminal, and a multiplexer, having a first input terminal, a second input terminal, a select terminal and an output terminal. The first input terminal and the select terminal are coupled to the gating signal. The second input terminal is coupled to the first terminal of the delay unit. The output terminal outputs the oscillating signal and is coupled to the second terminal of the delay unit. The delay unit delays the oscillating signal and outputs the delayed oscillating signal into the second input terminal. The multiplexer outputs a signal of the first input terminal or the second input terminal according to the gating signal. | 07-04-2013 |
| 20130222022 | SYSTEM AND METHOD FOR OSCILLATOR FREQUENCY CONTROL - Techniques to compensate for sources of temperature and process dependent errors within an oscillator system for frequency control oscillator output clock signal. The oscillator system may include a controller and an oscillator circuit. The techniques may include generating a pair of voltages, a first of which is temperature variant, having (approximately) known temperature variations across process, and a second of which is (approximately) temperature invariant. Each voltage may be scaled by a corresponding trim factor. The scaled voltages may be combined to generate a reference voltage. The reference voltage may compensate for process and temperature dependent error sources within the oscillator system to set the oscillator output clock signal frequency. | 08-29-2013 |
| 20130249608 | CONTROL SIGNAL GENERATOR FOR USE WITH A COMMAND DECODER - A semiconductor device includes a control signal generator configured to generate a control signal that is enabled in a predetermined duration in response to an enabling of a chip selection signal, a clock controller configured to transfer a clock as a decoding clock in a duration for enabling of the control signal and disable the decoding clock in a duration for disabling of the control signal, and a command decoder configured to generate an internal command by decoding the chip selection signal and one or more command signals in synchronization with the decoding clock. | 09-26-2013 |
| 20130257493 | LATCH WITH A FEEDBACK CIRCUIT - An apparatus may include a storage circuit that may have a first terminal and a second terminal and may have two cross-coupled inverters. The apparatus may include a feedback circuit coupled to the first terminal The feedback circuit may include electronic logic elements to determine if the storage circuit is in a metastable state. The feedback circuit may couple at least one of the first and second terminals to one of a voltage reference and a voltage source if determined that the storage circuit is in a metastable state. | 10-03-2013 |
| 20130271190 | VERNIER PHASE TO DIGITAL CONVERTER FOR A ROTARY TRAVELING WAVE OSCILLATOR - A phase to digital conversion circuit with improved resolution for a rotary traveling wave oscillator. The phase to digital conversion circuit connects with a closed loop transmission line via a plurality of signal lines or nodes distributed along the transmission line. As an oscillating signal propagates around the transmission line, a time waveform of the signal at each of the plurality of signal lines is transmitted to a corresponding plurality of latches. Upon a triggering condition, the plurality of latches simultaneously samples the signals from the plurality of signal lines. At least two reference clock signals are switchably coupled with the plurality of latches latch for triggering the plurality of latches based on an edge transition in each of the reference clock signals compared with an edge transition in each of the signals from the plurality of taps. | 10-17-2013 |
| 20130314134 | APPARATUS AND METHOD FOR SYNCHRONISING SIGNALS - Signal synchronisers synchronise input signals with a clock signal. The input of each synchroniser is connected to a first input and the output of each synchroniser is connected to a second input of a respective first gate arrangement. The first gate arrangements provide an output signal only if there is an input signal on the first input and none on the second input or vice versa. The outputs of each of the first gate arrangements is connected to respective inputs of a second gate arrangement, which provides an output signal if there is a signal on any of its inputs. The output of the second gate arrangement is connected to a third gate arrangement which operates such that the clock signal to the synchronisers is only enabled when there is a change to the state of a signal received at the input of at least one of the synchronisers. | 11-28-2013 |
| 20130335125 | INPUT SIGNAL PROCESSING DEVICE - An input signal processing device includes an oscillator circuit, a signal processing circuit, and a control circuit. The oscillator circuit performs an oscillation operation to output a clock signal. The signal processing circuit operates based on the clock signal outputted from the oscillator circuit. The signal processing circuit performs a predetermined process to an input signal when a level of the input signal changes and outputs a signal after the predetermined process. The control circuit instructs the oscillator circuit to start the oscillation operation based on a level change of the input signal. The control circuit instructs the oscillator circuit to stop the oscillation operation when the signal processing circuit finishes the predetermined process. | 12-19-2013 |
| 20140043073 | CLOCK SYNCHRONIZATION CIRCUIT AND SEMICONDUCTOR DEVICE - A clock synchronization circuit is configured to capture an input data bit according to an input clock signal, and to synchronize and output the input data bit. The clock synchronization circuit includes a clock buffer for generating an internal clock signal according to the input clock signal and transmitting the internal clock signal to a clock line. The clock synchronization circuit further includes a D flip-flop for capturing and outputting the input data bit at an edge timing of the internal clock signal. The clock buffer includes an inverter core portion and an electric current suppressing portion. The inverter core portion is configured to generate the internal clock signal through alternately supplying an electric current to the clock line and drawing the electric current from the clock line according to the input clock signal. The electric current suppressing portion is configured to suppress an amount of the electric current. | 02-13-2014 |
| 20140062548 | WIDE-RANGE GLITCH-FREE ASYNCHRONOUS CLOCK SWITCH - Embodiments include systems and methods for asynchronous, glitch-free clock switching across a wide range of clock frequencies with minimal clock down time. Embodiments effectively provide two stages of synchronization across two independent clock domains. In a first synchronization stage, a received, asynchronous clock select signal is translated into a synchronized clock select signal that is effectively synchronous with respect to a first clock domain and is still effectively asynchronous with respect to a second clock domain. In a second synchronization stage, the synchronized clock select signal is resynchronized so as to be effectively synchronous with respect to the second clock domain. The synchronized select signal can be used to disable the clock of the first clock domain, and the resynchronized clock select signal can be used to enable the clock of the second clock domain. | 03-06-2014 |
| 20140152356 | FREQUENCY TRACING CIRCUIT AND METHOD THEREOF - A frequency tracking circuit is disclosed. The frequency tracking circuit includes an edge selector, a phase-frequency processor and a digital controlled oscillator. The edge selector receives a data signal and feedback clock signal and sequentially outputs a data edge signal and a feedback-clock-edge signal. The phase-frequency processor receives the data edge signal and the feedback-clock-edge signal and outputs a frequency adjusting digital signal after executing differential operation according to a first phase difference and a second phase difference. The digital controlled oscillator receives the frequency adjusting digital signal so as to adjust frequency of the feedback clock signal. The phase-frequency processor outputs a frequency tracking signal to the edge selector, wherein the edge selector utilizes the frequency tracking signal for acquiring the data edge signal and utilizes the data edge signal for acquiring the feedback-clock-edge signal. | 06-05-2014 |
| 20140152357 | METHODS AND CIRCUITS FOR REDUCING CLOCK JITTER - A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly. | 06-05-2014 |
| 20140159786 | RECEIVER CIRCUIT - A receiver circuit includes a data interpolator to interpolate an input data signal and generate an interpolation data signal, a data determination unit to determine a data determination result of the interpolation data signal, a clock recovery unit to detect phase information based on a data determination result and output an interpolation code determining an interpolation rate to the data interpolator based on the detected phase information, a first interpolator to interpolate the input data signal and generate an interpolation data signal for an eye pattern monitor, a first determination unit for the eye pattern monitor to compare the interpolation data signal with a reference voltage, a match determination unit to determine whether the data determination result of the data determination unit matches a comparison result of the first determination unit, and an eye pattern regenerator to generate an eye pattern based on the phase information and a determination result. | 06-12-2014 |
| 20140203851 | DIGITAL CLOCK PLACEMENT ENGINE APPARATUS AND METHOD WITH DUTY CYCLE CORRECTION AND QUADRATURE PLACEMENT - A digital clock placement engine has circuitry that adjusts a duty cycle of a clock signal and adjusts the locations of the rising/falling edges of the clock signal for purposes of data sampling or other operations. In a forwarded-clock interface implementation, a clock signal is received along with a data signal, and the received clock signal may be distorted to due various factors. To enable the received data signal to be sampled correctly, the clock placement engine generates a recovered clock signal having rising and falling edges that are placed/timed between the rising and falling edges of the received clock signal. | 07-24-2014 |
| 20140203852 | JITTER MONITOR - A jitter monitor includes: a voltage generating circuit configured to generate a first voltage that is varied with time at a predetermined inclination; a voltage reducing circuit configured to reduce the first voltage by a predetermined voltage in synchronization with a first clock signal so as to generate a second voltage that is varied with time at the predetermined inclination in synchronization with the first clock signal; and a sampling circuit configured to sample a portion having the predetermined inclination of the second voltage. | 07-24-2014 |
| 20140218081 | SEMICONDUCTOR DEVICE AND CLOCK DATA RECOVERY SYSTEM INCLUDING THE SAME - A semiconductor device includes a latch circuit. The latch circuit includes a sampling section that latches a differential input signal applied from a differential input node to the gates of a differential pair of transistors, a common adjusting section that adjusts a common potential of the differential input signal by adjusting based on a current control signal the amount of current that is drawn from the differential input node, and a common control section that controls the current control signal so that the differential pair of transistors operate in a saturated region, and supplies the controlled current control signal to the common adjusting section. | 08-07-2014 |
| 20140266338 | BIASED BANG-BANG PHASE DETECTOR FOR CLOCK AND DATA RECOVERY - An apparatus includes a plurality of phase detector circuits and a summing circuit. Each of the plurality of phase detector circuits may be configured to generate a phase up signal and a phase down signal in response to a respective pair of data samples and intervening transition sample. The summing circuit may be configured to generate an adjustment signal in response to the phase up and phase down signals of the plurality of phase detector circuits. A sum of the phase up signals and a sum of the phase down signals are weighted to provide a bias to a phase adjustment. | 09-18-2014 |
| 20150084677 | APPARATUSES AND METHODS FOR MITIGATING UNEVEN CIRCUIT DEGRADATION OF DELAY CIRCUITS - Apparatuses and methods for mitigating uneven circuit degradation of delay circuits are disclosed. In an example method, an imbalance in transistor threshold voltages is detected between a transistor of a first delay circuit and a transistor of a second delay circuit that is series coupled to the first delay circuit, and a clock level of an input clock signal to the first delay circuit is switched responsive to detecting the imbalance. | 03-26-2015 |
| 20150097603 | APPARATUS AND METHOD FOR OFFSET CANCELLATION IN DUTY CYCLE CORRECTIONS - An electronic device includes a clock configured to transmit a first clock signal and a second clock signal for operation of the electronic device; a duty cycle corrector coupled to the clock to correct a duty cycle of the first and second clock signals, the duty cycle corrector being configured to: assign and store a first duty cycle correction code in response to the first clock signal; assign and store a second duty cycle correction code in response to the second clock signal; calculate an offset code based on the first and second duty cycle correction codes; and negate the offset code from results of duty cycle correction operations. | 04-09-2015 |
| 20160036449 | SIGNAL GENERATOR AND CONTROLLING METHOD THEREOF - There is provided a signal generator including: a signal data transmitter selectively transmitting sample data obtained by sampling a reference signal at a predetermined frequency or a preset peak value, based on a variation section of the reference signal; and a signal outputter converting the sample data or the peak value transmitted from the signal data transmitter into an analog form and outputting an output signal having a target frequency. | 02-04-2016 |
| 20160099718 | FREQUENCY DETECTION CIRCUIT AND RECEPTION CIRCUIT - A frequency detection circuit includes: a first comparison circuit configured to output a first comparison result produced by comparison between a second threshold value higher than a first threshold value; a second comparison circuit configured to output a second comparison result produced by comparison between a third threshold value lower than the first threshold value; a third comparison circuit configured to output a third comparison result produced by comparison between the input data, and the first threshold value at second timing of a second clock; a phase detector configured to determine in which one of the areas an edge of the input data is positioned among the three areas produced by dividing a phase in a one-bit width time into three areas; and a phase rotation detector configured to detect a rotation direction of the phase based on a change of a detection result in the phase detector. | 04-07-2016 |
| 20160147252 | CLOCK CIRCUIT AND METHOD OF OPERATING THE SAME - A clock gating circuit includes a first transistor, a first inverter and a second transistor. A first terminal of the first transistor receives a clock input signal. A second terminal of the first transistor is coupled to a first node. The first transistor adjusts a voltage of the first node to a first voltage based on the clock input signal. The first inverter is coupled to the first node and receives the voltage of the first node, and outputs a clock output signal. A first terminal of the second transistor receives the clock input signal. A second terminal of the second transistor is coupled to the first node and a second node. The second transistor adjusts the voltage of the first node or the second node to the second voltage, based on the clock input signal. | 05-26-2016 |
