| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 327154000 | With feedforward | 7 |
| 20090295438 | Optimum Timing of Write and Read Clock Paths - An apparatus and method for timing calibration of write and read-back data exchanges between respective dies of an external memory/external device has a master arbiter or, alternatively, a test mux between a system bus master interface and an external memory controller for driving the external memory/external device, a calibration circuit under control of the master arbiter via a test bus master interface to provide stepped-through time delays for test data exchanges between the dies, and the calibration circuit obtains pass/fail data indicating pass or fail of the varied time delays for the test data exchanges. A processor system at the system bus master interface selects calibration values corresponding to pass data, and applies the calibration values to the respective dies for timing of write and read-back data exchanges between the dies. | 12-03-2009 |
| 20100194454 | Phase adjusting apparatus and camera - A phase adjusting apparatus includes a comparison code generating section, a calculating section, and a delay section. The comparison code generating section individually generates a first comparison code having a phase of a head code advanced and a second comparison code having the phase of the head code delayed, the head code being included in serial transfer data. The calculating section acquires a direction of adjustment of a phase of the serial transfer data using a comparison result of the head code and the first comparison code and a comparison result of the head code and the second comparison code. The delay section adjusts a delay amount of the serial transfer data based on the direction of adjustment of the phase. | 08-05-2010 |
| 20140084974 | PHASE LOCKED LOOP WITH BURN-IN MODE - A phase locked loop having a normal mode and a burn-in mode. The logic portion is coupled to a logic power supply terminal and includes a clock receiver coupled to a phase frequency detector. The analog portion has a charge pump coupled to the phase frequency detector and to an analog power supply terminal. The analog portion also has a voltage controlled oscillator coupled to the charge pump at an analog node and to the analog power supply terminal. The phase locked loop has a node control circuit that is coupled to the analog node during the burn-in mode that controls a voltage at the analog node sufficiently below a voltage at the analog power supply terminal to avoid over-stressing the charge pump and the voltage controlled oscillator during the burn-in mode. | 03-27-2014 |
| 20140312942 | PHASE-LOCKED LOOP OUTPUTS WITH REDUCED REFERENCE SPURS AND NOISE - In some examples, a circuit is described. The circuit may include a voltage-controlled oscillator that may be configured to generate an output signal. The circuit may also include a control signal generation unit that may be configured to generate a control signal based on the output signal. The control signal generation unit may also be configured to provide the control signal to the voltage-controlled oscillator. The voltage-controlled oscillator and the control signal generation unit may be part of a phase-locked loop (PLL) included in the circuit. The circuit may also include a feed-forward network. The feed-forward network may be configured to provide a portion of the control signal to the voltage-controlled oscillator. The voltage-controlled oscillator may generate the output signal based on the control signal from the control signal generation unit and the portion of the control signal from the feed-forward network. | 10-23-2014 |
| 20150097602 | PROGRAMMABLE SLEW RATE PHASE LOCKED LOOP - A system includes a first phase-locked loop (PLL) circuit, a slew rate limiter and a second PLL. The first PLL is configured to receive an input signal, generate a first output identifying a frequency associated with the input signal, and generate a second output identifying phase information associated with the input signal. The slew rate limiter is configured to receive the first output from the first PLL, determine whether the frequency of the first output is changing at greater than a predetermined rate, and generate a first signal indicating whether the frequency is changing at greater than the predetermined rate. The second PLL is configured to receive the first signal from the slew rate limiter, receive the second output from the first PLL, and generate an output signal identifying an angle or phase information based on the first signal and the second output. | 04-09-2015 |
| 20150145566 | HYBRID ANALOG AND DIGITAL CONTROL OF OSCILLATOR FREQUENCY - A hybrid analog/digital control approach for a digitally controlled oscillator augments a digital control path with an analog control path that acts to center the digital control path control signal within its range. The digital control path controls a first group of varactors within an oscillator tank circuit using a digital filter and a delta sigma modulator, which generates a dithered control signal for at least one of the first group of varactors. The analog control path controls a second group of varactors in the tank circuit but actively tunes only one varactor at a time. The analog control path performs relatively low bandwidth centering of the digital control signal resulting in negligible impact on PLL bandwidth, stability, and noise performance. Instead, the digital control path dominates in setting the PLL dynamic and noise behavior, and has reduced range requirements due to the centering action. | 05-28-2015 |
| 20160087639 | PHASE TRACKER FOR A PHASE LOCKED LOOP - A phase locked loop includes a feedforward path receiving a reference signal having a reference frequency and outputting an output signal having an output frequency that is a function of the reference signal and a feedback signal. The phase locked loop further includes a feedback path having a divider circuit associated therewith that is configured to receive the output signal and generate the feedback signal having a reduced frequency based on a divide value of the divider circuit. The feedback signal is supplied to the feedforward path. The phase locked loop also includes a modulator circuit configured to receive modulation data and provide a divider control signal to the divider circuit to control the divide value thereof, and a phase tracker circuit configured to determine an amount of phase drift from an initial phase value of the output signal due to an interruption in a locked state of the phase locked loop. | 03-24-2016 |
