| Entries |
| Document | Title | Date |
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| 20080290463 | LATERAL BIPOLAR TRANSISTOR AND METHOD OF PRODUCTION - Emitter and collector regions of the bipolar transistor are formed by doped regions of the same type of conductivity, which are separated by doped semiconductor material of an opposite type of conductivity, the separate doped regions being arranged at a surface of a semiconductor body and being in electric contact with electrically conductive material that is introduced into trenches at the surface of the semiconductor body. | 11-27-2008 |
| 20080290464 | NPN DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of forming a semiconductor device is disclosed. The method includes providing a floor for a semiconductor device by utilizing a CMOS process. The method further includes providing a BiCMOS-like process on top of the floor to further fabricate the semiconductor device, wherein the BiCMOS-like process and the CMOS process provides the semiconductor device. | 11-27-2008 |
| 20080308903 | POLYCRYSTALLINE THIN FILM BIPOLAR TRANSISTORS - A semiconductor device comprising a bipolar transistor having a base region, an emitter region and a collector region, wherein the base region comprises polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide is described. The emitter region and collector region also may comprise polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide forming metal. The polycrystalline semiconductor material is preferably silicided polysilicon, which is formed in contact with C49 phase titanium silicide. | 12-18-2008 |
| 20090020851 | BICMOS DEVICES WITH A SELF-ALIGNED EMITTER AND METHODS OF FABRICATING SUCH BICMOS DEVICES - A method of fabricating an heterojunction bipolar transistor (HBT) structure in a bipolar complementary metal-oxide-semiconductor (BiCMOS) process selectively thickens an oxide layer overlying a base region in areas that are not covered by a temporary emitter and spacers such that the temporary emitter can be removed and the base-emitter junction can be exposed without also completely removing the oxide overlying the areas of the base region that are not covered by the temporary emitter or spacers. As a result, a photomask is not required to remove the temporary emitter and to expose the base-emitter junction. | 01-22-2009 |
| 20090085162 | SEMICONDUCTOR DEVICE AND INTEGRATED SEMICONDUCTOR CIRCUIT DEVICE - The present invention provides a semiconductor device that includes a plurality of transistor cells and makes it possible to achieve higher degree of integration and lower cost of an integrated semiconductor circuit device as the first object, and provide an integrated semiconductor circuit device of high density integration and compact construction at a low cost. | 04-02-2009 |
| 20090127659 | Bipolar junction transistor with a low collector resistance and method of forming the bipolar junction transistor in a CMOS process flow - The collector resistance of a bipolar junction transistor that is formed in a CMOS process is substantially reduced by forming a heavily-doped collector extension region that extends from a heavily-doped collector contact region down to a deep well of the same conductivity type to a point that lies close to the base of the transistor. | 05-21-2009 |
| 20090160025 | LATERAL BIPOLAR TRANSISTOR - A P+ base drawing diffusion region is formed on a substrate having an SOI structure. N+ emitter diffusion regions are formed on both sides of the P+ base drawing diffusion region through isolation insulating films interposed therebetween. A P type SOI layer, which serves as a base diffusion region, is formed so as to surround the N+ emitter diffusion regions, and conductive layers are formed thereon. Further, an N+ collector diffusion region is formed so as to surround the conductive layers. | 06-25-2009 |
| 20090174034 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SUCH A DEVICE - The invention relates to a semiconductor device ( | 07-09-2009 |
| 20090200641 | Semiconductor device and method of manufacturing the same - The invention relates to a semiconductor device ( | 08-13-2009 |
| 20090212393 | METHOD OF MANUFACTURING AN ELECTRONIC DEVICE INCLUDING A PNP BIPOLAR TRANSISTOR - A method of manufacturing an electronic device including a PNP bipolar transistor comprises forming a collector in a substrate, depositing a base layer and an emitter layer on the substrate, and growing a nitride interface layer on the base layer as a base current modulation means, such that the nitride interface layer is arranged between the base layer and the emitter layer. | 08-27-2009 |
| 20090243042 | LATERAL SEMICONDUCTOR DEVICE - A semiconductor device has a first main electrode and a second main electrode that are provided on a semiconductor layer. The semiconductor layer has: an n type first semiconductor region in contact with the first main electrode; a p type second semiconductor region in contact with the second main electrode; and an n type third semiconductor region provided between the first and second semiconductor regions. The third semiconductor region has a first layer and a second layer. The impurity concentration in the first layer is uniform. The second layer has a higher impurity concentration than the first layer that increases in a gradient from the first semiconductor region to the second semiconductor region. | 10-01-2009 |
| 20090250789 | METHODS OF COUNTER-DOPING COLLECTOR REGIONS IN BIPOLAR TRANSISTORS - The present invention provides a method of forming a bipolar transistor. The method includes doping a silicon layer with a first type of dopant and performing a first implant process to implant dopant of a second type opposite the first type in the silicon layer. The implanted dopant has a first dopant profile in the silicon layer. The method also includes performing a second implant process to implant additional dopant of the second type in the silicon layer. The additional implanted dopant has a second dopant profile in the silicon layer different than the first dopant profile. The method further includes growing an insulating layer formed over the silicon layer by consuming a portion of the silicon layer and the first type of dopant. | 10-08-2009 |
| 20090315145 | ADJUSTABLE BIPOLAR TRANSISTORS FORMED USING A CMOS PROCESS - By providing a novel bipolar device design implementation, a standard CMOS process ( | 12-24-2009 |
| 20100019350 | Resonant operating mode for a transistor - The PN junctions of a transistor are biased for operation in the active mode but an initial flow of current reverses the bias of the base-emitter junction causing the transistor to conduct a resonant current with a voltage less than the forward junction voltage of said base-emitter. | 01-28-2010 |
| 20100148308 | Dopant Profile Control for Ultrashallow Arsenic Dopant Profiles - A method of manufacturing a semiconductor device comprises growing or depositing an implantation oxide layer, implanting a dopant, activating the dopant, and removing the implantation oxide layer after the step of activating the dopant. | 06-17-2010 |
| 20100155894 | Fabricating Bipolar Junction Select Transistors For Semiconductor Memories - A bipolar junction transistor may act as a select device for a semiconductor memory. The bipolar junction transistor may be formed of a stack of base and collector layers. Sets of parallel trenches are formed in a first direction down to the base and in a second direction down to the collector. The trenches may be used to form local enhancement implants into the exposed portion of the base and collector in each trench. As a result of the local enhancement implants, in some embodiments, leakage current may be reduced, active current capability may be higher, gain may be higher, base resistance may be reduced, breakdown voltage may be increased, and parasitic effects with adjacent junctions may be reduced. | 06-24-2010 |
| 20100295157 | ESD PROTECTION DEVICE - An ESD protection device is described, which includes a first P-type doped region, a second P-type doped region, a first N-type doped region, a second N-type doped region and an isolation structure. The first P-type doped region is configured in a substrate. The second P-type doped region is configured in the first P-type doped region. The first N-type doped region is configured in the first P-type doped region and surrounds the second P-type doped region. The second N-type doped region is configured in the substrate and surrounds the first P-type doped region. The isolation structure is disposed between the first P-type doped region and the second N-type doped region, wherein a spacing is deployed between an outward edge of the first N-type doped region and the isolation structure. | 11-25-2010 |
| 20100320571 | BIPOLAR TRANSISTOR STRUCTURE AND METHOD INCLUDING EMITTER-BASE INTERFACE IMPURITY - A bipolar transistor structure and a method for fabricating the bipolar transistor structure include: (1) a collector structure located at least in-part within a semiconductor substrate; (2) a base structure contacting the collector structure; and (3) an emitter structure contacting the base structure. The interface of the emitter structure and the base structure includes an oxygen impurity and at least one impurity selected from the group consisting of a fluorine impurity and a carbon impurity, to enhance performance of a bipolar transistor within the bipolar transistor structure. The impurities may be introduced into the interface by plasma etch treatment, or alternatively a thermal treatment followed by an anhydrous ammonia and hydrogen fluoride treatment, of a base material from which is comprised the base structure. | 12-23-2010 |
| 20110089535 | Electrostatic Discharge Protection Device - The invention provides an electrostatic discharge (ESD) protection device having an ESD path between a first circuit and a second circuit. The electrostatic discharge protection device includes a first doped region having a first conductive type. A first well has a second conductive type opposite to the first conductive type. A second doped region and a third doped region are in the first well, respectively having the first and second conductive types. The first doped region is coupled to a power supply terminal or a ground terminal of the first circuit, and the second and third doped regions are both coupled to a power supply terminal or a ground terminal of the second circuit, respectively. | 04-21-2011 |
| 20110095398 | BIPOLAR SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SAME - A bipolar semiconductor device includes a collector region that is an n-type low-resistance layer formed in one surface of a semiconductor crystal substrate, an n-type first high-resistance region on the collector region, a p-type base region on the first high-resistance region, an n-type low-resistance emitter region that is formed in another surface of the semiconductor crystal substrate, an n-type second high-resistance region between the emitter region and the base region so as to contact the emitter region, an n-type recombination suppressing region around the second high-resistance region so as to adjoin the second high-resistance region, and a p-type low-resistance base contact region which is provided so as to adjoin the recombination suppressing region, and which contacts the base region. Each of doping concentrations of the second high-resistance region and the recombination suppressing region is equal to or lower than 1×10 | 04-28-2011 |
| 20110140239 | High Voltage Bipolar Transistor with Pseudo Buried Layers - A high voltage bipolar transistor with shallow trench isolation (STI) comprises the areas of a collector formed by implanting first electric type impurities into active area and connected with pseudo buried layers at two sides; Pseudo buried layers which are formed by implanting high dose first type impurity through the bottoms of STI at two sides if active area, and do not touch directly; deep contact through field oxide to contact pseudo buried layers and pick up the collectors; a base deposited on the collector by epitaxial growth and in-situ doped by second electric type impurity, in which the intrinsic base touches local collector and extrinsic base is used for base pick-up; a emitter which is a polysilicon layer deposited on the intrinsic base and doped with first electric type impurities. This invention makes the depletion region of collector/base junction from 1D (vertical) distribution to 2D (vertical and lateral) distribution. The bipolar transistor's breakdown voltages are increased by only enlarge active critical dimension (CD). This is low-cost process. | 06-16-2011 |
| 20110147892 | Bipolar Transistor with Pseudo Buried Layers - A structure and fabrication method for a bipolar transistor with shallow trench isolation (STI) comprises a collector formed by implanting first electric type impurity in active area; pseudo buried layers at the bottom of STI at both sides of active area by implanting heavy dose of first electric type impurity; deep contacts through field oxide to connect to pseudo buried layers and to pick up the collector; a base, a thin film deposited on the collector and doped with second electric type impurity; an emitter, a polysilicon film doped by heavy dose implant of first electric type impurity. This transistor has smaller device area, less parasitic effect, less photo layers and lower process cost. | 06-23-2011 |
| 20110156210 | SEMICONDUCTOR DEVICE - A semiconductor device according to embodiments of the invention includes an n | 06-30-2011 |
| 20110186965 | REVERSE-CONDUCTING INSULATED GATE BIPOLAR TRANSISTOR - Reverse-conducting insulated gate bipolar transistor in which IGBT region and FWD region are integrated into a single body in a semiconductor substrate with a common active region is disclosed. MOS gate structure is on a first major surface side. Rear surface side structure is in a second major surface side of the semiconductor substrate and includes a plurality of recessed parts vertical to the second major surface, which are repeated periodically along the second major surface. A plurality of protruding parts are interposed between the recessed parts. Rear surface side structure includes p type collector region on a bottom surface of the recessed part, n type first field stop region at a position deeper than the collector region, n type cathode region on the top surface of the protruding part, and n type second field stop region in the protruding part at a position deeper than the cathode region. | 08-04-2011 |
| 20110198727 | ESD PROTECTION DEVICE - An ESD protection device is described, which includes a P-body region, a P-type doped region, an N-type doped region and an N-sinker region. The P-body region is configured in a substrate. The P-type doped region is configured in the middle of the P-body region. The N-type doped region is configured in the P-body region and surrounds the P-type doped region. The N-sinker region is configured in the substrate and surrounds the P-body region. | 08-18-2011 |
| 20110233727 | VERTICAL SOI BIPOLAR JUNCTION TRANSISTOR AND MANUFACTURING METHOD THEREOF - The present invention discloses a vertical SOI bipolar junction transistor and a manufacturing method thereof. The bipolar junction transistor includes an SOI substrate from down to up including a body region, a buried oxide layer and a top silicon film; an active region located in the top silicon film formed by STI process; a collector region located in the active region deep close to the buried oxide layer formed by ion implantation; a base region located in the active region deep close to the top silicon film formed by ion implantation; an emitter and a base electrode both located over the base region; a side-wall spacer located around the emitter and the base electrode. The present invention utilizing a simple double poly silicon technology not only can improve the performance of the transistor, but also can reduce the area of the active region in order to increase the integration density. Furthermore, the present invention utilizes side-wall spacer process to improve the compatibility of SOI BJT and SOI CMOS, which simplifies the SOI BiCMOS process and thus reduce the cost. | 09-29-2011 |
| 20110260292 | Bipolar Junction Transistor Having a Carrier Trapping Layer - A bipolar junction transistor having a carrier trapping layer, comprises a semi-conductor substrate including a well with a first type ions formed thereon; two impurity regions with a second type ions formed opposite with each other over the well; an insulation layer over the well, and edges extend over the second two impurity regions; and a carrier trapping layer formed over the insulation layer. | 10-27-2011 |
| 20110304019 | METHOD OF MANUFACTURING A BIPOLAR TRANSISTOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICES OBTAINED THEREBY - Methods for manufacturing a bipolar transistor semiconductor device are described, along with devices fabricated in accordance with the methods. The methods include the steps of forming a stack of layers over a semiconductor body comprising a window definition layer ( | 12-15-2011 |
| 20120018845 | Polysilicon Plug Bipolar Transistor For Phase Change Memory - Memory devices and methods for manufacturing are described herein. A memory device described herein includes a plurality of memory cells. Memory cells in the plurality of memory cells comprise respective bipolar junction transistors and memory elements. The bipolar junction transistors are arranged in a common collector configuration and include an emitter comprising doped polysilicon having a first conductivity type, the emitter contacting a corresponding word line in a plurality of word lines to define a pn junction. The bipolar junction transistors include a portion of the corresponding word line underlying the emitter acting as a base, and a collector comprising a portion of the single-crystalline substrate underlying the base. | 01-26-2012 |
| 20120056305 | SPACER STRUCTURE FOR TRANSISTOR DEVICE AND METHOD OF MANUFACTURING SAME - The present disclosure provides a bipolar junction transistor (BJT) device and methods for manufacturing the BJT device. In an embodiment, the BJT device includes: a semiconductor substrate having a collector region, and a material layer disposed over the semiconductor layer. The material layer has a trench therein that exposes a portion of the collector region. A base structure, spacers, and emitter structure are disposed within the trench of the material layer. Each spacer has a top width and a bottom width, the top width being substantially equal to the bottom width. | 03-08-2012 |
| 20120068309 | Transistor and Method of Manufacturing a Transistor - In accordance with an embodiment of the present invention a transistor is disclosed. The transistor comprises a collector, a base and an emitter, wherein a first end width of the base is larger than a middle width of the base, wherein a first end width of the collector is larger than a middle width of the collector, or wherein a first end width of the emitter is larger than a middle width of the emitter. | 03-22-2012 |
| 20120098095 | BIPOLAR TRANSISTOR WITH IMPROVED STABILITY - Instability and drift sometimes observed in bipolar transistors, having a portion of the base extending to the transistor surface between the emitter and base contact, can be reduced or eliminated by providing a further doped region of the same conductivity type as the emitter at the transistor surface between the emitter and the base contact. The further region is desirably more heavily doped than the base region at the surface and less heavily doped than the adjacent emitter. In another embodiment, a still or yet further region of the same conductivity type as the emitter is provided either between the further region and the emitter or laterally within the emitter. The still or yet further region is desirably more heavily doped than the further region. Such further regions shield the near surface base region from trapped charge that may be present in dielectric layers or interfaces overlying the transistor surface. | 04-26-2012 |
| 20120098096 | BIPOLAR TRANSISTOR - A bipolar transistor comprises at least first and second connected emitter-base (EB) junctions having, respectively, different first and second EB junction depths, and a buried layer (BL) collector having a greater third depth. The emitters and bases corresponding to the different EB junctions are provided during a chain implant. An isolation region overlies the second EB junction location thereby providing its shallower EB junction depth. The BL collector does not underlie the first EB junction and is laterally spaced therefrom by a variable amount to facilitate adjusting the transistor's properties. In other embodiments, the BL collector can underlie at least a portion of the second EB junction. Regions of opposite conductivity type over-lie and under-lie the BL collector, which is relatively lightly doped, thereby preserving the breakdown voltage. The transistor can be readily “tuned” by mask adjustments alone to meet various device requirements. | 04-26-2012 |
| 20120104553 | Semiconductor device - A semiconductor device in which only the trigger voltage can be controlled without change in the hold voltage. In the semiconductor device, a protection device includes a lower doped collector layer, a sinker layer, a highly-doped collector layer, an emitter layer, a highly-doped base layer, a base layer, a first conductivity type layer, and a second conductivity type layer. The second conductivity type layer is formed in the lower doped collector layer and located between the base layer and first conductivity type layer. The second conductivity type layer has a higher impurity concentration than the lower doped collector layer. | 05-03-2012 |
| 20120112318 | TRANSISTOR AND PROCESS OF PRODUCING THE SAME, LIGHT-EMITTING DEVICE, AND DISPLAY - A transistor capable of modulating, at low voltages, a large current flowing between an emitter electrode and a collector electrode. A process of producing the transistor, a light-emitting device comprising the transistor, and a display comprising the transistor. The transistor comprises an emitter electrode and a collector electrode. Between the emitter electrode and the collector electrode are situated a semiconductor layer and a sheet base electrode. It is preferred that the semiconductor layer be situated between the emitter electrode and the base electrode and also between the collector electrode and the base electrode to constitute a second semiconductor layer and a first semiconductor layer, respectively. It is also preferred that the thickness of the base electrode be 80 nm or less. Furthermore, a dark current suppressor layer is situated at least between the emitter electrode and the base electrode, or between the collector electrode and the base electrode. | 05-10-2012 |
| 20120168907 | FLAT RESPONSE DEVICE STRUCTURES FOR BIPOLAR JUNCTION TRANSISTORS - Bipolar transistors with tailored response curves, as well as fabrication methods for bipolar transistors and design structures for BiCMOS integrated circuits. The bipolar transistor includes a first section of a collector region implanted with a first dopant concentration and a second section of the collector region implanted with a second dopant concentration that is higher than the first dopant concentration. A first emitter is formed in vertical alignment with the first section of the collector region. A second emitter is formed in vertical alignment with the second section of the collector region. | 07-05-2012 |
| 20120168908 | SPACER FORMATION IN THE FABRICATION OF PLANAR BIPOLAR TRANSISTORS - A bipolar transistor is fabricated having a collector ( | 07-05-2012 |
| 20120168909 | RADIATION HARDENED BIPOLAR INJUNCTION TRANSISTOR - A method for integrating a bipolar injunction transistor in a semiconductor chip includes the steps of forming an intrinsic base region of a second type of conductivity extending in the collector region from a main surface through an intrinsic base window of the sacrificial insulating layer, forming an emitter region of the first type of conductivity extending in the intrinsic base region from the main surface through an emitter window of the sacrificial insulating layer, removing the sacrificial insulating layer, forming an intermediate insulating layer on the main surface, and forming an extrinsic base region of the second type of conductivity extending in the intrinsic base region from the main surface through an extrinsic base window of the intermediate insulating layer | 07-05-2012 |
| 20120235280 | INTEGRATED CIRCUIT INCLUDING A BIPOLAR TRANSISTOR AND METHODS OF MAKING THE SAME - An integrated circuit includes a bipolar transistor disposed over a substrate. The bipolar transistor includes a base electrode disposed around at least one germanium-containing layer. An emitter electrode is disposed over the at least one germanium-containing layer. At least one isolation structure is disposed between the emitter electrode and the at least one germanium-containing layer. A top surface of the at least one isolation structure is disposed between and electrically isolating a top surface of the emitter electrode from a top surface of the at least one germanium-containing layer. | 09-20-2012 |
| 20120248573 | TUNABLE SEMICONDUCTOR DEVICE - Embodiments of the invention include a method for forming a tunable semiconductor device and the resulting structure. The invention comprises forming a semiconductor substrate. Next, pattern a first mask over the semiconductor substrate. Dope regions of the semiconductor substrate not protected by the first mask to form a first discontinuous subcollector. Remove the first mask. Pattern a second mask over the semiconductor substrate. Dope regions of the semiconductor substrate not protected by the second mask and on top of the first discontinuous subcollector to form a second discontinuous subcollector. Remove the second mask and form a collector above the second discontinuous subcollector. Breakdown voltage of the device may be tuned by varying the gaps separating doped regions within the first and second discontinuous subcollectors. Doped regions of the first and second discontinuous subcollectors may be formed in a mesh pattern. | 10-04-2012 |
| 20130009280 | BIPOLAR JUNCTION TRANSISTORS WITH A LINK REGION CONNECTING THE INTRINSIC AND EXTRINSIC BASES - Methods for fabricating bipolar junction transistors, bipolar junction transistors made by the methods, and design structures for a bipolar junction transistor. The bipolar junction transistor includes a dielectric layer on an intrinsic base and an extrinsic base at least partially separated from the intrinsic base by the dielectric layer. An emitter opening extends through the extrinsic base and the dielectric layer. The dielectric layer is recessed laterally relative to the emitter opening to define a cavity between the intrinsic base and the extrinsic base. The cavity is filled with a semiconductor layer that physically links the extrinsic base and the intrinsic base together. | 01-10-2013 |
| 20130093057 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first conductive type semiconductor layer formed on a substrate; a first conductive type embedded layer formed between the substrate and the semiconductor layer; a second conductive type well formed on the semiconductor layer; a first conductive type first contact layer that is positioned on the semiconductor layer, separate from the well; a second conductive type second contact layer formed on the well; a first conductive type third contact layer formed on the well between the first and second contact layers; and a first conductive type deep layer formed between the embedded layer and the first contact layer and in contact with the first contact layer. A minimum point in the effective impurity concentration profile along a straight line that extends in a vertical direction and passes through the embedded layer and the second part exists between the embedded layer and the first part. | 04-18-2013 |
| 20130119516 | PNP BIPOLAR JUNCTION TRANSISTOR FABRICATION USING SELECTIVE EPITAXY - Lateral PNP bipolar junction transistors, methods for fabricating lateral PNP bipolar junction transistors, and design structures for a lateral PNP bipolar junction transistor. An emitter and a collector of the lateral PNP bipolar junction transistor are comprised of p-type semiconductor material that is formed by a selective epitaxial growth process. The source and drain each directly contact a top surface of a device region used to form the emitter and collector. A base contact may be formed on the top surface and overlies an n-type base defined within the device region. The emitter is laterally separated from the collector by the base contact. Another base contact may be formed in the device region that is separated from the other base contact by the base. | 05-16-2013 |
| 20130168819 | Fin-like BJT - A bipolar junction transistor (BJT) formed using a fin field-effect transistor (FinFET) complimentary metal-oxide-semiconductor (CMOS) process flow is provided. The BJT includes an emitter fin, a base fin, and a collector fin formed on a substrate. The base fin encloses the emitter fin and collector fin encloses the emitter fin. In some embodiments, the emitter fin, base fin, and collector fin have a square shape when viewed from above and are concentric with each other. | 07-04-2013 |
| 20130168820 | POWER SIGE HETEROJUNCTION BIPOLAR TRANSISTOR (HBT) WITH IMPROVED DRIVE CURRENT BY STRAIN COMPENSATION - A power SiGe heterojunction bipolor transistor (HBT) with improved drive current by strain compensation and methods of manufacture are provided. A method includes adding carbon in a continuous steady concentration in layers of a device including a subcollector layer, a collector layer, a base buffer layer, a base layer, and an emitter buffer layer. | 07-04-2013 |
| 20130187256 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes an n-type first guard ring layer provided between an emitter layer and a collector layer on a surface side of a base layer, and having a higher n-type impurity concentration than the base layer, and an n-type second guard ring layer provided between the first guard ring layer and a buried layer, connected to the first guard ring layer and the buried layer, and having a higher n-type impurity concentration than the base layer. The first guard ring layer has an n-type impurity concentration profile decreasing toward the second guard ring layer side, and the second guard ring layer has an impurity concentration profile decreasing toward the first guard ring layer side. | 07-25-2013 |
| 20130207235 | SELF-ALIGNED EMITTER-BASE REGION - Aspects of the invention provide a method of forming a bipolar junction transistor. The method includes: providing a semiconductor substrate including a uniform silicon nitride layer over an emitter pedestal, and a base layer below the emitter pedestal; applying a photomask at a first end and a second end of a base region; and performing a silicon nitride etch with the photomask to simultaneously form silicon nitride spacers adjacent to the emitter pedestal and exposing the base region of the bipolar junction transistor. The silicon nitride etch may be an end-pointed etch. | 08-15-2013 |
| 20130207236 | HIGH-BETA BIPOLAR JUNCTION TRANSISTOR AND METHOD OF MANUFACTURE - An NPN bipolar junction transistor is disclosed that exhibits a collector-to-emitter breakdown voltage greater than 10 volts and a beta greater than 300. The large value of beta is obtained by fabricating the transistor with an extra IN-type layer that reduces recombination of electrons and holes. | 08-15-2013 |
| 20130249057 | SIGE HETEROJUNCTION BIPOLAR TRANSISTOR WITH AN IMPROVED BREAKDOWN VOLTAGE-CUTOFF FREQUENCY PRODUCT - The product of the breakdown voltage (BV | 09-26-2013 |
| 20130320498 | LOW VOLTAGE PROTECTION DEVICES FOR PRECISION TRANSCEIVERS AND METHODS OF FORMING THE SAME - A bi-directional protection device includes a bi-directional NPN bipolar transistor including an emitter/collector formed from a first n-well region, a base formed from a p-well region, and a collector/emitter formed from a second n-well region. P-type active regions are formed in the first and second n-well regions to form a PNPNP structure, which is isolated from the substrate using dual-tub isolation consisting of an n-type tub and a p-type tub. The dual-tub isolation prevents induced latch-up during integrated circuit powered stress conditions by preventing the wells associated with the PNPNP structure from injecting carriers into the substrate. The size, spacing, and doping concentrations of active regions and wells associated with the PNPNP structure are selected to provide fine-tuned control of the trigger and holding voltage characteristics to enable the bi-directional protection device to be implemented in high voltage applications using low voltage precision interface signaling. | 12-05-2013 |
| 20130334664 | INTERFACE CONTROL IN A BIPOLAR JUNCTION TRANSISTOR - Methods of fabricating bipolar junction transistors, bipolar junction transistors, and design structures for a bipolar junction transistor. A first portion of the intrinsic base layer is masked while a second portion of an intrinsic base layer is etched. As a consequence of the masking, the second portion of the intrinsic base layer is thinner than the first portion of the intrinsic base layer. An emitter and an extrinsic base layer are formed in respective contacting relationships with the first and second portions of the intrinsic base layer. | 12-19-2013 |
| 20140021587 | LOCAL WIRING FOR A BIPOLAR JUNCTION TRANSISTOR INCLUDING A SELF-ALIGNED EMITTER REGION - Aspects of the invention provide for a bipolar transistor of a self-aligned emitter. In one embodiment, the invention provides a method of forming local wiring for a bipolar transistor with a self-aligned sacrificial emitter, including: performing an etch to remove the sacrificial emitter to form an emitter opening between two nitride spacers; depositing an in-situ doped emitter into the emitter opening; performing a recess etch to partially remove a portion of the in-situ doped emitter; depositing a silicon dioxide layer over the recessed in-situ doped emitter; planarizing the silicon dioxide layer via chemical mechanical polishing; etching an emitter trench over the recessed in-situ doped emitter; and depositing tungsten and forming a tungsten wiring within the emitter trench via chemical mechanical polishing. | 01-23-2014 |
| 20140054747 | BIPOLAR TRANSISTOR - A bipolar transistor having an upper surface, comprises a multilevel collector structure formed in a base region of opposite conductivity type and having a first part of a first vertical extent coupled to a collector contact, an adjacent second part having a second vertical extent a third part of a third vertical extent and desirably of a depth different from a depth of the second part, coupled to the second part by a fourth part desirably having a fourth vertical extent less than the third vertical extent. A first base region portion overlies the second part, a second base region portion separates the third part from an overlying base contact region, and other base region portions laterally surround and underlie the multilevel collector structure. An emitter proximate the upper surface is laterally spaced from the multilevel collector structure. This combination provides improved gain, Early Voltage and breakdown voltages. | 02-27-2014 |
| 20140061858 | Semiconductor Device with Diagonal Conduction Path - A method of fabricating a bipolar transistor including emitter and base regions having first and second conductivity types, respectively, includes forming an isolation region at a surface of a semiconductor substrate, the isolation region having an edge that defines a boundary of an active area of the emitter region, and implanting dopant of the second conductivity type through a mask opening to form the base region in the semiconductor substrate. The mask opening spans the edge of the isolation region such that an extent to which the dopant passes through the isolation region varies laterally to establish a variable depth contour of the base region. | 03-06-2014 |
| 20140084420 | METHOD TO BRIDGE EXTRINSIC AND INTRINSIC BASE BY SELECTIVE EPITAXY IN BICMOS TECHNOLOGY - A method of forming a heterojunction bipolar transistor. The method includes providing a structure comprising at least an intrinsic base region and an emitter pedestal region. A stack is formed on the intrinsic base region. The stack comprises a polysilicon layer and a top sacrificial oxide layer. A trench is formed in the structure. The trench circumscribes the intrinsic base region and the stack. An extrinsic base is formed at two regions around the stack. The extrinsic base is formed by a selective epitaxial growth process to create a bridge over the trench. The bridge connects the two regions. An opening is provided in the stack. The opening exposes a portion of the intrinsic base region. An emitter is formed in the opening. | 03-27-2014 |
| 20140110825 | Compound Semiconductor Lateral PNP Bipolar Transistors - Compound semiconductor lateral PNP bipolar transistors are fabricated based on processes traditionally used for formation of compound semiconductor NPN heterojunction bipolar transistors and hence such PNP bipolar transistors can be fabricated inexpensively using existing fabrication technologies. In particular, GaAs-based lateral PNP bipolar transistors are fabricated using GaAs-based NPN heterojunction bipolar transistor fabrication processes. | 04-24-2014 |
| 20140131837 | GAN VERTICAL BIPOLAR TRANSISTOR - An embodiment of a semiconductor device includes a III-nitride base structure of a first conductivity type, and a III-nitride emitter structure of a second conductivity type having a first surface and a second surface. The second surface is substantially opposite the first surface. The first surface of the III-nitride emitter structure is coupled to a surface of the III-nitride base structure. The semiconductor also includes a first dielectric layer coupled to the second surface of the III-nitride emitter structure, and a spacer coupled to a sidewall of the III-nitride emitter structure and the surface of the III-nitride base structure. The semiconductor also includes a base contact structure with a III-nitride material coupled to the spacer, the surface of the III-nitride base structure, and the first dielectric layer, such that the first dielectric layer and the spacer are disposed between the base contact structure and the III-nitride emitter structure. | 05-15-2014 |
| 20140151852 | BIPOLAR JUNCTION TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE - Fabrication methods, device structures, and design structures for a bipolar junction transistor. The device structure includes a collector region, an intrinsic base formed on the collector region, an emitter coupled with the intrinsic base and separated from the collector by the intrinsic base, and an isolation region extending through the intrinsic base to the collector region. The isolation region is formed with a first section having first sidewalls that extend through the intrinsic base and a second section with second sidewalls that extend into the collector region. The second sidewalls are inclined relative to the first sidewalls. The isolation region is positioned in a trench that is formed with first and second etching process in which the latter etches different crystallographic directions of a single-crystal semiconductor material at different etch rates. | 06-05-2014 |
| 20140159206 | Methods and Apparatus for ESD Structures - Methods and apparatus for ESD structures. A semiconductor device includes a first active area containing an ESD cell coupled to a first terminal and disposed in a well; a second active area in the semiconductor substrate, the second active area comprising a first diffusion of the first conductivity type for making a bulk contact to the well; and a third active area in the semiconductor substrate, separated from the first and second active areas by another isolation region, a portion of the third active area comprising an implant diffusion of the first conductivity type within a first diffusion of the second conductivity type and adjacent a boundary with the well of the first conductivity type; wherein the third active area comprises a diode coupled to the terminal and reverse biased with respect to the well of the first conductivity type. | 06-12-2014 |
| 20140159207 | ESD Protection Structure, Integrated Circuit and Semiconductor Device - Implementations are presented herein that include an ESD protection structure. The structure may include a plurality of first doped regions forming first terminals of a plurality of transistors, a plurality of second doped regions forming second terminals of the plurality of transistors, and a third doped region surrounding the plurality of first doped regions and the plurality of second doped regions to form a common third terminal of the plurality of transistors. The plurality of first doped regions and the plurality of second doped regions may be arranged in an alternating pattern such that an ESD discharge current received on any one of the plurality of first doped regions dissipates through at least two of the plurality of second doped regions. | 06-12-2014 |
| 20140210051 | METHOD FOR IMPLEMENTING DEEP TRENCH ENABLED HIGH CURRENT CAPABLE BIPOLAR TRANSISTOR FOR CURRENT SWITCHING AND OUTPUT DRIVER APPLICATIONS - A method and structures are provided for implementing deep trench enabled high current capable bipolar transistor for current switching and output driver applications. A deep oxygen implant is provided in a selected region of substrate. A first deep trench and second deep trench are formed above the deep oxygen implant. The first deep trench is a generally large rectangular box deep trench of minimum width and the second deep trench is a second small area deep trench centered within the first rectangular box deep trench. Ion implantation at relatively high ion pressure and annealing is utilized to form highly doped N+ regions or P+ regions both inside and outside the outside the first deep trench and around the outside the second deep trench region. These regions provide the collector and emitter respectively, and the existing substrate region provides the base region between the collector and emitter regions. | 07-31-2014 |
| 20140217551 | TRENCH ISOLATION FOR BIPOLAR JUNCTION TRANSISTORS IN BICMOS TECHNOLOGY - Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first isolation structure is formed in a substrate to define a boundary for a device region. A collector is formed in the device region, and a second isolation structure is formed in the device region. The second isolation structure defines a boundary for the collector. The second isolation structure is laterally positioned relative to the first isolation structure to define a section of the device region between the first and second isolation structures. | 08-07-2014 |
| 20140231961 | SEMICONDUCTOR DEVICE AND RELATED FABRICATION METHODS - Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a collector region of semiconductor material having a first conductivity type, a base region of semiconductor material within the collector region, the base region having a second conductivity type opposite the first conductivity type, and a doped region of semiconductor material having the second conductivity type, wherein the doped region is electrically connected to the base region and the collector region resides between the base region and the doped region. In exemplary embodiments, the dopant concentration of the doped region is greater than a dopant concentration of the collector region to deplete the collector region as the electrical potential of the base region exceeds that of the collector region. | 08-21-2014 |
| 20140231962 | BIPOLAR JUNCTION TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A bipolar junction transistor (BJT) is provided. The BJT can include a semiconductor substrate, a first well disposed in the substrate and implanted with a first impurity, a second well disposed at one side of the first well and implanted with a second impurity, a first device isolation layer disposed in the first well and defining an emitter area, and a second device isolation layer disposed in the second well and defining a collector area, The BJT can also include an emitter having a second impurity, a base having a first impurity, a collector having a second impurity, and a high concentration doping area having a second impurity at high concentration. The high concentration doping area can be provided at one side of the collector in the second well. | 08-21-2014 |
| 20140239451 | Semiconductor Devices Including A Lateral Bipolar Structure And Fabrication Methods - A semiconductor device includes an emitter region, a collector region and a base region. The emitter region is implanted in a semiconductor substrate. The collector region is implanted in the semiconductor substrate. The base region is disposed between the emitter region and collector region. The base region includes no more than one LDD region and no more than one halo region. The base region contacts directly with at least one of the emitter region and the collector region. | 08-28-2014 |
| 20140327110 | METHOD OF MANUFACTURING A BIPOLAR TRANSISTOR, BIPOLAR TRANSISTOR AND INTEGRATED CIRCUIT - Consistent with an example embodiment, a bipolar transistor comprises an emitter region vertically separated from a collector region in a substrate by a base region. The bipolar transistor further comprises a field plate electrically connected to the emitter region; the field plate extends from the emitter region along the base region into the collector region and the field plate is laterally electrically insulated from the base region and the collector region by a spacer. The spacer comprises an electrically isolating material that includes a silicon nitride layer and is vertically electrically isolated from the substrate by a further electrically isolating material. | 11-06-2014 |
| 20140332927 | SELF-ALIGNED BIPOLAR JUNCTION TRANSISTOR HAVING SELF-PLANARIZING ISOLATION RAISED BASE STRUCTURES - A collector region is formed between insulating shallow trench isolation regions within a substrate. A base material is epitaxially grown on the collector region and the shallow trench isolation regions. The base material forms a base region on the collector region and extrinsic base regions on the shallow trench isolation regions. Further, a sacrificial emitter structure is patterned on the base region and sidewall spacers are formed on the sacrificial emitter structure. Planar raised base structures are epitaxially grown on the base region and the extrinsic base regions, and the upper layer of the raised base structures is oxidized. The sacrificial emitter structure is removed to leave an open space between the sidewall spacers and an emitter is formed within the open space between the sidewall spacers. The upper layer of the raised base structures comprises a planar insulator electrically insulating the emitter from the raised base structures. | 11-13-2014 |
| 20150008561 | BIPOLAR TRANSISTOR HAVING SINKER DIFFUSION UNDER A TRENCH - A bipolar transistor includes a substrate having a semiconductor surface, a first trench enclosure and a second trench enclosure outside the first trench enclosure both at least lined with a dielectric extending downward from the semiconductor surface to a trench depth, where the first trench enclosure defines an inner enclosed area. A base and an emitter formed in the base are within the inner enclosed area. A buried layer is below the trench depth including under the base. A sinker diffusion includes a first portion between the first and second trench enclosures extending from a topside of the semiconductor surface to the buried layer and a second portion within the inner enclosed area, wherein the second portion does not extend to the topside of the semiconductor surface. | 01-08-2015 |
| 20150021738 | BIPOLAR JUNCTION TRANSISTORS WITH AN AIR GAP IN THE SHALLOW TRENCH ISOLATION - Device structures, fabrication methods, and design structures for a bipolar junction transistor. A trench isolation region is formed in a substrate. The trench isolation region is coextensive with a collector in the substrate. A base layer is formed on the collector and on a first portion of the trench isolation region. A dielectric layer is formed on the base layer and on a second portion of the trench isolation region peripheral to the base layer. After the dielectric layer is formed, the trench isolation region is at least partially removed to define an air gap beneath the dielectric layer and the base layer. | 01-22-2015 |
| 20150021739 | PROTECTION DEVICE AND RELATED FABRICATION METHODS - Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a base region of semiconductor material having a first conductivity type, an emitter region within the base region having the opposite conductivity type, and a collector region of semiconductor material having the second conductivity type, wherein at least a portion of the base region resides between the emitter region and the collector region. A depth of the collector region is greater than a depth of the emitter region and less than or equal to a depth of the base region such that a distance between a lateral boundary of the emitter region and a proximal lateral boundary of the collector region is greater than zero and the collector region does not overlap or otherwise underlie the emitter region. | 01-22-2015 |
| 20150041956 | ISOLATION SCHEME FOR BIPOLAR TRANSISTORS IN BICMOS TECHNOLOGY - Device structures and design structures for a bipolar junction transistor. The device structure includes a collector region in a substrate, a plurality of isolation structures extending into the substrate and comprised of an electrical insulator, and an isolation region in the substrate. The isolation structures have a length and are arranged with a pitch transverse to the length such that each adjacent pair of the isolation structures is separated by a respective section of the substrate. The isolation region is laterally separated from at least one of the isolation structures by a first portion of the collector region. The isolation region laterally separates a second portion of the collector region from the first portion of the collector region. The device structure further includes an intrinsic base on the second portion of the collector region and an emitter on the intrinsic base. The emitter has a length transversely oriented relative to the length of the isolation structures. | 02-12-2015 |
| 20150054132 | LATERAL BIPOLAR JUNCTION TRANSISTOR AND FABRICATION METHOD THEREOF - Provided is a lateral BJT including a substrate, a well region, an area, at least one lightly doped region, a first doped region, and a second doped region. The substrate is of a first conductivity type. The well region is of a second conductivity type and is in the substrate. The area is in the well region. The at least one lightly doped region is in the well region below the area. The first doped region and the second doped region are of the first conductivity type and are in the well region on both sides of the area. The first doped region is connected to a cathode. The second doped region is connected to an anode, wherein the doping concentration of the at least one lightly doped region is lower than that of each of the first doped region, the second doped region, and the well region. | 02-26-2015 |
| 20150123245 | BIPOLAR JUNCTION TRANSISTORS WITH SELF-ALIGNED TERMINALS - Device structures, design structures, and fabrication methods for a bipolar junction transistor. A first layer comprised of a first semiconductor material and a second layer comprised of a second semiconductor material are disposed on a substrate containing a first terminal of the bipolar junction transistor. The second layer is disposed on the first layer and a patterned etch mask is formed on the second layer. A trench extends through the pattern hardmask layer, the first layer, and the second layer and into the substrate. The trench defines a section of the first layer stacked with a section of the second layer. A selective etching process is used to narrow the section of the second layer relative to the section of the first layer to define a second terminal and to widen a portion of the trench in the substrate to undercut the section of the first layer. | 05-07-2015 |
| 20160005840 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device including a bipolar transistor in which a polysilicon film is used for an emitter electrode. The bipolar transistor includes a collector region formed in an Si substrate, a base layer formed on the collector region, an emitter region formed in an upper part spaced apart from the collector region of the base layers, and a silicon oxide film formed on the base layer and covering a joint portion of the base layer and the emitter region. The density of fluorine existent at an interface between the joint portion and the silicon oxide film is equal to or higher than 1×10 | 01-07-2016 |
| 20160155661 | CONTACT MODULE FOR OPTIMIZING EMITTER AND CONTACT RESISTANCE | 06-02-2016 |
