| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257587000 | With specified electrode means | 26 |
| 20090194846 | Fully Cu-metallized III-V group compound semiconductor device with palladium/germanium/copper ohmic contact system - The present invention discloses a fully Cu-metallized III-V group compound semiconductor device, wherein the fully Cu-metallized of a III-V group compound semiconductor device is realized via using an N-type gallium arsenide ohmic contact metal layer formed of a palladium/germanium/copper composite metal layer, a P-type gallium arsenide ohmic contact metal layer formed of a platinum/titanium/platinum/copper composite metal layer, and interconnect metals formed of a titanium/platinum/copper composite metal layer. Thereby, the fabrication cost of III-V group compound semiconductor devices can be greatly reduced, and the performance of III-V group compound semiconductor devices can be greatly promoted. Besides, the heat-dissipation effect can also be increased, and the electric impedance can also be reduced. | 08-06-2009 |
| 20090212394 | BIPOLAR TRANSISTOR AND METHOD OF FABRICATING THE SAME - The invention provides a bipolar transistor with an improved performance because of a reduced collector series resistance and a reduced collector to substrate capacitance. The bipolar transistor includes a protrusion ( | 08-27-2009 |
| 20090218658 | SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND MANUFACTURING METHOD OF THE SAME - The present invention provides a technology that makes it possible to enhance the gain and the efficiency of an RF bipolar transistor. Device isolation is given between a p+ type isolation region and an n+ type collector embedded region and between a p+ type isolation region and an n type collector region (an n+ type collector extraction region) with an isolation section that surrounds the collector extraction region in a plan view and is formed by embedding a dielectric film in a groove penetrating an isolation section, a collector region, and a collector embedded region and reaching a substrate. Further, a current route is formed between an emitter wiring (a wiring) and the substrate with an electrically conductive layer formed by embedding the electrically conductive layer in a groove penetrating a dielectric film, silicon oxide films, a semiconductor region, and the isolation regions and reaching the substrate, and thereby the impedance between the emitter wiring and the substrate is reduced. | 09-03-2009 |
| 20090321879 | SILICIDED BASE STRUCTURE FOR HIGH FREQUENCY TRANSISTORS - High frequency performance of (e.g., silicon) bipolar devices ( | 12-31-2009 |
| 20100052102 | SEMICONDUCTOR DEVICE - Emitter contact holes formed under emitter electrodes in a first layer and emitter through holes formed thereon are arranged so as not to overlap each other, and, for each emitter electrode, the multiple emitter contact holes and the multiple emitter through holes are provided so as to be separated from each other. Thereby, the top surface of an emitter electrode in a second layer is influenced by at most only a level difference of each emitter through hole formed in an insulating film having a larger thickness, and thus the flatness of the top surface of the emitter electrode in the second layer is improved. Accordingly, fixation failure of a metal plate can be avoided. | 03-04-2010 |
| 20100078765 | Power semiconductor - A power semiconductor component is described. One embodiment provides a semiconductor body having an inner zone and an edge zone. A base zone of a first conduction type is provided. The base zone is arranged in the at least one inner zone and the at least one edge zone. An emitter zone of a second conduction type is provided. The emitter zone is arranged adjacent to the base zone in a vertical direction of the semiconductor body. A field stop zone of the first conduction type is provided. The field stop zone is arranged in the base zone and has a first field stop zone section having a first dopant dose in the edge zone and a second field stop zone section having a second dopant dose in the inner zone. The first dopant dose is higher than the second dopant dose. | 04-01-2010 |
| 20100155896 | HIGH-FREQUENCY BIPOLAR TRANSISTOR AND METHOD FOR THE PRODUCTION THEREOF - A high-frequency bipolar transistor includes an emitter contact adjoining an emitter connection region, a base contact adjoining a base connection region, and a collector contact adjoining a collector connection region. A first insulation layer is disposed on the base connection region. The collector connection region contains a buried layer, which connects the collector contact to a collector zone. A silicide or salicide region is provided on the buried layer and connects the collector contact to the collector zone in a low-impedance manner. A second insulation layer is disposed on the collector connection region but not on the silicide region. | 06-24-2010 |
| 20120018846 | Surge-Current-Resistant Semiconductor Diode With Soft Recovery Behavior and Methods for Producing a Semiconductor Diode - A bipolar semiconductor component, in particular a diode, comprising an anode structure which controls its emitter efficiency in a manner dependent on the current density in such a way that the emitter efficiency is low at small current densities and sufficiently high at large current densities, and an optional cathode structure, which can inject additional holes during commutation, and production methods therefor. | 01-26-2012 |
| 20120032303 | Bipolar Junction Transistor Based on CMOS Technology - The present invention relates to semiconductor technologies, and more particularly to a bipolar junction transistor (BJT) in a CMOS base technology and methods of forming the same. The BJT includes a semiconductor substrate having an emitter region, a base having a first contact, and a collector having a second contact and a well plug; a first silicide film on the first contact; a second silicide film on the second contact; a first silicide blocking layer on or over the semiconductor substrate between the first and second silicide films, and a second silicide blocking layer on the semiconductor substrate between the first silicide film and the emitter region. | 02-09-2012 |
| 20120104555 | Topside structures for an insulated gate bipolar transistor (IGBT) device to achieve improved device performances - This invention discloses an insulated gate bipolar transistor (IGBT) device formed in a semiconductor substrate. The IGBT device has a split-shielded trench gate that includes an upper gate segment and a lower shield segment. The IGBT device may further include a dummy trench filled with a dielectric layer disposed at a distance away from the split-shielded trench gate. The IGBT device further includes a body region extended between the split-shielded trench gate and the dummy trench encompassing a source region surrounding the split-shielded trench gate near a top surface of the semiconductor substrate. The IGBT device further includes a heavily doped N region disposed below the body region and above a source-dopant drift region above a bottom body-dopant collector region at a bottom surface of the semiconductor substrate. In an alternative embodiment, the IGBT may include a planar gate with a trench shield electrode. | 05-03-2012 |
| 20120119331 | Area-Efficient High Voltage Bipolar-Based ESD Protection Targeting Narrow Design Windows - An area-efficient, high voltage, single polarity ESD protection device ( | 05-17-2012 |
| 20120187538 | BIPOLAR TRANSISTOR WITH IMPROVED GAIN - Insufficient gain in bipolar transistors ( | 07-26-2012 |
| 20120261799 | SEMICONDUCTOR DEVICE AND RADIO COMMUNICATION DEVICE - A technology which allows a reduction in the thermal resistance of a semiconductor device used in a radio communication device, and the miniaturization thereof is provided. For example, the semiconductor device can include a plurality of unit transistors Q, transistor formation regions | 10-18-2012 |
| 20130032927 | System for Self-Aligned Contacts - A system for forming self-aligned contacts includes electroplating a first metal contact onto a Group III-V semiconductor substrate, the first metal contact having a greater height than width and having a straight sidewall profile, etching back the semiconductor substrate down to a base layer to expose an emitter semiconductor layer under the first metal contact, conformally depositing a dielectric layer on a vertical side of the first metal contact, a vertical side of the emitter semiconductor layer and on the base layer, anisotropically etching the dielectric layer off of the semiconductor substrate to form a dielectric sidewall spacer on the vertical side of the first metal contact and providing a second metal contact immediately adjacent the dielectric sidewall spacer. | 02-07-2013 |
| 20130037914 | NOVEL STRUCTURE OF NPN-BJT FOR IMPROVING PUNCH THROUGH BETWEEN COLLECTOR AND EMITTER - A bipolar junction transistor and a manufacturing method for the same are provided. The bipolar junction transistor includes a well region, an emitter electrode, a base electrode, a collector electrode, and a conductive layer. The emitter electrode, the base electrode and the collector electrode are separated from each other by the well region. The conductive layer is on the well region between the base electrode and the collector electrode. | 02-14-2013 |
| 20150130025 | TRANSISTOR FABRICATING METHOD AND TRANSISTOR - The invention provides a method for fabricating a transistor and a transistor, wherein the method for fabricating a transistor includes: growing a second oxide layer on the surface of a substrate on which a first oxide layer and a first base region are formed, wherein the second oxide layer is formed above the first base region; forming an emitter region in a first preset area on the second oxide layer; forming a contact hole in a second preset area on the second oxide layer, wherein the second preset area does not overlap with the first preset area; injecting doping elements into the surface of the first base region in the area of the contact hole; and thermally processing the substrate to activate the doping elements to form a second base region. The invention may fabricate the dense base region lithography layer and the contact hole lithography layer in an integrate process ingeniously to thereby perform self-alignment between the dense base region lithography layer and the contact hole lithography layer and address the problem deviation of alignment between the dense base area and the contact hole. | 05-14-2015 |
| 20160204234 | BIPOLAR TRANSISTOR WITH CARBON ALLOYED CONTACTS | 07-14-2016 |
| 20160380087 | LATERAL BIPOLAR JUNCTION TRANSISTOR (BJT) ON A SILICON-ON-INSULATOR (SOI) SUBSTRATE - A bipolar transistor is supported by a substrate including a semiconductor layer overlying an insulating layer. A transistor base is formed by a base region in the semiconductor layer that is doped with a first conductivity type dopant at a first dopant concentration. The transistor emitter and collector are formed by regions doped with a second conductivity type dopant and located adjacent opposite sides of the base region. An extrinsic base includes an epitaxial semiconductor layer in contact with a top surface of the base region. The epitaxial semiconductor layer is doped with the first conductivity type dopant at a second dopant concentration greater than the first dopant concentration. Sidewall spacers on each side of the extrinsic base include an oxide liner on a side of the epitaxial semiconductor layer and the top surface of the base region. | 12-29-2016 |
| 257588000 | Including polycrystalline semiconductor as connection | 8 |
| 20080230872 | BIPOLAR TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A bipolar transistor and a method for manufacturing the same. The bipolar transistor can include a collector region formed in a substrate, an epitaxial layer formed over the substrate including the collector region, a base region formed in the epitaxial layer, an emitter region formed in the base region, an oxide layer formed on sidewalls of a trench extending through the emitter region, the base region, the epitaxial layer and in the collector region, and a polysilicon layer formed in the trench. | 09-25-2008 |
| 20090283864 | Semiconductor device - In order to reduce a device area, a bipolar transistor using temperature characteristics of a forward voltage generated between an emitter and a base has a structure in which a high concentration second conductivity type impurity region for a base electrode and a high concentration first conductivity type impurity region for a collector electrode are brought into direct contact with each other to prevent formation of an unnecessary isolation region. Further, an emitter region is disposed to self-align with a device isolation insulating film or a polycrystalline silicon arranged on a surface of a semiconductor substrate. | 11-19-2009 |
| 20100090310 | BIPOLAR TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A bipolar transistor includes an isolation layer formed in a bipolar region on a semiconductor substrate, a conductive film formed over an upper portion of the isolation layer, n+ and p+ junction regions formed within the conductive film, a first silicide film formed over portions of an upper boundary of the n+ and p+ junction regions, the first silicide film defining openings over the upper boundary of the n+ and p+ junction regions, a second silicide film formed in the openings defined by the first silicide film over the upper boundary portions of the n+ and p+ junction regions, a plurality of plugs connected to the second silicide film, and a plurality of electrodes connected to each of the plugs. In this way, embodiments not only suppress the occurrence of parasitic junction between wells, but also simplify the processes by omitting well processes by forming an isolation layer in a bipolar region, forming a conductive film, and applying ion-implantation process to the conductive film to form a junction region. | 04-15-2010 |
| 20100181649 | POLYSILICON PILLAR BIPOLAR TRANSISTOR WITH SELF-ALIGNED MEMORY ELEMENT - Memory cells having memory elements self-aligned with the emitters of bipolar junction transistor access devices are described herein, as well as methods for manufacturing such devices. A memory device as described herein comprises a plurality of memory cells. Memory cells in the plurality of memory cells include a bipolar junction transistor comprising an emitter comprising a pillar of doped polysilicon. The memory cells include an insulating element over the emitter and having an opening extending through the insulating layer, the opening centered over the emitter. The memory cells also include a memory element within the opening and electrically coupled to the emitter. | 07-22-2010 |
| 20100320572 | Thin-Body Bipolar Device - A thin-body bipolar device includes: a semiconductor substrate, a semiconductor fin constructed over the semiconductor substrate, a first region of the semiconductor fin having a first conductivity type, the first region serving as a base of the thin-body bipolar device, and a second and third region of the semiconductor fin having a second conductivity type opposite to the first conductivity type, the second and third region being both juxtaposed with and separated by the first region, the second and third region serving as an emitter and collector of the thin-body bipolar device, respectively. | 12-23-2010 |
| 20120319243 | BIPOLAR JUNCTION TRANSISTOR - In accordance with one embodiment, the present invention provides a bipolar junction transistor including an emitter region; a base region; a first isolation between the emitter region and the base region; a gate on the first isolation region and overlapping at least a portion of a periphery of the emitter region; a collector region; and a second isolation between the base region and the collector region. | 12-20-2012 |
| 20130277805 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A semiconductor structure includes a substrate, a first well having a first conductive type, a second well having a second conductive type, a body region, a first doped region, a second doped region, a third doped region and a field plate. The first and second wells are formed in the substrate. The body region is formed in the second well. The first and second doped regions are formed in the first well and the body region, respectively. The second and first doped regions have the same polarities, and the dopant concentration of the second doped region is higher than that of the first doped region. The third doped region is formed in the second well and located between the first and second doped regions. The third and first doped regions have reverse polarities. The field plate is formed on the surface region between the first and second doped regions. | 10-24-2013 |
| 20150340440 | BIPOLAR TRANSISTOR - A modified bipolar transistor is provided which can provide improved gain, Early voltage, breakdown voltage and linearity over a finite range of collector voltages. It is known that the gain of a transistor can change with collector voltage. This document teaches a way of reducing this variation by providing structures for the depletion regions with the device to preferentially deplete with. As a result the transistor's response can be made more linear. | 11-26-2015 |
