Class / Patent application number | Description | Number of patent applications / Date published |
257592000 | With base region having specified doping concentration profile or specified configuration (e.g., inactive base more heavily doped than active base or base region has constant doping concentration portion (e.g., epitaxial base)) | 14 |
20080217742 | TAILORED BIPOLAR TRANSISTOR DOPING PROFILE FOR IMPROVED RELIABILITY - Bipolar transistor device structures that improve bipolar device reliability with little or no negative impact on device performance. In one embodiment, the bipolar device has a collector of first conductivity type material formed in a substrate, a base of a second conductivity type material including an extrinsic base layer and an intrinsic base layer, a raised emitter of a first conductivity type semiconductor material formed on the intrinsic base layer, and, a dielectric material layer separating the intrinsic base region and the raised emitter region, and, a thin “shunt” layer of dopant of second conductivity type material added to the region below the emitter dielectric layer. In a second embodiment, a selectively implanted collector (pedestal implant) is added to the vertical bipolar transistor device to enable a reduction in overall subcollector doping level to improve reliability without sacrificing device performance. These solutions add no additional masking steps and only one additional implantation step. | 09-11-2008 |
20080283967 | Semiconductor device - In a semiconductor device including a bipolar transistor, a base region has a two layer structure including a first base region, and a second base region which is provided around the first base region and has a lower impurity density than that of the first base region and has a shallower depth than that of the first base region. | 11-20-2008 |
20090026578 | Vertical NPN Transistor Fabricated in a CMOS Process With Improved Electrical Characteristics - A vertical NPN bipolar transistor includes a P-type semiconductor structure, an N-well as the collector, a P-Base region in the N-well and an N-type region as the emitter. The transistor further includes P-type region formed in the P-Base region and underneath the field oxide layer where the P-type region has a doping concentration higher than the P-base region. The P-type region functions to inhibit the lateral parasitic bipolar action so that the transistor action is confined to the intrinsic base region vertically underneath the emitter. In one embodiment, the P-type region is a boron field doping region. The boron field doping region can be the same field doping region used to form channel stops for NMOS transistors in a CMOS fabrication process. | 01-29-2009 |
20090146258 | SELF-ALIGNED VERTICAL PNP TRANSISTOR FOR HIGH PERFORMANCE SiGe CBiCMOS PROCESS - A structure and a process for a self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process. Embodiments include SiGe CBiCMOS with high-performance SiGe NPN transistors and PNP transistors. As the PNP transistors and NPN transistors contained different types of impurity profile, they need separate lithography and doping step for each transistor. The process is easy to integrate with existing CMOS process to save manufacturing time and cost. As plug-in module, fully integration with SiGe BiCMOS processes. High doping Polysilicon Emitter can increase hole injection efficiency from emitter to base, reduce emitter resistor, and form very shallow EB junction. Self-aligned N+ base implant can reduce base resistor and parasitical EB capacitor. Very low collector resistor benefits from BP layer. PNP transistor can be Isolated from other CMOS and NPN devices by BNwell, Nwell and BN+ junction. | 06-11-2009 |
20110101500 | JUNCTION FIELD EFFECT TRANSISTOR - A bipolar transistor, comprising a collector, a base and an emitter, in which the collector comprises a relatively heavily doped region, and a relatively lightly doped region adjacent the base, and in which the relatively heavily doped region is substantially omitted from an intrinsic region of the transistor. | 05-05-2011 |
20110121428 | HIGH GAIN TUNABLE BIPOLAR TRANSISTOR - An improved bipolar transistor ( | 05-26-2011 |
20110175198 | ESD PROTECTION WITH INCREASED CURRENT CAPABILITY - A stackable electrostatic discharge (ESD) protection clamp ( | 07-21-2011 |
20120061802 | BIPOLAR JUNCTION TRANSISTOR - A bipolar junction transistor includes a semiconductor island on an insulating substrate; an emitter and at least one of a collector and sub collector within the semiconductor island, the emitter and the at least one of the collector and the sub collector being of a first conductivity type; a base within the semiconductor island separating the emitter and the at least one of the collector and the sub collector, the base being of a second conductivity type; a base contact region within the semiconductor island, the base contact region being of the second conductivity type; and a connecting base region adjacent the base within the semiconductor island and connecting the base to the base contact region while not directly contacting the emitter, the connecting base region being of the second conductivity type with a doping concentration less than a doping concentration of the base contact region. | 03-15-2012 |
20130056855 | METHOD OF MANUFACTURING IC COMPRISING A BIPOLAR TRANSISTOR AND IC - Disclosed is an integrated circuit and a method of manufacturing an integrated circuit comprising a bipolar transistor, the method comprising providing a substrate comprising a pair of isolation regions separated by an active region comprising a collector; forming a base layer stack over said substrate; forming a migration layer having a first migration temperature and an etch stop layer; forming a base contact layer having a second migration temperature; etching an emitter window in the base contact layer, thereby forming cavities extending from the emitter window; and exposing the resultant structure to the first migration temperature in a hydrogen atmosphere, thereby filling the cavities with the migration layer material. | 03-07-2013 |
20130168822 | SELF ALIGNED STRUCTURES AND DESIGN STRUCTURE THEREOF - Vertical bipolar junction structures, methods of manufacture and design structures. The method includes forming one or more sacrificial structures for a bipolar junction transistor (BJT) in a first region of a chip. The method includes forming a mask over the one or more sacrificial structures. The method further includes etching an opening in the mask, aligned with the one or more sacrificial structures. The method includes forming a trench through the opening and extending into diffusion regions below the one or more sacrificial structures. The method includes forming a base region of the BJT by depositing an epitaxial material in the trench, in contact with the diffusion regions. The method includes forming an emitter contact by depositing a second epitaxial material on the base region within the trench. The epitaxial material for the emitter region is of an opposite dopant type than the epitaxial material of the base region. | 07-04-2013 |
20130307122 | BIPOLAR TRANSISTOR WITH EMBEDDED EPITAXIAL EXTERNAL BASE REGION AND METHOD OF FORMING THE SAME - The present invention discloses a bipolar transistor with an embedded epitaxial external base region, which is designed to solve the problem of the TED effect with the prior art structures. The bipolar transistor with an embedded epitaxial external base region of the present invention comprises at least a collector region, a base region and an external base region on the collector region, an emitter on the base region, and sidewalls at both sides of the emitter. The external base region is grown through an in-situ doping selective epitaxy process and is embedded in the collector region. A portion of the external base region is located beneath the sidewalls. The present invention discloses a method of forming a bipolar transistor with an embedded epitaxial external base region. The bipolar transistor with an embedded epitaxial external base region of the present invention avoids the TED effect and reduces the resistance of the external base region of the device so that the performance of the device is improved. The method of forming a bipolar transistor with an embedded epitaxial external base region of the present invention achieves the aforesaid bipolar transistor with an embedded epitaxial external base region, and features concise steps, a low cost and simple operations, and the structure obtained has good performance. | 11-21-2013 |
20140124895 | RADIATION INDUCED DIODE STRUCTURE - A semiconductor device containing an NPN bipolar junction transistor may be formed by forming a p-type radiation induced diode structure (RIDS) region in an intrinsic p-type base region of the NPN bipolar junction transistor at a boundary of the intrinsic p-type base region with a dielectric layer over a substrate of the semiconductor device, between an emitter of the NPN bipolar junction transistor and an extrinsic p-type base region of the NPN bipolar junction transistor. The p-type RIDS region has a doping density high enough to prevent inversion of a surface of the p-type RIDS region adjacent to the dielectric layer when trapped charge is accumulated in the dielectric layer, while the intrinsic p-type base region may invert from the trapped charge forming the radiation induced diode structure. The p-type RIDS region is separated from the emitter and from the extrinsic base region by portions of the intrinsic base region. | 05-08-2014 |
20160380055 | EXTRINSIC BASE DOPING FOR BIPOLAR JUNCTION TRANSISTORS - Device structure and fabrication methods for a bipolar junction transistor. A base layer is formed and an emitter is formed on a first portion of the base layer. A dopant-containing layer is deposited on a second portion of the base layer. Dopant is transferred from the dopant-containing layer into the second portion of the base layer to define an extrinsic base of the device structure. | 12-29-2016 |
20160380086 | DEVICE PARAMETER NORMALIZATION ABOUT A PERIPHERY OF A NON-CIRCULAR EMITTER OF A LATERAL BIPOLAR TRANSISTOR - Apparatus and associated methods relate to varying the base width around a non-circular emitter of a lateral bipolar transistor to vary a device parameter so as to compensate for variations in the device parameter caused by curvature variations along a periphery of the non-circular emitter. In an illustrative embodiment, the non-circular emitter can be an elongated emitter. In some embodiments, where the emitter has lower periphery curvature, the base region can be made narrower than where the emitter has higher periphery curvature. In an exemplary embodiment, such base-width variation can compensate for beta, for example. Using this technique, a beta corresponding to the narrower base region can be substantially equal to a beta corresponding to a wider base region. Varying base width to compensate for geometrically induced parameter variations can advantageously minimize the overall device size of a lateral PNP device rated for a specified current. | 12-29-2016 |