| Entries |
| Document | Title | Date |
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| 20080197411 | MOS TRANSISTOR DEVICE IN COMMON SOURCE CONFIGURATION - A semiconductor device includes a semiconductor substrate, a first p-channel laterally diffused metal oxide semiconductor (LDMOS) transistor formed over the semiconductor substrate and additional p-channel LDMOS transistors formed over the semiconductor substrate. First drain and gate electrodes are formed over the substrate and are coupled to the first LDMOS transistor. Additional drain and gate electrodes are formed over the substrate and are coupled to the second LDMOS transistor. A common source electrode for the first and second LDMOS transistors is also formed over the substrate. | 08-21-2008 |
| 20080237705 | Ldmos Transistor - The LDMOS transistor ( | 10-02-2008 |
| 20080237706 | Lateral MOSFET - A lateral MOSFET formed in a substrate of a first conductivity type includes a gate formed atop a gate dielectric layer over a surface of the substrate, a drain region of a second conductivity type, a source region of a second conductivity type, and a body region of the first conductivity type which extends under the gate. The body region may have a non-monotonic vertical doping profile with a portion located deeper in the substrate having a higher doping concentration than a portion located shallower in the substrate. The lateral MOSFET may be drain-centric, with the source region and an optional dielectric-filled trench surrounding the drain region. | 10-02-2008 |
| 20080246086 | SEMICONDUCTOR DEVICES HAVING CHARGE BALANCED STRUCTURE - A laterally diffused metal-oxide-semiconductor transistor device includes a substrate having a first conductivity type with a semiconductor layer formed over the substrate. A source region and a drain extension region of the first conductivity type are formed in the semiconductor layer. A body region of a second conductivity type is formed in the semiconductor layer. A conductive gate is formed over a gate dielectric layer that is formed over a channel region. A drain contact electrically connects the drain extension region to the substrate and is laterally spaced from the channel region. The drain contact includes a highly-doped drain contact region formed between the substrate and the drain extension region in the semiconductor layer, wherein a topmost portion of the highly-doped drain contact region is spaced from the upper surface of the semiconductor layer. A source contact electrically connects the source region to the body region. | 10-09-2008 |
| 20080258215 | LDMOS Device - An LDMOS transistor comprises source, channel and extended drain regions. The extended drain region comprises a plurality of islands that have a conductivity type that is opposite to the extended drain region. The islands have a depth less than a depth of the extended drain region. | 10-23-2008 |
| 20080290410 | Mosfet With Isolation Structure and Fabrication Method Thereof - A MOSFET with an isolation structure is provided. An N-type MOSFET includes a first N-type buried layer and a P-type epitaxial layer disposed in a P-type substrate. A P-type FET includes a second N-type buried layer and the P-type epitaxial layer disposed in the P-type substrate. The first, second N-type buried layers and the P-type epitaxial layer provide isolation between FETs. In addition, a plurality of separated P-type regions disposed in the P-type epitaxial layer further provides an isolation effect. A first gap exists between a first thick field oxide layer and a first P-type region, for raising a breakdown voltage of the N-type FET. A second gap exists between a second thick field oxide layer and a second N-well, for raising a breakdown voltage of the P-type FET. | 11-27-2008 |
| 20080290411 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device including at least one drift region formed near a channel region on a substrate, a first buried insulating layer formed in the drift region, and a first reduced surface field region interposed between the first buried insulating layer and the drift region. Accordingly, the semiconductor device provides first reduced surface field regions arranged between drift regions and first buried insulating layers, thus having advantages of improved junction integrity, suitability for LDMOS transistors employing a high operation voltage and reduced total size. | 11-27-2008 |
| 20080315308 | LOW ON-RESISTANCE LATERAL DOUBLE-DIFFUSED MOS DEVICE AND METHOD OF FABRICATING THE SAME - A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region. | 12-25-2008 |
| 20090001461 | LATERAL DMOS DEVICE AND METHOD FOR FABRICATING THE SAME - An LDMOS device and a method for fabricating the same that may include a first conductivity-type semiconductor substrate having an active area and a field area; a second conductivity-type deep well formed on the first conductivity-type semiconductor substrate; a second conductivity-type adjusting layer located in the second conductivity-type deep well; a first conductivity-type body formed in the second conductivity-type deep well; an insulating layer formed on the first conductivity-type semiconductor substrate in the active area and the field area; a gate area formed on the first conductivity-type semiconductor substrate in the active area; a second conductivity-type source area formed in the first conductivity-type body; a second conductivity-type drain area formed in the second conductivity-type deep well. Accordingly, such an LDMOS device has a high breakdown voltage without an increase in on-resistance. | 01-01-2009 |
| 20090001462 | Lateral Power MOSFET with High Breakdown Voltage and Low On-Resistance - A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring in the HVW and occupying a top portion of the HVW, wherein the field ring is of the first conductivity type; an insulation region over and in contact with the field ring and a portion of the HVW; a gate electrode partially over the insulation region; a drain region in the HVW, wherein the drain region is of the second conductivity type; and wherein the HVW horizontally extends further toward the drain region than the pre-HVW; and a source region adjacent to, and on an opposite side of the gate electrode than the drain region. | 01-01-2009 |
| 20090020813 | FORMATION OF LATERAL TRENCH FETS (FIELD EFFECT TRANSISTORS) USING STEPS OF LDMOS (LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR) TECHNOLOGY - A semiconductor structure and a method forming the same. The method includes providing a semiconductor structure which includes a semiconductor substrate. The semiconductor substrate includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface. The method further includes simultaneously forming a first doped transistor region of a first transistor and a first doped Source/Drain portion of a second transistor on the semiconductor substrate. The first doped transistor region is not a portion of a Source/Drain region of the first transistor. The first doped transistor region and the first doped Source/Drain portion comprise dopants of a first doping polarity. The method further includes forming a second gate dielectric layer and a second gate electrode region of the second transistor on the semiconductor substrate. The second gate dielectric layer is sandwiched between and electrically insulates the second gate electrode region and the semiconductor substrate. | 01-22-2009 |
| 20090020814 | High Voltage Semiconductor Device with Floating Regions for Reducing Electric Field Concentration - A high voltage semiconductor device includes a source region of a first conductivity type having an elongated projection with two sides and a rounded tip in a semiconductor substrate. A drain region of the first conductivity type is laterally spaced from the source region in the semiconductor substrate. A gate electrode extends along the projection of the source region on the semiconductor substrate between the source and drain regions. Top floating regions of a second conductivity type are disposed between the source and drain regions in the shape of arched stripes extending along the rounded tip of the projection of the source region. The top floating regions are laterally spaced from one another by regions of the first conductivity type to thereby form alternating P-N regions along the lateral dimension. | 01-22-2009 |
| 20090065863 | LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE - In one example embodiment, an LDMOS device includes a first n-type well formed on a p-type substrate, a plurality of isolation layers formed in the first n-type well, a p-type ion implantation region formed on a surface of each of the isolation layers, and a gate selectively formed on the first n-type well and the isolation layers. | 03-12-2009 |
| 20090065864 | Semiconductor Device and Method of Fabricating the Same - A semiconductor device and a method of fabricating the same are provided. The semiconductor device can include a buried conductive layer in a semiconductor substrate, an epitaxial layer on the buried conductive layer, and a plug passing through the epitaxial layer. The plug can be electrically connected to the buried conductive layer and can have an insulating layer around it, isolating the plug from an adjacent active area. | 03-12-2009 |
| 20090078996 | Semiconductor device - A semiconductor device according to the present invention includes: an insulating layer; a semiconductor layer of a first conductive type laminated on the insulating layer; an annular deep trench having a thickness reaching the insulating layer from a top surface of the semiconductor layer; a body region of a second conductive type formed across an entire thickness of the semiconductor layer along a side surface of the deep trench in an element forming region surrounded by the deep trench; a drift region of the first conductive type constituted of a remainder region besides the body region in the element forming region; a source region of the first conductive type formed in a top layer portion of the body region; a drain region of the first conductive type formed in a top layer portion of the drift region; and a first conductive type region formed in the drift region, having a deepest portion reaching a position deeper than the drain region, and having a first conductive type impurity concentration higher than the first conductive type impurity concentration of the semiconductor layer and lower than the first conductive type impurity concentration of the drain region. | 03-26-2009 |
| 20090085112 | LATERAL DIFFUSION METAL-OXIDE-SEMICONDUCTOR STRUCTURE - A lateral diffusion metal-oxide-semiconductor (LDMOS) structure comprises a gate, a source, a drain and a shallow trench isolation. The shallow trench isolation is formed between the drain and the gate to withstand high voltages, applied to the drain, and is associated with the semiconductor substrate to form a recess. As such, the surface of the shallow trench isolation is lower than the surface of the semiconductor substrate. Optionally, the surface of the shallow trench isolation is lower than the surface of the semiconductor substrate by 300-1500 angstroms. | 04-02-2009 |
| 20090085113 | Semiconductor device - A semiconductor device according to the present invention includes: a semiconductor layer of a first conductivity type; an annular deep trench penetrating the semiconductor layer in the depth direction to surround an element forming region; a drain region of a second conductivity type formed in a surface layer portion of the semiconductor layer in the element forming region; a drift region of the second conductivity type formed in the surface layer portion of the semiconductor layer to come into contact with the drain region in the element forming region; a body region of the first conductivity type formed in the surface layer portion of the semiconductor layer at an interval from the drift region in the element forming region; a source region of the second conductivity type formed in a surface layer portion of the body region; and a first high-concentration buried region, formed in the semiconductor layer between a portion opposed to the source region in the depth direction and the deep trench, having a higher impurity concentration than that of the semiconductor layer. | 04-02-2009 |
| 20090096022 | LATERAL DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE - An exemplary lateral diffused metal oxide semiconductor device includes a first-type substrate, a gate oxide film disposed on the first-type substrate, a poly gate disposed on the gate oxide film, a first second-type slightly doped region formed in the first-type substrate and acting as a well, a first first-type highly doped region formed in the well and acting as a body, a first second-type highly doped region formed in the body and acting as a source, a second second-type highly doped region formed in the well and acting as a drain, a second first-type highly doped region formed in the body, and a first fist-type doped region formed in the body and is beneath the source. | 04-16-2009 |
| 20090127620 | SEMICONDUCTOR DOPING WITH REDUCED GATE EDGE DIODE LEAKAGE - Semiconductor doping techniques, along with related methods and structures, are disclosed that produce components having a more tightly controlled source and drain extension region dopant profiles without significantly inducing gate edge diode leakage. The technique follows the discovery that carbon, which may be used as a diffusion suppressant for dopants such as boron, may produce a gate edge diode leakage if present in significant quantities in the source and drain extension regions. As an alternative to placing carbon in the source and drain extension regions, carbon may be placed in the source and drain regions, and the thermal anneal used to activate the dopant may be relied upon to diffuse a small concentration of the carbon into the source and drain extension regions, thereby suppressing dopant diffusion in these regions without significantly inducing gate edge diode leakage. The increased concentration of carbon in the source and drain regions may permit heavier doping of the source/drain region, leading to improved gate capacitance. | 05-21-2009 |
| 20090159970 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - Provided are a semiconductor device which can be manufactured at low cost and has a low on-resistance and a high withstand voltage, and its manufacturing method. The semiconductor device comprises an N-type well area formed on a P-type semiconductor substrate, a P-type body area formed within the well area, an N-type source area formed within the body area, an N-type drain area formed at a distance from the body area within the well area, a gate insulating film formed so as to overlay a part of the body area, a gate electrode formed on the gate insulating film and a P-type buried diffusion area which makes contact with the bottom of the body area and extends to an area beneath the drain area in a direction parallel to the surface of the semiconductor substrate within the well area. | 06-25-2009 |
| 20090166736 | LATERAL DOUBLE DIFUSED METAL OXIDE SEMICONDUCTOR TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A lateral double diffused metal oxide semiconductor a lateral double diffused metal oxide semiconductor (LDMOS) transistor which may include a first conductive type semiconductor substrate and a shallow trench isolation film defining an active region in the substrate. A second conductive type body region may be disposed over a portion of the top of the semiconductor substrate. A first conductive type source region may be disposed in the top of the body region. A first conductive type extended drain region may be disposed over a portion of the top of the semiconductor substrate and spaced from the body region. A gate dielectric film covers surfaces of the second conductive type body region and first conductive type source region and a portion of the top of the first conductive type semiconductor substrate. A gate conductive film may extend from the first conductive type source region, over the gate dielectric film, over the shallow trench isolation film, and inside the shallow trench isolation film. Therefore, embodiments prevent the disturbance in flow of current in an on-state by the STI, making it possible to obtain improved on-state resistance characteristics. | 07-02-2009 |
| 20090212361 | Semiconductor device and method of manufacturing the same - A LOCOS offset type MOS transistor includes a MOS transistor including: a gate electrode formed on a gate oxide film, the gate oxide film being formed on a surface of a semiconductor substrate of a first conductivity type; a LOCOS oxide film and a first offset diffusion layer of a second conductivity type, which are formed on the surface of the semiconductor substrate at one of both sides and only one side of the gate electrode, a part of a region of the LOCOS oxide film, which is not an end of the LOCOS oxide film, being removed; and one of both of a source diffusion layer and a drain diffusion layer of the second conductivity type and only a drain diffusion layer of the second conductivity type is formed in the first offset diffusion layer corresponding to the region in which the LOCOS oxide film is removed. Accordingly, a semiconductor device may be provided including the MOS transistor which has a high break down voltage and ensures a proper operation even at a voltage of 50 V or higher by covering a region in which electric field accumulation is caused below the drain diffusion layer with the offset diffusion layer. | 08-27-2009 |
| 20090218622 | LDMOS TRANSISTOR - The LDMOS transistor ( | 09-03-2009 |
| 20090256199 | LATERAL METAL OXIDE SEMICONDUCTOR DRAIN EXTENSION DESIGN - A semiconductor device comprising source and drain regions and insulating region and a plate structure. The source and drain regions are on or in a semiconductor substrate. The insulating region is on or in the semiconductor substrate and located between the source and drain regions. The insulating region has a thin layer and a thick layer. The thick layer includes a plurality of insulating stripes that are separated from each other and that extend across a length between the source and the drain regions. The plate structure is located between the source and the drain regions, wherein the plate structure is located on the thin layer and portions of the thick layer, the plate structure having one or more conductive bands that are directly over individual ones of the plurality of insulating stripes. | 10-15-2009 |
| 20090273032 | LDMOS Device and Method for Manufacturing the Same - Provided is a LDMOS device and method for manufacturing. The LDMOS device includes a second conductive type buried layer formed in a first conductive type substrate. A first conductive type first well is formed in the buried layer and a field insulator with a gate insulating layer at both sides are formed on the first well. On one side of the field insulator is formed a first conductive type second well and a source region formed therein. On the other side of the field insulator is formed an isolated drain region. A gate electrode is formed on the gate insulating layer on the source region and a first field plate is formed on a portion of the field insulator and connected with the gate electrode. A second field plate is formed on another portion of the field insulator and spaced apart from the first field plate. | 11-05-2009 |
| 20090283827 | Formation Of A MOSFET Using An Angled Implant - A LDMOS transistor having a channel region located between an outer boundary of an n-type region and an inner boundary of a p-body region. A width of the LDMOS channel region is less than 80% of a distance between an outer boundary of an n | 11-19-2009 |
| 20090302385 | HIGH PERFORMANCE LDMOS DEVICE HAVING ENHANCED DIELECTRIC STRAIN LAYER - An LDMOS device includes a substrate having a surface and a gate electrode overlying the surface and defining a channel region in the substrate below the gate electrode. A drain region is spaced apart from the channel region by an isolation region. The isolation region includes a region of high tensile stress and is configured to induce localized stress in the substrate in close proximity to the drain region. The region of high tensile stress in the isolation region can be formed by high-stress silicon oxide or high-stress silicon nitride. In a preferred embodiment, the isolation region is a shallow trench isolation region formed in the substrate intermediate to the gate electrode and the drain region. | 12-10-2009 |
| 20090315109 | SEMICONDUCTOR DEVICE HAVING OTP CELLS AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a deep N-type well region which may be formed by applying an ion-implantation process, using a mask, to a predetermined pattern over a portion of a semiconductor substrate over which an oxide film is formed, a dwell region which may be formed by applying an ion-implantation process, using a mask, to a predetermined pattern over a portion of the N-type well region, a shallow N-type well region and a drain region which may be respectively formed by applying an ion-implantation process, using a mask, to a predetermined pattern over a portion of the deep N-type well region, a source region which may be formed by applying an ion-implantation process, using a mask, to a predetermined pattern over a portion of the dwell region, a contact hole which may be formed by being filled with a metal after forming an inter-metal dielectric layer over a portion of the semiconductor substrate over which the source region is formed, and a metal line formed over a portion of the contact hole. | 12-24-2009 |
| 20090321827 | SEMICONDUCTOR DEVICE REDUCING OUTPUT CAPACITANCE DUE TO PARASITIC CAPACITANCE - Plural through-holes are formed in a region of a semiconductor substrate positioned below a drain region (an element region other than a P-type well region). According to this configuration, an opposing area of the drain region and the semiconductor substrate can be reduced. Therefore, a drain-substrate capacitance Cdsub is reduced, and an output capacitance Coss of an SOI LDMOSFET can be reduced as a result. | 12-31-2009 |
| 20100001345 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate having a first conductivity type; a well having a second conductivity type and provided inside the semiconductor substrate; a first impurity region having the first conductivity type and provided within the well; a second impurity region having the second conductivity type, provided inside the well and away from the first impurity region; and a third impurity region having a first conductivity type, provided surrounding the well and away from the second impurity region. In this semiconductor device, the well is formed to be deeper than the first impurity region, the second impurity region, and the third impurity region, in a thickness direction of the semiconductor substrate; and a minimum distance between the first impurity region and the second impurity region is smaller than a minimum distance between the second impurity region and the third impurity region. | 01-07-2010 |
| 20100006936 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer of a first conductivity type; a deep well of a second conductivity type formed in a portion of an upper layer portion of the semiconductor layer; a well of the first conductivity type formed in a portion of an upper layer portion of the deep well; a source layer of the second conductivity type formed in the well; a drain layer of the second conductivity type formed in the well apart from the source layer; and a contact layer of the second conductivity type formed outside the well in an upper layer portion of the deep well and connected to the drain layer. The drain layer is electrically connected to the deep well via the well by applying a driving voltage between the source layer and the drain layer. | 01-14-2010 |
| 20100006937 | Lateral Double Diffused Metal Oxide Semiconductor (LDMOS) Device and Method of Manufacturing LDMOS Device - A method for manufacturing a lateral double diffused metal oxide semiconductor (LDMOS) device includes forming an oxide layer on a semiconductor substrate, forming first and second trenches by partially etching the oxide layer and the semiconductor substrate, forming a small trench overlapping with the second trench so that the second trench has a stepped structure, and depositing one or more dielectric layers so that the first trench forms a device isolation layer defining a semiconductor device region and the second trench having a stepped structure forms a drain extension device isolation layer. The breakdown voltage of the LDMOS device may be improved while reducing the on-resistance, thereby improving the operational reliability of the device. | 01-14-2010 |
| 20100013012 | INTEGRATED COMPLEMENTARY LOW VOLTAGE RF-LDMOS - Complementary RF LDMOS transistors have gate electrodes over split gate oxides. A source spacer of a second conductivity type extends laterally from the source tap of a first conductivity type to approximately the edge of the gate electrode above the thinnest gate oxide. A body of a first conductivity type extends from approximately the bottom center of the source tap to the substrate surface and lies under most of the thin section of the split gate oxide. The source spacer is approximately the length of the gate sidewall oxide and is self aligned with gate electrode. The body is also self aligned with gate electrode. The drain is surrounded by at least one buffer region which is self aligned to the other edge of the gate electrode above the thickest gate oxide and extends to the below the drain and extends laterally under the thickest gate oxide. Both the source tap and drain are self aligned with the gate side wall oxides and are thereby spaced apart laterally from the gate electrode. | 01-21-2010 |
| 20100025763 | Semiconductor on Insulator Devices Containing Permanent Charge - A lateral SOI device may include a semiconductor channel region connected to a drain region by a drift region. An insulation region on the drift layer is positioned between the channel region and the drain region. Permanent charges may be embedded in the insulation region sufficient to cause inversion in the insulation region. The semiconductor layer also overlies a global insulation layer, and permanent charges are preferably embedded in at least selected areas of this insulation layer too. | 02-04-2010 |
| 20100025764 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided is a manufacturing method for an offset MOS transistor capable of operating safely even under a voltage of 50 V or higher. In the offset MOS transistor which includes a LOCOS oxide film, the LOCOS oxide film formed in a periphery of a drain diffusion layer, in which a high withstanding voltage is required, is etched, and the drain diffusion layer is formed so as to spread into a surface region of a semiconductor substrate located below a region in which the LOCOS oxide film is thinned. As a result, end portions of the drain diffusion layer are covered by an offset diffusion layer, whereby electric field concentration occurring in a region of a lower portion of the drain diffusion layer can be relaxed. | 02-04-2010 |
| 20100025765 | DUAL GATE LDMOS DEVICES - An embodiment of an N-channel device has a lightly doped substrate in which adjacent or spaced-apart P and N wells are provided. A lateral isolation wall surrounds at least a portion of the substrate and is spaced apart from the wells. A first gate overlies the P well or the substrate between the wells or partly both. A second gate, spaced apart from the first gate, overlies the N-well. A body contact to the substrate is spaced apart from the isolation wall by a first distance within the space charge region of the substrate to isolation wall PN junction. When the body contact is connected to the second gate, a predetermined static bias Vg | 02-04-2010 |
| 20100032758 | LDMOS DEVICE FOR ESD PROTECTION CIRCUIT - A LDMOS device for an ESD protection circuit is provided. The LDMOS device includes a substrate of a first conductivity type, a deep well region of a second conductivity type, a body region of the first conductivity type, first and second doped regions of the second conductivity type, and a gate electrode. The deep well region is disposed in the substrate. The body region and the first doped region are respectively disposed in the deep well region. The second doped region is disposed in the body region. The gate electrode is disposed on the deep well region between the first and second doped regions. It is noted that the body region does not include a doped region of the first conductivity type having a different doped concentration from the body region. | 02-11-2010 |
| 20100059819 | POWER TRANSISTOR WITH METAL SOURCE AND METHOD OF MANUFACTURE - A metal source power transistor device and method of manufacture is provided, wherein the metal source power transistor having a source which is comprised of metal and which forms a Schottky barrier with the body region and channel region of the transistor. The metal source power transistor is unconditionally immune from parasitic bipolar action and, therefore, the effects of snap-back and latch-up, without the need for a body contact. The ability to allow the body to float in the metal source power transistor reduces the process complexity and allows for more compact device layout. | 03-11-2010 |
| 20100065909 | Semiconductor device and method for making the same - To provide a semiconductor device and a method of making the same, the device being capable of preventing decrease in the withstanding voltage along the direction perpendicular to the source-drain direction and thereby improving the resistance to an overvoltage (overcurrent), the device includes: a p-type semiconductor substrate | 03-18-2010 |
| 20100084708 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first conductivity-type deep well formed in a substrate, a plurality of device isolation layers formed in the substrate in which the first conductivity-type deep well is formed, a second conductivity-type well formed on a portion of the first conductivity-type deep well between two of the device isolation layers, a first gate pattern formed over a portion of the second conductivity-type well, a second gate pattern formed over one of the device isolation layers, a source region formed in an upper surface of the second conductivity-type well to adjoin a first side of the first gate pattern, a first drain region formed to include the interface between an upper surface of the second conductivity-type well adjoining a second side of the first gate pattern and an upper surface of the first conductivity-type deep well adjoining the second side of the first gate pattern, and a second drain region formed in an upper surface of the first conductivity-type deep well to be spaced from the second conductivity-type well. | 04-08-2010 |
| 20100096697 | HIGH VOLTAGE DEVICE HAVING REDUCED ON-STATE RESISTANCE - A semiconductor device includes a semiconductor substrate, a source region and a drain region formed in the substrate, a gate structure formed on the substrate disposed between the source and drain regions, and a first isolation structure formed in the substrate between the gate structure and the drain region, the first isolation structure including projections that are located proximate to an edge of the drain region. Each projection includes a width measured in a first direction along the edge of the drain region and a length measured in a second direction perpendicular to the first direction, and adjacent projections are spaced a distance from each other. | 04-22-2010 |
| 20100102388 | LDMOS Transistor Having Elevated Field Oxide Bumps And Method Of Making Same - A low Rdson LDMOS transistor having a shallow field oxide region that separates a gate electrode of the transistor from a drain diffusion region of the transistor. The shallow field oxide region is formed separate from the field isolation regions (e.g., STI regions) used to isolate circuit elements on the substrate. Fabrication of the shallow field oxide region is controlled such that this region extends below the upper surface of the semiconductor substrate to a depth that is much shallower than the depth of field isolation regions. For example, the shallow field oxide region may extend below the upper surface of the substrate by only Angstroms or less. As a result, the current path through the resulting LDMOS transistor is substantially unimpeded by the shallow field oxide region, resulting in a low on-resistance. | 04-29-2010 |
| 20100123196 | LDMOS Transistor and Method for Manufacturing the Same - A LDMOS transistor and a method for manufacturing the same are disclosed. A lateral double diffused metal oxide semiconductor (LDMOS) transistor includes a first dielectric layer formed on a top surface of a substrate; a plurality of second dielectric layers on a top surface of the first dielectric layer; a plurality of contact plugs spaced apart by a predetermined distance in an active region of the substrate, passing through the first and second dielectric layers; and a bridge metal line formed in the second dielectric layers, inter-connecting the contact plugs in a horizontal direction. The bridge metal line formed to inter-connect the contact plugs allows for more current to flow in the presently disclosed LDMOS transistor than in a conventional LDMOS transistor of identical size. | 05-20-2010 |
| 20100140700 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing a semiconductor device. A semiconductor device may include a substrate and a laterally diffused metal oxide semiconductor (LDMOS) device. A semiconductor device may include a second conductive type well formed on and/or over a substrate. An LDMOS device may include a drain disposed on and/or over a substrate. An LDMOS device may include a field oxide at one side of a drain, a first conductive type impurity layer on and/or over a substrate, under a field oxide, and/or a second conductive type impurity layer between a first conductive type impurity layer and a field oxide. | 06-10-2010 |
| 20100140701 | Semiconductor Device and Method of Manufacturing the Same - A semiconductor device and a method of manufacturing the same are disclosed. The method includes forming ion impurity regions of a first conductivity type by forming a trench in a semiconductor substrate and implanting impurity ions into a lower portion of the trench at different depths; forming an oxide region in the substrate adjacent to one end of the trench; forming a device isolation film filling the trench; forming a high voltage well in the substrate and a second conductivity type body in the high voltage well; forming a gate on the semiconductor substrate partially overlapping the device isolation film; forming second well in the semiconductor substrate at one side of the device isolation film overlapping the ion diffusion regions and the oxide region; and forming source regions in the body and a drain region in the second well. | 06-10-2010 |
| 20100140702 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and a method of manufacturing a semiconductor device. A semiconductor device may include an epitaxial layer over a semiconductor substrate, a first well region over a epitaxial layer, a first isolation layer and/or a third isolation layer at opposite sides of said first well region and/or a second isolation layer over a first well region between first and third isolation layers. A semiconductor device may include a gate over a second isolation layer. A semiconductor device may include a second well region over a first well region between a third isolation layer and a gate, a first ion-implanted region over a second well region between a third isolation layer and a gate, and/or a second ion-implanted region between a first ion-implanted region and a gate. A semiconductor device may include an accumulation channel between a second well region and a gate. | 06-10-2010 |
| 20100140703 | Semiconductor Device and Method for Manufacturing the Same - A semiconductor device and a method for manufacturing the same are disclosed. The semiconductor device includes a substrate having a first conductor-type, a buried layer of a second conductor-type on the substrate, a drain, and a first guard-ring on one side of the drain, a second guard-ring on one side of the first guard-ring, and a third guard-ring on one side of the second guard-ring. | 06-10-2010 |
| 20100140704 | Lateral Double Diffused Metal Oxide Semiconductor Device And Method of Making The Same - An LDMOS device and method for making the same are disclosed. The LDMOS device comprises a first well, a second well, a third well, a first ion implantation region, and a second ion implantation region. The first well is in a semiconductor substrate. The second well is in the first well. The third well is first well adjacent to the second well. The first ion implantation region is in the second well. The second ion implantation region is in the third well. A device isolation layer structure between a P-type well region and a P-type body of the LDMOS device may be eliminated, thereby preventing a reduction in the doping concentration of the P-type well, thus minimizing leakage current and maintaining a high breakdown voltage. | 06-10-2010 |
| 20100148256 | LATERAL DIFFUSED METAL OXIDE SEMICONDUCTOR (LDMOS) DEVICES WITH ELECTROSTATIC DISCHARGE (ESD) PROTECTION CAPABILITY IN INTEGRATED CIRCUIT - Lateral diffused metal oxide semiconductor (LDMOS) devices with electrostatic discharge (ESD) protection capability are presented for integrated circuits. The LDMOS device includes a semiconductor substrate with an epi-layer thereon. Patterned isolations are disposed on the epi-layer, thereby defining a first active region and a second active region. An N-type double diffused drain (NDDD) region is formed in the first active region and a N | 06-17-2010 |
| 20100148257 | MOS-FET Having a Channel Connection, and Method for the Production of a MOS-FET Having a Channel Connection - A MOSFET comprising a substrate of a semiconductor material; source/drain regions, which are arranged at a distance from each other at a surface of the substrate; a gate electrode arranged above an area of the surface of the substrate between the source/drain regions, the gate electrode being electrically insulated from the semiconductor material; at least one recess in the gate electrode, a through-contact arranged in the recess of the gate electrode, the through-contact being electrically insulated from the gate electrode; a terminal contact on the semiconductor material; and a terminal conductor arranged on the side of the gate electrode that faces away from the substrate, wherein the through-contact electrically connects the terminal contact to the terminal conductor. | 06-17-2010 |
| 20100148258 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate formed therein with a first conductive type well, and an LDMOS device formed on the substrate. The LDMOS device includes a gate electrode, gate oxides formed below the gate electrode, a source region formed in the substrate at one side of the gate electrode, and a drain region formed in the substrate at an opposite side of the gate electrode. The gate oxide includes first and second gate oxides disposed side-by-side and having thicknesses different from each other. | 06-17-2010 |
| 20100163989 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A method for fabrication of a semiconductor device is provided. A first type doped body region is formed in a first type substrate. A first type heavily-doped region is formed in the first type doped body region. A second type well region and second type bar regions are formed in the first type substrate with the second type bar regions between the second type well region and the first type doped body region. The first type doped body region, the second type well region, and each of the second type bar regions are separated from each other by the first type substrate. The second type bar regions are inter-diffused to form a second type continuous region adjoining the second type well region. A second type heavily-doped region is formed in the second type well region. | 07-01-2010 |
| 20100163990 | Lateral Double Diffused Metal Oxide Semiconductor Device - Disclosed is a lateral double diffused metal oxide semiconductor (LDMOS) device and methods of making the same. The LDMOS device may include a semiconductor substrate comprising a buried region and a first well region, a gate on the semiconductor substrate, a body region in the first well region and a source region in the body region on one side of the gate, a drift region and a drain region in the drift region on an opposite side of the gate relative to the body region, a second well region, a first deep sink region and a third well region in the first well region, and a second deep sink region in the first well region. | 07-01-2010 |
| 20100163991 | LATERALLY DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR, AND METHOD FOR FABRICATING THE SAME - A laterally double-diffused metal oxide semiconductor (LDMOS) and a method for fabrication thereof includes a well region formed in a semiconductor substrate having an active region defined by device isolation layers, a body region formed over the well region, a drain region spaced from the body region at a constant interval and formed above the well region, a source region and a source contact region formed in the body region in structural communication with the source region, a drift region having a trench formed therein formed in the well region between the body region and the drain region, and a gate formed over the semiconductor substrate which partially overlaps the source region and the drift region. | 07-01-2010 |
| 20100163992 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a high voltage first conduction type well in a semiconductor substrate, a second conduction type body in the high voltage first conduction type well, a source region in the second conduction type body, a trench in the high voltage first conduction type well, a first isolation oxide, an impurity doped polysilicon film, and a second isolation oxide stacked in the trench in succession, a drain region in the high voltage first conduction type well on one side of the trench, and a polygate on and/or over the high voltage first conduction type well. | 07-01-2010 |
| 20100171175 | Structure For High Voltage/High Current MOS Circuits - A semiconductor structure for high voltage/high current MOS circuits is provided, including a deep N-well (NMD), a P-well (PW) disposed within NWD, a plurality of field oxide regions (FOX), a plurality of doping regions, including both N+ regions and P+ regions, disposed within NWD and PW, a gate (G) connected to a doping region, a bulk pad (B) connected to a doping regions, a source pad (S) connected to a doping regions and a drain pad (D) connected to a doping region. The top view of the present invention shows that the regions are of non-specific shapes and overlaid in a radial manner, with doping region connected to B being encompassed by doping region connected to S, which in turn encompassed by G, encompassed by FOX, encompassed by doping region connected to D. As long as the regions are overlaid in a manner that one region surrounds another region so that the electric current flows from S towards D in a radiating manner, the geometry and the layout of the semiconductor structure of the present invention can be varied. | 07-08-2010 |
| 20100207207 | SEMICONDUCTOR STRUCTURE - The invention provides a semiconductor structure. A first type body doped region is deposited on a first type substrate. A first type heavily-doped region having a finger portion with an enlarged end region is deposited on the first type body doped region. A second type well region is deposited on the first type substrate. A second type heavily-doped region is deposited on the second type well region. An isolation structure is deposited between the first type heavily-doped region and the second type heavily-doped region. A gate structure is deposited on the first type substrate between the first type heavily-doped region and the isolation structure. | 08-19-2010 |
| 20100237416 | BOTTOM-DRAIN LDMOS POWER MOSFET STRUCTURE HAVING A TOP DRAIN STRAP - Lateral DMOS devices having improved drain contact structures and methods for making the devices are disclosed. A semiconductor device comprises a semiconductor substrate; an epitaxial layer on top of the substrate; a drift region at a top surface of the epitaxial layer; a source region at a top surface of the epitaxial layer; a channel region between the source and drift regions; a gate positioned over a gate dielectric on top of the channel region; and a drain contact trench that electrically connects the drift layer and substrate. The contact trench includes a trench formed vertically from the drift region, through the epitaxial layer to the substrate and filled with an electrically conductive drain plug; electrically insulating spacers along sidewalls of the trench; and an electrically conductive drain strap on top of the drain contact trench that electrically connects the drain contact trench to the drift region. | 09-23-2010 |
| 20100270615 | METHOD FOR INCREASING BREAKING DOWN VOLTAGE OF LATERAL DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTOR - A lateral diffused metal oxide semiconductor transistor is disclosed. A p-type bulk is disposed on a substrate. An n-type well region is disposed in the p-type bulk. A plurality of field oxide layers are disposed on the p-type bulk and the n-type well region. A gate structure is disposed on a portion of the p-type bulk and one of the plurality of field oxide layers. At least one deep trench isolation structure is disposed in the p-type bulk and adjacent to the n-type well region. | 10-28-2010 |
| 20100270616 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - There is provided a semiconductor device in which the degradation of electric characteristics can be inhibited. A semiconductor substrate has a main surface, and a trench in the main surface. A buried insulating film is buried in the trench. The trench has one wall surface and the other wall surface which oppose each other. A gate electrode layer is located over at least the buried insulating film. The trench has angular portions which are located between the main surface of at least either one of the one wall surface and the other wall and a bottom portion of the trench. | 10-28-2010 |
| 20100289078 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In order to further improve a driving performance without increasing an element area in a lateral MOS having a high driving performance, in which a gate width is increased per unit area by forming a plurality of trenches horizontally with respect to a gate length direction, the semiconductor device includes: a well region which is formed of a high resistance first conductivity type semiconductor at a predetermined depth from a surface of a semiconductor substrate; a plurality of trenches which extend from a surface to a midway depth in the well region; a gate insulating film which is formed on surfaces of concave and convex portions formed by the trenches; a gate electrode embedded inside the trenches; a gate electrode film which is formed on the surface of the substrate in contact with the gate electrode embedded inside the trenches in regions of the concave and convex portions, the regions excluding vicinities of both ends of the trenches; another gate electrode film which is embedded inside the trenches in the vicinities of the both ends of the trenches in contact with the gate electrode film so that a surface of the another gate electrode film is located at a position deeper than the surface of the semiconductor substrate; and a source region and a drain region which are formed as two low resistance second conductivity type semiconductor layers formed from a part of the semiconductor surface, the part being out of contact with the another gate electrode film, so as to be shallower than the depth of the well region. | 11-18-2010 |
| 20100295126 | High dielectric constant gate oxides for a laterally diffused metal oxide semiconductor (LDMOS) - An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes a first heavily doped region to represent a source region. A second heavily doped region represents a drain region of the semiconductor device. A metal region represents a gate region of the semiconductor device. The semiconductor device includes a gate oxide positioned between the source region and the drain region, below the gate region. The semiconductor device uses a high dielectric constant (high-κ dielectric) material. | 11-25-2010 |
| 20100301413 | Fabrication of lateral double-diffused metal oxide semiconductor (LDMOS) devices - Methods of making, structures, devices, and/or applications for lateral double-diffused metal oxide semiconductor (LDMOS) transistors are disclosed. In one embodiment, a method of fabricating an LDMOS transistor with source, drain, and gate regions on a substrate, can include: forming p-type and n-type buried layer (PBL, NBL) regions; growing an epitaxial (N-EPI) layer on the NBL/PBL regions; forming a p-doped deep p-well (DPW) region on the PBL region; forming a well region in the N-EPI layer; forming a doped body region; after the doped body region formation, forming an active area and a field oxide (FOX) region, and forming a drain oxide between the source and drain regions of the LDMOS transistor; after the doped body region formation, forming a gate oxide adjacent to the source and drain regions, and forming a gate on the gate oxide and a portion of the drain oxide; and forming a doped drain region, and first and second doped source regions. | 12-02-2010 |
| 20100301414 | HIGH VOLTAGE NMOS WITH LOW ON RESISTANCE AND ASSOCIATED METHODS OF MAKING - High voltage NMOS devices with low on resistance and associated methods of making are disclosed herein. In one embodiment, a method for making N typed MOSFET devices includes forming an N-well and a P-well with twin well process, forming field oxide, forming gate comprising an oxide layer and a conducting layer, forming a P-base in the P-well, the P-base being self-aligned to the gate, side diffusing the P-base to contact the N-well, and forming N+ source pickup region and N+ drain pickup region. | 12-02-2010 |
| 20110012196 | Isolated drain-centric lateral MOSFET - A lateral MOSFET formed in a substrate of a first conductivity type includes a gate formed atop a gate dielectric layer over a surface of the substrate, a drain region of a second conductivity type, a source region of a second conductivity type, and a body region of the first conductivity type which extends under the gate. The body region may have a non-monotonic vertical doping profile with a portion located deeper in the substrate having a higher doping concentration than a portion located shallower in the substrate. The lateral MOSFET is drain-centric, with the source region and a dielectric-filled trench surrounding the drain region. | 01-20-2011 |
| 20110024839 | Lateral DMOS Field Effect Transistor with Reduced Threshold Voltage and Self-Aligned Drift Region - A method of forming a lateral DMOS transistor includes performing a low energy implantation using a first dopant type and being applied to the entire device area. The dopants of the low energy implantation are blocked by the conductive gate. The method further includes performing a high energy implantation using a third dopant type and being applied to the entire device area. The dopants of the high energy implantation penetrate the conductive gate and is introduced into the entire device active area including underneath the conductive gate. After annealing, a double-diffused lightly doped drain (DLDD) region is formed from the high and low energy implantations and is used as a drift region of the lateral DMOS transistor. The DLDD region overlaps with the body region at a channel region and interacts with the dopants of the body region to adjust a threshold voltage of the lateral DMOS transistor. | 02-03-2011 |
| 20110042743 | LDMOS Using A Combination of Enhanced Dielectric Stress Layer and Dummy Gates - First example embodiments comprise forming a stress layer over a MOS transistor (such as a LDMOS Tx) comprised of a channel and first, second and third junction regions. The stress layer creates a stress in the channel and the second junction region of the Tx. Second example embodiments comprise forming a MOS FET and at least a dummy gate over a substrate. The MOS is comprised of a gate, channel, source, drain and offset drain. At least one dummy gate is over the offset drain. A stress layer is formed over the MOS and the dummy gate. The stress layer and the dummy gate improve the stress in the channel and offset drain region | 02-24-2011 |
| 20110049623 | Short Channel Lateral MOSFET and Method - A short channel Lateral MOSFET (LMOS) and method are disclosed with interpenetrating drain-body protrusions (IDBP) for reducing channel-on resistance while maintaining high punch-through voltage. The LMOS includes lower device bulk layer; upper source and upper drain region both located atop lower device bulk layer; both upper source and upper drain region are in contact with an intervening upper body region atop lower device bulk layer; both upper drain and upper body region are shaped to form a drain-body interface; the drain-body interface has an IDBP structure with a surface drain protrusion lying atop a buried body protrusion while revealing a top body surface area of the upper body region; gate oxide-gate electrode bi-layer disposed atop the upper body region forming an LMOS with a short channel length defined by the horizontal length of the top body surface area delineated between the upper source region and the upper drain region. | 03-03-2011 |
| 20110073945 | PROCESS FOR MANUFACTURING AN INTEGRATED DEVICE WITH "DAMASCENE" FIELD INSULATION, AND INTEGRATED DEVICE MADE BY SUCH PROCESS - An integrated device includes a semiconductor body, in which an STI insulation structure is formed, which delimits laterally first active areas and at least one second active area, respectively, in a low-voltage region and in a power region of the semiconductor body. The integrated device moreover includes low-voltage CMOS components, accommodated in the first active areas, and a power component in the second active area. The power component has a source region, a body region, a drain-contact region, and at least one field-insulating region, set between the body region and the drain-contact region. The field-insulating region is provided entirely on the semiconductor body. | 03-31-2011 |
| 20110079849 | LATERAL-DIFFUSION METAL-OXIDE-SEMICONDUCTOR DEVICE - A lateral-diffusion metal-oxide-semiconductor device includes a source in a racetrack shaped active area, a first field oxide region isolating and surrounding the racetrack shaped active area, a racetrack shaped gate surrounding the source, and a drain disposed at one side of the gate opposite to the source. The source includes a P+ doping region in a P well and an N+ doping region butting on the P+ doping region. | 04-07-2011 |
| 20110089492 | High voltage semiconductor device with JFET regions containing dielectrically isolated junctions and method of fabricating the same - A high-voltage field-effect device contains an extended drain or “drift” region including an embedded stack of JFET regions separated by intervening layers of the drift region. Each of the JFET regions is filled with material of an opposite conductivity type to that of the drift region, and the floor and ceiling of each JFET region is lined with an oxide layer. When the device is blocking a voltage in the off condition, the semiconductor material inside the JFET regions and in the drift region that separates the JFET regions is depleted. This improves the voltage-blocking ability of the device while conserving chip area. The oxide layer prevents dopant from the JFET regions from diffusing into the drift region. | 04-21-2011 |
| 20110108916 | Semiconductor Devices and Methods - Disclosed herein are Lateral Diffused Metal Oxide Semiconductor (LDMOS) device and trench isolation related devices, methods, and techniques. | 05-12-2011 |
| 20110115020 | SEMICONDUCTOR DEVICE - A semiconductor device includes a second conductive-type deep well configured above a substrate. The deep well includes an ion implantation region and a diffusion region. A first conductive-type first well is formed in the diffusion region. A gate electrode extends over portions of the ion implantation region and of the diffusion region, and partially overlaps the first well. The ion implantation region has a uniform impurity concentration whereas the impurity concentration of the diffusion region varies from being the highest concentration at the boundary interface between the ion implantation region and the diffusion region to being the lowest at the portion of the diffusion region that is the farthest away from the boundary interface. | 05-19-2011 |
| 20110133279 | SEMICONDUCTOR DEVICE - The semiconductor device includes: a first conductive-type first well and a second conductive-type second well configured over a substrate to contact each other; a second conductive-type anti-diffusion region configured in an interface where the first conductive-type first well contacts the second conductive-type second well over the substrate; and a gate electrode configured to simultaneously cross the first conductive-type first well, the second conductive-type anti-diffusion region, and the second conductive-type second well over the substrate. | 06-09-2011 |
| 20110193161 | METHOD AND APPARATUS OF FORMING A GATE - The present disclosure provides a semiconductor device having a transistor. The transistor includes a substrate and first and second wells that are disposed within the substrate. The first and second wells are doped with different types of dopants. The transistor includes a first gate that is disposed at least partially over the first well. The transistor further includes a second gate that is disposed over the second well. The transistor also includes source and drain regions. The source and drain regions are disposed in the first and second wells, respectively. The source and drain regions are doped with dopants of a same type. | 08-11-2011 |
| 20110193162 | LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTOR WITH PARTIALLY UNSILICIDED SOURCE/DRAIN - A method of fabricating a laterally diffused metal oxide semiconductor (LDMOS) transistor includes forming a dummy gate over a substrate. A source and a drain are formed over the substrate on opposite sides of the dummy gate. A first silicide is formed on the source. A second silicide is formed on the drain so that an unsilicided region of at least one of the drain or the source is adjacent to the dummy gate. The unsilicided region of the drain provides a resistive region capable of sustaining a voltage load suitable for a high voltage LDMOS application. A replacement gate process is performed on the dummy gate to form a gate. | 08-11-2011 |
| 20110233673 | LATERAL-DIFFUSION METAL-OXIDE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a lateral-diffusion metal-oxide semiconductor (LDMOS) device is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a first region and a second region both having a first conductive type in the semiconductor substrate, wherein the first region not contacting the second region; and performing a thermal process to diffuse the dopants within the first region and the second region into the semiconductor substrate to form a deep well, wherein the doping concentration of the deep well is less than the doping concentration of the first region and the second region. | 09-29-2011 |
| 20110241112 | LDMOS Device with P-Body for Reduced Capacitance - A transistor includes an n-well implanted in a substrate, a source region including a p-body region, a n+ region and a p+ region in the p-body region, a drain region comprising a n+ region, and a gate between the source region and the drain region. The p-body region includes a first implant region having a first depth, a first lateral spread and a first concentration of a p-type impurity, and a second implant region having a second depth, a second lateral spread and a second concentration of the p-type impurity. The second depth is less than the first depth, the second lateral spread is greater than the first lateral spread and the second concentration is greater than the first concentration. The p+ region and n+ region abut the second implant region. | 10-06-2011 |
| 20110241113 | Dual Gate LDMOS Device with Reduced Capacitance - A transistor includes an n-well implanted in a substrate, a source region including a p-body region in the n-well, and a n+ region and a p+ region in the p-body region, a drain region including a n+ region, and a dual gate between the source region and the drain region. The dual gate includes a first gate on a side closer to the source region and a second gate on a side closer to the drain region, the first gate separated from the second gate by a pre-determined distance sufficient that a capacitance between the gate and the drain is at least 15% lower than a capacitance of a transistor of the same unit cell size and configuration excepting that the first gate and second gate abut. | 10-06-2011 |
| 20110241114 | HIGH VOLTAGE MOS TRANSISTOR - A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS) and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. One portion of the second well surrounds the source and the other portion of the second well extends laterally from the first portion in the first well. | 10-06-2011 |
| 20110260247 | LDMOS TRANSISTORS WITH A SPLIT GATE - A transistor including a source region, drain region, channel region, drift region, isolation region, a first gate structure over the channel region, and a second gate structure over the isolation region is provided. The drift region includes a first portion located under the isolation region and a second portion located laterally adjacent to the isolation region. The first gate structure is separated by a first separation space from the second gate structure. The first separation space is located over a portion of the second portion of the drift region and a portion of the isolation region. | 10-27-2011 |
| 20110266620 | TRANSISTOR STRUCTURE WITH FEED-THROUGH SOURCE-TO-SUBSTRATE CONTACT - An LDMOS (laterally diffused metal oxide semiconductor) structure connects the source to a substrate and also the gate shield while utilizing a reduced area for such contacts. The structure includes an electrically conductive substrate layer, a source, and a drain contact; the drain contact is separated from the substrate layer by at least one intervening layer. An electrically conductive trench-like feed-through element passes through the intervening layer and contacts the substrate and the source to electrically connect the drain contact and the substrate layer. | 11-03-2011 |
| 20110284958 | Semiconductor Component - A semiconductor component may include a semiconductor layer which has a front side and a back side, a first terminal electrode on the front side, a second terminal electrode on the back side, a first dopant region of a first conduction type on the front side, which is electrically connected to one of the terminal electrodes, a second dopant region of a second conduction type in the semiconductor layer, which is electrically connected to the other terminal electrode, a pn junction being formed between the first and second dopant regions, a dielectric layer on the back side between the semiconductor layer and the second terminal electrode, and the dielectric layer having an opening through which an electrical connection between the second terminal electrode and the first or second dopant region is passed. | 11-24-2011 |
| 20110309443 | METHOD FOR CONTROLLING IMPURITY DENSITY DISTRIBUTION IN SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MADE THEREBY - The present invention discloses a method for controlling the impurity density distribution in semiconductor device and a semiconductor device made thereby. The control method includes the steps of: providing a substrate; defining a doped area which includes at least one first region; partially masking the first region by a mask pattern; and doping impurities in the doped area to form one integrated doped region in the first region, whereby the impurity concentration of the first region is lower than a case where the first region is not masked by the mask pattern. | 12-22-2011 |
| 20120032262 | ENHANCED HVPMOS - A p-channel LDMOS device with a controlled n-type buried layer (NBL) is disclosed. A Shallow Trench Isolation (STI) oxidation is defined, partially or totally covering the drift region length. The NBL layer, which can be defined with the p-well mask, connects to the n-well diffusion, thus providing an evacuation path for electrons generated by impact ionization. High immunity to the Kirk effect is also achieved, resulting in a significantly improved safe-operating-area (SOA). The addition of the NBL deep inside the drift region supports a space-charge depletion region which increases the RESURF effectiveness, thus improving BV. An optimum NBL implanted dose can be set to ensure fully compensated charge balance among n and p doping in the drift region (charge balance conditions). The p-well implanted dose can be further increased to maintain a charge balance, which leads to an Rdson reduction. | 02-09-2012 |
| 20120037988 | RESURF DEVICE INCLUDING INCREASED BREAKDOWN VOLTAGE - A semiconductor device can include a source region near a working top surface of a semiconductor region. The device can also include a gate located above the working top surface and located laterally between the source and a drain region. The source region and the gate can at least partially laterally overlap a body region near the working top surface. The source region can include a first portion having the first conductivity type, a second portion having a second conductivity type, and a third portion having the second conductivity type. The second portion can be located laterally between the first and third portions and can penetrate into the semiconductor region to a greater depth than the third portion but no more than the first portion. The lateral location of the third portion can be determined at least in part using the lateral location of the gate. | 02-16-2012 |
| 20120037989 | LDMOS HAVING SINGLE-STRIP SOURCE CONTACT AND METHOD FOR MANUFACTURING SAME - LDMOS devices having a single-strip contact pad in the source region, and related methods of manufacturing are disclosed. The LDMOS may comprise a first well lightly doped with a first dopant and formed into a portion of a substrate, the first well having a drain region at its surface heavily doped with the first dopant, and a second well lightly doped with a second dopant formed in another portion of the substrate, the second well having a source region at its surface comprising first portions heavily doped with the first dopant directly adjacent second portions heavily doped with the second dopant. Also, the LDMOS device may comprise a field oxide at the upper surface of the substrate between the source and drain regions, and contacting the first well but separated from the second well, and a gate formed partially over the field oxide and partially over the source region. The LDMOS may also comprise contact pads in contact with the gate, and source and drain regions, wherein the contact pad in contact with the source regions comprises a single-strip of conductive material extending across the source region. | 02-16-2012 |
| 20120061758 | SEMICONDUCTOR DEVICE AND RELATED MANUFACTURING METHOD - A semiconductor device and a related fabrication process are presented here. The device includes a support substrate, a buried oxide layer overlying the support substrate, a first semiconductor region located above the buried oxide layer and having a first conductivity type. The device also includes second, third, fourth, and fifth semiconductor regions. The second semiconductor region is located above the first semiconductor region, and it has a second conductivity type. The third semiconductor region is located above the second semiconductor region, and it has the first conductivity type. The fourth semiconductor region is located above the third semiconductor region, and it has the second conductivity type. The fifth semiconductor region extends through the fourth semiconductor region and the third semiconductor region to the second semiconductor region, and it has the second conductivity type. | 03-15-2012 |
| 20120091527 | LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR (LDMOS) TRANSISTORS - Methods of making, structures, devices, and/or applications for lateral double-diffused metal oxide semiconductor (LDMOS) transistors are disclosed. In one embodiment, an LDMOS transistor can include: (i) an n-doped deep n-well (DNW) region on a substrate; (ii) a gate oxide and a drain oxide between a source region and a drain region of the LDMOS transistor, the gate oxide being adjacent to the source region, the drain oxide being adjacent to the drain region; (iii) a conductive gate over the gate oxide and a portion of the drain oxide; (iv) a p-doped p-body region in the source region; (v) an n-doped drain region in the drain region; (vi) a first n-doped n+ region and a p-doped p+ region adjacent thereto in the p-doped p-body region of the source region; and (vii) a second n-doped n+ region in the drain region. | 04-19-2012 |
| 20120098065 | LOW RESISTANCE LDMOS WITH REDUCED GATE CHARGE - An integrated circuit containing an MOS transistor with a drain drift region adjacent to the channel region, a field oxide element in the drain region, a first gate section over the channel region and a second gate section over the field oxide element, with a gap between the gate sections so that at least half of the drift region is not covered by gate. A process of forming an integrated circuit containing an MOS transistor with a drain drift region adjacent to the channel region, a field oxide element in the drain region, a first gate section over the channel region and a second gate section over the field oxide element, with a gap between the gate sections so that at least half of the drift region is not covered by gate, so that the source/drain implant is blocked from the drift region below the gap. | 04-26-2012 |
| 20120104494 | SEMICONDUCTOR DEVICE - A field-effect transistor ( | 05-03-2012 |
| 20120126323 | SEMICONDUCTOR DEVICE HAVING A SPLIT GATE AND A SUPER-JUNCTION STRUCTURE - A semiconductor device comprises a source region, a drain region, and a drift region between the source and drain regions. A split gate is disposed over a portion of the drift region, and between the source and drain regions. The split gate includes first and second gate electrodes separated by a gate oxide layer. A super-junction structure is disposed within the drift region between the gate and the drain region. | 05-24-2012 |
| 20120126324 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The invention provides an LDMOS transistor of which the time-dependent degrading of the performance due to the trapping of hot electrons in the gate insulation film is decreased. A body layer is disposed in a surface portion of an N− type semiconductor layer. A source layer including an N− type layer is disposed in a surface portion of the body layer. An N− type drift layer is formed in a surface portion of the N− type semiconductor layer. This drift layer includes a first region having a first N type impurity concentration peak region and a second region having a second N type impurity concentration peak region that is positioned deeper than the first N type impurity concentration peak region, the second region adjoining this first region. An N+ type drain layer is formed in a surface portion of the second region. | 05-24-2012 |
| 20120153391 | MODULAR LOW STRESS PACKAGE TECHNOLOGY - A semiconductor subassembly, a modular sidewall element having modular dimensions that accommodates placement of the semiconductor subassembly in a modular layout and a semiconductor substrate base element coupled to the modular sidewall element. The semiconductor substrate base element has at least one semiconductor element with a layout sized to be accommodated by modular dimensions of the modular sidewall element and the semiconductor substrate base element configured to form a base of the semiconductor subassembly. | 06-21-2012 |
| 20120161233 | Reduction of Parasitic Capacitance in a Semiconductor Device - An apparatus is disclosed to increase a reduced a parasitic capacitance of a semiconductor device. The semiconductor device includes a modified gate region to effectively reduce an overlap capacitance and modified well regions to effectively reduce a junction capacitance. The modified gate region includes a doped region and an undoped to decrease an effective area of the overlap capacitance. The modified well regions are separated by a substantially horizontal distance to increase an effective distance of the junction capacitance. This decrease in the effective area of the overlap capacitance and this increase in the effective distance of the junction capacitance reduces the parasitic capacitance of the semiconductor device. | 06-28-2012 |
| 20120187485 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - According to an embodiment of the invention, a semiconductor device includes a substrate, a second conductive type source region formed in the substrate, a second conductive type drain region formed in the substrate, a first conductive type channel region formed in the substrate, a second conductive type drift region formed between the first conductive type channel region and the second conductive type drain region, an insulator film buried on a surface of the second conductive type drift region, and a gate electrode including an opening between the first conductive type channel region and the insulator film and covering a surface of the substrate from the first conductive type channel region to part of the insulator film via a gate insulator. The second conductive type drift region includes a second portion of the second conductive type drift region formed in the substrate below the opening. | 07-26-2012 |
| 20120193711 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A gate electrode, an element isolation film and a drain region in an LDMOS transistor formation region and a gate electrode, an element isolation film and an anode region in an ESD protection element formation region are formed to satisfy relationships of A | 08-02-2012 |
| 20120199904 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A field drain insulating part has a first insulating film and a high dielectric constant insulating film. The first insulating film is positioned at least in the center of the field drain insulating part in a plan view. The high dielectric constant insulating film is positioned at a part close to a drain region in the edge of the bottom surface of the field drain insulating part, and has a higher dielectric constant than the first insulating film. The high dielectric constant insulating film is not positioned in the center of the field drain insulating part in a plan view. | 08-09-2012 |
| 20120199905 | SEMICONDUCTOR DEVICE - A semiconductor device with improved characteristics is provided. The semiconductor device includes a LDMOS, a source plug electrically coupled to a source region of the LDMOS, a source wiring disposed over the source plug, a drain plug electrically coupled to a drain region of the LDMOS, and a drain wiring disposed over the drain plug. The structure of the source plug of the semiconductor device is devised. The semiconductor device is structured such that the drain plug is linearly disposed to extend in a direction Y, and the source plug includes a plurality of separated source plugs arranged at predetermined intervals in the direction Y. In this way, the separation of the source plug decreases an opposed area between the source plug and the drain plug, and can thus decrease the parasitic capacitance therebetween. | 08-09-2012 |
| 20120211834 | MULTI-LEVEL LATERAL FLOATING COUPLED CAPACITOR TRANSISTOR STRUCTURES - A semiconductor device includes an active region having a first floating charge control structure and a termination region having a second floating charge control structure. The second floating charge control structure is at least twice as long as the first floating control structure. | 08-23-2012 |
| 20120273885 | High-Voltage Transistor Structure with Reduced Gate Capacitance - In one embodiment, a high voltage field-effect transistor (HVFET) includes a field oxide layer that covers a first well region, the field oxide layer having a first thickness and extending in a second lateral direction from a drain region to near a second well region. A gate oxide covers a channel region and has a second dimension in a first lateral direction. A gate extends in the second lateral direction from the source region to over a portion of the field oxide layer, the gate being insulated from the channel region by the gate oxide, the gate extending in the first lateral dimension over an inactive area of the HVFET beyond the second dimension of the gate oxide, the gate being insulated from the first and second well regions over the inactive area by the field oxide layer. | 11-01-2012 |
| 20120280321 | SEMICONDUCTOR DEVICE - A field-effect transistor ( | 11-08-2012 |
| 20120299096 | HIGH VOLTAGE AND ULTRA-HIGH VOLTAGE SEMICONDUCTOR DEVICES WITH INCREASED BREAKDOWN VOLTAGES - A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages. | 11-29-2012 |
| 20120306014 | STRESS ENHANCED LDMOS TRANSISTOR TO MINIMIZE ON-RESISTANCE AND MAINTAIN HIGH BREAKDOWN VOLTAGE - A lateral diffused metal-oxide-semiconductor field effect transistor (LDMOS transistor) employs a stress layer that enhances carrier mobility (i.e., on-current) while also maintaining a high breakdown voltage for the device. High breakdown voltage is maintained, because an increase in doping concentration of the drift region is minimized. A well region and a drift region are formed in the substrate adjacent to one another. A first shallow trench isolation (STI) region is formed on and adjacent to the well region, and a second STI region is formed on and adjacent to the drift region. A stress layer is deposited over the LDMOS transistor and in the second STI region, which propagates compressive or tensile stress into the drift region, depending on the polarity of the stress layer. A portion of the stress layer can be removed over the gate to change the polarity of stress in the inversion region below the gate. | 12-06-2012 |
| 20120319202 | High Voltage Device and Manufacturing Method Thereof - The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a first conductive type substrate having a device region; a gate, which is located on a surface of the substrate; a second conductive type source and a second conductive type drain in the device region at different sides of the gate respectively; and a second conductive type drift region, which is located in the device region, between the source and the drain. The gate includes: a conductive layer for receiving a gate voltage; and multiple dielectric layers with different thicknesses, located at different horizontal positions. From cross-section view, each dielectric layer is between the conductive layer and the substrate, and the multiple dielectric layers are arranged in an order from thinner to thicker from a side closer to the source to a side closer to the drain. | 12-20-2012 |
| 20130015523 | FABRICATION OF LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR (LDMOS) DEVICES - Methods of making, structures, devices, and/or applications for lateral double-diffused metal oxide semiconductor (LDMOS) transistors are disclosed. In one embodiment, a method of fabricating an LDMOS transistor with source, drain, and gate regions on a substrate, can include: forming p-type and n-type buried layer (PBL, NBL) regions; growing an epitaxial (N-EPI) layer on the NBL/PBL regions; forming a p-doped deep p-well (DPW) region on the PBL region; forming a well region in the N-EPI layer; forming a doped body region; forming an active area and a field oxide (FOX) region, and forming a drain oxide between the source and drain regions of the LDMOS transistor; forming a gate oxide adjacent to the source and drain regions, and forming a gate on the gate oxide and a portion of the drain oxide; and forming a doped drain region, and first and second doped source regions. | 01-17-2013 |
| 20130032881 | Asymmetric Source-Drain Field Effect Transistor and Method of Making - The present invention is related to microelectronic device technologies. A method for making an asymmetric source-drain field-effect transistor is disclosed. A unique asymmetric source-drain field-effect transistor structure is formed by changing ion implantation tilt angles to control the locations of doped regions formed by two ion implantation processes. The asymmetric source-drain field-effect transistor has structurally asymmetric source/drain regions, one of which is formed of a P-N junction while the other one being formed of a mixed junction, the mixed junction being a mixture of a Schottky junction and a P-N junction. | 02-07-2013 |
| 20130056824 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor device and a manufacturing method for the same are provided. The semiconductor device comprises a first doped region, a second doped region, a dielectric structure and a gate structure. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity and is adjacent to the first doped region. The dielectric structure comprises a first dielectric portion and a second dielectric portion separated from each other. The dielectric structure is formed on the first doped region. The gate structure is on a part of the first doped region or second doped region adjacent to the first dielectric portion. | 03-07-2013 |
| 20130062694 | SEMICONDUCTOR DEVICE WITH HIGH-VOLTAGE BREAKDOWN PROTECTION - A semiconductor device includes: a semiconductor substrate having a first conductivity type; a well having a second conductivity type and provided inside the semiconductor substrate; a first impurity region having the first conductivity type and provided within the well; a second impurity region having the second conductivity type, provided inside the well and away from the first impurity region; and a third impurity region having a first conductivity type, provided surrounding the well and away from the second impurity region. In this semiconductor device, the well is formed to be deeper than the first impurity region, the second impurity region, and the third impurity region, in a thickness direction of the semiconductor substrate; and a minimum distance between the first impurity region and the second impurity region is smaller than a minimum distance between the second impurity region and the third impurity region. | 03-14-2013 |
| 20130093016 | LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An LDMOS device may include at least one of a second conduction type buried layer and a first conduction type drain extension region. An LDMOS device may include a second conduction type drain extension region configured to be formed in a portion of the first conduction type drain extension region. The second conduction type drain extension region may include a gate pattern and a drain region. An LDMOS device may include a first conduction type body having surface contact with the second conduction type drain extension region and may include a source region. An LDMOS device may include a first guard ring formed around the second conduction type drain extension region. An LDMOS device may include a second guard ring configured to be formed around the first guard ring and configured to be connected to a different region of the second conduction type buried layer. | 04-18-2013 |
| 20130093017 | LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An LDMOS device includes a second conduction type buried layer, a first conduction type drain extension region configured to be formed on and/or over a region of the second conduction type buried layer, a second conduction type drain extension region configured to be formed in a partial region of the first conduction type drain extension region, a first conduction type body, a first guard ring configured to be formed around the second conduction type drain extension region and configured to include a second conduction type impurity layer, and a second guard ring configured to be formed around the first guard ring and configured to include a high-voltage second conduction type well and a second conduction type impurity layer. Further, the second conduction type impurity layer of the first guard ring and the second conduction type impurity layer of the second guard ring operate as an isolation. | 04-18-2013 |
| 20130119467 | DEVICES, METHODS, AND SYSTEMS WITH MOS-GATED TRENCH-TO-TRENCH LATERAL CURRENT FLOW - A DMOS transistor is fabricated with its source/body/deep body regions formed on the walls of a first set of trenches, and its drain regions formed on the walls of a different set of trenches. A gate region that is formed in a yet another set of trenches can be biased to allow carriers to flow from the source to the drain. Lateral current low from source/body regions on trench walls increases the active channel perimeter to a value well above the amount that would be present if the device was fabricated on just the surface of the wafer. Masking is avoided while open trenches are present. A transistor with a very low on-resistance per unit area is obtained. | 05-16-2013 |
| 20130168769 | P-CHANNEL LDMOS TRANSISTOR AND METHOD OF PRODUCING A P-CHANNEL LDMOS TRANSISTOR - The p-channel LDMOS transistor comprises a semiconductor substrate ( | 07-04-2013 |
| 20130187226 | LATERAL DOUBLE DIFFUSED MOS TRANSISTORS AND METHODS OF FABRICATING THE SAME - A lateral double diffused MOS transistor including substrate of a first conductivity type, drift region of a second conductivity type and body region of the first conductivity type disposed in the substrate, source region of the second conductivity type disposed in the body region, drain region of the second conductivity type disposed in the drift region, isolation layer disposed in the drift region to surround sidewalls of the drain region, gate insulation layer and gate electrode sequentially stacked generally on the body region, first field plate extending from the gate electrode to overlap the drift region and to overlap a portion of the isolation layer, second field plate disposed above the isolation layer spaced apart from the first field plate, and coupling gate disposed above the isolation layer generally between the drain region and the second field plate, wherein the coupling gate is electrically connected to the second field plate. | 07-25-2013 |
| 20130207187 | INSULATED GATE BIPOLAR TRANSISTOR STRUCTURE HAVING LOW SUBSTRATE LEAKAGE - A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate. | 08-15-2013 |
| 20130214355 | HIGH VOLTAGE LDMOS DEVICE - A high voltage lateral double diffused metal-oxide-semiconductor field effect transistor (LDMOS) comprises a substrate; an epitaxy layer on the substrate; a drift region on the epitaxy layer; and a drain region and a source region at two ends. At least one pair of n-type and p-type semiconductor regions is arranged alternately above the interface of the substrate and the epitaxy layer and firmly attached to a lower surface of the drifting region; the n-type and p-type semiconductor regions are firmly closed to each other and arranged to form a lateral PN junction; and the p-type semiconductor region and the drifting region form a vertical PN junction. The n-type and p-type semiconductor regions are also totally called “a reduced surface field (RESURF) layer in body”, and the LDMOS device with a RESURF layer in body effectively solves conflict between raising reverse withstand voltage and reducing forward on-resistance of the current LDMOS devices. | 08-22-2013 |
| 20130221438 | HIGH VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE AND LAYOUT PATTERN THEREOF - A layout pattern of a high voltage metal-oxide-semiconductor transistor device includes a first doped region having a first conductivity type, a second doped region having the first conductivity type, and an non-continuous doped region formed in between the first doped region and the second doped region. The non-continuous doped region includes a plurality of gaps formed therein. The non-continuous doped region further includes a second conductivity type complementary to the first conductivity type. | 08-29-2013 |
| 20130234249 | Methods and Apparatus for LDMOS Transistors - An LDMOS transistor includes a gate including a conductive material over an insulator material, a source including a first impurity region and a second impurity region, a third impurity region, and a drain including a fourth impurity region and a fifth impurity region. The first impurity region is of a first type, and the second impurity region is of an opposite second type. The third impurity region extends from the source region under the gate and is of the first type. The fourth impurity region is of the second type, the fifth impurity region is of the second type, and the fourth impurity region impinges the third impurity region. | 09-12-2013 |
| 20130240990 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor structure and a semiconductor device manufactured using the same are disclosed. In replacement gate process, the present invention is capable of reducing contact resistance at source/drain regions through forming doped amorphous Si layers above source/drain regions, forming contact holes ( | 09-19-2013 |
| 20130256795 | LDMOS WITH ACCUMULATION ENHANCEMENT IMPLANT - A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor device includes an enhancement implant region formed in a portion of an accumulation region proximate a P-N junction between body and drift drain regions. The enhancement implant region contains additional dopants of the same conductivity type as the drift drain region. There is a gap between the enhancement implant region and the P-N junction. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 10-03-2013 |
| 20130264640 | DRAIN EXTENDED MOS TRANSISTOR HAVING SELECTIVELY SILICIDED DRAIN - A method of forming a drain extended metal-oxide-semiconductor (MOS) transistor includes forming a gate structure including a gate electrode on a gate dielectric on a semiconductor surface portion of a substrate. The semiconductor surface portion has a first doping type. A source is formed on one side of the gate structure having a second doping type. A drain is formed including a highly doped portion on another side of the gate structure having the second doping type. A masking layer is formed on a first portion of a surface area of the highly doped drain portion. A second portion of the surface area of the highly doped drain portion does not have the masking layer. Selectively siliciding is used to form silicide on the second portion. The masking layer blocks siliciding on the first portion so that the first portion is silicide-free. | 10-10-2013 |
| 20130277741 | LDMOS DEVICE WITH FIELD EFFECT STRUCTURE TO CONTROL BREAKDOWN VOLTAGE, AND METHODS OF MAKING SUCH A DEVICE - In one embodiment of an LDMOS device disclosed herein, the device includes a source region, a drain region and a gate electrode that are formed in and above a semiconducting substrate, wherein the gate electrode is generally laterally positioned between the source region and the drain region, a metal-1 field plate positioned above the gate electrode, and a silicide block layer that is positioned in an area between the gate electrode and the drain region. The device further includes at least one source contact that is conductively coupled to the metal-1 field plate and a conductive structure that is conductively coupled to the metal-1 field plate, wherein at least a first portion of the conductive structure extends downward toward the substrate in the area between the gate electrode and the drain region. | 10-24-2013 |
| 20130277742 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and extending down from the surface of the substrate, and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug including a first portion and a second portion electrically connected to each other, and the first portion electrically connected to the gate electrode, and the second portion penetrating into the isolation. | 10-24-2013 |
| 20130307070 | Double Diffused Drain Metal Oxide Semiconductor Device and Manufacturing Method Thereof - The present invention discloses a double diffused drain metal oxide semiconductor (DDMOS) device and a manufacturing method thereof. The DDDMOS device is formed in a substrate, and includes: a drift region, a gate, a source, a drain, a dielectric layer, and a conductive layer. The drift region includes a first region and a second region. The gate is formed on the substrate, and overlaps the first region from top view. The source and drain are formed at both sides of the gate respectively, and the drain is located in the second region. The drain and the gate are separated by a portion of the second region from top view. The dielectric layer is formed by dielectric material on the gate and the second region. The conductive layer is formed by conductive material on the dielectric layer, and overlaps at least part of the second region from top view. | 11-21-2013 |
| 20130307071 | HIGH VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE AND LAYOUT PATTERN THEREOF - A layout pattern of a high voltage metal-oxide-semiconductor transistor device includes a first doped region having a first conductivity type, a second doped region having the first conductivity type, and an non-continuous doped region formed in between the first doped region and the second doped region. The non-continuous doped region further includes a plurality of third doped regions, a plurality of gaps, and a plurality of fourth doped regions. The gaps and the third doped regions s are alternately arranged, and the fourth doped regions are formed in the gaps. The third doped regions include a second conductivity type complementary to the first conductivity type, and the fourth doped regions include the first conductivity type. | 11-21-2013 |
| 20130307072 | Double Diffused Metal Oxide Semiconductor Device and Manufacturing Method Thereof - The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device is formed in a first conductive type substrate, and includes a second conductive type high voltage well, a field oxide region, a gate, a second conductive type source, a second conductive type drain, a first conductive type body region, and a first conductive type deep well. The deep well is formed beneath and adjacent to the high voltage well in a vertical direction. The deep well and the high voltage well are defined by a same lithography process step. | 11-21-2013 |
| 20130341719 | Hybrid High Voltage Device and Manufacturing Method Thereof - The present invention discloses a hybrid high voltage device and a manufacturing method thereof. The hybrid high voltage device is formed in a first conductive type substrate, and includes at least one lateral double diffused metal oxide semiconductor (LDMOS) device region and at least one vent device region, wherein the LDMOS device region and the vent device region are connected in a width direction and arranged in an alternating order. Besides, corresponding high voltage wells, sources, drains, body regions, and gates of the LDMOS device region and the vent device region are connected to each other respectively. | 12-26-2013 |
| 20140015049 | SEMICONDUCTOR DEVICE - An LDMOSFET includes a semiconductor substrate having a first semiconductor region formed of a feeding region of a first conduction type at a position where a field oxide film is not present on a surface layer of a semiconductor region in which the field oxide film is selectively formed, and a second semiconductor region formed of a well region of a second conduction type which is an opposite conduction type, and feeding regions of the first and second conduction types formed on an upper layer of the well region, and a gate electrode that faces the well region through a gate oxide film. The feeding region is formed at a distance from the field oxide film in an end portion in a longitudinal direction, and desirably the feeding region is intermittently formed at given intervals in the longitudinal direction, and the feeding region is applied to the first semiconductor region. | 01-16-2014 |
| 20140021543 | LOW THRESHOLD VOLTAGE METAL OXIDE SEMICONDUCTOR - A semiconductor device includes a source region disposed with a semiconductor substrate; a drain region disposed with the semiconductor substrate; a gate region disposed onto the semiconductor substrate and positioned between the source region and the drain region. The semiconductor device also includes a gate oxide region disposed onto the semiconductor substrate in contact with the gate region and a well region implanted onto the semiconductor substrate and under the gate region and the gate oxide region. The gate oxide region has a lower outer edge portion that contacts the well region. | 01-23-2014 |
| 20140021544 | Double Diffused Drain Metal Oxide Semiconductor Device and Manufacturing Method Thereof - The present invention discloses a double diffused drain metal oxide semiconductor (DDDMOS) device and a manufacturing method thereof. The DDDMOS device is formed in a substrate, and includes a first well, a gate, a diffusion region, a source, and a drain. A low voltage device is also formed in the substrate, which includes a second well and a lightly doped drain (LDD) region, wherein the first well and the diffusion region are formed by process steps which also form the second well and the LDD region in the low voltage device, respectively. | 01-23-2014 |
| 20140027848 | Lateral Semiconductor Device and Manufacturing Method Therefor - A method produces a semiconductor device including a semiconductor body, an electrode thereon, and an insulating structure insulating the electrode from the semiconductor body. The semiconductor body includes a first contact region of a first conductivity type, a body region of a second conductivity type, a drift region of the first conductivity type, and a second contact region having a higher maximum doping concentration than the drift region. The insulating structure includes a gate dielectric portion forming a first horizontal interface. with the drift region and has a first maximum vertical extension A field dielectric portion forms with the drift region second and third horizontal interfaces arranged below the main surface. A second maximum vertical extension of the field dielectric portion is larger than the first maximum vertical extension. A third maximum vertical extension of the field dielectric portion is larger than the second maximum vertical extension. | 01-30-2014 |
| 20140027849 | LDMOS DEVICE AND METHOD FOR IMPROVED SOA - A lateral-diffused-metal-oxide-semiconductor device having improved safe-operating-area is provided. The LDMOS device includes spaced-apart source and drain, separated by a first insulated gate structure, and spaced-apart source and body contact The spaced-apart source and BC are part of the emitter-base circuit of a parasitic bipolar transistor that can turn on prematurely, thereby degrading the SOA of prior art four-terminal LDMOS devices. Rather than separating the source and BC with a shallow-trench-isolation region as in the prior art, the semiconductor surface in the gap between the spaced-apart source and BC has there-over a second insulated gate structure, with its gate conductor electrically tied to the BC. When biased, the second insulated gate structure couples the source and BC lowering the parasitic resistance in the emitter-base circuit, thereby delaying turn-on of the parasitic transistor and improving the SOA of such 4-T LDMOS devices. | 01-30-2014 |
| 20140027850 | LDMOS DEVICE WITH STEP-LIKE DRIFT REGION AND FABRICATION METHOD THEREOF - An LDMOS device is disclosed. The LDMOS device includes: a substrate having a first type of conductivity; a drift region having a second type of conductivity and being formed in the substrate; a doped region having the first type of conductivity and being formed in the substrate, the doped region being located at a first end of the drift region and laterally adjacent to the drift region; and a heavily doped drain region having the second type of conductivity and being formed in the substrate, the heavily doped drain region being located at a second end of the drift region, wherein the drift region has a step-like top surface with at least two step portions, and wherein a height of the at least two step portions decreases progressively in a direction from the doped region to the drain region. A method of fabricating LDMOS device is also disclosed. | 01-30-2014 |
| 20140035035 | INSULATED GATE BIPOLAR TRANSISTOR STRUCTURE HAVING LOW SUBSTRATE LEAKAGE - A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate. | 02-06-2014 |
| 20140035036 | SEMICONDUCTOR DEVICE - A lateral semiconductor device including a semiconductor substrate; a buried oxide layer formed on the semiconductor substrate, and an active layer formed on the buried oxide layer. The active layer includes a first conductivity type well region, a second conductivity type well region, and a first conductivity type drift region interposed between the first conductivity type well region and the second conductivity type well region. A region where current flows because of carriers moving between the first conductivity type well region and the second conductivity type well region, and a region where no current flows are formed alternately between the first conductivity type well region and the second conductivity type well region, in a direction perpendicular to a carrier moving direction when viewed in a plan view. | 02-06-2014 |
| 20140048877 | LATERAL DIFFUSION METAL OXIDE SEMICONDUCTOR TRANSISTOR STRUCTURE - A lateral diffusion metal-oxide-semiconductor (LDMOS) transistor structure comprises a barrier layer, a semiconductor layer, a source, a first drain and a guard ring. The barrier layer with a first polarity is disposed in a substrate. The semiconductor layer with a second polarity is disposed on the barrier layer. The source has a first polarity region and a second polarity region both formed in the semiconductor layer. The first drain is disposed in the semiconductor layer and has a drift region with the second polarity. The guard ring with the first polarity extends downward from a surface of the semiconductor layer in a manner of getting in touch with the barrier layer and to surround the source and the drain, and is electrically connected to the source. | 02-20-2014 |
| 20140048878 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a P+ substrate; a P− epitaxial layer over the P+ substrate; a P-well and an N− drift region in the P− epitaxial layer and laterally adjacent to each other; an N+ source region in the P-well and connected to a front-side metal via a first contact electrode; an N+ drain region in the N− drift region and connected to the front-side metal via a second contact electrode; a gate structure on the P− epitaxial layer and connected to the front-side metal via a third contact electrode; and a metal plug through the P− epitaxial layer and having one end in contact with the P+ substrate and the other end connected to the front-side metal, the metal plug being adjacent to one side of the N+ source region that is farther from the N− drift region. A method for fabricating the semiconductor device is also disclosed. | 02-20-2014 |
| 20140048879 | LDMOS DEVICE WITH STEP-LIKE DRIFT REGION AND FABRICATION METHOD THEREOF - An LDMOS device is disclosed. The LDMOS device includes: a substrate having a first type of conductivity; a drift region having a second type of conductivity and a doped region having the first type of conductivity both formed in the substrate; a drain region having the second type of conductivity and being formed in the drift region, the drain region being located at an end of the drift region farther from the doped region; and a buried layer having the first type of conductivity and being formed in the drift region, the buried layer being in close proximity to the drain region and having a step-like bottom surface, and wherein a depth of the buried layer decreases progressively in a direction from the drain region to the doped region. A method of fabricating LDMOS device is also disclosed. | 02-20-2014 |
| 20140048880 | LDMOS WITH ACCUMULATION ENHANCEMENT IMPLANT - A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor device includes an enhancement implant region formed in a portion of an accumulation region proximate a P-N junction between body and drift drain regions. The enhancement implant region contains additional dopants of the same conductivity type as the drift drain region. There is a gap between the enhancement implant region and the P-N junction. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 02-20-2014 |
| 20140061791 | MOS TRANSISTOR - A MOS transistor is described, including: a source region and a drain region in a semiconductor substrate, an isolation between the source region and the drain region, a first gate conductor between the source region and the isolation, at least one conductive plug electrically connected to the first gate conductor and penetrating into the isolation, and at least one second gate conductor on the isolation, which is electrically connected to the first gate conductor and the at least one conductive plug. One of the at least one conductive plug is between the first gate conductor and the at least one second gate conductor. | 03-06-2014 |
| 20140070315 | Double-Resurf LDMOS With Drift And PSURF Implants Self-Aligned To A Stacked Gate "BUMP" Structure - A double-RESURF LDMOS transistor has a gate dielectric structure including a shallow field “bump” oxide region and an optional raised dielectric structure that provides a raised support for the LDMOS transistor's polysilicon gate electrode. Fabrication of the shallow field oxide region is performed through a hard “bump” mask and controlled such that the bump oxide extends a minimal depth into the LDMOS transistor's drift (channel) region. The hard “bump” mask is also utilized to produce an N-type drift (N-drift) implant region and a P-type surface effect (P-surf) implant region, whereby these implants are “self-aligned” to the gate dielectric structure. The N-drift implant is maintained at Vdd by connection to the LDMOS transistor's drain diffusion. An additional Boron implant is utilized to form a P-type buried layer that connects the P-surf implant to the P-body region of the LDMOS transistor, whereby the P-surf implant is maintained at 0V. | 03-13-2014 |
| 20140097492 | SEMICONDUCTOR STRUCTURE - A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate, a dielectric layer, a dielectric structure and an electrode structure. The dielectric layer is on an upper substrate surface of the semiconductor substrate. The dielectric structure and the semiconductor substrate have opposing first and second interfaces therebetween. The electrode structure comprises an electrode truck portion and at least one electrode branch portion. The at least one electrode branch portion is extended from the electrode truck portion down into the dielectric structure. The at least one electrode branch portion and the first interface have the smallest gap distance substantially bigger than 300 Å therebetween. | 04-10-2014 |
| 20140103431 | LATERALLY DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTORS HAVING A REDUCED SURFACE FIELD STRUCTURES - An LDMOS transistor includes a substrate of semiconductor material, an insulator layer overlying the substrate, a semiconductor layer overlying the insulator layer, a RESURF region, and a gate. The semiconductor layer includes a first conductivity type well region, a second conductivity type source region in contact with the first conductivity type well region, a second conductivity type drain region. The RESURF region includes at least one first conductivity type material portion, and at least one portion of the at least one first conductivity type material portion electrically coupled to the first conductivity type well region. A semiconductor material having a second conductivity type is located below the RESURF region. The second conductivity type semiconductor material is also located over a part of the RESURF region. The gate is located over the first conductivity type well region and over the RESURF region. | 04-17-2014 |
| 20140103432 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a base region of a second conductivity type, a drift region of a first conductivity type, an insulating layer, a drain region of the first conductivity type, a gate oxide film, a gate electrode, a first main electrode, and a second main electrode. The base region includes a source region of the first conductivity type. The drift region is adjacent to the base region. The insulating layer is provided from a surface to inside of the drift region. The drain region is provided in the surface of the drift region and opposed to the source region across the base region and the insulating layer. The gate oxide film is provided on a surface of the base region. The gate electrode is provided on the gate oxide film. The first main electrode is connected to the source region. The second main electrode is connected to the drain region. As viewed in a direction perpendicular to the surface of the base region, the source region and at least a part of the drain region extend generally parallel in a line shape, and a length of a portion of the drift region sandwiched between the insulating layer and the base region is shorter in the generally parallel extending direction than in a direction generally perpendicular to the generally parallel extending direction. | 04-17-2014 |
| 20140110782 | Source Tip Optimization For High Voltage Transistor Devices - The present disclosure provides a method for fabricating a high-voltage semiconductor device. The method includes designating first, second, and third regions in a substrate. The first and second regions are regions where a source and a drain of the semiconductor device will be formed, respectively. The third region separates the first and second regions. The method further includes forming a slotted implant mask layer at least partially over the third region. The method also includes implanting dopants into the first, second, and third regions. The slotted implant mask layer protects portions of the third region therebelow during the implanting. The method further includes annealing the substrate in a manner to cause diffusion of the dopants in the third region. | 04-24-2014 |
| 20140117446 | LDMOS Device with Minority Carrier Shunt Region - A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and having a first conductivity type, a gate structure supported by the semiconductor substrate between the source and drain regions, a well region in the semiconductor substrate, having a second conductivity type, and in which a channel region is formed under the gate structure during operation, and a shunt region adjacent the well region in the semiconductor substrate and having the second conductivity type. The shunt region has a higher dopant concentration than the well region to establish a shunt path for charge carriers of the second conductivity type that electrically couples the well region to a potential of the source region. | 05-01-2014 |
| 20140124858 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device is provided. The device includes a semiconductor substrate and a gate structure thereon. A well region is formed in the semiconductor substrate. A drain region and a source region are respectively formed in the semiconductor substrate inside and outside of the well region. At least one set of the first and second heavily doped regions is formed in the well region between the drain region and the source region, wherein the first and second heavily doped regions are stacked vertically from bottom to top and have a doping concentration which is larger than that of the well region. The semiconductor substrate and the first heavily doped region have a first conductivity type and the well region and the second heavily doped region have a second conductivity type. A method for fabricating a semiconductor device is also disclosed. | 05-08-2014 |
| 20140131798 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate including a first semiconductor layer on the semiconductor substrate; multiple semiconductor elements in the semiconductor substrate; and an ineffective region. Each semiconductor element includes: a second semiconductor layer in a surface portion of the first semiconductor layer; a third semiconductor layer disposed in another surface portion of the first semiconductor layer and spaced a part from the second semiconductor layer; and a control layer disposed on a portion of the first semiconductor layer between the second semiconductor layer and the third semiconductor layer. The ineffective region is disposed in the semiconductor substrate between at least two adjacent semiconductor elements; and does not provide a function of the semiconductor elements. | 05-15-2014 |
| 20140151799 | Double Diffused Drain Metal Oxide Semiconductor Device and Manufacturing Method Thereof - The present invention discloses a double diffused drain metal oxide semiconductor (DDDMOS) device and a manufacturing method thereof. The DDDMOS device is formed in a substrate, and includes a first well, a gate, a diffusion region, a source, and a drain. A low voltage device is also formed in the substrate, which includes a second well and a lightly doped drain (LDD) region, wherein the first well and the diffusion region are formed by process steps which also form the second well and the LDD region in the low voltage device, respectively. | 06-05-2014 |
| 20140151800 | LATERAL DOUBLE-DIFFUSED MOSFET - A LDMOS transistor is implemented in a first impurity region on a substrate. The LDMOS transistor has a source that includes a second impurity region. The second impurity region is implanted into the surface of the substrate within the first impurity region. Additionally, the LDMOS transistor has a drain that includes a third impurity region. The third impurity region is implanted into the surface of the substrate within the first impurity region. The third impurity region is spaced a predetermined distance away from a gate of the LDMOS transistor. The drain of the LDMOS transistor further includes a fourth impurity region within the third impurity region. The fourth impurity region provides an ohmic contact for the drain. | 06-05-2014 |
| 20140159153 | RF LDMOS DEVICE AND METHOD OF FORMING THE SAME - A radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) device is disclosed, which includes: a gate structure on a surface of a substrate; and a source region and a drain region beneath the surface of the substrate, the source region and the drain region formed on opposite sides of the gate structure, wherein the gate structure includes a first section proximal to the source region and a second section proximal to the drain region, and wherein the first section of the gate structure has a dopant concentration at least one decimal order higher than a dopant concentration of the second section of the gate structure. A method of forming an RF LDMOS device is also disclosed. With the gate structure including two sections having different dopant concentrations, the present invention is capable of reducing the hot carrier injection effect while possessing a low on-resistance. | 06-12-2014 |
| 20140159154 | Semiconductor Device with an Insulating Structure for Insulating an Electrode from a Semiconductor Body - A semiconductor device includes an electrode arranged on a main surface of a semiconductor body and an insulating structure insulating the electrode from the semiconductor body. The insulating structure includes in a vertical cross-section a gate dielectric portion forming a first horizontal interface at least with a drift region of the device and having a first maximum vertical extension between the first horizontal interface and the electrode, and a field dielectric portion forming with the drift region second, third and fourth horizontal interfaces. The second through fourth horizontal interfaces are arranged below the main surface. The third horizontal interface is arranged between the second and fourth horizontal interfaces. A second maximum vertical extension is larger than the first maximum vertical extension and a third maximum vertical extension is larger than the second maximum vertical extension. The electrode only partially overlaps the third horizontal interface. | 06-12-2014 |
| 20140159155 | HIGH VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE AND LAYOUT PATTERN THEREOF - A layout pattern of an implant layer includes at least a linear region and at least a non-linear region. The linear region includes a plurality of first patterns to accommodate first dopants and the non-linear region includes a plurality of second patterns to accommodate the first dopants. The linear region abuts the non-linear region. Furthermore, a pattern density of the first patterns in the linear region is smaller than a pattern density of the second patterns in the non-linear region. | 06-12-2014 |
| 20140167159 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The invention provides an LDMOS transistor of which the time-dependent degrading of the performance due to the trapping of hot electrons in the gate insulation film is decreased. A body layer is disposed in a surface portion of an N−-type semiconductor layer. A source layer including an N−-type layer is disposed in a surface portion of the body layer. An N− type drift layer is formed in a surface portion of the N−-type semiconductor layer. This drift layer includes a first region having a first N type impurity concentration peak region and a second region having a second N type impurity concentration peak region that is positioned deeper than the first N type impurity concentration peak region, the second region adjoining this first region. An N+ type drain layer is formed in a surface portion of the second region. | 06-19-2014 |
| 20140175547 | SEMICONDUCTOR DEVICE HAVING VARYING P-TOP AND N-GRADE REGIONS - An improved semiconductor is provided whereby n-grade and the p-top layers are defined by a series of discretely placed n-type and p-type diffusion segments. Also provided are methods for fabricating such a semiconductor. | 06-26-2014 |
| 20140197489 | Power MOSFETs and Methods for Forming the Same - Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape. A sum of a depth of the second drift region, a depth of the gate dielectric, and a depth of the gate electrode may be of substantially a same value as a depth of the first drift region. The first drift region and the second drift region may be formed at the same time, using the gate electrode as a part of the implanting mask. | 07-17-2014 |
| 20140197490 | SEMICONDUCTOR DEVICE - A semiconductor device with improved characteristics is provided. The semiconductor device includes a LDMOS, a source plug electrically coupled to a source region of the LDMOS, a source wiring disposed over the source plug, a drain plug electrically coupled to a drain region of the LDMOS, and a drain wiring disposed over the drain plug. The structure of the source plug of the semiconductor device is devised. The semiconductor device is structured such that the drain plug is linearly disposed to extend in a direction Y, and the source plug includes a plurality of separated source plugs arranged at predetermined intervals in the direction Y. In this way, the separation of the source plug decreases an opposed area between the source plug and the drain plug, and can thus decrease the parasitic capacitance therebetween. | 07-17-2014 |
| 20140203359 | BUTTED SOI JUNCTION ISOLATION STRUCTURES AND DEVICES AND METHOD OF FABRICATION - A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer on a buried oxide (BOX) layer of a silicon-on-insulator substrate; a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer, a doped region in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer, doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer, doped to a third dopant concentration, on the first epitaxial layer in the trench; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration. | 07-24-2014 |
| 20140217501 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The invention provides a semiconductor device, including: a substrate having a first conductivity type, including: a body region having the first conductivity type; a source region formed in the body region; a drift region having a second conductivity type adjacent to the body region; and a drain region formed in the drift region; a multiple reduced surface field (RESURF) structure embedded in the drift region of the substrate; and a gate dielectric layer formed over the substrate; wherein the first conductivity type is opposite to the second conductivity type. | 08-07-2014 |
| 20140264584 | LATERAL DOUBLE-DIFFUSED HIGH VOLTAGE DEVICE - A method of forming a device is disclosed. The method includes providing a substrate with a device region. The method also includes forming a transistor in the device region. The transistor includes a gate having first and second sides along a gate direction. The transistor also includes a first doped region adjacent to a first side of the gate, a second doped region adjacent to a second side of the gate, and a channel under the gate. The transistor further includes a channel trench in the channel of the gate, wherein the channel trench is along a trench direction which is at an angle θ other than 90° with respect to the gate direction. | 09-18-2014 |
| 20140264585 | SEMICONDUCTOR DEVICE INCLUDING LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR - A semiconductor device and method of manufacturing the same are provided. A device can include an LDMOS region and a high side region on a semiconductor substrate. The device can further include an insulating region separating the LDMOS region from the high side region and the insulating region can include a plurality of second conductive type wells, a plurality of second conductive type buried layer patterns, or both. | 09-18-2014 |
| 20140264586 | BOOTSTRAP FET AND METHOD OF MANUFACTURING THE SAME - A laterally diffused metal oxide semiconductor (LDMOS) device, and a method of manufacturing the same are provided. The LDMOS device can include a drain region of a bootstrap field effect transistor (FET), a source region of the bootstrap FET, a drift region formed between the drain region and the source region, and a gate formed at one side of the source region and on the drift region. | 09-18-2014 |
| 20140264587 | LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR AND METHOD FOR FABRICATING THE SAME - A laterally-diffused metal oxide semiconductor (LDMOS) device and method of manufacturing the same are provided. The LDMOS device can include a drift region, a source region and a drain region spaced a predetermined interval apart from each other in the drift region, a field insulating layer formed in the drift region between the source region and the drain region, and a first P-TOP region formed under the field insulating layer. The LDMOS device can further include a gate polysilicon covering a portion of the field insulating layer, a gate electrode formed on the gate polysilicon, and a contact line penetrating the gate electrode, the gate polysilicon, and the field insulating layer. | 09-18-2014 |
| 20140264588 | Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) with Step Oxide - The present disclosure relates to a method of ultra-high voltage UHV device formation which utilizes a composite step oxide as a gate oxide to achieve isolation of the gate and drain-side spacer from the drain region. The thickness of the step gate oxide improves device breakdown voltage, and allows for the drain to be self-aligned to the gate, thus reducing device drift region and improves device on state resistance. The composite isolation layer comprises two or more dielectric layers which are formed through a series of deposition and etch steps including thermal oxidation and chemical vapor deposition. The composite isolation layer may then be etched to form a self-align structure which utilizes the spacers as hard mask to achieve a reduced device pitch relative to some prior art methods. A thicker gate oxide under one or both spacers can improve yield and high temperature operating life of the UHV device. | 09-18-2014 |
| 20140284716 | LDMOS DEVICE WITH MINORITY CARRIER SHUNT REGION - A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and having a first conductivity type, a gate structure supported by the semiconductor substrate between the source and drain regions, a first well region in the semiconductor substrate, having a second conductivity type, and in which a channel region is formed under the gate structure during operation, and a second well region adjacent the first well region, having the second conductivity type, and having a higher dopant concentration than the first well region, to establish a path to carry charge carriers of the second conductivity type away from a parasitic bipolar transistor involving a junction between the channel region and the source region. | 09-25-2014 |
| 20140306285 | SEMICONDUCTOR POWER DEVICE - Provided is a semiconductor power device. The semiconductor power device includes a well disposed in a substrate, a gate overlapping the well, a source region disposed at one side of the gate, a buried layer disposed in the well, and a drain region or a drift region contacting the buried layer. | 10-16-2014 |
| 20140319610 | Lateral Power Semiconductor Device and Method for Manufacturing a Lateral Power Semiconductor Device - A lateral power semiconductor device includes a semiconductor body having a first surface and a second opposite surface, a first main electrode, a second main electrode, a plurality of switchable semiconductor cells and at least one curved semiconductor portion. The first main electrode includes at least two sections and is arranged on the first surface. The second main electrode is arranged on the first surface and between the two sections of the first main electrode. The plurality of switchable semiconductor cells is arranged between a respective one of the two sections of the first main electrode and the second main electrode and is configured to provide a controllable conductive path between the first main electrode and the second main electrode. The curved semiconductor portion is between the first main electrode and the second main electrode and has increasing doping concentration from the first main electrode to the second main electrode. | 10-30-2014 |
| 20140327075 | HIGH VOLTAGE AND ULTRA-HIGH VOLTAGE SEMICONDUCTOR DEVICES WITH INCREASED BREAKDOWN VOLTAGES - A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages. | 11-06-2014 |
| 20140332886 | SINGLE POLY PLATE LOW ON RESISTANCE EXTENDED DRAIN METAL OXIDE SEMICONDUCTOR DEVICE - A semiconductor device, in particular, an extended drain metal oxide semiconductor (ED-MOS) device, defined by a doped shallow drain implant in a drift region. For example, an extend drain n-channel metal oxide semiconductor (ED-NMOS) device is defined by an n doped shallow drain (NDD) implant in the drift region. The device is also characterized by conductive layer separated from a substrate in part by a thin oxide layer and in another part by a thick/thin oxide layer. A method of fabricating a semiconductor device, in particular an ED-NMOS device, having a doped shallow drain implant of a drift region is also provided. A method is also provided for fabricating conductive layer disposed in part across a thin oxide layer and in another part across a thick/thin oxide layer. | 11-13-2014 |
| 20140339636 | HIGH VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE - A high voltage metal-oxide-semiconductor (HV MOS) transistor device includes a substrate, a drifting region formed in the substrate, a plurality of isolation structures formed in the drift region and spaced apart from each other by the drift region, a plurality of doped islands respectively formed in the isolation structures, a gate formed on the substrate, and a source region and a drain region formed in the substrate at respective two sides of the gate. The gate covers a portion of each isolation structure. The drift region, the source region, and the drain region include a first conductivity type, the doped islands include a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other. | 11-20-2014 |
| 20140339637 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A semiconductor device may include a semiconductor substrate, a first conductive type well and a second conductive type drift region in the semiconductor substrate, the drift region including a first drift doping region and a second drift doping region, the second drift doping region vertically overlapping the well, and a first conductive type body region in the well, the body region being in contact with a side of the first drift doping region. The first drift doping region and the second doping region may include a first conductive type dopant and a second conductive type dopant, and an average density of the first conductive type dopant in the first drift doping region may be less than an average density of the first conductive type dopant in the second drift doping region. | 11-20-2014 |
| 20140361365 | SELF-ALIGNED CHANNEL DRIFT DEVICE AND METHODS OF MAKING SUCH A DEVICE - One illustrative device includes a source region and a drain region formed in a substrate, wherein the source/drain regions are doped with a first type of dopant material, a gate structure positioned above the substrate that is laterally positioned between the source region and the drain region and a drain-side well region positioned in the substrate under a portion, but not all, of the entire lateral width of the drain region, wherein the drain-side well region is also doped with the first type of dopant material. The device also includes a source-side well region positioned in the substrate under an entire width of the source region and under a portion, but not all, of the drain region and a part of the extension portion of the drain region is positioned under a portion of the gate structure. | 12-11-2014 |
| 20140361366 | LATERAL DOUBLE DIFFUSION METAL-OXIDE-SEMICONDUCTOR (LDMOS) TRANSISTORS AND FABRICATION METHOD THEREOF - A lateral double diffusion metal-oxide-semiconductor (LDMOS) transistor is provided. The LDMOS transistor includes a semiconductor substrate having a well region and a drain region in the well region. The LDMOS transistor also includes at least one drifting region in the well region and an annular source region in the drifting region surrounding the drain region. Further, the LDMOS transistor includes at least one annular isolation structure surrounding the drain region in the drifting region. Further, the LDMOS transistor also includes an annular gate dielectric layer on the well region and an annular gate on the annular gate dielectric layer. | 12-11-2014 |
| 20140367778 | LATERAL DIFFUSION METAL OXIDE SEMICONDUCTOR (LDMOS) - A lateral diffusion metal oxide semiconductor (LDMOS) comprises a semiconductor substrate having an STI structure in a top surface of the substrate, a drift region below the STI structure, and a source region and a drain region on opposite sides of the STI structure. A gate conductor is on the substrate over a gap between the STI structure and the source region and partially overlaps the drift region. A conformal dielectric layer is on the top surface and forms a mesa above the gate conductor. The conformal dielectric layer has a conformal etch-stop layer embedded therein. Contact studs extend through the dielectric layer and the etch-stop layer, and are connected to the source region, drain region, and gate conductor. A source electrode contacts the source contact stud, a gate electrode contacts the gate contact stud, and a drain electrode contacts the drain contact stud. A drift electrode is over the drift region. | 12-18-2014 |
| 20150014771 | DUAL L-SHAPED DRIFT REGIONS IN AN LDMOS DEVICE AND METHOD OF MAKING THE SAME - A semiconductor device comprising dual L-shaped drift regions in a lateral diffused metal oxide semiconductor (LDMOS) and a method of making the same. The LDMOS in the semiconductor device comprises a trench isolation region or a deep trench encapsulated by a liner, a first L-shaped drift region, and a second L-shaped drift region. The LDMOS comprising the dual L-shape drift regions is integrated with silicon-germanium (SiGe) technology. The LDMOS comprising the dual L-shape drift regions furnishes a much higher voltage drop in a lateral direction within a much shorter distance from a drain region than the traditional LDMOS does. | 01-15-2015 |
| 20150021687 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SEMICONDUCTOR STRUCTURE WITH DEEP TRENCH ISOLATION STRUCTURES - The density of a transistor array is increased by forming one or more deep trench isolation structures in a semiconductor material. The deep trench isolation structures laterally surround the transistors in the array. The deep trench isolation structures limit the lateral diffusion of dopants and the lateral movement of charge carriers. | 01-22-2015 |
| 20150035056 | SEMICONDUCTOR DEVICE - A semiconductor device includes an N | 02-05-2015 |
| 20150048451 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor device and a manufacturing method for the same are provided. The semiconductor substrate includes a gate structure, a first doped contact region, a second doped contact region and a well doped region. The gate structure is on the semiconductor substrate, and has a first gate sidewall and a second gate sidewall opposite to the first gate sidewall. The first doped contact region has a first type conductivity and is formed in the semiconductor substrate on the first gate sidewall of the gate structure. The second doped contact region has the first type conductivity and is formed in the semiconductor substrate on the second gate sidewall of the gate structure. The well doped region has the first type conductivity and is under the first doped contact region. | 02-19-2015 |
| 20150048452 | ULTRA-HIGH VOLTAGE SEMICONDUCTOR HAVING AN ISOLATED STRUCTURE FOR HIGH SIDE OPERATION AND METHOD OF MANUFACTURE - A semiconductor device, in particular, an ultra-high metal oxide semiconductor (UHV MOS) device, is defined by a doped gradient structure in a drain region. For example, an ultra-high n-type metal oxide semiconductor (UHV NMOS) device is defined by an n-doped gradient structure in the drain region. The n-doped gradient structure has at least one of a high voltage n- (HVN-) well, a drain side high voltage n-type deep (HVND) well, and a drain side n-type well (NW) disposed in the drain region. A drain side n+ well is additionally disposed in the at least one of the HVN- well, the drain side HVND well, and the drain side NW. A method of manufacturing a UHV NMOS device having a doped gradient structure of a drain region is also provided. | 02-19-2015 |
| 20150054073 | SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - Semiconductor devices and methods for manufacturing the same are provided. In one embodiment, the method may include: forming a first shielding layer on a substrate, and forming one of source and drain regions with the first shielding layer as a mask; forming a second shielding layer on the substrate, and forming the other of the source and drain regions with the second shielding layer as a mask; removing a portion of the second shielding layer which is next to the other of the source and drain regions; forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of a remaining portion of the second shielding layer; and forming a stressed interlayer dielectric layer on the substrate. | 02-26-2015 |
| 20150054074 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - Semiconductor devices and methods of manufacturing the same are provided. In one embodiment, the method may include: forming a first shielding layer on a substrate; forming one of source and drain regions with the first shielding layer as a mask; forming a second shielding layer on the substrate, and removing the first shielding layer; forming a shielding spacer on a sidewall of the second shielding layer; forming the other of the source and drain regions with the second shielding layer and the shielding spacer as a mask; removing at least a portion of the shielding spacer; and forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of the second shielding layer or a possible remaining portion of the shielding spacer. | 02-26-2015 |
| 20150054075 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device. An n-type transistor is formed on a (551) surface of a silicon substrate. A silicide layer region in contact with a diffusion region (heavily doped region) of the n-type transistor has a thickness not more than 5 nm. A metal layer region in contact with the silicide layer has a thickness of 25 nm (inclusive) to 400 nm (inclusive). A barrier height between the silicide layer region and the diffusion region has a minimum value in this thickness relationship. | 02-26-2015 |
| 20150054076 | HIGH VOLTAGE DEVICE - A method of forming a device is presented. The method includes providing a substrate having a device region which includes a source region, a gate and a drain region defined thereon. The method also includes implanting the gate. The gate comprises one or more doped portions with different dopant concentrations. A source and a drain are formed in the source region and drain region. The drain is separated from the gate on a second side of the gate and the source is adjacent to a first side of the gate. | 02-26-2015 |
| 20150069507 | MOS TRANSISTOR AND METHOD FOR MANUFACTURING MOS TRANSISTOR - A novel MOS transistor, which includes a source region, a drain region, a channel region, an isolation region, a drift region, a gate dielectric layer, a gate electrode and a field plate, is provided. The gate electrode has a first portion and a second portion. The first portion of a first conductivity type is located over the channel region and has a width equal to or greater than a distance of the gate electrode overlapped with the channel region. The second portion is un-doped and located over the isolation region. Accordingly, the MOS transistor allows higher process freedom saves production cost, as well as improves reliability. | 03-12-2015 |
| 20150069508 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of epitaxial layers stacked over a supportive substrate, a first buried impurity region formed to share the supportive substrate with a lowermost epitaxial layer among the multiple epitaxial layers, one or more second buried impurity regions formed to be coupled with the first buried impurity region and share an N | 03-12-2015 |
| 20150069509 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate having a supporting substrate, wherein a first epitaxial layer and a second epitaxial are sequentially stacked, an isolation region including a first buried impurity region of a second conductivity type and a second buried impurity region of the second conductivity type wherein the first buried impurity region is formed from the supporting substrate to the first epitaxial layer, and the second buried impurity region is formed from the first epitaxial layer to the second epitaxial layer and is in contact with an edge of the first buried impurity region, a third buried impurity region of a first conductivity type formed from the first epitaxial layer to the second epitaxial layer, located in the second buried impurity region and overlapped with the first buried impurity region, and a transistor formed over the second epitaxial layer and overlapped with the third buried impurity region. | 03-12-2015 |
| 20150102406 | LATERAL DOUBLE DIFFUSED METAL-OXIDE-SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A LDMOS device includes a substrate having opposite first and second surfaces; a well region in a portion of the substrate; a gate structure over a portion of the substrate; a first doped region disposed in a portion of the well region from a first side; a second doped region disposed in the well region from a second side; a third doped region disposed in the first doped region; a fourth doped region disposed in the second doped region; a first trench in the third doped region, the first doped region, the well region, and the substrate adjacent to the first surface; a conductive contact in the first trench; a second trench in the substrate adjacent to the second surface; a first conductive layer in second trench; and a second conductive layer over the second surface of the substrate and the first conductive layer. | 04-16-2015 |
| 20150102407 | LATERAL DOUBLE DIFFUSED METAL-OXIDE-SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A lateral double diffused metal-oxide-semiconductor device includes: an epitaxial semiconductor layer disposed over a semiconductor substrate; a gate dielectric layer disposed over the epitaxial semiconductor layer; a gate stack disposed over the gate dielectric layer; a first doped region disposed in the epitaxial semiconductor layer from a first side of the gate stack; a second doped region disposed in the epitaxial semiconductor layer from a second side of the gate stack; a third doped region disposed in the first doping region; a fourth doped region disposed in the second doped region; an insulating layer covering the third doped region, the gate dielectric layer, and the gate stack; a conductive contact disposed in the insulating layer, the third doped region, the first doped region and the epitaxial semiconductor layer; and a fifth doped region disposed in the epitaxial semiconductor layer under the conductive contact. | 04-16-2015 |
| 20150102408 | Semiconductor Device - A semiconductor device with improved characteristics is provided. The semiconductor device includes a LDMOS, a source plug electrically coupled to a source region of the LDMOS, a source wiring disposed over the source plug, a drain plug electrically coupled to a drain region of the LDMOS, and a drain wiring disposed over the drain plug. The structure of the source plug of the semiconductor device is devised. The semiconductor device is structured such that the drain plug is linearly disposed to extend in a direction Y, and the source plug includes a plurality of separated source plugs arranged at predetermined intervals in the direction Y. In this way, the separation of the source plug decreases an opposed area between the source plug and the drain plug, and can thus decrease the parasitic capacitance therebetween. | 04-16-2015 |
| 20150137230 | LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR AND MANUFACTURING METHOD THEREOF - A laterally diffused metal oxide semiconductor (LDMOS) and a manufacturing method thereof are provided. The LDMOS includes a substrate, a gate, a first well and a shallow trench isolation (STI). The gate is disposed above the substrate. The gate has a first gate region having a first dopant type and a second gate region having a second dopant type. The first well is disposed in the substrate. The STI is contacted with the first well and partially overlaps with the gate. | 05-21-2015 |
| 20150137231 | LATERAL DOUBLE DIFFUSED METAL-OXIDE-SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A lateral double diffused metal-oxide-semiconductor device includes: a semiconductor substrate; an epitaxial semiconductor layer disposed over the semiconductor substrate; a gate structure disposed over the epitaxial semiconductor layer; a first doped region disposed in the epitaxial semiconductor layer at a first side of the gate structure; a second doped region disposed in the epitaxial semiconductor layer at a second side of the gate structure; a third doped region disposed in the first doped region; a fourth doped region disposed in the second doped region; a trench formed in the third doped region, the first doped region and the epitaxial semiconductor layer under the first doped region; a conductive contact formed in the trench; and a fifth doped region disposed in the epitaxial semiconductor layer under the trench. | 05-21-2015 |
| 20150137232 | LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention discloses a lateral double diffused metal oxide semiconductor (LDMOS) device and a manufacturing method thereof. The LDMOS device includes: drift region, an isolation oxide region, a first oxide region, a second oxide region, a gate, a body region, a source, and a drain. The isolation oxide region, the first oxide region, and the second oxide region have an isolation thickness, a first thickness, and a second thickness respectively, wherein the second thickness is less than the first thickness. The present invention can reduce a conduction resistance without decreasing a breakdown voltage of the LDMOS device by the first oxidation region and the second oxidation region. | 05-21-2015 |
| 20150145039 | SEMICONDUCTOR DEVICE HAVING DRAIN SIDE CONTACT THROUGH BURIED OXIDE - A semiconductor device configured to provide high heat dissipation and improve breakdown voltage comprises a substrate, a buried oxide layer over the substrate, a buried n+ region in the substrate below the buried oxide layer, and an epitaxial layer over the buried oxide layer. The epitaxial layer comprises a p-well, an n-well, and a drift region between the p-well and the n-well. The semiconductor device also comprises a source contact, a first electrode electrically connecting the source contact to the p-well, and a gate over a portion of the p-well and a portion of the drift region. The semiconductor device further comprises a drain contact, and a second electrode extending from the drain contact through the n-well and through the buried oxide layer to the buried n+ region. The second electrode electrically connects the drain contact to the n-well and to the buried n+ region. | 05-28-2015 |
| 20150311338 | SEMICONDUCTOR DEVICE INCLUDING AN N-WELL STRUCTURE - A device comprising a p-type base region, and a p-type region formed over the p-type base region and in contact with the p-type base region is disclosed. The device also includes an n-well region surrounded by the p-type region, wherein the n-well is formed from an n-type epitaxial layer and the p-type region is formed by counter-doping the same n-type epitaxial layer. | 10-29-2015 |
| 20150318378 | LOW LEAKAGE, HIGH FREQUENCY DEVICES - Low leakage, high frequency devices and methods of manufacture are disclosed. The method of forming a device includes implanting a lateral diffusion drain implant in a substrate by a blanket implantation process. The method further includes forming a self-aligned tapered gate structure on the lateral diffusion drain implant. The method further includes forming a halo implant in the lateral diffusion drain implant, adjacent to the self-aligned tapered gate structure and at least partially under a source region of the self-aligned tapered gate structure. | 11-05-2015 |
| 20150333177 | SEMICONDUCTOR DEVICE WITH COMPOSITE DRIFT REGION AND RELATED FABRICATION METHOD - A device includes a semiconductor substrate, a body region in the semiconductor substrate having a first conductivity type and in which a channel is formed during operation, source and drain regions in the semiconductor substrate and having a second conductivity type, the source region being disposed on the body region, and a composite drift region in the semiconductor substrate, having the second conductivity type, and through which charge carriers from the source region drift to reach the drain region after passing through the channel. The composite drift region includes a first section adjacent the channel, a second section adjacent the drain region, and a third section disposed between the first and second sections. The first and second sections have a lower effective dopant concentration level than the third section. | 11-19-2015 |
| 20150357463 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a channel-forming region of a first conductivity type; a first main electrode region of a second conductivity type disposed in a portion of an upper part of the channel-forming region; a drift region of the second conductivity type that is disposed in an upper part of the channel-forming region apart from the first main electrode region; a second main electrode region of the second conductivity type that is disposed in a part of an upper part of the drift region; and a stopper region of the second conductivity type that is disposed at an end region of the drift region apart from the first main electrode region and has a higher concentration than the drift region. The stopper region restricts extension of a depletion layer developing at the boundary of the pn junction between the channel-forming region and the drift region. | 12-10-2015 |
| 20150364598 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - The present disclosure provides a method for forming a Lateral Double-Diffused MOSFET (LDMOS). The method includes providing a semiconductor substrate having a first conductivity type; forming a first shallow trench isolation (STI) structure in the semiconductor substrate; and applying a first ion implantation to form a drift region of a second conductivity type into the semiconductor substrate with the drift region surrounding the first STI structure. The method also includes applying a counter-doping implantation to form a counter-doped region having the first conductivity in the drift region and forming a body region on one side of the drift region in the semiconductor substrate. The method further includes forming a gate structure on the semiconductor substrate, wherein one end of the gate structure extends to an area on the body region another end of the gate structure extends to an area on the first STI region. | 12-17-2015 |
| 20160035884 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, and a P-well and an N-type drift region disposed in the semiconductor substrate. The P-well includes a lower well region and an upper well region disposed above the lower well region. The lower well region includes a first surface that is near the N-type drift region, and the upper well region includes a second surface that is near the N-type drift region. A distance from the first surface of the lower well region to the N-type drift region is greater than a distance from the second surface of the upper well region to the N-type drift region. | 02-04-2016 |
| 20160064487 | POWER INTEGRATED DEVICES, ELECTRONIC DEVICES AND ELECTRONIC SYSTEMS INCLUDING THE SAME - A power integrated device includes a drift region disposed in a substrate, a source region disposed in the substrate spaced apart from the drift region, a drain region disposed in the drift region, a gate insulation layer and a gate electrode sequentially stacked on the substrate between the source region and the drift region, a trench isolation layer disposed in the drift region adjacent to a side of the drain region, and a deep trench field insulation layer disposed in the drift region adjacent to another side of the drain region, wherein a vertical height of the deep trench field insulation layer is greater than a width of the deep trench field insulation layer. | 03-03-2016 |
| 20160064552 | LDMOS TRANSISTOR AND FABRICATION METHOD THEREOF - A LDMOS transistor includes a semiconductor substrate with a first doping type; a plurality of first trenches formed in the semiconductor substrate; a wave-shaped drift region with an increased conductive path and a second doping type formed on the semiconductor substrate between adjacent first trenches and the semiconductor substrate exposed by side and bottom surfaces of the first trenches; a first shallow trench isolation (STI) structure formed in each of the first trenches; a body region with the first doping type formed in semiconductor substrate at one side of the drift region; a gate structure formed over portions of the body region, the drift region and the first STI structure most close to the body region; a source region formed in the body region; and a drain region formed in the drift region at one side of the first STI structure most far away from the body region. | 03-03-2016 |
| 20160087060 | SEMICONDUCTOR DEVICE WITH PARTIALLY UNSILICIDED SOURCE/DRAIN - A transistor includes a substrate and a gate over the substrate. The transistor further includes a source and a drain over the substrate on opposite sides of the gate. The transistor further includes a channel region beneath the gate separating the source from the drain, the channel region having a channel width with respect to a surface of the substrate greater than a width of the gate with respect to the surface of the substrate. The transistor further includes a silicide over a first portion of the drain, wherein a second portion of the drain, closer to the gate than the first portion, is an unsilicided region. | 03-24-2016 |
| 20160099347 | LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - Provided is a manufacturing method for a laterally diffused metal oxide semiconductor device, comprising the following steps: growing an oxide layer on a substrate of a wafer (S | 04-07-2016 |
| 20160111509 | METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE HAVING A DRAIN SIDE DUMMY CONTACT - A MOS transistor device includes a substrate including a gate formed thereon, and a spacer being formed on a sidewall of the gate; a source region and a drain region formed in the substrate; and at least a first dummy contact formed above the substrate on a drain side of the gate. More important, the first dummy contact is formed apart from a surface of the substrate. | 04-21-2016 |
| 20160118495 | INTEGRATED BREAKDOWN PROTECTION - A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. At least one of the body region and the device isolating region includes a plurality of peripheral, constituent regions disposed along a lateral periphery of the active area, each peripheral, constituent region defining a non-uniform spacing between the device isolating region and the body region. The non-uniform spacing at a respective peripheral region of the plurality of peripheral, constituent regions establishes a first breakdown voltage lower than a second breakdown voltage in the conduction path. | 04-28-2016 |
| 20160141414 | METHOD AND APPARATUS FOR POWER DEVICE WITH DEPLETION STRUCTURE - A semiconductor device is provided. The semiconductor device includes a substrate of a first conductivity type and an epitaxial structure of the first conductivity type disposed on the substrate. The semiconductor device further includes a well region having a first doping concentration of a second conductivity type disposed in the epitaxial structure and the substrate. The semiconductor device further includes a drain region and a source region respectively formed in the epitaxial structure inside and outside of the well region. The semiconductor device further includes a body region of the first conductivity type disposed under the source region, and a pair of first and second doped regions disposed in the well region between the drain region and the source region. The first and second doped regions extend outside of the well region and toward the body region. | 05-19-2016 |
| 20160141420 | HIGH-VOLTAGE FINFET DEVICE HAVING LDMOS STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The high-voltage FinFET device includes: at least one fin structure, a working gate, a shallow trench isolation structure, and a first dummy gate. The fin structure includes a first-type well region and a second-type well region adjacent to the first-type well region, and further includes a first part and a second part. A trench is disposed between the first part and the second part and disposed in the first-type well region. A drain doped layer is disposed on the first part which is disposed in the first-type well region, and a source doped layer is disposed on the second part which is disposed in the second-type well region. The working gate is disposed on the fin structure which is disposed in the first-type well region and in the second-type well region. | 05-19-2016 |
| 20160148996 | DIODE AND SIGNAL OUTPUT CIRCUIT INCLUDING THE SAME - A diode includes: a p-type semiconductor substrate; an n-type semiconductor layer; a p-type isolation region formed to surround a predetermined region of the n-type semiconductor layer on the p-type semiconductor substrate; an n-type buried layer formed across the p-type semiconductor layer and the n-type semiconductor layer within the predetermined region; an n-type collector wall formed in the n-type semiconductor layer; a p-type anode region and a plurality of n-type cathode regions formed in a diode formation region; and a p-type guard ring formed to surround the diode formation region in a region between the diode formation region of the surface layer of the n-type semiconductor layer and the p-type isolation region. A transistor for reducing a leakage current is formed by the p-type anode region, the p-type guard ring, and an n-type semiconductor between the p-type anode region and the p-type guard ring. | 05-26-2016 |
| 20160149031 | SEMICONDUCTOR DEVICES INCLUDING PATTERNS IN A SOURCE REGION - Semiconductor devices are provided. A semiconductor device includes a substrate including a well region. The semiconductor device includes a source region in the well region. The semiconductor device includes a drain region. The semiconductor device includes a gate electrode that is between the source and drain regions, when viewed in a plan view. Moreover, the semiconductor device includes first and second patterns, in the source region, that are spaced apart from each other when viewed in the plan view. | 05-26-2016 |
| 20160163857 | SEMICONDUCTOR DEVICE - A semiconductor device with improved characteristics is provided. The semiconductor device includes a LDMOS, a source plug electrically coupled to a source region of the LDMOS, a source wiring disposed over the source plug, a drain plug electrically coupled to a drain region of the LDMOS, and a drain wiring disposed over the drain plug. The structure of the source plug of the semiconductor device is devised. The semiconductor device is structured such that the drain plug is linearly disposed to extend in a direction Y, and the source plug includes a plurality of separated source plugs arranged at predetermined intervals in the direction Y. In this way, the separation of the source plug decreases an opposed area between the source plug and the drain plug, and can thus decrease the parasitic capacitance therebetween. | 06-09-2016 |
| 20160172485 | SEMICONDUCTOR DEVICE | 06-16-2016 |
| 20160172489 | SEMICONDUCTOR DEVICE AND RELATED FABRICATION METHODS | 06-16-2016 |
| 20160181400 | LDMOS Device and Its Manufacturing Method | 06-23-2016 |
| 20160181419 | SEMICONDUCTOR DEVICE | 06-23-2016 |
| 20160190269 | TAPERED GATE OXIDE IN LDMOS DEVICES - Approaches for LDMOS devices are provided. A method of forming a semiconductor structure includes forming a gate dielectric including a first portion having a first uniform thickness, a second portion having a second uniform thickness different than the first uniform thickness, and a transition portion having tapered surface extending from the first portion to the second portion. The gate dielectric is formed on a planar upper surface of a substrate. The tapered surface is at an acute angle relative to the upper surface of the substrate. | 06-30-2016 |
