| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257340000 | With means (other than self-alignment of the gate electrode) to decrease gate capacitance (e.g., shield electrode) | 10 |
| 20090065862 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device comprising: a base layer of a first conductivity type selectively formed above a semiconductor substrate; a gate electrode formed on the base layer via the insulating film; a source layer of a second conductivity type selectively formed at a surface of the base layer at one side of the gate electrode; an channel implantation layer selectively formed at the surface of the base layer so as to be adjacent to the source layer below the gate electrode, the channel implantation layer having a higher concentration than the base layer; a RESURF layer of the second conductivity type selectively formed at the surface of the base layer at the other side of the gate electrode; and a drain layer of a second conductivity type being adjacent to the RESURF layer, a portion of the drain layer overlapping the base layer, and the drain layer having a higher concentration than the RESURF layer. | 03-12-2009 |
| 20100327349 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a semiconductor device having an LDMOSFET, a source electrode is at the back surface thereof. Therefore, to reduce electric resistance between a source contact region in the top surface and the source electrode at the back surface, a poly-silicon buried plug is provided which extends from the upper surface into a P | 12-30-2010 |
| 20110254088 | Power MOSFET With Embedded Recessed Field Plate and Methods of Fabrication - Semiconductor power devices, and related methods, wherein a recessed contact makes lateral ohmic contact to the source diffusion, but is insulated from the underlying recessed field plate (RFP). Such an insulated RFP is here referred to as an embedded recessed field plate (ERFP). | 10-20-2011 |
| 20110266619 | SEMICONDUCTOR TRANSISTOR COMPRISING TWO ELECTRICALLY CONDUCTIVE SHIELD ELEMENTS - It is disclosed a semiconductor transistor, comprising a semiconductor substrate ( | 11-03-2011 |
| 20130175617 | Semiconductor Device With an Oversized Local Contact as a Faraday Shield - This application is directed to a semiconductor device with an oversized local contact as a Faraday shield, and methods of making such a semiconductor device. One illustrative device disclosed herein includes a transistor comprising a gate electrode and a source region, a source region conductor that is conductively coupled to the source region, a Faraday shield positioned above the source region conductor and the gate electrode and a first portion of a first primary metallization layer for an integrated circuit device positioned above and electrically coupled to the Faraday shield. | 07-11-2013 |
| 20140239392 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A technique for improving characteristics of a semiconductor device (DMOSFET) is provided. A semiconductor device is configured so as to include: an n-type source layer ( | 08-28-2014 |
| 20150340448 | METHOD FOR CREATION OF THE GATE SHIELD IN ANALOG/RF POWER ED-CMOS IN SIGE BICMOS TECHNOLOGIES - A method of fabricating a MOSFET transistor in a SiGe BICMOS technology and resulting structure having a drain-gate feedback capacitance shield formed between a gate electrode and the drain region. The shield does not overlap the gate and thereby minimizes effect on the input capacitance of the transistor. The process does not require complex or costly processing since the shield is composed of bipolar base material commonly used in SiGe BICMOS technologies. | 11-26-2015 |
| 20160056114 | TRENCHED FARADAY SHIELDING - A device includes a semiconductor substrate having a surface with a trench, first and second conduction terminals supported by the semiconductor substrate, a control electrode supported by the semiconductor substrate between the first and second conduction terminals and configured to control flow of charge carriers during operation between the first and second conduction terminals, and a Faraday shield supported by the semiconductor substrate and disposed between the control electrode and the second conduction terminal. At least a portion of the Faraday shield is disposed in the trench. | 02-25-2016 |
| 20160141406 | Semiconductor to Metal Transition - A semiconductor device includes a diffusion barrier layer, a first semiconductor region having first charge carriers of a first conductivity type and a second semiconductor region having second charge carriers. The first semiconductor region includes a transition region in contact with the second semiconductor region, the transition region having a first concentration of the first charge carriers, a contact region in contact with the diffusion barrier layer, the contact region having a second concentration of the first charge carriers, wherein the second concentration is higher than the first concentration, and a damage region between the contact region and the transition region. The damage region is configured for reducing the lifetime and/or the mobility of the first charge carriers of the damage region as compared to the lifetime and/or the mobility of the first charge carriers of the contact region and the transition region. | 05-19-2016 |
| 20160197180 | POWER SEMICONDUCTOR TRANSISTOR WITH IMPROVED GATE CHARGE | 07-07-2016 |
