| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257333000 | With thick insulator to reduce gate capacitance in non-channel areas (e.g., thick oxide over source or drain region) | 22 |
| 20080211018 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - This semiconductor device includes a trench gate transistor including a groove formed on a semiconductor, a gate electrode formed in the groove via a gate insulating film, and a source and a drain disposed near the gate electrode on the semiconductor substrate via the gate insulating film. The gate electrode extends from an inner side of the groove to an outer side of the groove. The gate electrode has a misalignment portion in a width direction from the inner side of the groove to the outer side of the groove. The misalignment portion of the gate electrode is formed at a side higher than an opening edge of the groove. A height from the opening edge of the groove to the misalignment portion is larger than a thickness of the gate insulating film. | 09-04-2008 |
| 20080246082 | Trenched mosfets with embedded schottky in the same cell - A semiconductor power device includes trenched semiconductor power device comprising a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an insulation layer covering the trenched semiconductor power device with a source-body contact trench opened therethrough the source and body regions and extending into an epitaxial layer below the body regions and filled with contact metal plug therein. The semiconductor power device further includes an embedded Schottky diode disposed near a bottom of the source-body contact trench below the contact metal plug wherein the Schottky diode further includes a Schottky barrier layer having a barrier height for reducing a leakage current through the embedded Schottky diode during a reverse bias between the drain and the source. | 10-09-2008 |
| 20090072306 | Semiconductor device and method of manufacturing semiconductor device - A semiconductor device according to the present invention includes a semiconductor layer. A first conductivity type region is formed on a base layer portion of the semiconductor layer. A body region of a second conductivity type is formed on the semiconductor layer to be in contact with the first conductivity type region. A trench in which a gate electrode is embedded through a gate insulating film is formed on the semiconductor layer. The trench penetrates through the body region, so that a deepest portion thereof reaches the first conductivity type region. A source region of the first conductivity type is formed on a surface layer portion of the semiconductor layer around the trench. The gate insulating film includes a thick-film portion having a relatively large thickness on a bottom surface of the trench. | 03-19-2009 |
| 20090114983 | Power Transistor Capable of Decreasing Capacitance between Gate and Drain - A power transistor capable of decreasing capacitance between a gate and a drain includes a backside mental layer, a substrate formed on the backside mental layer, a semiconductor layer formed on the substrate, and a frontside mental layer formed on the semiconductor layer. The semiconductor layer comprises a first trench structure comprising a gate oxide layer, a second trench structure comprising a p-well junction formed around a second trench, a p-body region formed outside the first trench structure and the second trench structure, a first n+ source region formed on the p-body region and beside a sidewall of the first trench structure, a second n+ source region formed on the p-body region and between another sidewall of the first trench structure and the second trench structure, and a dielectric layer formed on the first trench structure, the first n+ source region, and the second n+ source region. | 05-07-2009 |
| 20090206401 | TRENCH TRANSISTOR AND METHOD FOR FABRICATING A TRENCH TRANSISTOR - A trench transistor having a semiconductor body, in which a trench structure and an electrode structure embedded in the trench structure is disclosed. The electrode structure is electrically insulated from the semiconductor body by an insulation structure. The electrode structure has a gate electrode structure and a field electrode structure arranged below the gate electrode structure and electrically insulated from the latter. There is provided between the gate electrode structure and the field electrode structure a shielding structure for reducing the capacitive coupling between the gate electrode structure and the field electrode structure. | 08-20-2009 |
| 20100090275 | TRANSISTOR STRUCTURE HAVING AN ACTIVE REGION AND A DIELECTRIC PLATFORM REGION - A semiconductor device is formed having lower gate-to-drain capacitance. The semiconductor device having an active region ( | 04-15-2010 |
| 20100140693 | Inverted-trench grounded-source FET structure using conductive substrates, with highly doped substrates - This invention discloses an inverted field-effect-transistor (iT-FET) semiconductor device that includes a source disposed on a bottom and a drain disposed on a top of a semiconductor substrate. The semiconductor power device further comprises a trench-sidewall gate placed on sidewalls at a lower portion of a vertical trench surrounded by a body region encompassing a source region with a low resistivity body-source structure connected to a bottom source electrode and a drain link region disposed on top of said body regions thus constituting a drift region. The drift region is operated with a floating potential said iT-FET device achieving a self-termination. | 06-10-2010 |
| 20100140694 | SEMICONDUCTOR DEVICE HAVING SUB-SURFACE TRENCH CHARGE COMPENSATION REGIONS AND METHOD - In one embodiment, a semiconductor device is formed having sub-surface charge compensation regions in proximity to channel regions of the device. The charge compensation trenches comprise at least two opposite conductivity type semiconductor layers. A channel connecting region electrically couples the channel region to one of the at least two opposite conductivity type semiconductor layers. | 06-10-2010 |
| 20100171173 | TRENCH MOSFET WITH IMPROVED SOURCE-BODY CONTACT - A trench MOSFET with improved source-body contact structure is disclosed. The improved contact structure can enlarge the P+ area below to wrap the sidewalls and bottom of source-body contact within P-body region to further enhance the avalanche capability. On the other hand, one of the embodiments disclosed a wider tungsten plug structure to connect source metal, which helps to further reduce the source contact resistance. | 07-08-2010 |
| 20110057259 | METHOD FOR FORMING A THICK BOTTOM OXIDE (TBO) IN A TRENCH MOSFET - A method for forming a thick bottom oxide in the bottom of a trench used in a vertical MOSFET. Initially, an n-type substrate has an n-type epitaxial layer grown thereon. A top portion of the n-type epitaxial layer is implanted with p-type dopants to provide a p-layer. A trench is then etched into the p- and n-type epitaxial layer. A high density plasma chemical vapor deposition (HDPCVD) process is used to either partially or fully fill the trench. Any oxide on the top surface of the p-layer is then removed, such as by using a chemical mechanical polishing step. Then, an isotropic etching step, such as a wet etch, is used to remove the silicon dioxide from the trench, while leaving a thick bottom oxide at the bottom of the trench. The HDPCVD process utilizes minimal thermal budget to form the thick bottom oxide. | 03-10-2011 |
| 20110147835 | SEMICONDUCTOR DEVICES HAVING REDUCED GATE-DRAIN CAPACITANCE - Embodiments of a semiconductor device include a semiconductor substrate having a first surface and a second surface opposed to the first surface, a trench formed in the semiconductor substrate and extending from the first surface partially through the semiconductor substrate, a gate electrode material deposited in the trench, and a void cavity in the semiconductor substrate between the gate electrode material and the second surface. A portion of the semiconductor substrate is located between the void cavity and the second surface. | 06-23-2011 |
| 20110204440 | Shielded gate trench (SGT) mosfet devices and manufacturing processes - This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one of the cells constituting an active cell has a source region disposed next to a trenched gate electrically connecting to a gate pad and surrounding the cell. The trenched gate further has a bottom-shielding electrode filled with a gate material disposed below and insulated from the trenched gate. At least one of the cells constituting a source-contacting cell surrounded by the trench with a portion functioning as a source connecting trench is filled with the gate material for electrically connecting between the bottom-shielding electrode and a source metal disposed directly on top of the source connecting trench. The semiconductor power device further includes an insulation protective layer disposed on top of the semiconductor power device having a plurality of source openings on top of the source region and the source connecting trench provided for electrically connecting to the source metal and at least a gate opening provided for electrically connecting the gate pad to the trenched gate. | 08-25-2011 |
| 20120146137 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTORDEVICE - A semiconductor device according to the present invention includes a semiconductor layer. A first conductivity type region is formed on a base layer portion of the semiconductor layer. A body region of a second conductivity type is formed on the semiconductor layer to be in contact with the first conductivity type region. A trench in which a gate electrode is embedded through a gate insulating film is formed on the semiconductor layer. The trench penetrates through the body region, so that a deepest portion thereof reaches the first conductivity type region. A source region of the first conductivity type is formed on a surface layer portion of the semiconductor layer around the trench. The gate insulating film includes a thick-film portion having a relatively large thickness on a bottom surface of the trench. | 06-14-2012 |
| 20120168860 | TRANSISTOR AND METHOD FOR FORMING THE SAME - The invention provides a method for forming a transistor, which includes: providing a substrate, a semiconductor layer being formed on the substrate; forming a dummy gate structure on the semiconductor layer; forming a source region and a drain region in the substrate and the semiconductor layer and at opposite sides of the dummy gate structure; forming an interlayer dielectric layer on the semiconductor layer; removing the dummy gate structure for forming an opening in the interlayer dielectric layer; non-crystallizing the semiconductor layer exposed in the opening for forming a channel layer; annealing the channel layer so that the channel layer and the substrate have same crystal orientation; and forming a metal gate structure in the opening, the metal gate being formed on the channel layer. Saturation current of the transistor is raised, and the performance of a semiconductor device is promoted. | 07-05-2012 |
| 20120319198 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device including a substrate, a spacer and a high-k dielectric layer having a U-shape profile is provided. The spacer located on the substrate surrounds and defines a trench. The high-k dielectric layer having a U-shape profile is located in the trench, and the high-k dielectric layer having a U-shape profile exposes an upper portion of the sidewalls of the trench. | 12-20-2012 |
| 20130240988 | TRANSISTORS COMPRISING HIGH-K METAL GATE ELECTRODE STRUCTURES AND EMBEDDED STRAIN-INDUCING SEMICONDUCTOR ALLOYS FORMED IN A LATE STAGE - In sophisticated semiconductor devices, replacement gate approaches may be applied in combination with a process strategy for implementing a strain-inducing semiconductor material, wherein superior proximity of the strain-inducing semiconductor material and/or superior robustness of the replacement gate approach may be achieved by forming the initial gate electrode structures with superior uniformity and providing at least one cavity for implementing the strained channel regions in a very advanced manufacturing stage, i.e., after completing the basic transistor configuration. | 09-19-2013 |
| 20130277737 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a gate metal buried within a trench included in a semiconductor substrate including an active region defined by an isolation layer, a spacer pattern disposed on an upper portion of a sidewall of a gate metal, a first gate oxide layer disposed between the spacer pattern and the trench, a second gate oxide layer disposed below the first gate oxide layer and the gate metal, and a junction region disposed in the active region to overlap the first gate oxide layer. | 10-24-2013 |
| 20130341712 | TRENCH SHIELDING STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHOD - A shielding structure for a semiconductor device includes a plurality of trenches. The trenches include passivation liners and shield electrodes, which are formed therein. In one embodiment, the shielding structure is placed beneath a control pad. In another embodiment, the shielding structure is placed beneath a control runner. | 12-26-2013 |
| 20140061783 | SUPER-JUNCTION DEVICE AND METHOD OF FORMING THE SAME - A super-junction device including a unit region is disclosed. The unit region includes a heavily doped substrate; a first epitaxial layer over the heavily doped substrate; a second epitaxial layer over the first epitaxial layer; a plurality of first trenches in the second epitaxial layer; an oxide film in each of the plurality of first trenches; and a pair of first films on both sides of each of the plurality of first trenches, thereby forming a sandwich structure between every two adjacent ones of the plurality of first trenches, the sandwich structure including two first films and a second film sandwiched therebetween, the second film being formed of a portion of the second epitaxial layer between the two first films of a sandwich structure. A method of forming a super-junction device is also disclosed. | 03-06-2014 |
| 20140346592 | SEMICONDUCTOR DEVICE - A vertical MOSFET includes: a semiconductor substrate comprising a drain layer, a drift layer, a body layer, and a source layer; and a trench gate penetrating through the source layer and the body layer from an upper surface of the semiconductor substrate and reaching the drift layer. The trench gate includes a gate electrode; a first insulating film disposed on a bottom surface of a trench formed in the semiconductor substrate; a second insulating film disposed at least on a side surface of the trench, and in contact with the body layer; and a third insulating film disposed between the gate electrode and the second insulating film, and formed of a material of which dielectric constant is higher than a dielectric constant of the second insulating film. | 11-27-2014 |
| 20160380096 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer. A first conductivity type region is formed on a base layer portion of the semiconductor layer. A body region of a second conductivity type is formed on the semiconductor layer to be in contact with the first conductivity type region. A trench in which a gate electrode is embedded through a gate insulating film is formed on the semiconductor layer. The trench penetrates through the body region, so that a deepest portion thereof reaches the first conductivity type region. A source region of the first conductivity type is formed on a surface layer portion of the semiconductor layer around the trench. The gate insulating film includes a thick-film portion having a relatively large thickness on a bottom surface of the trench. | 12-29-2016 |
| 20190148542 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | 05-16-2019 |
