| Entries |
| Document | Title | Date |
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| 20080197392 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device has bit lines, capacitors, bit contacts and capacitor contacts, wherein the bit lines are provided over a semiconductor substrate, the bit lines are connected to the semiconductor substrate through the bit contacts, the capacitors are connected to the semiconductor substrate through the capacitor contacts, and wherein in two adjacent bit lines, pitch d | 08-21-2008 |
| 20080203453 | SEMICONDUCTOR STRUCTURES AND MEMORY DEVICE CONSTRUCTIONS - The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions can be provided in pairs, with one of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The source/drain regions extending to the digit line can have the same composition as the source/drain regions extending to the memory storage devices, or can have different compositions from the source/drain regions extending to the memory storage devices. The invention also includes methods of forming semiconductor structures. In exemplary methods, a lattice comprising a first material is provided to surround repeating regions of a second material. At least some of the first material is then replaced with a gateline structure, and at least some of the second material is replaced with vertical source/drain regions. | 08-28-2008 |
| 20080210999 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor substrate; a memory cell selection transistor that is formed on the semiconductor substrate and has a source and a drain; a contact plug; a polysilicon interlayer film that is formed above the memory cell selection transistor and has a cylinder-shaped through-hole; and a storage capacity part that is formed in the through-hole and is connected to the source and the drain of the memory cell selection transistor via the contact plug, wherein a boundary between a bottom and a side wall of the through-hole has a curved surface. | 09-04-2008 |
| 20080211000 | Semiconductor device having transistors each having gate electrode of different metal ratio and production process thereof - A semiconductor device with integrated MIS field-effect transistors includes a first transistor containing a first gate electrode having a composition represented by MAx and a second transistor containing a second gate electrode having a composition represented by MAy, wherein M is at least one metal element selected from the group consisting of W, Mo, Ni, Pt, Ta, Pd, Co and Ti; A is silicon and/or germanium; 0| 09-04-2008 | |
| 20080217670 | Methods of manufacturing a semiconductor device; method of manufacturing a memory cell; semiconductor device; semiconductor processing device; integrated circuit having a memory cell - Methods of manufacturing a semiconductor device, a method of manufacturing a memory cell, a semiconductor device, a semiconductor processing device, and a memory cell, are provided. In one embodiment a method of manufacturing a semiconductor device is provided including forming a metal doped chalcogenide layer using light irradiation at least partially during provision of the metal. | 09-11-2008 |
| 20080224196 | SEMICONDUCTOR DEVICE AND MANUFACTURING PROCESS FOR THE SAME - A semiconductor device includes a first inverter, a second inverter, and an inner wiring connecting the inverters, in which the inner wiring forms a capacitor element, and the capacitor element includes an interlayer insulation film having an aperture on a semiconductor substrate, a lower electrode covering a bottom wall and a side wall of the aperture, the bottom wall being the semiconductor substrate and the side wall being a part of the interlayer insulation film, a capacitor insulation film arranged on the lower electrode and a part of the interlayer insulation film, the capacitor insulation film covering corners of the capacitor insulation film, the corners being situated at opposite side of the semiconductor substrate, and an upper electrode on the capacitor insulation film, the upper electrode covering the aperture. | 09-18-2008 |
| 20080230820 | SEMICONDUCTOR DEVICE - Coexistence of the realization of high-capacity of a capacitive element and the area reduction of a semiconductor device is aimed at. A plurality of capacitive elements from which a kind differs mutually are accumulated and arranged on a semiconductor substrate, and they are connected in parallel. These capacitive elements are arranged to the same plane region, and make a plane size almost the same. A lower capacitive element is an MOS type capacitive element which uses as both electrodes the n-type semiconductor region formed in the semiconductor substrate, and the upper electrode formed via the insulation film on the n-type semiconductor region. The MIM type capacitive element formed with the pattern of the comb-type of a wiring is arranged in the upper part of a lower capacitive element, and this is connected with a lower capacitive element in parallel. | 09-25-2008 |
| 20080230821 | Semiconductor device - In a semiconductor device which can perform data communication through wireless communication, to suppress transmission and the like of an AC signal, the semiconductor device includes an input circuit to which a radio signal is input, a first circuit, which generates a constant voltage, such as a constant voltage circuit or a limiter circuit, a second circuit to which the generated constant voltage is input and which can change impedance of the semiconductor device, and a filter provided between the first circuit and the second circuit. Transmission of an AC signal is suppressed by the filter, and malfunctions or operation defects such as complete inoperative due to variation in the constant voltage is prevented. | 09-25-2008 |
| 20080237672 | High density memory - In one embodiment of the invention, a method of forming a semiconductor device includes forming a dynamic random access memory using spacer-defined lithography. | 10-02-2008 |
| 20080246067 | Dram device and method of manufacturing the same - In a DRAM device and a method of manufacturing the same, a multiple tunnel junction (MTJ) structure is provided, which includes conductive patterns and nonconductive patterns alternately stacked on each other. The nonconductive patterns have a band gap larger than a band gap of the conductive patterns. A gate insulation layer and a gate electrode are formed on a sidewall of the MTJ structure. A word line is connected with the MTJ structure, and a bit line is connected with one of top and bottom surfaces of the MTJ structure. A capacitor is connected with one of top and bottom surfaces of the MTJ structure that is not connected with the bit line. Current leakage in the DRAM device is reduced and a unit cells may be vertically stacked on the substrate, so a smaller surface area of the substrate is required for the DRAM device. | 10-09-2008 |
| 20080251824 | Semiconductor memory device and manufacturing method thereof - A semiconductor memory device and a manufacturing method thereof are provided which enable cell-contact plugs to be formed at high yields and the yields of semiconductor memory devices to be improved in the manufacturing process. The semiconductor memory device includes: a semiconductor substrate; MOS transistors which are formed on a surface of the semiconductor substrate; a cell-contact plug which is made of poly-silicon film, is located between gates of the MOS transistors, and is connected to a source or a drain of one of the MOS transistors; a pad metal layer which is formed on the cell-contact plug; an interlayer dielectric film which is formed on the pad metal layer; a storage capacitor which is formed on the interlayer dielectric film; and a contact plug which is formed inside an opening which penetrates the interlayer dielectric film, and connects the storage capacitor with the pad metal layer. | 10-16-2008 |
| 20080258196 | SEMICONDUCTOR STRUCTURE OF A DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor structure of a display device and the method for fabricating the same are provided. The semiconductor structure is formed on a substrate having a TFT region and a pixel capacitor region thereon. A TFT, including a gate electrode, a source electrode, a drain electrode, a channel layer, and a gate insulating layer, is formed on the TFT region of the substrate. A pixel capacitor is formed on the pixel capacitor region, wherein the pixel capacitor comprises a bottom electrode formed on a bottom dielectric layer, an interlayer dielectric layer formed on the bottom electrode, a top electrode formed on the interlayer dielectric layer, a contact plug passing through the interlayer dielectric layer and electrically connected to the top and bottom electrodes, a capacitor dielectric layer formed on the top electrode, a transparent electrode formed on the capacitor dielectric layer and electrically connected to the drain electrode. | 10-23-2008 |
| 20080277707 | SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF - It is an object of the invention to provide a digital circuit which can operate normally regardless of binary potentials of an input signal. A semiconductor device having a correcting unit and a logic unit wherein the correcting unit includes a capacitor, first and second switches, wherein the first electrode of the capacitor is connected to the input terminal and the second electrode of the capacitor is connected to the gate of the transistor in the logic circuit, wherein the first switch controls the connection between a gate and drain of the transistor and the second switch controls the potential to be supplied to the drain of the transistor is provided. | 11-13-2008 |
| 20080277708 | SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - A highly integrated semiconductor device has a device isolation layer demarcating a first active region in a first region of a substrate, and a second active region in a second region of the substrate. A first gate pattern and a second gate pattern are formed on the first active region and the second active region, respectively. A first spacer layer and a second spacer layer are formed over the gate patterns. Then, the second and first spacer layers in the first region are anisotropically etched to form a gate spacer on sidewalls of the first gate pattern. The gate spacer has a lower spacer section formed from the first spacer layer and an upper spacer section formed from the second spacer layer. Then, ions are implanted into the first active region. Subsequently, the upper spacer section and the second spacer layer on the first and second regions, respectively, are removed. A selective growth process is then performed to form a buffer insulating layer on the first active region beside the lower spacer sections. An etch stop layer and an interlayer dielectric may be then formed on the substrate. | 11-13-2008 |
| 20080283889 | SEMICONDUCTOR DEVICE - The present invention aims to enhance the reliability of a semiconductor device having first through fourth capacitive elements. The first through fourth capacitive elements are disposed over a semiconductor substrate. A series circuit of the first and second capacitive elements and a series circuit of the third and fourth capacitive elements are coupled in parallel between first and second potentials. Lower electrodes of the first and third capacitive elements are respectively formed by a common conductor pattern and coupled to the first potential. Lower electrodes of the second and fourth capacitive elements are respectively formed by a conductor pattern of the same layer as the above conductor pattern and coupled to the second potential. Upper electrodes of the first and second capacitive elements are respectively formed by a common conductor pattern and brought to a floating potential. Upper electrodes of the third and fourth capacitive elements are respectively formed by a conductor pattern of the same layer as the above conductor pattern and brought to a floating potential, but not coupled to the upper electrodes of the first and second capacitive elements by a conductor. | 11-20-2008 |
| 20080303075 | METHOD FOR FORMING ELEMENT ISOLATION STRUCTURE OF SEMICONDUCTOR DEVICE, ELEMENT ISOLATION STRUCTURE OF SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR MEMORY DEVICE - A method for forming an element isolation structure of a semiconductor device, includes: a trench forming step of forming a trench on a semiconductor substrate; and a laminating step of forming alternately multilayered film in the trench by sequentially and alternately laminating a plurality of first insulating films that apply tensile stress to the semiconductor substrate and a plurality of second insulating films that apply compression stress to the semiconductor substrate so that the trench is filled with the alternately multilayered film. | 12-11-2008 |
| 20090001436 | Memory device - Disclosed is a memory device having a transistor, the transistor including a substrate; a gate electrode formed on the substrate; an insulation layer formed on the gate electrode, the gate electrode and the insulation layer forming a convex portion; a conductive layer formed at a top of the convex portion; a source electrode formed on one side of the convex portion on the substrate; a drain electrode formed on the other side of the convex portion on the substrate where the source electrode is not formed; and a semiconductor layer formed on the insulation layer existing between the conductive layer and the source electrode and between the conductive layer and the drain electrode. | 01-01-2009 |
| 20090014765 | High voltage operating field effect transistor, bias circuit therefor and high voltage circuit thereof - A high voltage operating field effect transistor has a source region and a drain region spaced apart from each other in a surface of a substrate. The source region is operative to receive at least one of a signal electric potential and a signal current. A semiconductor channel formation region is disposed in the surface of the substrate between the source region and the drain region. A gate region is disposed above the channel formation region and is operative to receive a bias electric potential having an absolute value equal to or larger than a first constant electric potential which changes according to an increase or decrease in a drain electric potential. A gate insulating film region is disposed between the channel formation region and the gate region. | 01-15-2009 |
| 20090026515 | Semiconductor memory device and method of forming the same - Example embodiments relate to a semiconductor memory device and a method of forming the semiconductor memory device. The semiconductor memory device may include a first interlayer insulating layer on a semiconductor substrate. A bit line may be arranged in a first direction on the first interlayer insulating layer. A bit line contact pad may be disposed in the first interlayer insulating layer and electrically connected to the bit line. A storage contact pad may be disposed in the first interlayer insulating layer. A top surface of the bit line contact pad may be lower than a top surface of the storage contact pad. | 01-29-2009 |
| 20090039402 | SEMICONDUCTOR DEVICE WITH ASYMMETRIC TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A semiconductor device with an asymmetric transistor and a method for fabricating the same are provided. The semiconductor device includes: a substrate having a plurality of first active regions, at least one second active region, and a plurality of device isolation regions; gate patterns formed in a step structure over a border region between individual first active regions and second active region, wherein one side of the individual gate pattern is formed over a portion of the individual first active region, and the other side of the individual gate pattern is formed over a portion of the second active region; spacers formed on lateral walls of the gate patterns; first cell junction regions formed in the first active regions, for connecting to storage nodes; and a second cell junction region formed in the second active region, for connecting to a bit line. | 02-12-2009 |
| 20090045444 | INTEGRATED DEVICE AND CIRCUIT SYSTEM - An integrated circuit, comprising a substrate stack, comprising a first substrate and a second substrate, the first substrate comprising a first contact field on a side face of the substrate stack and the second substrate comprising a second contact field on the side face; a side substrate, comprising a first contact pad and a second contact pad, the first contact pad being coupled to the second contact pad; first connection, connecting the first contact field and the first contact pad; and a second connection, connecting the second contact field and the second contact pad. | 02-19-2009 |
| 20090057738 | CAPACITOR FOR SEMICONDUCTOR DEVICE - A capacitor for a semiconductor device having a dielectric film between an upper electrode and a lower electrode is featured in that the dielectric film includes an alternately laminated film of hafnium oxide and titanium oxide at an atomic layer level. | 03-05-2009 |
| 20090057739 | Ge channel device and method for fabricating ge channel device - The Ge channel device comprises: a Ge channel layer ( | 03-05-2009 |
| 20090065835 | Capacitorless DRAM and methods of manufacturing and operating the same - Example embodiments provide a capacitorless dynamic random access memory (DRAM), and methods of manufacturing and operating the same. The capacitorless DRAM according to example embodiments may include a semiconductor layer separated from a top surface of a substrate and that contains a source region, a drain region, and a channel region, a charge reserving layer formed on the channel region, and a gate formed on the substrate to contact the channel region and the charge reserving layer. | 03-12-2009 |
| 20090065836 | SEMICONDUCTOR DEVICE HAVING MIM CAPACITOR AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having an MIM capacitor and a method of manufacturing the same. In one example embodiment, a semiconductor device having an MIM capacitor includes a lower electrode including a pair of metal patterns spaced apart from each other, a dielectric formed so as to cover the surfaces of the spaced-apart metal patterns of the lower electrode, a metal plug formed on the dielectric, and an upper electrode made of a metal and formed on the metal plug. | 03-12-2009 |
| 20090065837 | SEMICONDUCTOR MEMORY DEVICE HAVING CAPACITOR FOR PERIPHERAL CIRCUIT - Provided is a semiconductor memory device having peripheral circuit capacitors. In the semiconductor memory device, a first node is electrically connected to a plurality of lower electrodes of a plurality of capacitors in a peripheral circuit region to connect at least a portion of the capacitors in parallel. A second node is electrically connected to a plurality of upper electrodes of the capacitors in the peripheral circuit region to connect at least a portion of the capacitors in parallel. The first node is formed at substantially the same level as a bit line in a cell array region and is formed of the same material used to form the bit line. | 03-12-2009 |
| 20090072288 | Terraced Film Stack - A process and apparatus directed to forming a terraced film stack of a semiconductor device, for example, a DRAM memory device, is disclosed. The present invention addresses etch undercut resulting from materials of different etch selectivity used in the film stack, which if not addressed can cause device failure. | 03-19-2009 |
| 20090078980 | Method for Producing an Integrated Circuit, Integrated Circuit, DRAM Device and Memory Module - A method for producing an integrated circuit is disclosed. The integrated circuit includes an insulating material and a semiconducting material adjacent the insulating material. The semiconducting material is partially removed and the surface of the partially removed semiconducting material is treated. The insulating material is partially removed. | 03-26-2009 |
| 20090085081 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device with high response speed and high reliability. In the method for manufacturing a semiconductor device of the invention, a bonding layer is formed over a substrate, an insulating film and a storage capacitor portion lower electrode are formed over the bonding layer, a single crystal silicon layer is formed over the insulating film, a storage capacitor portion insulating film is formed over the storage capacitor portion lower electrode, a wiring is formed over the storage capacitor portion insulating film, a channel forming region and a low concentration impurity region are formed over the single crystal silicon layer, and a gate insulating film and a gate electrode are formed over the single crystal silicon layer. The storage capacitor portion insulating film is formed by depositing a YSZ film with a single crystal silicon layer used as a base film, whereby the permittivity increases and thus the leakage current from the storage capacitor portion is suppressed. | 04-02-2009 |
| 20090090946 | DRAM CELL WITH MAGNETIC CAPACITOR - A DRAM cell includes a substrate, a transistor, and a magnetic capacitor. The substrate is composed of semiconductor material with a main surface, the transistor is formed at the main surface, and the magnetic capacitor is formed in a metal layer. The transistor includes a source region and a drain region formed at the main surface of the substrate. The transistor also includes a control gate placed between the source region and the drain region, and separated from the substrate by a thin control dielectric. The magnetic capacitor includes a first electrode layer, a dielectric layer formed on the surface of the first electrode layer, and a second electrode layer formed on the surface of the dielectric layer. The DRAM cell increases the density, simplifies the manufacturing process, and reduces or eliminates the refresh rate. A DRAM cell with the magnetic capacitor formed in multiple layers is also provided. | 04-09-2009 |
| 20090090947 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate having a first area and a second area, a first active structure disposed in the first area, a second active structure disposed in the second area, a first transistor disposed in the first area and a second transistor disposed in the second area. The second active structure may have a height substantially the same as a height of the first active structure. The first transistor includes a first gate structure enclosing an upper portion of the first active structure, a first impurity region formed at a lower portion of the first active structure, and a second impurity region formed at the upper portion of the first active structure. The second transistor includes a second gate structure formed on the second active structure and third impurity regions formed at an upper portion of the second active structure. | 04-09-2009 |
| 20090090948 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - In a semiconductor device comprising a capacitive element, an area of the capacitive element is reduced without impairing performance, and further, without addition of an extra step in a manufacturing process. A first capacitor is formed between an active region of a semiconductor substrate provided through a first capacitive insulating film and a lower electrode comprised of a conductor film in the same layer as a select gate electrode of a select, a second capacitor is formed between the lower electrode, and an upper electrode comprised of a conductor film in the same layer as a memory gate electrode of a memory, provided through the second capacitive insulating film in the same layer as the insulating films of a multi-layer structure, including a charge storage layer, and a stacking-type capacitive element is comprised of the first capacitor and the second capacitor, wherein a planar shape of the lower electrode is a grid-like shape having a plurality of lengths of linear conductor films each having a first width, formed along a first direction with a first interval provided therebetween, and a plurality of lengths of linear conductor films each having a second width, formed along a second direction (the direction intersecting the first direction) with a second interval provided therebetween. | 04-09-2009 |
| 20090090949 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: an active region insulated by an element-isolation insulating film embedded on a semiconductor substrate; multiple element forming sections that are provided in the active region; a semiconductor element that is formed in each of the element forming sections; and a channel stopper that is provided in the active region to insulate the element forming sections from each other. The channel stopper comprises: a fin that protrudes between grooves provided in the element-isolation insulating film and on both sides of the active region; a dummy-gate insulating film that covers the fin; and a dummy gate electrode that straddles the fin. | 04-09-2009 |
| 20090095995 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode. | 04-16-2009 |
| 20090095996 | Semiconductor device - A semiconductor device includes a substrate including an active region, a first impurity region, second impurity regions, a word line and a bit line. The active region has end portions extending in a first direction and a central portion extending in a second direction inclined relative to the first direction. The first impurity region is disposed at the central portion, and the second impurity regions are disposed at the end portions. The word line extends in a third direction substantially perpendicular to the first direction. The bit line extends in the first direction. The bit line is electrically connected to the first impurity region. The second impurity regions may be symmetrical to each other centering adjacent two word lines and adjacent one bit line. The semiconductor device may have improved sensing margin by reducing the capacitance of the bit line. | 04-16-2009 |
| 20090095997 | EPITAXIAL SILICON GROWTH - Memory cell structures, including PSOIs, NANDs, NORs, FinFETs, etc., and methods of fabrication have been described that include a method of epitaxial silicon growth. The method includes providing a silicon layer on a substrate. A dielectric layer is provided on the silicon layer. A trench is formed in the dielectric layer to expose the silicon layer, the trench having trench walls in the <100> direction. The method includes epitaxially growing silicon between trench walls formed in the dielectric layer. | 04-16-2009 |
| 20090101955 | MOLECULAR ELECTRONIC DEVICE AND METHOD OF FABRICATING THE SAME - A molecular electronic device, and a method of fabricating the same, includes a first electrode having a plurality of prominences and depressions on which a plurality of molecules are self-assembled. Capacitance of a molecular electronic device used as a capacitor is increased by forming prominences and depressions on the surface of the first electrode thereby enabling more molecules to be self-assembled on the surface of the lower electrode. | 04-23-2009 |
| 20090114966 | DRAM DEVICE HAVING A GATE DIELECTRIC LAYER WITH MULTIPLE THICKNESSES - A transistor device employed in a support circuit of a DRAM includes a semiconductor substrate having thereon a gate trench, a recessed gate embedded in the gate trench, a source doping region disposed at one side of the recessed gate, a drain doping region disposed at the other side of the recessed gate, and a gate dielectric layer between the recessed gate and the semiconductor substrate. The gate dielectric layer has at least two thicknesses that render the high-voltage transistor device asymmetric. The thicker gate dielectric layer is between the recessed gate and the drain doping region, while the thinner gate dielectric layer is between the recessed gate and the source doping region. | 05-07-2009 |
| 20090114967 | TRANSISTORS HAVING A CHANNEL REGION BETWEEN CHANNEL-PORTION HOLES AND METHODS OF FORMING THE SAME - According to some embodiments of the invention, transistors have channel regions between channel-portion holes. Methods of forming the same include at least two channel-portion holes disposed in a semiconductor substrate. Line patterns are formed in parallel to be spaced apart from each other on a main surface of the semiconductor substrate to fill the channel-portion holes. A channel region is disposed in the semiconductor substrate below the line patterns. At this time, the channel region is formed between the channel-portion holes and also covers lower portions of the channel-portion holes. Driving current capability and refresh characteristics of DRAMs utilizing the inventive transistors are improved. | 05-07-2009 |
| 20090121268 | Semiconductor Memory Devices Having Vertical Channel Transistors and Related Methods - A semiconductor memory device may include a semiconductor substrate with an active region extending in a first direction parallel with respect to a surface of the semiconductor substrate. A pillar may extend from the active region in a direction perpendicular with respect to the surface of the semiconductor substrate with the pillar including a channel region on a sidewall thereof. A gate insulating layer may surround a sidewall of the pillar, and a word line may extend in a second direction parallel with respect to the surface of the semiconductor substrate. Moreover, the first and second directions may be different, and the word line may surround the sidewall of the pillar so that the gate insulating layer is between the word line and the pillar. A contact plug may be electrically connected to the active region and spaced apart from the word line, and a bit line may be electrically connected to the active region through the contact plug with the plurality of bit lines extending in the first direction. Related methods are also discussed. | 05-14-2009 |
| 20090127605 | Semiconductor device and method for manufacturing the same - A semiconductor device includes: n transistor elements; n resistive elements; and n capacitive elements, each kind of elements coupled in series between the first and second terminals. The gate of each transistor element has a gate pad, and each transistor element includes transistor pads disposed on both sides. Each resistive element includes resistive pads disposed on both sides. Each capacitive element includes capacitive pads disposed on both sides. The gate pad other than the first stage transistor element, a corresponding resistive pad, and a corresponding capacitive pad are electrically coupled. One transistor pad, one resistive pad, and one capacitive pad in the first stage are electrically coupled. One transistor pad, one resistive pad, and one capacitive pad in the n-th stage are electrically coupled. | 05-21-2009 |
| 20090127606 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A driving circuit and a bus to transmit an output signal from the driving circuit are provided. The driving circuit includes a first P-channel transistor, a second P-channel transistor, an N-channel transistor and a capacitor. The first P-channel transistor includes a drain, a source to connect with a higher potential and a gate to receive a first input signal. The second P-channel transistor includes a drain connected to the bus, a source connected to the drain of the first P-channel transistor and a gate to receive a second input signal. The N-channel transistor includes a drain connected to the drain of the second P-channel transistor, a source to connect with a lower potential and a gate to receive the second input signal. The capacitor includes one end connected to the drain of the first P-channel transistor and another end to connect with the lower potential. | 05-21-2009 |
| 20090127607 | SEMICONDUCTOR DEVICE INCLUDING A TCAM HAVING A STORAGE ELEMENT FORMED WITH A DRAM - In order to improve the discharging speed of potential from a match line, a semiconductor device includes a capacitor, a memory transistor having a source/drain region connected to a storage node of the capacitor, a search transistor having a gate electrode connected to the storage node, and a stacked contact connecting a match line and the source/drain region of the search transistor. The storage node has a configuration in which a sidewall of the storage node facing the match line partially recedes away from the stacked contact such that a portion of the sidewall in front of the stacked contact in plan view along the direction of the match line is located farther away from the stacked contact than the remaining portion of the sidewall. | 05-21-2009 |
| 20090134441 | INTEGRATED ELECTRONIC CIRCUIT INCORPORATING A CAPACITOR - A non-volatile memory element includes a transistor for selecting the element and a capacitor for recording a binary value by electrical breakdown of an insulating layer of the capacitor. A structure of the memory element is modified in order to allow a higher degree of integration of the element within an electronic circuit of the MOS type. In addition, the memory element is made more robust with respect to a high electrical voltage (VDD) used for recording the binary value. The transistor includes a drain in the substrate with electric field drift in a longitudinal direction extending towards the capacitor. The electric field drift region for the drain includes a first extension underneath the gate of the transistor opposite the source and a second extension underneath the insulating layer of the capacitor. Doping of the substrate for the electric field drift region is limited to a region substantially corresponding to a distance between the gate and an electrode of the capacitor. | 05-28-2009 |
| 20090140307 | CONDUCTIVE LINE COMPRISING A CAPPING LAYER - An integrated circuit includes a conductive line, the conductive line having a conductive layer made of a metal or a first compound including a metal and a capping layer made of a second compound comprising the metal, the capping layer being in contact with the conductive layer, the first compound being different from the second compound. | 06-04-2009 |
| 20090140308 | Semiconductor device having capacitor formed on plug, and method of forming the same - A semiconductor device includes a silicon substrate, a capacitor element having a lower electrode, a capacitor dielectric film, a TiN film, and a W film, and an interlayer insulation film covering the end and a portion of the upper surface of the lower electrode and disposed with a concave portion at a position corresponding to the lower electrode. The lower electrode is disposed selectively at the bottom of the concave portion, the upper surface of the lower electrode is exposed from the interlayer insulation film in the region for forming the concave portion, the side wall for the concave portion of the interlayer insulation film situates to the inner side of the lower electrode from the end of the lower electrode, and the capacitor dielectric film is disposed so as to cover the upper surface of the lower electrode and cover the interlayer insulation from the side wall for the concave portion to the upper surface of the interlayer insulation film. | 06-04-2009 |
| 20090140309 | SEMICONDUCTOR DEVICE WITH LESS POWER SUPPLY NOISE - A semiconductor device includes a first power supply line; a second power supply line; a first cell arrangement area in which a first cell is arranged; and a switch area in which a switching transistor and a decoupling capacitance are arranged. The first cell is provided in a first well of a first conductive type, the switching transistor is provided in a second well of the first conductive type, and the decoupling capacitance is provided in a separation area of a second conductive type to separate the first well and the second well from each other. The switching transistor connects the first power supply line and the second power supply line in response to a control signal, the first cell operates with power supplied from the second power supply line, and the decoupling capacitance is connected with the first power supply line. | 06-04-2009 |
| 20090152608 | DRAM Cell Transistor Device and Method - A method for forming a memory device. The method provides a protective layer overlying a surface region of a substrate before threshold voltage implant. The method then includes depositing a photo resist layer and patterning the photo resist by selectively removing a portion of the photo resist to expose the protective layer overlying a first region while maintaining the photo resist overlying a second region. The method includes implanting impurities for threshold voltage adjustment into the first region while the second region is substantially free of the impurities for threshold voltage adjustment. The method also includes forming a source region and a drain region. The method further includes providing a conductive structure over the source region. A junction between the conductive structure and the source region is substantially within the second region. The method then provides a storage capacitor in electrical contact with the source region via the conductive structure. | 06-18-2009 |
| 20090152609 | Semiconductor integrated circuit device - A semiconductor integrated circuit device which is formed on an area comprises a first storage node which is formed on a first area having a first conductive type of the area, the first storage node having a first level, a second storage node which is formed on a second area having second conductive type of the area, the second storage node having a second level opposite to the first level and a well boundary which is sandwiched between the first area and the second area, wherein the second storage node has two diagonal lines, thereby, the first area having a first part sandwiched between the diagonal lines extended from the second storage node through the well boundary, and a second part which is the other part of the first part, wherein the first storage node is placed outside a region between the extended lines of two diagonal lines extending from the second storage node to the well boundary direction, and wherein the second storage node is placed outside a region between the extended lines of two diagonal lines extending from the first storage node to the well boundary direction. | 06-18-2009 |
| 20090152610 | SEMICONDUCTOR MEMORY DEVICE - This disclosure concerns a semiconductor memory device including bit lines; word lines; semiconductor layers arranged to correspond to crosspoints of the bit lines and the word lines; bit line contacts connecting between a first surface region and the bit lines, the first surface region being a part of a surface region of the semiconductor layers directed to the word lines and the bit lines; and a word-line insulating film formed on a second surface region adjacent to the first surface region, the second surface region being a part of out of the surface region, the word-line insulating film electrically insulating the semiconductor layer and the word line, wherein the semiconductor layer, the word line and the word-line insulating film form a capacitor, and when a potential difference is given between the word line and the bit line, the word-line insulating film is broken in order to store data. | 06-18-2009 |
| 20090152611 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device comprises a first contact plug, a first structure and a second insulating layer, or comprises a first contact plug, a first structure, a protruding region and a second insulating layer. The first contact plug extends in a predetermined direction and including a step converting a cross section area of the first contact plug perpendicular to the predetermined direction discontinuously via the step in one end side. The second insulating layer is formed on side surface of a part of the first contact plug closer to the first structure than the step, or on side surfaces of the protruding region and a part of the first contact plug closer to the first structure than the step. | 06-18-2009 |
| 20090152612 | HIGH YIELD, HIGH DENSITY ON-CHIP CAPACITOR DESIGN - A capacitance circuit assembly mounted on a semiconductor chip, and methods for forming the same, are provided. A plurality of divergent capacitors is provided in a parallel circuit connection between first and second ports, the plurality providing at least one Metal Oxide Silicon Capacitor and at least one Vertical Native Capacitor or Metal-Insulator-Metal Capacitor. An assembly has a vertical orientation, a Metal Oxide Silicon capacitor located at the bottom and defining a footprint, with a middle Vertical Native Capacitor having a plurality of horizontal metal layers, including a plurality of parallel positive plates alternating with a plurality of parallel negative plates. In another aspect, vertically asymmetric orientations provide a reduced total parasitic capacitance. | 06-18-2009 |
| 20090159946 | Logic Non-Volatile Memory Cell with Improved Data Retention Ability - A memory cell includes a semiconductor substrate; and a first, a second, and a third transistor. The first transistor includes a first dielectric over the semiconductor substrate; and a first floating gate over the first dielectric. The second transistor is electrically coupled to the first transistor and includes a second dielectric over the semiconductor substrate; and a second floating gate over the second dielectric. The first and the second floating gates are electrically disconnected. The memory cell further includes a first capacitor; a second capacitor electrically coupled to the first capacitor; a third capacitor; a fourth capacitor electrically coupled to the third capacitor, wherein each of the first, the second, the third and the fourth capacitors includes the semiconductor substrate as one of the capacitor plates. The third transistor is a selector of the memory cell and is electrically coupled to the first and the second transistors. | 06-25-2009 |
| 20090166697 | Semiconductor Device and Method of Fabricating the Same - Disclosed are a semiconductor device and method of fabricating the same. The semiconductor device includes a floating gate on a semiconductor layer; a first contact on the floating gate; a MIM capacitor including a lower electrode, an insulating layer, and an upper electrode on the first contact; a second contact on a drain region of the semiconductor layer; a metal island on the second contact; a via on the metal island; and a bit line on the via. | 07-02-2009 |
| 20090166698 | CAPACITOR AND METHOD OF MANUFACTURING THE SAME - A capacitor with a mixed structure of a Metal Oxide Semiconductor (MOS) capacitor and a Poly-silicon Insulator Poly-silicon (PIP) capacitor includes a substrate and a diffusion junction region formed over the substrate. A high concentration diffusion junction region may be formed in a portion of the diffusion junction region. An oxide layer may be formed over the substrate, the oxide layer having an opening that exposes a portion of the high concentration diffusion junction region. A first polysilicon plate may be formed over a portion of the oxide layer and spaced from the opening, and a nitride layer may be formed over a portion of the first polysilicon plate. A sidewall may be formed over a side of the first polysilicon layer, over a side of the nitride layer, and over a portion of the oxide layer between the side of the polysilicon layer and the opening. A second polysilicon plate may be formed over the nitride layer, over the sidewall, and over the high concentration diffusion junction region. | 07-02-2009 |
| 20090166699 | Semiconductor Constructions - In some embodiments, an opening is formed through a first material, and sidewall topography of the opening is utilized to form a pair of separate anistropically etched spacers. The spacers are utilized to pattern lines in material underlying the spacers. Some embodiments include constructions having one or more openings which contain steep sidewalls joining to one another at shallow sidewall regions. The constructions may also contain lines along and directly against the steep sidewalls, and spaced from one another by gaps along the shallow sidewall regions. | 07-02-2009 |
| 20090173979 | ALD OF AMORPHOUS LANTHANIDE DOPED TiOX FILMS - The use of atomic layer deposition (ALD) to form an amorphous dielectric layer of titanium oxide (TiO | 07-09-2009 |
| 20090184350 | Non-volatile semiconductor memory device - A non-volatile semiconductor memory device having a memory cell in which operating potentials are few and the scale of the peripheral circuitry is reduced includes a select transistor having a source/drain on both sides of a channel of a semiconductor substrate and having a gate electrode disposed on the channel via a thick gate insulating film; an element isolation region formed on the semiconductor substrate in an area adjacent to the select transistor; an antifuse adjacent to the element isolation region, having a lower electrode formed on the semiconductor substrate and having an upper electrode disposed on the semiconductor substrate in an area between the element isolation region and lower electrode via a thin gate insulating film; and a connection contact electrically connecting the source and upper electrode and contacting the source and the upper electrode. | 07-23-2009 |
| 20090184351 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, an active region formed in the semiconductor substrate and extending in a first direction, the active region including a transistor sub-region and a capacitor sub-region, a first trench extending around the transistor sub-region, an isolation layer disposed in the first trench, a second trench extending around the capacitor sub-region, a first transistor including a first insulating layer disposed on the transistor sub-region, the first transistor including a first conductive layer disposed on the first insulating layer, and a first capacitor including a second insulating layer extending over the capacitor sub-region and a sidewall of the second trench, the first capacitor including a second conductive layer disposed on the second insulating layer, the active region having an end portion in the first direction opposite to the transistor sub-region and extending across the first capacitor. | 07-23-2009 |
| 20090184352 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes: a semiconductor substrate; a lateral MOSFET formed in an upper portion of a first region of the semiconductor substrate; a vertical MOSFET formed in a second region of the semiconductor substrate; a backside electrode formed on a lower surface of the semiconductor substrate and connected to a lower region of source/drain regions of the vertical MOSFET; and a connecting member penetrating the semiconductor substrate and connecting one of source/drain regions of the lateral MOSFET to the backside electrode. | 07-23-2009 |
| 20090184353 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To prevent two contacts that have different heights, share at least one interlayer insulating film and are disposed close to each other from being short-circuited to each other due to misalignment thereof, a semiconductor device according to the invention has a recess in an interlayer insulating film in which a first contact hiving a lower height, the recess being formed by the upper surface of the first contact, and a silicon nitride sidewall is formed in the recess to extend from the upper surface of the first contact and along the side surface of the recess. | 07-23-2009 |
| 20090184354 | SEMICONDUCTOR DEVICE COMPRISING CAPACITOR AND METHOD OF FABRICATING THE SAME - A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface. A semiconductor device organized as just described, permits implementation having a high density of integration while ensuring the capacitor exhibits high reliability and a constant capacitance. | 07-23-2009 |
| 20090184355 | INTEGRATED CIRCUIT ARRANGEMENT WITH CAPACITOR AND FABRICATION METHOD - An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs. | 07-23-2009 |
| 20090194802 | Semiconductor Constructions, and DRAM Arrays - The invention includes methods for utilizing partial silicon-on-insulator (SOI) technology in combination with fin field effect transistor (finFET) technology to form transistors particularly suitable for utilization in dynamic random access memory (DRAM) arrays. The invention also includes DRAM arrays having low rates of refresh. Additionally, the invention includes semiconductor constructions containing transistors with horizontally-opposing source/drain regions and channel regions between the source/drain regions. The transistors can include gates that encircle at least three-fourths of at least portions of the channel regions, and in some aspects can include gates that encircle substantially an entirety of at least portions of the channel regions. | 08-06-2009 |
| 20090200593 | SEMICONDUCTOR DEVICE HAVING MOS-TRANSISTOR FORMED ON SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING THEREOF - A semiconductor device comprises MOS transistors sequentially arranged in the plane direction of a substrate, wherein a gate electrode and a wiring portion for connecting between the gate electrodes to each other are implanted into a layer that is lower than a surface of the substrate in which a diffusion layer has been formed. A first device isolation area with a STI structure for separating the diffusion layers that function as a source/drain area is formed on the surface of the substrate. A second device isolation area with the STI structure for separating channel areas of the MOS transistors adjacent to each other is formed in a layer that is lower than a layer that has the first device isolation area. | 08-13-2009 |
| 20090218608 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME - In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel type MISFETs whose gate electrodes and drains are respectively cross-connected, is formed in a shape that protrudes from the surface of a silicon oxide film. A silicon nitride film used as a capacitive insulating film, and an upper electrode are formed on the wiring. A capacitance can be formed of the wiring, the silicon nitride film and the upper electrode. | 09-03-2009 |
| 20090218609 | Semiconductor Memory Devices Including Offset Bit Lines - A semiconductor memory device may include a substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and the plurality of active regions may be provided in a plurality of columns of active regions in the direction of the second axis. A plurality of wordline pairs may be provided on the substrate, with each wordline pair crossing active regions of a respective column of active regions defining a drain portion of each active region between wordlines of the respective wordline pair. A plurality of bitlines on the substrate may cross the plurality of wordline pairs, with each bitline being electrically coupled to a respective drain portion of an active region of each column, and with each bitline being arranged between the respective drain portion and another drain portion of an adjacent active region of the same column. | 09-03-2009 |
| 20090218610 | Semiconductor Memory Devices Including Diagonal Bit Lines - A semiconductor memory device may include a semiconductor substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and the plurality of active regions may be provided in a plurality of columns in the direction of the second axis. A plurality of wordline pairs may be provided on the substrate, with each wordline pair crossing active regions of a respective column of active regions defining a drain portion of each active region between wordlines of the respective wordline pair. A plurality of bitlines on the substrate may cross the plurality of wordline pairs, with each bitline being electrically coupled to a drain portion of a respective active region of each column, and with each bitline crossing drain portions of active regions of adjacent columns in different directions so that different portions of a same bitline are aligned in different directions on different active regions of adjacent columns. | 09-03-2009 |
| 20090224303 | High voltage capacitor and manufacture method thereof - A high voltage capacitor and a manufacture method thereof are provided. The high voltage capacitor comprises a double diffused drain layer, an oxide layer and a poly-crystal silicon layer. The double diffused drain layer is used as a bottom electrode plate of a high voltage capacitor. The oxide layer is formed on the double diffused drain layer, and is completely overlapped on the double diffused drain layer. The poly-crystal silicon layer is formed on the oxide layer, and is used as a top electrode plate of the high voltage capacitor. | 09-10-2009 |
| 20090230446 | Semiconductor device and bypass capacitor module - A semiconductor device includes an Si substrate having a first surface provided with semiconductor elements, such as a CMOS transistor and a diode, and a second surface opposite to the first surface. On one of the first and the second surfaces, a bypass capacitor is formed. The bypass capacitor includes a Vcc power supply layer and a GND layer which serve to supply a power supply voltage to the semiconductor element, and a high dielectric constant layer sandwiched between the Vcc power supply layer and the GND layer. | 09-17-2009 |
| 20090230447 | Semiconductor Device and Method for Manufacturing the Same - A semiconductor device may include a capacitor and a transistor on a silicon-on-insulator (SOI) substrate and a method for manufacturing the semiconductor device may include forming such a structure. A semiconductor device, formed on a silicon-on-insulator structure including first and second silicon layers and a insulating layer buried between the first and the second silicon layers, may include a capacitor including one electrode formed in a doped region of the first silicon layer and the other electrode formed in a well region of the second silicon layer. | 09-17-2009 |
| 20090230448 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF - In a semiconductor integrated circuit device, testing pads ( | 09-17-2009 |
| 20090236647 | SEMICONDUCTOR DEVICE WITH CAPACITOR - An embodiment of the invention is a semiconductor structure, comprising: a semiconductor chip at least partially embedded within a support; and a capacitor disposed outside the lateral boundary of the chip, the capacitor electrically coupled to the chip. | 09-24-2009 |
| 20090236648 | SEMICONDUCTOR DEVICE - To improve a performance of a semiconductor device having a capacitance element. An MIM type capacitance element, an electrode of which is formed with comb-shaped metal patterns composed of the wirings, is formed over a semiconductor substrate. A conductor pattern, which is a dummy gate pattern for preventing dishing in a CMP process, and an active region, which is a dummy active region, are disposed below the capacitance element, and these are coupled to shielding metal patterns composed of the wirings and then connected to a fixed potential. Then, the conductor pattern and the active region are disposed so as not to overlap the comb-shaped metal patterns in the wirings in a planar manner. | 09-24-2009 |
| 20090250736 | Semiconductor device - In a semiconductor device and associated methods, the semiconductor device includes a substrate, an insulation layer on the substrate, a conductive structure on the insulation layer, the conductive structure including at least one metal silicide film pattern, a semiconductor pattern on the conductive structure, the semiconductor pattern protruding upwardly from the conductive structure, a gate electrode at least partially enclosing the semiconductor pattern, the gate electrode being spaced apart from the conductive structure, a first impurity region at a lower portion of the semiconductor pattern, and a second impurity region at an upper portion of the semiconductor pattern. | 10-08-2009 |
| 20090250737 | SECURE MEMORY DEVICE OF THE ONE-TIME PROGRAMMABLE TYPE - The integrated circuit includes a memory device of the irreversibly electrically programmable type. This device includes several memory cells, each memory cell having a dielectric zone positioned between a first electrode and a second electrode. Each memory cell is further associated with an access transistor. At least one first electrically conductive link electrically couples to the first electrodes of at least two memory cells, these first two electrodes being coupled to one and the same bias voltage. The first electrically conductive link is positioned in substantially a same plane as the first electrodes of the two memory cells. | 10-08-2009 |
| 20090256180 | Standard cell having compensation capacitance - A standard cell includes a capacity element which is made up of a first well diffusion layer into which a first conductive impurity is diffused in a region from a surface of a substrate to a predetermined depth, an insulation film which is provided on the first well diffusion layer, and a first dummy pattern which is provided on the insulation film. | 10-15-2009 |
| 20090256181 | MEMORY ARRAY WITH ULTRA-THIN ETCHED PILLAR SURROUND GATE ACCESS TRANSISTORS AND BURIED DATA/BIT LINES - A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally upward and aligned generally atop a corresponding data/bit line. The access transistors have a pillar extending generally upward with a source region formed so as to be in electrical communication with the corresponding data/bit line and a drain region formed generally at an upper portion of the pillar and a surround gate structure substantially completely encompassing the pillar in lateral directions and extending substantially the entire vertical extent of the pillar and word lines extending generally in a second direction and in electrical contact with a corresponding surround gate structure at least a first surface thereof such that bias voltage applied to a given word line is communicated substantially uniformly in a laterally symmetric extent about the corresponding pillar via the surround gate structure. | 10-15-2009 |
| 20090256182 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes a memory cell portion and a peripheral circuit portion. The memory cell portion includes a pillar capacitor with a lower electrode, a dielectric film, and an upper electrode sequentially formed on a side surface of a first insulating portion which is parallel to a predetermined direction, and a transistor electrically connected to the lower electrode. The peripheral circuit portion includes a plate electrode, a cylinder capacitor with an upper electrode, a dielectric film, and a lower electrode sequentially formed on a side surface of the plate electrode which is parallel to the predetermined direction, and a transistor electrically connected to the lower electrode. | 10-15-2009 |
| 20090267124 | INTEGRATED CIRCUIT HAVING EFFICIENTLY PACKED DECOUPLING CAPACITORS - An integrated circuit includes a substrate having a semiconducting surface ( | 10-29-2009 |
| 20090278183 | Semiconductor Device with Channel of Fin Structure and Method for Manufacturing the Same - Provided are a semiconductor device with a channel of a FIN structure and a method for manufacturing the same. In the method, a device isolation layer defining an active region is formed on a semiconductor substrate. A recess trench with a first width is formed in the active region, and a trench with a second width larger than the first width is formed in the device isolation layer. The trench formed in the device isolation layer is filled with a capping layer. A cleaning process is performed on the recess trench to form a bottom protrusion of a FIN structure including a protrusion and a sidewall. Gate stacks filling the recess trench are formed. A landing plug, which is divided by the capping layer filling the trench, is formed between the gate stacks. | 11-12-2009 |
| 20090283810 | Integrated Circuit Arrangements With ESD-Resistant Capacitor and Corresponding Method of Production - A circuit arrangement including a capacitor in an n-type well is disclosed. A specific polarization of the capacitor ensures that a depletion zone arises in the well and the capacitor has a high ESD strength. An optionally present auxiliary doping layer ensures a high area capacitance of the capacitor despite high ESD strength. | 11-19-2009 |
| 20090289288 | INTEGRATED CIRCUIT INCLUDING AN INSULATING STRUCTURE BELOW A SOURCE/DRAIN REGION AND METHOD - An integrated circuit including an insulating structure below a source/drain region and a method. One embodiment includes a memory cell with an access transistor and a storage element. A first source/drain region of the access transistor is electrically coupled to the storage element. A first insulating structure is disposed between the first source/drain region and a first portion of a semiconductor substrate, the first portion being arranged below the first source/drain region. A channel region of the access transistor is formed between the first and a second source/drain region of the access transistor in an active area being electrically coupled to the first portion of the semiconductor substrate. | 11-26-2009 |
| 20090289289 | DRAM CELL WITH MAGNETIC CAPACITOR - A DRAM cell includes a substrate, a transistor, and a magnetic capacitor. The substrate is composed of semiconductor material with a main surface, the transistor is formed at the main surface, and the magnetic capacitor is formed in a metal layer. The magnetic capacitor includes a first magnetic layer, a dielectric layer formed on the surface of the first magnetic layer, and a second magnetic layer formed on the surface of the dielectric layer. The dielectric layer is a non-conductive material and the first magnetic layer and the second magnetic layer are formed by an alloy of CoNiFe. | 11-26-2009 |
| 20090294819 | METHODS FOR ENHANCING CAPACITORS HAVING ROUGHENED FEATURES TO INCREASE CHARGE-STORAGE CAPACITY - Structures and methods for making a semiconductor structure are discussed. The semiconductor structure includes a rough surface having protrusions formed from an undoped silicon film. If the semiconductor structure is a capacitor, the protrusions help to increase the capacitance of the capacitor. The semiconductor structure also includes a relatively smooth surface abutting the rough surface, wherein the relatively smooth surface is formed from a polycrystalline material. | 12-03-2009 |
| 20090302364 | ELECTRONIC DEVICE INCLUDING A RESISTOR-CAPACITOR FILTER AND A PROCESS OF FORMING THE SAME - A process of forming an electronic device can include forming a capacitor dielectric layer over a base region, wherein the base region includes a base semiconductor material, forming a gate dielectric layer over a substrate, forming a capacitor electrode over the capacitor dielectric layer, forming a gate electrode over the gate dielectric layer, and forming an input terminal and an output terminal to the capacitor electrode. The input terminal and the output terminal can be spaced apart from each other and are connected to different components within the electronic device. A filter can include the base region, the capacitor dielectric layer, and the capacitor electrode. A transistor structure can include the gate dielectric layer and the gate electrode. An electronic device can include a low-pass filter and a transistor structure, such as an n-channel transistor or a p-channel transistor. | 12-10-2009 |
| 20090309146 | SEMICONDUCTOR DEVICE - A disclosed semiconductor device includes a MOS transistor that causes no problems concerning the formation of a thick gate insulating film and that is applicable to high withstand voltage devices. A drain region has a double diffusion structure including an N-drain region | 12-17-2009 |
| 20090315090 | Isolation Trenches with Conductive Plates - Methods of forming isolation trenches, semiconductor devices, structures thereof, and methods of operating memory arrays are disclosed. In one embodiment, an isolation trench includes a recess disposed in a workpiece. A conductive material is disposed in a lower portion of the channel. An insulating material is disposed in an upper portion of the recess over the conductive material. | 12-24-2009 |
| 20090315091 | GATE STRUCTURE, AND SEMICONDUCTOR DEVICE HAVING A GATE STRUCTURE - A gate structure can include a polysilicon layer, a metal layer on the polysilicon layer, a metal silicide nitride layer on the metal layer and a silicon nitride mask on the metal silicide nitride layer | 12-24-2009 |
| 20090321802 | PUMPING MOS CAPACITOR - A pumping MOS capacitor includes a substrate which is conductive and includes an irregular surface, a dielectric film formed along the irregular surface of the substrate and a gate formed on the dielectric film. | 12-31-2009 |
| 20090321803 | Semiconductor device and method of manufacturing the same - A semiconductor device includes a substrate having a cell array region and a peripheral circuit region, a lower structure on the substrate in the cell array region, a first insulation layer on the substrate across the cell array region and the peripheral circuit region, the lower structure being covered with the first insulation layer, a capacitor on the first insulation layer in the cell array region, the capacitor including a lower electrode, a dielectric layer patter, and an upper electrode, a second insulation layer on the first insulation layer, the capacitor being covered with the second insulation layer, a first upper wiring structure on the second insulation layer, the first upper wiring structure being electrically connected to the capacitor and including an upper wiring and a mask pattern, and at least one dummy structure in the peripheral circuit region. | 12-31-2009 |
| 20100001327 | Semiconductor device - In a semiconductor device, the semiconductor device may include a first active structure, a first gate insulation layer, a first gate electrode, a first impurity region, a second impurity region and a contact structure. The first active structure may include a first lower pattern in a first region of a substrate and a first upper pattern on the first lower pattern. The first gate insulation layer may be formed on a sidewall of the first upper pattern. The first gate electrode may be formed on the first gate insulation layer. The first impurity region may be formed in the first lower pattern. The second impurity region may be formed in the first upper pattern. The contact structure may surround an upper surface and an upper sidewall of the first upper pattern including the second impurity region. Accordingly, the contact resistance between the contact structure and the second impurity region may be decreased and structural stability of the contact structure may be improved. | 01-07-2010 |
| 20100001328 | SEMICONDUCTOR DEVICE HAVING AN ANTI-PAD PEELING-OFF STRUCTURE - A bonding pad having an anti-pad peeling-off structure is disclosed. In a method of forming the bonding pad, after a metal pad layer is formed, a slit is formed in the metal pad layer. A protecting layer is formed on the metal pad layer. The protecting layer is partially removed to expose the metal pad such that a portion of the protecting layer remains in the slits to be connected to the main protecting layer. The protecting layer formed in the slit is connected to the protecting layer such that the residual protecting layer pattern buffer when physical impacts are generated, to prevent peeling-off of the metal pad layer. | 01-07-2010 |
| 20100006912 | Planar Metal-Insulator-Metal Circuit Element and Method for Planar Integration of Same - A complementary metal-oxide-semiconductor (CMOS) static random-access-memory (SRAM) element comprising a planar metal-insulator-metal (MIM) capacitor is disclosed, and the planar MIM capacitor is electrically connected to the transistors in the CMOS memory element to reduce the effects of charged particle radiation on the CMOS memory element. Methods for immunizing a CMOS SRAM element to the effects of charged particle radiation are also disclosed, along with methods for manufacturing CMOS SRAM including planar MIM capacitors as integrated circuits. | 01-14-2010 |
| 20100012995 | LOCALIZED BIASING FOR SILICON ON INSULATOR STRUCTURES - A silicon-on-insulator device has a localized biasing structure formed in the insulator layer of the SOI. The localized biasing structure includes a patterned conductor that provides a biasing signal to distinct regions of the silicon layer of the SOI. The conductor is recessed into the insulator layer to provide a substantially planar interface with the silicon layer. The conductor is connected to a bias voltage source. In an embodiment, a plurality of conductor is provided that respectively connected to a plurality of voltage sources. Thus, different regions of the silicon layer are biased by different bias signals. | 01-21-2010 |
| 20100019299 | Memory device - A memory device includes a MOS transistor including a gate structure, a first impurity region, a second impurity region, and a floating body positioned between the first and the second impurity regions on a semiconductor substrate including a buried oxide layer. The memory device includes a charge storage structure of the non-volatile memory device electrically connected to the second impurity region of the MOS transistor. | 01-28-2010 |
| 20100019300 | MULTILAYER INTEGRATED CIRCUIT HAVING AN INDUCTOR IN STACKED ARRANGEMENT WITH A DISTRIBUTED CAPACITOR - Some embodiments provide a multilayer integrated circuit, including: a semiconductor substrate including a plurality of channels extending into the substrate from a surface of the substrate; a distributed capacitor including a plurality of gates formed on the surface of the substrate over the channels, and further including an insulator between the gates and the channels, the gates being spaced apart along the surface of the substrate; an interconnect layer formed over the distributed capacitor, the interconnect layer including a plurality of conductors, at least a first conductor being connected to at least some of the gates and at least a second conductor being connected to at least some of the channels; and an inductor formed over the interconnect layer, the inductor including at least conductor arranged on a layer. | 01-28-2010 |
| 20100025748 | SEMICONDUCTOR DEVICE WITH A DYNAMIC GATE-DRAIN CAPACITANCE - A semiconductor device with a dynamic gate drain capacitance. One embodiment provides a semiconductor device. The device includes a semiconductor substrate, a field effect transistor structure including a source region, a first body region, a drain region, a gate electrode structure and a gate insulating layer. The gate insulating layer is arranged between the gate electrode structure and the body region. The gate electrode structure and the drain region partially form a capacitor structure including a gate-drain capacitance configured to dynamically change with varying reverse voltages applied between the source and drain regions. The gate-drain capacitance includes at least one local maximum at a given threshold or a plateau-like course at given reverse voltage. | 02-04-2010 |
| 20100032739 | Methods Of Forming Vertical Field Effect Transistors, vertical field effect transistors, and dram cells - A method of forming a vertical field effect transistor includes etching an opening into semiconductor material. Sidewalls and radially outermost portions of the opening base are lined with masking material. A semiconductive material pillar is epitaxially grown to within the opening adjacent the masking material from the semiconductor material at the opening base. At least some of the masking material is removed from the opening. A gate dielectric is formed radially about the pillar. Conductive gate material is formed radially about the gate dielectric. An upper portion of the pillar is formed to comprise one source/drain region of the vertical transistor. Semiconductive material of the pillar received below the upper portion is formed to comprise a channel region of the vertical transistor. Semiconductor material adjacent the opening is formed to comprise another source/drain region of the vertical transistor. Other aspects and implementations are contemplated. | 02-11-2010 |
| 20100032740 | Semiconductor device and method of manufacturing the same - A semiconductor device that enables placement of a line or the like under a fuse without any additional step and a method of manufacturing the same are provided. The semiconductor device includes a plurality of first capacitor holes made in an insulating layer, a capacitor formed in the first capacitor holes, a DRAM cell made up of the capacitor and a transistor coupled to the capacitor, a plurality of second capacitor holes made in the insulating layer, and a fuse formed between the second capacitor holes. | 02-11-2010 |
| 20100044765 | SEMICONDUCTOR DEVICE - Provided is a metal oxide semiconductor (MOS) capacitor, in which trenches ( | 02-25-2010 |
| 20100052024 | CAPACITOR INSULATING FILM, METHOD OF FORMING THE SAME, CAPACITOR AND SEMICONDUCTOR DEVICE USING THE CAPACITOR INSULATING FILM - A capacitor insulating film may include, but is not limited to, strontium, titanium, and oxygen. The capacitor insulating film has a ratio of a spectrum intensity of (200) crystal face of the capacitor insulating film to a spectrum intensity of (111) crystal face of the capacitor insulating film in the range of 1.0 to 2.3. Each of the spectrum intensities of (200) crystal face and (111) crystal face is measured by an X-ray diffraction method. | 03-04-2010 |
| 20100059805 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate having an active region and an isolation region. A gate structure is provided on the semiconductor device. First and second impurity regions are provided in the substrate on both sides of the gate structure. A pad electrode is provided to contact the first impurity region. Because the pad electrode is provided on the first impurity region of the semiconductor device, the contact plug does not directly contact the active region. Accordingly, failures caused by damage to the active region may be prevented. | 03-11-2010 |
| 20100065898 | Integrated circuit semiconductor device having different gate stacks in cell region and core/peripheral region and method of manufacturing the same - The integrated circuit semiconductor device includes a semiconductor substrate having a cell region and a core/peripheral region, a first gate stack including a first gate insulating film and a first gate electrode on the semiconductor substrate in the cell region, wherein the first gate insulating film includes a silicon oxide film and the first gate electrode includes a poly-silicon film doped with impurities, and a second gate stack including a second gate insulating film and a second gate electrode on the semiconductor substrate of the core/peripheral region, the second gate insulating film includes a high dielectric film having a higher dielectric constant than that of the silicon oxide film and the second gate electrode includes a metal film. | 03-18-2010 |
| 20100072531 | Method for Forming a Memory Cell Comprising a Capacitor Having a Strontium Titaniumoxide Based Dielectric Layer and Devices Obtained Thereof - A method is disclosed for manufacturing Sr | 03-25-2010 |
| 20100078694 | SEMICONDUCTOR COMPONENT HAVING A DRIFT ZONE AND A DRIFT CONTROL ZONE - A description is given of a normally on semiconductor component having a drift zone, a drift control zone and a drift control zone dielectric arranged between the drift zone and the drift control zone. | 04-01-2010 |
| 20100078695 | Low Leakage Capacitors Including Portions in Inter-Layer Dielectrics - An integrated circuit structure includes a semiconductor substrate including a first region and a second region; an insulation region in the second region of the semiconductor substrate; and an inter-layer dielectric (ILD) over the insulation region. A transistor is in the first region. The transistor includes a gate dielectric and a gate electrode over the gate dielectric. A first conductive line and a second conductive line are over the insulation region. The first conductive line and the second conductive line are substantially parallel to each other and extending in a first direction. A first metal line and a second metal line are in a bottom metal layer (M | 04-01-2010 |
| 20100078696 | SEMICONDUCTOR MEMORY DEVICE WITH POWER DECOUPLING CAPACITORS AND METHOD OF FABRICATION - Provided is a semiconductor memory device including a capacitor structure extending over core and peripheral areas of a substrate. Respective portions of the capacitor structure function as memory cell capacitors in the core area and as first and second capacitors in the peripheral area. A combination of the first and second capacitors functions as a first power decoupling capacitor, and a transistor disposed in the peripheral area functions as a second power decoupling capacitor. | 04-01-2010 |
| 20100078697 | Semiconductor device including capacitor and method for manufacturing the same - A semiconductor device according to the present invention uses a capacitor including a capacitive insulating film sandwiched between an upper electrode and a lower electrode. The lower electrode of the capacitor is constructed by overlappingly connecting a plurality of electrode portions together. A lower electrode portion (plug type electrode) of the adjacent electrode portions is made of columnar tungsten. The lower electrode portion further includes a conductive film (barrier film) that covers a side surface and a bottom surface of the tungsten. A top surface of the tungsten is covered with a bottom portion of an upper electrode portion (cylinder type electrode). | 04-01-2010 |
| 20100078698 | Vertical semiconductor device, dram device including the same - A vertical semiconductor device, a DRAM device, and associated methods, the vertical semiconductor device including single crystalline active bodies vertically disposed on an upper surface of a single crystalline substrate, each of the single crystalline active bodies having a first active portion on the substrate and a second active portion on the first active portion, and the first active portion having a first width smaller than a second width of the second active portion, a gate insulating layer on a sidewall of the first active portion and the upper surface of the substrate, a gate electrode on the gate insulating layer, the gate electrode having a linear shape surrounding the active bodies, a first impurity region in the upper surface of the substrate under the active bodies, and a second impurity region in the second active portion. | 04-01-2010 |
| 20100084697 | NOVEL CAPACITORS AND CAPACITOR-LIKE DEVICES - A capacitor and capacitor-like device or any other device showing capacitive effects, including FETs, transmission lines, piezoelectric and ferroelectric devices, etc., with at least two electrodes, of which at least one electrode consists of or comprises a material or is generated as electron system, whose absolute value of the electronic charging energy as defined by the charging-induced change of E | 04-08-2010 |
| 20100090263 | MEMORY DEVICES INCLUDING SEMICONDUCTOR PILLARS - One embodiment relates to an integrated circuit that includes a memory array of pillars arranged in rows and columns. The pillars are separated from one another by row trenches and column trenches. The column trenches include a pair of parallel column trenches. A first trench of the pair includes two parallel bit lines coupled to pillars adjacent to the first trench. A second trench of the pair is free of bit lines. Other methods, devices, and systems are also disclosed. | 04-15-2010 |
| 20100096680 | OC DRAM CELL WITH INCREASED SENSE MARGIN - A memory device and method of making the memory device. The memory device comprises a storage transistor at a surface of a substrate. The storage transistor comprises a body portion between first and second source/drain regions, wherein the source/drain regions are regions of a first conductivity type. The storage transistor also comprises a gate structure that wraps at least partially around the body portion in at least two spatial planes. A bit line is connected to the first source/drain region and a word line is connected to the gate structure. | 04-22-2010 |
| 20100096681 | Cell structure for a semiconductor memory device and method of fabricating the same | 04-22-2010 |
| 20100102371 | Semiconductor devices including buried gate electrodes and isolation layers and methods of forming semiconductor devices including buried gate electrodes and isolation layers using self aligned double patterning - A semiconductor device, including a semiconductor substrate including isolations defining active regions of the semiconductor substrate, and a plurality of buried gate electrodes between a pair of the isolations, wherein each of the buried gate electrodes and the isolations includes a conductive layer and a capping layer. | 04-29-2010 |
| 20100109062 | SEMICONDUCTOR DEVICE - A dummy transistor and a field effect transistor are arranged in a second direction. The dummy transistor is located at least at one end in a second direction. | 05-06-2010 |
| 20100117129 | Scratch protection for direct contact sensors - In capacitive sensor circuits where physical contact is required and excess pressure may be inadvertently applied to the sensor surface, aluminum is not sufficiently hard to provide “scratch” protection and may delaminate, causing circuit failure, even if passivation integrity remains intact. Because hard passivation layers alone provide insufficient scratch resistance, at least the capacitive electrodes and preferably all metallization levels within the sensor circuit in the region of the capacitive electrodes between the surface and the active regions of the substrate are formed of a conductive material having a hardness greater than that of aluminum. The selected conductive material preferably has a hardness which is at least as great as the lowest hardness for any interlevel dielectric or passivation material employed. The selected conductive material is employed for each metallization level between the surface and the active regions, including contacts and vias, landing pads, interconnects, capacitive electrodes, and electrostatic discharge protection lines. Tungsten is a suitable conductive material, for which existing processes may be substituted in place of aluminum metallization processes. | 05-13-2010 |
| 20100117130 | HIGH PERFORMANCE CAPACITORS IN PLANAR BACK GATES CMOS - A method of manufacture and device for a dual-gate CMOS structure. The structure includes a first plate in an insulating layer and a second plate above the insulating layer electrically corresponding to the first plate. An isolation structure is between the first plate and the second plate. | 05-13-2010 |
| 20100127316 | STRUCTURE FOR PROTECTING METAL-INSULATOR-METAL CAPACITOR IN MEMORY DEVICE FROM CHARGE DAMAGE - A dynamic random access memory (DRAM) device has a metal-insulator-metal (MIM) capacitor electrically connected to a PN junction diode through a metal bridge for protecting the MIM capacitor from charge damage generated in back end of line (BEOL) plasma process. | 05-27-2010 |
| 20100140676 | Semiconductor devices including buried gate electrodes including bitline shoulder attack protection and methods of forming such semiconductor devices - A semiconductor device, including a semiconductor substrate including isolations defining active regions of the semiconductor substrate, a plurality of buried gate electrodes extending below an upper surface of the active regions of the semiconductor device, a plurality of bit lines extending on the semiconductor substrate along a first direction, a plurality of insulating patterns extending on the semiconductor substrate along a second direction that crosses the first direction, and a plurality of capping patterns extending over the bit lines, wherein the insulating patterns and the capping pattern both include insulating material and at least a portion of corresponding ones of the insulating patterns and the capping patterns are in direct contact with each other. | 06-10-2010 |
| 20100140677 | SEMICONDUCTOR DEVICE - A semiconductor device of the present invention has a first contact and a second contact which are located over a device isolation film so as to be opposed with each other, and have a length in the horizontal direction larger than the height; a first electro-conductive pattern located on the first contact and is formed in at least a single interconnect layer; a second electro-conductive pattern located on the second contact so as to be opposed with the first electro-conductive pattern; and an interconnect formed in an upper interconnect layer which is located above the first electro-conductive pattern and the second electro-conductive pattern, so as to be located in a region above the first electro-conductive pattern and the second electro-conductive pattern. | 06-10-2010 |
| 20100148233 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING SEMICONDUCTOR DEVICE - A semiconductor device include a semiconductor substrate comprising a substrate body, a base over the substrate body and a pillar over a first region of the base; a buried line adjacent to a side surface of the base; a first diffusion layer over a second region of the base; a second diffusion layer over the pillar, the second diffusion layer being higher in level than the first diffusion layer; and a third diffusion layer disposed between the buried line and the semiconductor substrate. The third diffusion layer is different in level from the first diffusion layer. The top level of the third diffusion layer is lower than the top level of the first diffusion layer. | 06-17-2010 |
| 20100148234 | SUBRESOLUTION SILICON FEATURES AND METHODS FOR FORMING THE SAME - Novel etch techniques are provided for shaping silicon features below the photolithographic resolution limits. FinFET devices are defined by recessing oxide and exposing a silicon protrusion to an isotropic etch, at least in the channel region. In one implementation, the protrusion is contoured by a dry isotropic etch having excellent selectivity, using a downstream microwave plasma etch. | 06-17-2010 |
| 20100148235 | SEMICONDUCTOR INTEGRATED CIRCUIT, STANDARD CELL, STANDARD CELL LIBRARY, SEMICONDUCTOR INTEGRATED CIRCUIT DESIGNING METHOD, AND SEMICONDUCTOR INTEGRATED CIRCUIT DESIGNING EQUIPMENT - A semiconductor integrated circuit includes a first transistor which is formed of a first gate extending in a first direction and a first diffusion region and which is capable of being active, a second transistor which is formed of a second gate extending in the first direction and a second diffusion region and which is arranged adjacent to the first transistor in a second direction intersected at a right angle with the first direction, and a third gate which extends in the first direction and which is arranged adjacent in the second direction to the first transistor on an opposite side to the second transistor. A space between the first gate and the second gate is larger than a space between the first gate and the third gate. | 06-17-2010 |
| 20100155798 | SEMICONDUCTOR MEMORY DEVICE INCLUDING CELL ISOLATION STRUCTURE USING INACTIVE TRANSISTORS - Disclosed herein is a semiconductor memory device including floating body cells. The semiconductor memory device includes memory cell active regions formed on a Silicon-On Isolator (SOI) semiconductor substrate, a plurality of floating body cell transistors formed in the memory cell active regions, and inactive transistors for providing cell isolation that are formed between the plurality of floating body cell transistors. Here, the inactive transistors for providing cell isolation are controlled so that they always are in an OFF state while the semiconductor memory device is operating. | 06-24-2010 |
| 20100155799 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A first MOS transistor includes, as a first impurity region, a pair of first source/drain regions including first portions formed in a semiconductor substrate and second portions formed so as to project upward from the first portions. A second MOS transistor includes a pair of second source/drain regions including second impurity regions formed in the semiconductor substrate, third impurity regions located in contact with the second impurity regions so as to project upward from the semiconductor substrate, and fourth impurity regions located on the third impurity regions. The concentration of impurities in the third impurity regions is lower than that of impurities in the fourth impurity regions. The concentration of impurities in the first impurity regions is lower than that of impurities in the second impurity regions. The first, the second, the third and the fourth impurity regions are same conductivity type. | 06-24-2010 |
| 20100155800 | Creating Integrated Circuit Capacitance from Gate Array Structures - Techniques for using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise placing a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for one or more N-fets to a power supply ground, and coupling gates for the one or more P-fets and the drains and sources for one or more N-fets to a positive voltage of the power supply. In some embodiments, source-to-drain leakage current for capacitive apparatuses of P-fets and N-fets are minimized by biasing one or more P-fets and one or more N-fets to the positive voltage and the ground, respectively. In other embodiments, the capacitive structures may be implemented using fusible elements to isolate the capacitive structures in case of shorts. | 06-24-2010 |
| 20100163945 | Embedded memory cell and method of manufacturing same - An embedded memory cell includes a semiconducting substrate ( | 07-01-2010 |
| 20100163946 | SEMICONDCUTOR DEVICE HAVING VERTICAL GATE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming buried bit lines separated from each other by a trench in a substrate, forming a plurality of first pillar holes that expose a top surface of the substrate, forming first active pillars buried in the first pillar holes, forming a gate conductive layer over entire surface of a resultant structure including the first active pillars, forming a gate electrode by etching the gate conducting layer to cover the first active pillars, forming a plurality of second pillar holes that expose the first active pillars by partially etching the gate electrode, and forming second active pillars buried in the second pillar holes and connected to the first active pillars. | 07-01-2010 |
| 20100163947 | METHOD FOR FABRICATING PIP CAPACITOR - A PIP capacitor and methods thereof. A method of fabricating a PIP capacitor may include forming a field oxide film over a silicon substrate to define a device isolating region and/or an active region. A method of fabricating a PIP capacitor may include forming a lower polysilicon electrode having doped impurities on and/or over an field oxide film. A method of fabricating a PIP capacitor may include performing an oxidizing step to form a first oxide film over a polysilicon and/or a second oxide film on and/or over an active region. A method of fabricating a PIP capacitor may include forming an upper polysilicon electrode on and/or over a region of a first oxide film and forming a gate electrode on and/or over a second oxide film at substantially the same time. A method of fabricating a PIP capacitor may include forming a polysilicon resistor. A PIP capacitor is disclosed. | 07-01-2010 |
| 20100163948 | Integrated Circuit Having Efficiently Packed Decoupling Capacitors - An integrated circuit includes a substrate having a semiconducting surface ( | 07-01-2010 |
| 20100171159 | LAYOUT OF SEMICONDUCTOR DEVICE - A layout of a semiconductor device is disclosed, which forms one transistor in one active region to reduce the number of occurrences of a bridge encountered between neighboring layers, thereby improving characteristics of the semiconductor device. Specifically, the landing plug connected to the bit line contact is reduced in size, so that a process margin of word lines is increased to increase a channel length, thereby reducing the number of occurrences of a bridge encountered between the landing plug and the word line. | 07-08-2010 |
| 20100176430 | Semiconductor Device with Reduced Parasitic Inductance - The present invention provides a technology for reducing the parasitic inductance of the main circuit of a power source unit. In a non-insulated DC-DC converter having a circuit in which a power MOSFET for high side switch and a power MOSFET for low side switch are connected in series, the power MOSFET for high side switch and the power MOSFET for low side switch are formed of n-channel vertical MOSFETs, and a source electrode of the power MOSFET for high side switch and a drain electrode of the power MOSFET for low side switch are | 07-15-2010 |
| 20100207179 | DYNAMIC RANDOM ACCESS MEMORY CELL INCLUDING AN ASYMMETRIC TRANSISTOR AND A COLUMNAR CAPACITOR - A semiconductor fin having a doping of the first conductivity type and a semiconductor column are formed on a substrate. The semiconductor column and an adjoined end portion of the semiconductor fin are doped with dopants of a second conductivity type, which is the opposite of the first conductivity type. The doped semiconductor column constitutes an inner electrode of a capacitor. A dielectric layer and a conductive material layer are formed on the semiconductor fin and the semiconductor column. The conductive material layer is patterned to form an outer electrode for the capacitor and a gate electrode. A single-sided halo implantation may be performed. Source and drain regions are formed in the semiconductor fin to form an access transistor. The source region is electrically connected to the inner electrode of the capacitor. The access transistor and the capacitor collectively constitute a DRAM cell. | 08-19-2010 |
| 20100207180 | HIGH-PERFORMANCE ONE-TRANSISTOR FLOATING-BODY DRAM CELL DEVICE - Provided is a one-transistor (1T) floating-body DRAM cell device including a substrate; a gate stack which is formed on the substrate; a control electrode which is disposed on the substrate and of which some or entire portion is surrounded by the gate stack; a semiconductor layer which is formed on the gate stack; a source and a drain which are formed in the surface of the semiconductor layer and of which lower surfaces are not in contact with the gate stack; a gate insulating layer which is formed on the semiconductor layer; and a gate electrode which is formed on the gate insulating layer, wherein the remaining portion of the semiconductor layer excluding the source and the drain is configured as a floating body. The miniaturization characteristic and performance of a MOS-based DRAM cell device can be improved, and a memory capacity can be increased. | 08-19-2010 |
| 20100213520 | Semiconductor integrated circuit device and method of manufacturing the same - Provided is a semiconductor integrated circuit device including a capacitor element with an improved TDDB life. A semiconductor integrated circuit device ( | 08-26-2010 |
| 20100213521 | Semiconductor devices and methods of forming semiconductor devices - A semiconductor device includes a back bias dielectric including a negative fixed charge, a gate electrode overlapping the back bias dielectric, a semiconductor layer disposed between the gate electrode and the back bias dielectric, and a gate dielectric disposed between the semiconductor layer and the gate electrode, wherein the negative fixed charge accumulates holes at a surface of the semiconductor layer facing the back bias dielectric. | 08-26-2010 |
| 20100224922 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a first multi-layered structure; a first insulating film over the first multi-layered structure, the first insulating film containing fluorine; and a second insulating film over the first insulating film. | 09-09-2010 |
| 20100230733 | VERTICAL GATED ACCESS TRANSISTOR - According to one embodiment of the present invention, a method of forming an apparatus comprises forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a substrate. At least one of the shallow trenches is positioned between two deep trenches. The plurality of shallow trenches and the plurality of deep trenches are parallel to each other. The method further comprises depositing a layer of conductive material over the first region and a second region of the substrate. The method further comprises etching the layer of conductive material to define a plurality of lines separated by a plurality of gaps over the first region of the substrate, and a plurality of active device elements over the second region of the substrate. The method further comprises masking the second region of the substrate. The method further comprises removing the plurality of lines from the first region of the substrate, thereby creating a plurality of exposed areas from which the plurality of lines were removed. The method further comprises etching a plurality of elongate trenches in the plurality of exposed areas while the second region of the substrate is masked. | 09-16-2010 |
| 20100237394 | Semiconductor memory device - A semiconductor memory device includes unit active regions, word lines extending in a first direction over the unit active region, bit lines extending on the word lines in a second direction substantially perpendicularly to the first direction, first pad contacts in contact with central portions of the unit active regions, the first pad contacts being arranged between the word lines, direct contacts electrically connected between the first pad contacts and the bit lines, second pad contacts in contact with edge portions of the unit active regions, the second pad contacts being arranged between the word lines and between the bit lines, buried contacts electrically connected to the second pad contacts, and capacitors electrically connected to the buried contacts. | 09-23-2010 |
| 20100244109 | TRENCHED METAL-OXIDE-SEMICONDUCTOR DEVICE AND FABRICATION THEREOF - A fabrication method of a trenched metal-oxide-semiconductor device is provided. After the formation of the gate dielectric layer, a first poly-silicon layer is deposited along the profile of the gate trench. Then, impurities of first conductivity type are implanted to the first poly-silicon layer at the bottom of the gate trench. Then, a second poly-silicon layer with second conductivity type is deposited over the first poly-silicon layer. The impurities in the first poly-silicon layer and the second poly-silicon layer are then driven by an annealing step to form a first doping region with first conductivity type located at the bottom of the gate trench and a second doping region with second conductivity type. | 09-30-2010 |
| 20100244110 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first transistor, a second transistor, an insulation interlayer pattern and a capacitor. The first transistor is formed in a first region of a substrate. The first transistor has a pillar protruding upwardly from the substrate and an impurity region provided in an upper portion of the pillar. The second transistor is formed in a second region of the substrate. The insulation interlayer pattern is formed on the first region and the second region to cover the second transistor and expose an upper surface of the pillar. The insulation interlayer pattern has an upper surface substantially higher than the upper surface of the pillar in the first region. The capacitor is formed on the impurity region in the upper portion of the pillar and is electrically connected to the impurity region. | 09-30-2010 |
| 20100244111 | Semiconductor Structure of a Display Device and Method for Fabricating the Same - A semiconductor structure of a display device and the method for fabricating the same are provided. The semiconductor structure is formed on a substrate having a TFT region and a pixel capacitor region thereon. A TFT, including a gate electrode, a source electrode, a drain electrode, a channel layer, and a gate insulating layer, is formed on the TFT region of the substrate. A pixel capacitor is formed on the pixel capacitor region, wherein the pixel capacitor comprises a bottom electrode formed on a bottom dielectric layer, an interlayer dielectric layer formed on the bottom electrode, a top electrode formed on the interlayer dielectric layer, a contact plug passing through the interlayer dielectric layer and electrically connected to the top and bottom electrodes, a capacitor dielectric layer formed on the top electrode, a transparent electrode formed on the capacitor dielectric layer and electrically connected to the drain electrode. | 09-30-2010 |
| 20100264477 | Semiconductor Devices - Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment includes providing a workpiece having a first orientation and at least one second orientation. The semiconductor device is implanted with a dopant species using a first implantation process in the first orientation of the workpiece. The semiconductor device is implanted with the dopant species using a second implantation process in the at least one second orientation of the workpiece, wherein the second implantation process is different than the first implantation process. | 10-21-2010 |
| 20100270602 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory device and a method for manufacturing the same are disclosed, which reduce parasitic capacitance generated between a storage node contact and a bit line of a high-integration semiconductor device. A method for manufacturing a semiconductor memory device includes forming a buried word line in an active region of a cell region, forming an insulation layer in the cell region and a lower electrode layer of a gate in a peripheral region so that a height of the insulation layer is substantially equal to that of the lower electrode layer, and providing a first conductive layer over the cell region and the peripheral region to form a bit line layer and an upper electrode layer. | 10-28-2010 |
| 20100270603 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device comprises gates comprising a first conductive layer, landing plug contacts formed adjacent to the gate and formed of a second conductive layer, a bit line formed over the landing plug contacts and formed of a third conductive layer, and storage electrode contacts formed over the landing plug contacts and the bit line and formed of a fourth conductive layer. The first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer are made of the same material. | 10-28-2010 |
| 20100276739 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The semiconductor device includes a device isolation structure formed in a semiconductor substrate to define an active region, a bridge type channel structure formed in the active region, and a coaxial type gate electrode surrounding the bridge type channel structure of a gate region. The bridge type channel structure is separated from the semiconductor substrate thereunder by a predetermined distance in a vertical direction. | 11-04-2010 |
| 20100283091 | SEMICONDUCTOR DEVICE HAVING A REDUCED BIT LINE PARASITIC CAPACITANCE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having a reduced bit line parasitic capacitance and a method of making same is presented. The semiconductor device includes a first, second, third, and fourth interlayer dielectric layers, first and second bit lines, first and second landing plug and first and second storage node contacts. An optional capacitor may be added to complete a CMOS configuration for the semiconductor device. The storage node contacts traverse through the interlayer dielectric layer and are electrically coupled to their respective landing plug contacts. The storage node contacts are deliberately offset, relative to the center of the corresponding landing plug contacts, at a predetermined distance in a direction away from the first bit line. This offsetting aids reducing the parasitic capacitance between the bit line and a storage node. | 11-11-2010 |
| 20100283092 | SEMICONDUCTOR DEVICE - The semiconductor device includes a first conductor formed over a semiconductor substrate; a first insulator formed over the first conductor; a second insulator formed over the first insulator, the second insulator having an etching characteristic different from an etching characteristic of the first insulator; a second conductor formed on the second insulator, the second conductor being in contact with the second insulator; a third insulator formed over the second conductor, the third insulator having an etching characteristic different from the etching characteristic of the second insulator; a first contact hole formed through the third insulator and the second conductor, the first contact hole reaching the second insulator; a third conductor formed in the first contact hole, wherein a side wall of the third conductor is electrically connected to a side wall of the second conductor; a second contact hole formed through the third insulator and the first insulator, the second contact hole reaching the first conductor; and a fourth conductor formed in the second contact hole, wherein the fourth conductor is electrically connected to the first conductor. | 11-11-2010 |
| 20100289069 | SEMICONDUCTOR INTEGRATED-CIRCUIT DEVICE - A semiconductor integrated-circuit device is disclosed. The semiconductor integrated-circuit device uses a filter, which includes a standard capacitor, as a standard cell connecting a memory cell with a logic cell. As such, the semiconductor integrated-circuit device can minimize a glitch phenomenon of power/ground voltages and provide stability of power/ground voltages. | 11-18-2010 |
| 20100295109 | Memory Arrays, Semiconductor Constructions And Electronic Systems - Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include 0C1T memory having transistor gates entirely over SOI, and methods of forming such 0C1T memory. | 11-25-2010 |
| 20100308388 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a semiconductor device and a method of manufacturing the semiconductor device, for example, a semiconductor device using carbon nanotubes or nanowires as lower electrodes of a capacitor, and a method of manufacturing the semiconductor device. The semiconductor device may include a lower electrode including a plurality of tubes or wires on a semiconductor substrate, a dielectric layer on the surface of the lower electrode, and an upper electrode on the surface of the dielectric layer, wherein the plurality of tubes or wires radiate outwardly from each other centering on the lower portion of the plurality of tubes or wires. Thus, the off current of the capacitor may be increased by increasing the surface area of the lower electrodes of the capacitor. | 12-09-2010 |
| 20100314674 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor chip including an interlayer insulating film, a first area, and a first crack stopper. The first area includes a plurality of capacitors, each of which includes a lower electrode and a dielectric film sequentially formed on the inner wall of a first opening and an upper electrode buried in the first opening, and a plate electrode provided to be electrically connected to the upper electrode of each of the capacitors. The first crack stopper includes first and second films sequentially formed on the inner wall of a second opening, a third film buried in the second opening, and an upper area provided to be in contact with the third film. | 12-16-2010 |
| 20100327334 | FLOATING BODY MEMORY CELL APPARATUS AND METHODS - Some embodiments include apparatus and methods having a base; a memory cell including a body, a source, and a drain; and an insulation material electrically isolating the body, the source, and the drain from the base, where the body is configured to store information. The base and the body include bulk semiconductor material. Additional apparatus and methods are described. | 12-30-2010 |
| 20110001174 | Memory Cells, And Methods Of Forming Memory Cells - Some embodiments include memory cells that contain floating bodies and diodes. The diodes may be gated diodes having sections doped to a same conductivity type as the floating bodies, and such sections of the gated diodes may be electrically connected to the floating bodies. The floating bodies may be adjacent channel regions, and spaced from the channel regions by a dielectric structure. The dielectric structure of a memory cell may have a first portion between the floating body and the diode, and may have a second portion between the floating body and the channel region. The first portion may be more leaky to charge carriers than the second portion. The diodes may be formed in semiconductor material that is different from a semiconductor material that the channel regions are in. The floating bodies may have bulbous lower regions. Some embodiments include methods of making memory cells. | 01-06-2011 |
| 20110001175 | SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF - The present invention relates to a highly integrated semiconductor device in which a capacitor is formed between adjacent gate patterns by using a nanotube process. A semiconductor memory device according to an example embodiment of the present invention includes a capacitor formed on a first side of a source/drain region positioned between gate patterns of adjacent cell transistors; a plate layer connected to an upper portion of the capacitor, the plate layer being formed in a direction intersecting the gate pattern; and a bit line connected to a second side of the source/drain region of the cell transistor, the bit line being formed in the direction intersecting the gate pattern. | 01-06-2011 |
| 20110006351 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate; an impurity-doped region at a top surface of the semiconductor substrate; an insulating region located around the impurity-doped region on the top surface of the semiconductor substrate; a gate electrode on the impurity-doped region; a first electrode and a second electrode located on the impurity-doped region, sandwiching the gate electrode; a first pad located on the insulating region and connected to the gate electrode; a second pad facing the first pad across the impurity-doped region, on the insulating region, and connected to the second electrode; and a conductor located between the first electrode and the second pad on the insulating region. | 01-13-2011 |
| 20110006352 | REVERSE ENGINEERING RESISTANT READ ONLY MEMORY - A read only memory is manufactured with a plurality of transistors ( | 01-13-2011 |
| 20110012181 | METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVCIE HAVING CAPACITOR ELEMENT - In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance. | 01-20-2011 |
| 20110012182 | Semiconductor Constructions and Transistors, and Methods of Forming Semiconductor Constructions and Transistors - The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate is formed within the semiconductor substrate between the pair of the source/drain regions. | 01-20-2011 |
| 20110012183 | WIRELESS CHIP - An ID tag capable of communicating data wirelessly, the size of which is reduced, and where the size of an IC chip is reduced, a limited area of the chip is effectively used, current consumption is reduced, and communication distance is prevented from decreasing. The ID tag of the invention includes an IC chip having an integrated circuit, a resonance capacitor portion and a storage capacitor portion, and an antenna formed over the IC chip so as to overlap at least partially with an insulating film interposed therebetween. The antenna, the insulating film and wirings or semiconductor films forming the integrated circuit are stacked, and one or both of capacitors in the resonance capacitor portion and the storage capacitor portion are formed by this stacked structure. | 01-20-2011 |
| 20110018044 | ETCH STOP LAYERS AND METHODS OF FORMING THE SAME - A semiconductor device includes a MOSFET, and a plurality of stress layers disposed on the MOSFET, wherein the stress layers include a first stress layer disposed on the MOSFET and a second stress layer disposed on the first stress layer, the first stress layer has a first stress and the second stress layer has a second stress, and the first stress is different from the second stress. | 01-27-2011 |
| 20110018045 | DRAM Arrays, Vertical Transistor Structures, and Methods of Forming Transistor Structures and DRAM Arrays - The invention includes a method of forming a semiconductor construction. Dopant is implanted into the upper surface of a monocrystalline silicon substrate. The substrate is etched to form a plurality of trenches and cross-trenches which define a plurality of pillars. After the etching, dopant is implanted within the trenches to form a source/drain region that extends less than an entirety of the trench width. The invention includes a semiconductor construction having a bit line disposed within a semiconductor substrate below a first elevation. A wordline extends elevationally upward from the first elevation and substantially orthogonal relative to the bit line. A vertical transistor structure is associated with the wordline. The transistor structure has a channel region laterally surrounded by a gate layer and is horizontally offset relative to the bit line. | 01-27-2011 |
| 20110024811 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A method for forming a semiconductor device is disclosed. The method for forming the semiconductor device includes forming a pad insulating layer on a semiconductor substrate, forming a recess by etching the pad insulating layer and the semiconductor substrate, forming a buried gate buried in the recess, forming an insulating layer for defining a bit line contact hole over the buried gate and the pad insulating layer, forming a bit line over a bit line contact for filling the bit line contact hole, and forming a storage electrode contact hole by etching the insulating layer and the pad insulating layer to expose the semiconductor substrate. As a result, the method increases the size of an overlap area between a storage electrode contact and an active region without an additional mask process, resulting in a reduction in cell resistance. | 02-03-2011 |
| 20110024812 | RESONANT BODY TRANSISTOR AND OSCILLATOR - A resonator body has an inversion gate, an accumulation gate, and a center region. The resonator body also has a source contact coupled to the center region and a drain contact coupled to the center region. The resonator body further has a first dielectric layer coupled between the inversion gate and the center region. The resonator body also has a second dielectric layer coupled between the accumulation gate and the center region. A resonant body transistor is also disclosed. The resonant body transistor has an inversion gate electrode, an accumulation gate electrode, a source electrode, a drain electrode, and a plurality of anchor beams. The resonant body transistor also has a resonator body coupled-to and suspended-from the inversion gate electrode, the accumulation gate electrode, the source electrode, and the drain electrode by the plurality of anchor beams. A resonant body oscillator is also disclosed. | 02-03-2011 |
| 20110024813 | MOS CAPACITOR STRUCTURES - Methods and apparatus are described for MOS capacitors (MOS CAPs). The apparatus comprises a substrate having Ohmically coupled N and P semiconductor regions covered by a dielectric. A conductive electrode overlies the dielectric above these N and P regions. Use of the Ohmically coupled N and P regions substantially reduces the variation of capacitance with applied voltage associated with ordinary MOS CAPs. When these N and P regions have unequal doping, the capacitance variation may still be substantially compensated by adjusting the properties of the dielectric above the N and P regions and/or relative areas of the N and P regions or both. Accordingly, such MOS CAPS may be more easily integrated with other semiconductor devices with minimal or no disturbance to the established integrated circuit (IC) manufacturing process and without significantly increasing the occupied area beyond that required for a conventional MOS CAP. | 02-03-2011 |
| 20110037109 | SEMICONDUCTOR DEVICES INCLUDING LOWER AND UPPER DEVICE ISOLATION PATTERNS - In some embodiments, a semiconductor substrate includes trenches defining active regions. The semiconductor device further includes lower and upper device isolation patterns disposed in the trenches. An intergate insulation pattern and a control gate electrode are disposed on the semiconductor substrate to cross over the active regions. A charge storage electrode is between the control gate electrode and the active regions. A gate insulation pattern is between the charge storage electrode and the active regions, and the intergate insulation pattern directly contacts the upper device isolation pattern between the active regions. | 02-17-2011 |
| 20110037110 | CAPACITOR AND METHOD FOR FABRICATIONG THE SAME, AND SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The semiconductor device comprises a device isolation region | 02-17-2011 |
| 20110042731 | STRUCTURE AND METHOD OF FORMING ENHANCED ARRAY DEVICE ISOLATION FOR IMPLANTED PLATE EDRAM - A method for forming a memory device in a semiconductor on insulator substrate is provided, in which a protective oxide that is present on the sidewalls of the trench protects the first semiconductor layer, i.e., SOI layer, of the semiconductor on insulator substrate during bottle etching of the trench. In one embodiment, the protective oxide reduces back channel effects of the transistors to the memory devices in the trench that are formed in the semiconductor on insulator substrate. In another embodiment, a thermal oxidation process increases the thickness of the buried dielectric layer of a bonded semiconductor on insulator substrate by oxidizing the bonded interface between the buried dielectric layer and at least one semiconductor layers of the semiconductor on insulator substrate. The increased thickness of the buried dielectric layer may reduce back channel effects in devices formed on the substrate having trench memory structures. | 02-24-2011 |
| 20110042732 | METHOD AND SYSTEM FOR CONTINUOUS LINE-TYPE LANDING POLYSILICON CONTACT (LPC) STRUCTURES - A method for making contact landing pad structures in a semiconductor integrated circuit device. The method includes forming an isolation region and forming active regions in the semiconductor substrate. The active regions are separated by the isolation region, and each of the active regions includes one or more contact regions. The method includes forming a raised structure between a first and second contact regions. The raised structure overlying the isolation region. The method includes depositing a cap layer and forming an interlayer dielectric layer overlying the cap layer. The method uses a mask pattern to selectively remove a portion of the photoresist layer to form a line type opening, which exposes a portion of the interlayer dielectric layer overlying at least the first and second contact regions. The method deposits a conductive fill material and performs a planarization process, whereby a plurality of conductive landing contact pads are formed. | 02-24-2011 |
| 20110042733 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a plurality of first electrodes standing over a substrate, and a supporter that supports the plurality of first electrodes in standing. The supporter includes a stack of first and second supporting films. The first supporting film has a compressive stress. The second supporting film has a tensile stress. | 02-24-2011 |
| 20110049594 | SILICON-ON-INSULATOR SUBSTRATE WITH BUILT-IN SUBSTRATE JUNCTION - A method of forming a SOI substrate, diodes in the SOI substrate and electronic devices in the SOI substrate and an electronic device formed using the SOI substrate. The method of forming the SOI substrate includes forming an oxide layer on a silicon first substrate; ion-implanting hydrogen through the oxide layer into the first substrate, to form a fracture zone in the substrate; forming a doped dielectric bonding layer on a silicon second substrate; bonding a top surface of the bonding layer to a top surface of the oxide layer; thinning the first substrate by thermal cleaving of the first substrate along the fracture zone to form a silicon layer on the oxide layer to formed a bonded substrate; and heating the bonded substrate to drive dopant from the bonding layer into the second substrate to form a doped layer in the second substrate adjacent to the bonding layer. | 03-03-2011 |
| 20110049595 | METHOD FOR FORMING MEMORY CELL TRANSISTOR - A method for forming a memory cell transistor is disclosed which includes providing a substrate, forming a trench structure in the substrate, depositing a conductive substance on the surface of the substrate to form a conductive member inside the trench structure, forming one or more dielectric layers on the surface of the substrate, forming one or more first conductive layers on top of the dielectric layers, and etching the first conductive layers and the dielectric layers to form a hole structure extending through the first conductive and the dielectric layers, reaching to the substrate surface. The formed memory cell transistor thus comprises a hole structure which is formed from the surface of the top first conductive layer, extending downwards through the first conductive layers and the dielectric layers, and reaching the substrate surface. One or more second conductive layers may be formed on top of the first conductive layers, with the second conductive layer material filling the hole structure. | 03-03-2011 |
| 20110049596 | Semiconductor Device Having Impurity Doped Polycrystalline Layer Including Impurity Diffusion Prevention Layer and Dynamic Random Memory Device Including the Semiconductor Device - Provided are semiconductor devices including a semiconductor substrate, an insulating layer including a contact hole through which the semiconductor substrate is exposed, and a polysilicon layer filling the contact hole. The polysilicon layer is doped with impurities and includes an impurity-diffusion prevention layer. In the semiconductor devices, the impurities included in the polysilicon layer do not diffuse into the insulating layer and the semiconductor substrate due to the impurity-diffusion prevention layers. | 03-03-2011 |
| 20110057239 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device comprises a capacitor in which a lower electrode, an adhesive layer, a capacitance insulating film, and an upper electrode are provided in series. The capacitance insulating film has laminated films in which a first metal oxide film and a second metal oxide film are alternatively laminated so that the first metal oxide film contacts with the adhesive layer. The adhesive layer has thickness of 0.3 nm or more and is an oxide film including at least one element selected from element contained in the lower electrode. | 03-10-2011 |
| 20110062505 | SEMICONDUCTOR DEVICE WITH CAPACITOR AND FUSE AND ITS MANUFACTURE - An upper electrode of a capacitor has a two-layer structure of first and second upper electrodes. A gate electrode of a MOS field effect transistor and a fuse are formed by patterning conductive layers used to form the lower electrode, first upper electrode and second upper electrode of the capacitor. In forming a capacitor and a fuse on a semiconductor substrate by a conventional method, at least three etching masks are selectively used to pattern respective layers to form the capacitor and fuse before wiring connection. The number of etching masks can be reduced in manufacturing a semiconductor device having capacitors, fuses and MOS field effect transistors so that the number of processes can be reduced and it becomes easy to improve the productivity and reduce the manufacture cost. | 03-17-2011 |
| 20110068383 | SEMICONDUCTOR DEVICE - It is an object of the present invention to surely protect a predetermined semiconductor element or a predetermined semiconductor element group in an analog block from a noise generated from a digital block. A semiconductor device according to the present invention includes a semiconductor substrate, a digital block to be a region in which a digital circuit is formed and an analog block to be a region in which an analog circuit is formed, arranged by separating an upper surface of the semiconductor substrate and a substrate potential fixing region provided on the semiconductor substrate so as to surround in a planar view the predetermined semiconductor element group in the analog block, and a pad connected to the substrate potential fixing region and receiving a predetermined potential from an external part. | 03-24-2011 |
| 20110079834 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device has: a MISFET having source/drain diffusion layers; first plugs respectively connected to the source/drain diffusion layers; a first interconnection connected to one of the source/drain diffusion layers through the first plug; a second plug electrically connected to the other Of the source/drain diffusion layers through the first plug; a second interconnection connected to the second plug; and a capacitor electrode located above a gate electrode of the MISFET. The first interconnection is formed not above the lower capacitor electrode, while the second interconnection is formed above the upper capacitor electrode. A plug connecting the first interconnection and another interconnection is not provided at an upper location of the one of the source/drain diffusion layers. The first interconnection is not provided at an upper location of the other of the source/drain diffusion layers. | 04-07-2011 |
| 20110084324 | RADIATION HARDENED MOS DEVICES AND METHODS OF FABRICATION - Radiation hardened NMOS devices suitable for application in NMOS, CMOS, or BiCMOS integrated circuits, and methods for fabricating them. A device includes a p-type silicon substrate, a field oxide surrounding a moat region on the substrate tapering through a bird's beak region to a gate oxide within the moat region, a heavily-doped p-type guard region underlying at least a portion of the bird's beak region and terminating at the inner edge of the bird's beak region, a gate crossing the moat region, and n-type source and drain regions spaced by a gap from the inner edge of the guard region. A variation of a local oxidation of silicon process is used with an additional bird's beak implantation mask as well as minor alterations to the conventional moat and n-type source/drain masks. The resulting devices have improved radiation tolerance while having a high breakdown voltage and minimal impact on circuit density. | 04-14-2011 |
| 20110084325 | DRAM STRUCTURE WITH A LOW PARASITIC CAPACITANCE AND METHOD OF MAKING THE SAME - An oxide spacer for stack DRAM gate stack is described, including: a semiconductor substrate with a memory array region and a periphery region, a plurality of gates disposed within the memory array region and the periphery region respectively, a silicon oxide spacer disposed on the gates, where the polysilicon contact plugs are formed by polysilicon deposition and chemical mechanical polish. After polysilicon contact plugs are formed, a silicon oxide layer is deposited to isolate the contacts and gate. The silicon oxide layer on top of contact plug is removed by chemical mechanical polish achieve planarization. | 04-14-2011 |
| 20110084326 | Densely-Paced Films of Lanthanide Oxide Nanoparticles Via Electrophoretic Deposition - A method of forming a film of lanthanide oxide nanoparticles. In one embodiment of the present invention, the method includes the steps of: (a) providing a first substrate with a conducting surface and a second substrate that is positioned apart from the first substrate, (b) applying a voltage between the first substrate and the second substrate, (c) immersing the first substrate and the second substrate in a solution that comprises a plurality of lanthanide oxide nanoparticles suspended in a non-polar solvent or apolar solvent for a first duration of time effective to form a film of lanthanide oxide nanoparticles on the conducting surface of the first substrate, and (d) after the immersing step, removing the first substrate from the solution and exposing the first substrate to air while maintaining the applied voltage for a second duration of time to dry the film of lanthanide oxide nanoparticles formed on the conducting surface of the first substrate. | 04-14-2011 |
| 20110089475 | MEMORY DEVICE AND SEMICONDUCTOR DEVICE - A memory device capable of data writing at a time other than during manufacturing is provided by using a memory element including an organic material. In a memory cell, a third conductive film, an organic compound, and a fourth conductive film are stacked over a semiconductor film provided with an n-type impurity region and a p-type impurity region, and a pn-junction diode is serially connected to the memory element. A logic circuit for controlling the memory cell includes a thin film transistor. The memory cell and the logic circuit are manufactured over one substrate at the same time. The n-type impurity region and the p-type impurity region of the memory cell are manufactured at the same time as the impurity region of the thin film transistor. | 04-21-2011 |
| 20110101433 | UNIT BLOCK CIRCUIT OF SEMICONDUCTOR DEVICE - A unit block circuit of a semiconductor device includes a first well, a first pickup unit configured to form a closed loop over the first well, a first transistor including a first gate and a first active region, and formed within the first pickup unit, and a first reservoir capacitor formed in a spare within the first pickup unit and arranged in a major-axis direction of the first gate of the first transistor, wherein the first reservoir capacitor comprises a second active region and a second gate, the second gate being formed over the second active region. | 05-05-2011 |
| 20110101434 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor storage device includes: memory cells including a transistor and a capacitor; bit lines; word lines; and sense amplifiers including first and second sense amplifiers, wherein the memory cells includes: a first memory cell group sharing a first auxiliary word line; and a second memory cell group sharing a second auxiliary word line, wherein the word lines includes a first word line coupled to the first auxiliary word line and a second word line coupled to the second auxiliary word line, the first word line is coupled to the first auxiliary word line in a first word line contact region, the second word line is coupled to the second auxiliary word line in a second word line contact region, the bit lines includes first and second bit lines coupled to the first sense amplifier on both sides of the first word line contact region. | 05-05-2011 |
| 20110108900 | BI-DIRECTIONAL SELF-ALIGNED FET CAPACITOR - A method of forming a field effect transistor (FET) capacitor includes forming a channel region; forming a gate stack over the channel region; forming a first extension region on a first side of the gate stack, the first extension region being formed by implanting a first doping material at a first angle such that a shadow region exists on a second side of the gate stack; and forming a second extension region on the second side of the gate stack, the second extension region being formed by implanting a second doping material at a second angle such that a shadow region exists on the first side of the gate stack. | 05-12-2011 |
| 20110115005 | MIM CAPACITOR STRUCTURE IN FEOL AND RELATED METHOD - A capacitor structure includes a semiconductor substrate; a first capacitor plate positioned on the semiconductor substrate, the first capacitor plate including a polysilicon structure having a surrounding spacer; a silicide layer formed in a first portion of an upper surface of the first capacitor plate; a capacitor dielectric layer formed over a second portion of the upper surface of the first capacitor plate and extending laterally beyond the spacer to contact the semiconductor substrate; a contact in an interlayer dielectric (ILD), the contact contacting the silicide layer and a first metal layer over the ILD; and a second capacitor plate over the capacitor dielectric layer, wherein a metal-insulator-metal (MIM) capacitor is formed by the first capacitor plate, the capacitor dielectric layer and the second capacitor plate and a metal-insulator-semiconductor (MIS) capacitor is formed by the second capacitor plate, the capacitor dielectric layer and the semiconductor substrate. | 05-19-2011 |
| 20110115006 | SUBSTRATE FOR SEMICONDUCTOR DEVICE, METHOD FOR PRODUCING THE SAME, SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS - A substrate for a semiconductor device includes a substrate; a transistor disposed on the substrate and including a semiconductor layer, a first insulating film provided in the form of islands so as to at least partly overlap with the semiconductor layer in plan view on the substrate, and a gate electrode disposed so as to face the semiconductor layer with the first insulating film therebetween; and a second insulating film that is disposed on the substrate as substantially the same film as the first insulating film and that is formed in the form of islands so that at least one of the material and the thickness of the second insulating film is different from that of the first insulating film. | 05-19-2011 |
| 20110115007 | Power Semiconductor Component with Plate Capacitor Structure Having an Edge Plate Electrically Connected to Source or Drain Potential - A lateral power semiconductor component has a front side, a rear side and a lateral edge. The component further includes a drift zone of a first conductivity type, a source zone of the first conductivity type, a body zone of a second conductivity type opposite the first conductivity type, and a drain zone of the first conductivity type. A gate forms a MOS structure with the drift zone, the source zone and the body zone. A horizontally extending field plate above each semiconductor region of the power semiconductor component forms a plate capacitor structure with an edge plate lying under the field plate. The edge plate includes a highly doped semiconductor material and is electrically connected to one of a source potential and a drain potential of the power semiconductor component. | 05-19-2011 |
| 20110121372 | EDRAM Architecture - A process for manufacturing an eDRAM device comprises fabricating semiconductor features on a semiconductor substrate, the semiconductor substrate including a DRAM area and logic area. The process also includes fabricating a first conductive layer in the DRAM area and in the logic area, the first conductive layer in communication with a first group of the semiconductor features. After fabricating the first conductive layer, a storage component is fabricated in communication with a second group of the semiconductor features within the DRAM area. | 05-26-2011 |
| 20110121373 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor memory device includes a substrate of a first impurity type, a first well region of a second impurity type in the substrate, the second impurity type being different from the first impurity type, a second well region of the first impurity type in the substrate, a patterned first dielectric layer on the substrate extending over the first and second well regions, a patterned first gate structure on the patterned first dielectric layer, a patterned second dielectric layer on the patterned first gate structure, and a patterned second gate structure on the patterned second dielectric layer. The patterned first gate structure may include a first section extending in a first direction and a second section extending in a second direction orthogonal to the first section, wherein the first section and the second section intersects each other in a cross pattern. The patterned second gate structure may include at least one of a first section extending in the first direction over the first section of the patterned first gate structure or a second section extending in the second direction over the second section of the patterned first gate structure. | 05-26-2011 |
| 20110121374 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A vertical transistor comprises a semiconductor region, a pillar region formed on the semiconductor region, a gate insulating film formed so as to cover a side surface of the pillar region, a gate electrode formed on the gate insulating film, a first impurity diffusion region formed in an upper portion of the pillar region, and a second impurity diffusion region formed in the semiconductor region so as to surround the pillar region. The first impurity diffusion region is formed so as to be spaced from the side surface of the pillar region. | 05-26-2011 |
| 20110121375 | SEMICONDUCTOR DEVICE - A semiconductor device of the present invention has a semiconductor substrate having a transistor formed thereon; a multi-layered interconnect formed on the semiconductor substrate, and having a plurality of interconnect layers, respectively composed of an interconnect and an insulating film, stacked therein; and a capacitance element having a lower electrode (lower electrode film), a capacitor insulating film, and an upper electrode (upper electrode film), all of which being embedded in the multi-layered interconnect, so as to compose a memory element, and further includes at least one layer of damascene-structured copper interconnect (second-layer interconnect) formed between the capacitance element and the transistor; the upper surface of one of the interconnects (second-layer interconnect) and the lower surface of the capacitance element are aligned nearly in the same plane; and at least one layer of copper interconnect (plate line interconnect) is formed over the capacitance element. | 05-26-2011 |
| 20110121376 | Dielectric Layers and Memory Cells Including Metal-Doped Alumina - A method of forming (and an apparatus for forming) a metal-doped aluminum oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process. | 05-26-2011 |
| 20110127594 | SEMICONDUCTOR DEVICE AND MANUFACTURING THE SAME - A semiconductor device including a MISFET formed in a well at a main surface of a substrate, a second MISFET formed at a main surface of the substrate, and a passive element formed over the main surface of the substrate and having two terminals. A conductive film is formed at a rear face of the semiconductor substrate. The conductive film is connected with a fixed potential and also electrically connected with the conductive film. | 06-02-2011 |
| 20110127595 | INTEGRATED CIRCUIT DEVICES INCLUDING A MULTI-LAYER STRUCTURE WITH A CONTACT EXTENDING THERETHROUGH - Integrated circuit devices have a first substrate layer and a first transistor on the first substrate layer. A first interlayer insulating film covers the first transistor. A second substrate layer is on the first interlayer insulating film and a second transistor is on the second substrate layer. A second interlayer insulating film covers the second transistor. A contact extends through the second interlayer insulating film, the second substrate layer and the first interlayer insulating film. The contact includes a lower contact and an upper contact that contacts an upper surface of the lower contact to define an interface therebetween. The interface is located at a height no greater than a height of a top surface of the second substrate and greater than a height of a bottom surface of the second substrate layer. | 06-02-2011 |
| 20110133261 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes an active region defined by an isolation region formed in a cell area, buried gates disposed in the active region and the isolation region, conduction layers disposed on the active region and having the same heights as an surface of the isolation region, and a line type storage node contact connected with one of the conduction layers. | 06-09-2011 |
| 20110133262 | Power Semiconductor Component with Plate Capacitor Structure and Edge Termination - A semiconductor component includes a body with a drift zone, a source zone, a body zone, and a drain zone. A gate forms a MOS structure with the drift zone, with the source zone and with the body zone. An edge termination between the lateral edge and the MOS structure includes a plurality of field rings which enclose the MOS structure. The lateral edge is at the same potential as the drift zone, and the edge termination reduces voltage between the lateral edge and the source zone. A horizontally extending edge plate is disposed at the front side between the lateral edge and the edge termination. The edge plate is at the same potential as the drift zone and forms a plate capacitor structure including a field plate lying above the edge plate. | 06-09-2011 |
| 20110133263 | SEMICONDUCTOR DEVICE HAVING REDUCED SUB-THRESHOLD LEAKAGE - A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least partially between the fin and the semiconductor substrate. The cavity may be formed within a shallow trench isolation structure, and it may also extend at least partially between the semiconductor substrate and one or both of the pillars. The cavities increase the impedance between the semiconductor substrate and the fin and/or pillars to decrease the sub-threshold leakage of the FinFET transistor. | 06-09-2011 |
| 20110140183 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a gate electrode on a gate insulating film over a semiconductor substrate, a first sidewall insulating film on a side surface of the gate electrode, and source and drain regions, each including a pocket diffusion layer of a first conductivity type, and first and second diffusion layers of a second conductivity type. The pocket diffusion layer is disposed in the semiconductor substrate. The first diffusion layer of a second conductivity type extends over the pocket diffusion layer. The first diffusion layer faces toward the gate electrode through the first sidewall insulating film. The second diffusion layer over the first diffusion layer is higher in impurity concentration than the first diffusion layer. The second diffusion layer is separated by the first diffusion layer from the pocket diffusion layer, and has a side surface which faces toward the first sidewall insulating film through the first diffusion layer. | 06-16-2011 |
| 20110140184 | SURROUND GATE ACCESS TRANSISTORS WITH GROWN ULTRA-THIN BODIES - A vertical transistor having an annular transistor body surrounding a vertical pillar, which can be made from oxide. The transistor body can be grown by a solid phase epitaxial growth process to avoid difficulties with forming sub-lithographic structures via etching processes. The body has ultra-thin dimensions and provides controlled short channel effects with reduced need for high doping levels. Buried data/bit lines are formed in an upper surface of a substrate from which the transistors extend. The transistor can be formed asymmetrically or offset with respect to the data/bit lines. The offset provides laterally asymmetric source regions of the transistors. Continuous conductive paths are provided in the data/bit lines which extend adjacent the source regions to provide better conductive characteristics of the data/bit lines, particularly for aggressively scaled processes. | 06-16-2011 |
| 20110140185 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF - In a semiconductor integrated circuit device, testing pads ( | 06-16-2011 |
| 20110147817 | SEMICONDUCTOR COMPONENT HAVING AN OXIDE LAYER - Semiconductor component having an oxide layer. One embodiment includes a first semiconductor region and a second semiconductor region. An oxide layer is arranged between the first and second semiconductor region. The first semiconductor region and the oxide layer form a first semiconductor-oxide interface. The second semiconductor region and the oxide layer form a second semiconductor-oxide interface. The oxide layer has a chlorine concentration, the chlorine concentration having a first maximum in the region of the first semiconductor-oxide interface, and having a second maximum in the region of the second semiconductor-oxide interface. | 06-23-2011 |
| 20110156116 | RELAXED-PITCH METHOD OF ALIGNING ACTIVE AREA TO DIGIT LINE - According to one aspect of the invention, a memory device is disclosed. The memory device comprises a substantially linear active area comprising a source and at least two drains defining a first axis. The memory device further comprises at least two substantially parallel word lines, at least a portion of a first word line located between a first drain and the source, and at least a portion of a second word line located between a second drain and the source, which word lines define a second axis. The memory device further comprises a digit line coupled to the source, wherein the digit line forms a substantially zig-zag pattern. | 06-30-2011 |
| 20110169061 | Semiconductor device and method for manufacturing the same - The semiconductor device comprises a first region, a guard ring surrounding the first region, and a second region outside of the guard ring. The first region includes a first electrode made of a first film which has conductivity. A surface of the first electrode in the first region is not covered with the second film. The guard ring includes the first film covering an inner wall of a groove having a recess shape, and a second film as an insulating film covering at least one portion of a surface of the first film in the groove. | 07-14-2011 |
| 20110169062 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes the following elements. An element isolation portion separates first and second diffusion regions in a semiconductor substrate each other. A first insulating film is formed over the element isolation portion and the first and second diffusion regions. First and second contact plugs are formed over the first and second diffusion regions, respectively. The first and second contact plugs penetrate the first insulating film. A first conductive layer is formed over the first insulating film over the element isolation portion. A second insulating film is formed over the first conductive layer. A third contact plug penetrates the second insulating film, the third contact plug connecting the first contact plug. A second conductive layer is formed over the second insulating film contacting the third contact plug. The first and second conductive layers partly overlap the element isolation portion. | 07-14-2011 |
| 20110169063 | INTEGRATED CIRCUITS AND TRANSISTOR DESIGN THEREFOR - The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions can be provided in pairs, with one of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The source/drain regions extending to the digit line can have the same composition as the source/drain regions extending to the memory storage devices, or can have different compositions from the source/drain regions extending to the memory storage devices. The invention also includes methods of forming semiconductor structures. In exemplary methods, a lattice comprising a first material is provided to surround repeating regions of a second material. At least some of the first material is then replaced with a gateline structure, and at least some of the second material is replaced with vertical source/drain regions. | 07-14-2011 |
| 20110180862 | EMBEDDED DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD - Embodiments of the invention provide an integrated circuit for an embedded dynamic random access memory (eDRAM), a semiconductor-on-insulator (SOI) wafer in which such an integrated circuit may be formed, and a method of forming an eDRAM in such an SOI wafer. One embodiment of the invention provides an integrated circuit for an embedded dynamic random access memory (eDRAM) comprising: a semiconductor-on-insulator (SOI) wafer including: an n-type substrate; an insulator layer atop the n-type substrate; and an active semiconductor layer atop the insulator layer; a plurality of deep trenches, each extending from a surface of the active semiconductor layer into the n-type substrate; a dielectric liner along a surface of each of the plurality of deep trenches; and an n-type conductor within each of the plurality of deep trenches, the dielectric liner separating the n-type conductor from the n-type substrate; wherein the n-type substrate, the dielectric liner, and the n-type conductor form a buried plate, a node dielectric, and a node plate, respectively, of a cell capacitor. | 07-28-2011 |
| 20110198677 | SYSTEMS AND METHODS FOR A CONTINUOUS-WELL DECOUPLING CAPACITOR - A decoupling capacitor includes a pair of MOS capacitors formed in wells of opposite plurality. Each MOS capacitor has a set of well-ties and a high-dose implant, allowing high frequency performance under accumulation or depletion biasing. The top conductor of each MOS capacitor is electrically coupled to the well-ties of the other MOS capacitor and biased consistently with logic transistor wells. The well-ties and/or the high-dose implants of the MOS capacitors exhibit asymmetry with respect to their dopant polarities. | 08-18-2011 |
| 20110198678 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - An electrostatic discharge (ESD) protection circuit, suitable for an input stage circuit including a first N channel metal oxide semiconductor (NMOS) transistor, is provided. The ESD protection circuit includes an P channel metal oxide semiconductor (PMOS) transistor and an impedance device, in which the PMOS transistor has a source coupled to a gate of the first NMOS transistor, and a drain coupled to a source of the first NMOS transistor, and the impedance device is coupled between a gate of the PMOS transistor and a first power rail to perform a initial-on ESD protection circuit. The ESD protection circuit formed by the PMOS transistor and the resistor is capable of increasing the turn-on speed of the ESD protection circuit and preventing the input stage circuit from a CDM ESD event. | 08-18-2011 |
| 20110204426 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a stacked structure that is formed by laminating a first insulating film, first conductive layer, second insulating film and second conductive layer on a semiconductor substrate and in which the first and second conductive layers are connected with a via electrically, an interlayer insulating film formed to electrically separate the second conductive layer into a first region including a connecting portion with the first conductive layer and a second region that does not include the connecting portion, a first contact plug formed on the first region and a second contact plug formed on the second region. An isolation insulating film is buried in portions of the substrate, first insulating film and first conductive layer in one peripheral portion on the second region side of the stacked structure and the second contact plug is formed above the isolation insulating film. | 08-25-2011 |
| 20110204427 | CAPACITOR HAVING AN ELECTRODE STRUCTURE, METHOD OF MANUFACTURING A CAPACITOR HAVING AN ELECTRODE STRUCTURE AND SEMICONDUCTOR DEVICE HAVING AN ELECTRODE STRUCTURE - A capacitor includes an object or a substrate including an insulation layer having an opening, an electrode structure having conductive patterns, a dielectric layer and an upper electrode. The electrode structure may have a first conductive pattern including metal and a second conductive pattern including metal oxide generated from the first conductive pattern. The first conductive pattern may fill the opening and may protrude over the insulation layer. The second conductive pattern may extend from the first conductive pattern. The electrode structure may additionally include a third conductive pattern disposed on the second conductive pattern. The capacitor including the electrode structure may ensure improved structural stability and electrical characteristics. | 08-25-2011 |
| 20110210384 | Scalable integrated MIM capacitor using gate metal - According to one embodiment, a scalable integrated MIM capacitor in a semiconductor die includes a high-k dielectric segment over a substrate and a metal segment over the high-k dielectric segment, where the metal segment forms a capacitor terminal of the integrated MIM capacitor. The capacitor further includes a filler laterally separating consecutive capacitor terminals, where the filler can be used as a capacitor dielectric of the integrated MIM capacitor. In one embodiment, the metal segment comprises a gate metal. In another embodiment, the integrated MIM capacitor is formed substantially concurrently with one or more transistors without requiring additional fabrication process steps. | 09-01-2011 |
| 20110215388 | PIN CAPACITOR OF SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A pin capacitor of a semiconductor device includes a first isolation layer formed in a substrate and defining a dummy active area, a plurality of gates formed over the first isolation layer, a spacer formed at both sidewalls of each of the gates, and a plug formed over the dummy active area and in contact with the spacer. The substrate and the plug are coupled to a ground unit, and the gate is coupled to a pad unit. That is, the pin capacitor includes a first capacitor including the gate, the isolation layer, and the substrate and a second capacitor including the gate, the spacer, and the plug, which are coupled in parallel to each other. | 09-08-2011 |
| 20110220977 | SEMICONDUCTOR DEVICES WITH BURIED BIT LINES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A semiconductor device, comprising: a vertical pillar transistor (VPT) formed on a silicon-on-insulator (SOI) substrate, the VPT including a body that has a lower portion and an upper portion, a source/drain node disposed at an upper end portion of the upper portion of the body and a drain/source node disposed at the lower portion of the body; a buried bit line (BBL) formed continuously on sidewalls and an upper surface of the lower portion, the BBL includes metal sificide; and a word line that partially enclosing the upper portion of the body of the VPT, wherein the BBL extends along a first direction and the word line extends in a second direction substantially perpendicular to the first direction. An offset region is disposed immediately beneath the word line. | 09-15-2011 |
| 20110220978 | SEMICONDUCTOR DEVICE - In an embodiment, provided is a semiconductor device in which a normally-on type FET; a capacitor having one electrode electrically connected to a gate of the FET and the other electrode electrically connected to an input terminal; and a diode having an anode electrode electrically connected to the gate of the FET and a cathode electrode electrically connected to a source of the FET are formed on the same chip on which the FET is formed. Also, the capacitor may have a structure in which an insulation film such as a dielectric substance is formed on a gate drawn electrode of the FET, and a metallic layer is formed on the insulation layer. | 09-15-2011 |
| 20110220979 | SEMICONDUCTOR DEVICE AND MULTI-LAYERED WIRING SUBSTRATE - There is provided a semiconductor device in which a wiring inductance of a DC/DC converter formed on a multi-layered wiring substrate can be reduced and the characteristics can be improved. In the semiconductor device, in an input-side capacitor, one capacitor electrode is electrically connected to a power-supply pattern between a control power MOSFET and a synchronous power MOSFET, and the other capacitor electrode is electrically connected to a ground pattern therebetween. The multi-layered wiring substrate includes: a via conductor arranged at a position of the one capacitor electrode for electrically connecting among a plurality of power-supply patterns in a thickness direction; and a via conductor arranged at a position of the other capacitor electrode for electrically connecting among a plurality of ground patterns in a thickness direction. | 09-15-2011 |
| 20110233628 | FIELD EFFECT TRANSISTOR SWITCH FOR RF SIGNALS AND METHOD OF MAKING THE SAME - A switching device has an input node, an output node, and a control node. The device includes: a substrate having a first side and a second side with a ground plane on the first side of the substrate and a mesa on the second side of the substrate. The mesa is made of a normally-conductive semiconductor material, and an isolation region substantially surrounds the mesa. A field effect transistor (FET) is on the mesa. The FET has an input terminal connected to the input node, an output terminal connected to the output node, and a gate. A capacitor is connected in series between the output terminal of the FET and the gate, and a resistor is connected in series between the control node and the gate. A gate electrode is directly connected to the gate. The gate electrode is disposed substantially entirely on the mesa. | 09-29-2011 |
| 20110233629 | Integrated Circuit Devices Having High Density Logic Circuits Therein Powered Using Multiple Supply Voltages - Integrated circuit devices include a substrate having a semiconductor substrate region therein containing multiple well regions of different conductivity type. A first semiconductor well region of first conductivity type is provided in the semiconductor substrate region. This first semiconductor well region has a first plurality of transistor regions therein arranged in a first zig-zag pattern extending across the semiconductor substrate region. A second semiconductor well region of second conductivity type is also provided in the semiconductor substrate region. This second semiconductor well region has a second plurality of transistor regions therein arranged in a second zig-zag pattern extending across the semiconductor substrate region. This second zig-zag pattern is intertwined with the first zig-zag pattern. A plurality of first transistors of second conductivity type are provided in the first plurality of transistor regions and a plurality of second transistors of first conductivity type are provided in the second plurality of transistors regions. | 09-29-2011 |
| 20110233630 | INTEGRATED CIRCUIT HAVING A SEMICONDUCTOR SUBSTRATE WITH BARRIER LAYER - An integrated circuit having a semiconductor substrate with a barrier layer is disclosed. The arrangement includes a semiconductor substrate and a metallic element. A carbon-based barrier layer is disposed between the semiconductor substrate and the metallic element. | 09-29-2011 |
| 20110254066 | SEMICONDUCTOR DEVICE - A semiconductor device includes, a semiconductor substrate, a first transistor of a first conductivity type, a second transistor of a second conductivity type, a first capacitor, and a first wiring. The semiconductor substrate includes first, second, and third regions. The third region is sandwiched between the first and second regions. The first transistor of the first conductivity type is disposed in the first region. The second transistor of the second conductivity type is disposed in the second region. The first capacitor is disposed in the third region. The first wiring electrically couples one of main electrodes of the first transistor and one of main electrodes of the second transistor. The first wiring passes above the first capacitor. | 10-20-2011 |
| 20110254067 | DRAM Layout with Vertical FETS and Method of Formation - DRAM cell arrays having a cell area of about 4F | 10-20-2011 |
| 20110254068 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention provides a semiconductor device in which a bottom-gate TFT or an inverted stagger TFT arranged in each circuit is suitably constructed in conformity with the functionality of the respective circuits, thereby attaining an improvement in the operating efficiency and reliability of the semiconductor device. In the structure, LDD regions in a pixel TFT are arranged so as not to overlap with a channel protection insulating film and to overlap with a gate electrode by at least a portion thereof. LDD regions in an N-channel TFT of a drive circuit is arranged so as not to overlap with a channel protection insulating film and to overlap with a gate electrode by at least a portion thereof. LDD regions in a P-channel TFT of the drive circuit is arranged so as to overlap with a channel protection insulating film and to overlap with the gate electrode. | 10-20-2011 |
| 20110260225 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a substrate and a plurality of unit cells vertically arranged on the substrate. | 10-27-2011 |
| 20110260226 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a gate formed over an active region of a semiconductor substrate, a first spacer formed at a sidewall of the gate, a first contact plug formed at a lower sidewall of the first spacer being coupled to the active region, a second spacer formed at a sidewall of the first spacer over the first contact plug, and a second contact plug formed over the first contact plug. | 10-27-2011 |
| 20110260227 | FIN FET AND METHOD OF FABRICATING SAME - A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode. | 10-27-2011 |
| 20110266601 | Single Gate Semiconductor Device - A semiconductor device has a gate multiple doping regions on both sides of the gate. The gate can be shared by a transistor and a capacitor. | 11-03-2011 |
| 20110266602 | SEMICONDUCTOR DEVICES INCLUDING STORAGE NODE LANDING PADS SEPARATED FROM BIT LINE CONTACT PLUGS - A Dynamic Random Access Memory (DRAM) device can include a semiconductor substrate that includes an active region including a source region therein. A gate line can cross the active region and a first contact plug can be on the active region adjacent to the gate line and can be connected to the source region. A conductive layer can be on the first contact plug to expose a portion of the first contact plug and a capacitor storage node electrode can be on the conductive layer. | 11-03-2011 |
| 20110278654 | SEMICONDUCTOR DEVICE - A semiconductor device comprises an interlayer insulation film, a wiring embedded in the interlayer insulation film and an air gap part formed between a side surface of the wiring and the interlayer insulation film. | 11-17-2011 |
| 20110278655 | Semiconductor Device with Circuit for Reduced Parasitic Inductance - Parasitic inductance of the main circuit of a power source unit is reduced. In a non-insulated DC-DC converter having a circuit in which a power MOSFET for high side switch and a power MOSFET for low side switch are connected in series, the power MOSFET for high side switch and the power MOSFET for low side switch are formed of n-channel vertical MOSFETs, and a source electrode of the power MOSFET for high side switch and a drain electrode of the power MOSFET for low side switch are electrically connected via the same die pad. | 11-17-2011 |
| 20110284939 | SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNEL TRANSISTOR AND METHODS OF FABRICATING THE SAME - A semiconductor memory device includes a first pair of pillars extending from a substrate to form vertical channel regions, the first pair of pillars having a first pillar and a second pillar adjacent to each other, the first pillar and the second pillar arranged in a first direction, a first bit line disposed on a bottom surface of a first trench formed between the first pair of pillars, the first bit line extending in a second direction that is substantially perpendicular to the first direction, a first contact gate disposed on a first surface of the first pillar with a first gate insulating layer therebetween, a second contact gate disposed on a first surface of the second pillar with a second gate insulating layer therebetween, the first surface of the first pillar and the first surface of the second pillar face opposite directions, and a first word line disposed on the first contact gate and a second word line disposed on the second contact gate, the word lines extending in the first direction. | 11-24-2011 |
| 20110284940 | Semiconductor Constructions And Electronic Systems - Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include 0C1T memory having transistor gates entirely over SOI, and methods of forming such 0C1T memory. | 11-24-2011 |
| 20110291166 | INTEGRATED CIRCUIT WITH FINFETS AND MIM FIN CAPACITOR - An integrated circuit having finFETs and a metal-insulator-metal (MIM) fin capacitor and methods of manufacture are disclosed. A method includes forming a first finFET comprising a first dielectric and a first conductor; forming a second finFET comprising a second dielectric and a second conductor; and forming a fin capacitor comprising the first conductor, the second dielectric, and the second conductor. | 12-01-2011 |
| 20110291167 | SEMICONDUCTOR DEVICE - In one embodiment, a semiconductor device includes a substrate having a through hole, and a MEMS capacitor provided above the substrate. The device further includes an integrated circuit configured to control the MEMS capacitor, the circuit including transistors on the substrate and being provided under the MEMS capacitor and on the substrate. Further, an area on the substrate immediately under the MEMS capacitor overlaps at least partially with the through hole. | 12-01-2011 |
| 20110291168 | SEMICONDUCTOR DEVICE HAVING ESD STRUCTURE - Semiconductor layers on active areas for transistors in a memory cell region (region A) and a peripheral circuit region (region B) are simultaneously epitaxially grown in the same thickness in which the adjacent semiconductor layers in region A do not come into contact with each other. Only semiconductor layer ( | 12-01-2011 |
| 20110298025 | FINFET-COMPATIBLE METAL-INSULATOR-METAL CAPACITOR - At least one semiconductor fin for a capacitor is formed concurrently with other semiconductor fins for field effect transistors. A lower conductive layer is deposited and lithographically patterned to form a lower conductive plate located on the at least one semiconductor fin. A dielectric layer and at least one upper conductive layer are formed and lithographically patterned to form a node dielectric and an upper conductive plate over the lower conductive plate as well as a gate dielectric and a gate conductor over the other semiconductor fins. The lower conductive plate, the node dielectric, and the upper conductive plate collectively form a capacitor. The finFETs may be dual gate finFETs or trigate finFETs. A buried insulator layer may be optionally recessed to increase the capacitance. Alternately, the lower conductive plate may be formed on a planar surface of the buried insulator layer. | 12-08-2011 |
| 20110298026 | LOGIC-BASED eDRAM USING LOCAL INTERCONNECTS TO REDUCE IMPACT OF EXTENSION CONTACT PARASITICS - An electronic device includes an active layer located over a substrate with the active layer having a logic circuit and an eDRAM cell. The electronic device also includes a first metallization level located over the active layer that provides logic interconnects and metal capacitor plates. The logic interconnects are connected to the logic circuit and the metal capacitor plates are connected to the eDRAM cell. The electronic device additionally includes a second metallization level located over the first metallization level that provides an interconnect connected to at least one of the logic interconnects, and a bit line that is connected to the eDRAM cell. A method of manufacturing an electronic device is also included. | 12-08-2011 |
| 20110298027 | SEMICONDUCTOR DEVICE - It is an object to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limitation on the number of writings. A semiconductor device includes a second transistor and a capacitor provided over a first transistor. A source electrode of the second transistor which is in contact with a gate electrode of the first transistor is formed using a material having etching selectivity with respect to the gate electrode. By forming the source electrode of the second transistor using a material having etching selectivity with respect to the gate electrode of the first transistor, a margin in layout can be reduced, so that the degree of integration of the semiconductor device can be increased. | 12-08-2011 |
| 20110309419 | PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A RESISTOR-CAPACITOR FILTER - A process of forming an electronic device can include forming a capacitor dielectric layer over a base region, wherein the base region includes a base semiconductor material, forming a gate dielectric layer over a substrate, forming a capacitor electrode over the capacitor dielectric layer, forming a gate electrode over the gate dielectric layer, and forming an input terminal and an output terminal to the capacitor electrode. The input terminal and the output terminal can be spaced apart from each other and are connected to different components within the electronic device. A filter can include the base region, the capacitor dielectric layer, and the capacitor electrode. A transistor structure can include the gate dielectric layer and the gate electrode. An electronic device can include a low-pass filter and a transistor structure, such as an n-channel transistor or a p-channel transistor. | 12-22-2011 |
| 20120001243 | SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limit on the number of write operations. The semiconductor device includes a first memory cell including a first transistor and a second transistor, a second memory cell including a third transistor and a fourth transistor, and a driver circuit. The first transistor and the second transistor overlap at least partly with each other. The third transistor and the fourth transistor overlap at least partly with each other. The second memory cell is provided over the first memory cell. The first transistor includes a first semiconductor material. The second transistor, the third transistor, and the fourth transistor include a second semiconductor material. | 01-05-2012 |
| 20120001244 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREFOR - In an active matrix type liquid crystal display device, in which functional circuits such as a shift register circuit and a buffer circuit are incorporated on the same substrate, an optimal TFT structure is provided along with the aperture ratio of a pixel matrix circuit is increased. There is a structure in which an n-channel TFT, with a third impurity region which overlaps a gate electrode, is formed in a buffer circuit, etc., and an n-channel TFT, in which a fourth impurity region which does not overlap the gate electrode, is formed in a pixel matrix circuit. A storage capacitor formed in the pixel matrix circuit is formed by a light shielding film, a dielectric film formed on the light shielding film, and a pixel electrode. Al is especially used in the light shielding film, and the dielectric film is formed anodic oxidation process, using an Al oxide film. | 01-05-2012 |
| 20120007159 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - It is an object to provide a semiconductor device integrating various elements without using a semiconductor substrate, and a method of manufacturing the same. According to the present invention, a layer to be separated including an inductor, a capacitor, a resistor element, a TFT element, an embedded wiring and the like, is formed over a substrate, separated from the substrate, and transferred onto a circuit board | 01-12-2012 |
| 20120012907 | Memory layout structure and memory structure - A memory layout structure is disclosed, in which, a lengthwise direction of each active area and each row of active areas form an included angle not equal to zero and not equal to 90 degrees, bit lines and word lines cross over each other above the active areas, the bit lines are each disposed above a row of active areas, bit line contact plugs or node contact plugs may be each disposed entirely on an source/drain region, or partially on the source/drain region and partially extend downward along a sidewall (edge wall) of the substrate of the active area to carry out a sidewall contact. Self-aligned node contact plugs are each disposed between two adjacent bit lines and between two adjacent word lines. | 01-19-2012 |
| 20120012908 | SEMICONDUCTOR DEVICE - The semiconductor device of the present invention includes a source electrode, a drain electrode, a gate electrode and a gate power feeding line. The gate electrode is disposed between said source electrode and said drain electrode. The gate power feeding line is connected to both ends of said gate electrode. | 01-19-2012 |
| 20120012909 | SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL HAVING CHARGE ACCUMULATION LAYER - A semiconductor device includes MOS transistors, capacitor elements, a voltage generating circuit, a contact plug, and a memory cell. The MOS transistor and the capacitor element are formed on a first one of the element regions and a second one of the element regions, respectively. In the voltage generating circuit, current paths of the MOS transistors are series-connected and the capacitor elements are connected to the source or drain of the MOS transistors. The contact plug is formed on the source or the drain to connect the MOS transistors or one of the MOS transistors and one of the capacitor elements. A distance between the gate and the contact plug both for a first one of the MOS transistors located in the final stage in the series connection is larger than that for a second one of the MOS transistors located in the initial stage in the series connection. | 01-19-2012 |
| 20120012910 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To prevent two contacts that have different heights, share at least one interlayer insulating film and are disposed close to each other from being short-circuited to each other due to misalignment thereof, a semiconductor device according to the invention has a recess in an interlayer insulating film in which a first contact having a lower height, the recess being formed by the upper surface of the first contact, and a silicon nitride sidewall is formed in the recess to extend from the upper surface of the first contact and along the side surface of the recess. | 01-19-2012 |
| 20120025282 | Raised Source/Drain Field Effect Transistor - In one exemplary embodiment of the invention, a semiconductor structure includes: a substrate; and a plurality of devices at least partially overlying the substrate, where the plurality of devices include a first device coupled to a second device via a first raised source/drain having a first length, where the first device is further coupled to a second raised source/drain having a second length, where the first device comprises a transistor, where the first raised source/drain and the second raised source/drain at least partially overly the substrate, where the second raised source/drain comprises a terminal electrical contact, where the second length is greater than the first length. | 02-02-2012 |
| 20120025283 | MEMORY DEVICE - In a semiconductor device having an enlarged contact area between a contact structure and a substrate, the substrate may include a first region on which a conductive structure is arranged and a second region defining the first region. The first region may include a multi-faced polyhedral recess of which at least one of the sidewalls is slanted with respect to a surface of the substrate. An insulation layer may be formed on the substrate to a thickness that is sufficient to cover the conductive structure. The insulation layer has a contact hole that may be communicated with the recess. The active region of the substrate is exposed through the contact hole. A conductive pattern is positioned in the recess and the contact hole. Accordingly, the contact resistance at the active region of the substrate may be kept to a relatively low value even though the gap distances and line width of pattern lines are reduced. | 02-02-2012 |
| 20120025284 | Semiconductor Device - A semiconductor device includes a material with which off-state current of a transistor can be sufficiently small; for example, an oxide semiconductor material is used. Further, transistors of memory cells of the semiconductor device, which include an oxide semiconductor material, are connected in series. Further, the same wiring (the j-th word line (j is a natural number greater than or equal to 2 and less than or equal to m)) is used as a wiring electrically connected to one of terminals of a capacitor of the j-th memory cell and a wiring electrically connected to a gate terminal of a transistor, in which a channel is formed in an oxide semiconductor layer, of the (j−1)-th memory cell. Therefore, the number of wirings per memory cell and the area occupied by one memory cell are reduced. | 02-02-2012 |
| 20120025285 | SYSTEM WITH LOGIC AND EMBEDDED MIM CAPACITOR - An embedded memory system includes an array of random access memory (RAM) cells, on the same substrate as an array of logic transistors. Each RAM cell includes an access transistor and a capacitor structure. The capacitor structure is fabricated by forming a metal-insulator-metal capacitor in a dielectric layer. The embedded RAM system includes fewer metal layers in the logic region than in the memory region | 02-02-2012 |
| 20120025286 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming silicon pillar | 02-02-2012 |
| 20120032242 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: a diffusion layer configuring a memory cell, and a diffusion layer configuring a dummy cell formed over the semiconductor substrate, interlayer insulating films formed over the semiconductor substrate, a cylinder layer insulating film including at least one concavity overlapping a diffusion layer and formed over an interlayer insulating film, a contact plug formed over one diffusion layer, a contact plug formed over another diffusion layer, a lower electrode formed over the side surfaces and bottom surface of the concavity and coupled to the diffusion layer by way of the contact plug, a dielectric material film formed over the lower electrode, over the cylinder layer insulating film and over the contact plug, and coupling by way of the contact plug to the diffusion layer, and an upper electrode formed over the inductive film material. | 02-09-2012 |
| 20120037969 | MONOLITHIC MICROWAVE INTEGRATED CIRCUIT - Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ≧100 Ohm-cm) semiconductor substrates ( | 02-16-2012 |
| 20120037970 | MICROELECTRONIC MEMORY DEVICES HAVING FLAT STOPPER LAYERS AND METHODS OF FABRICATING THE SAME - Memory devices comprise a microelectronic substrate including a cell array region and a peripheral region adjacent the cell array region, the cell array region including therein an array of memory cells and the peripheral region including therein peripheral circuits for the array of memory cells, the microelectronic substrate including a lower layer that extends across the cell array region and across the peripheral region and that includes a flat outer surface from the cell array region to the peripheral region. A signal transfer conductor layer extends in the cell array region beneath the flat outer surface of the lower layer and extends in the peripheral region above the flat outer surface of the lower layer. An insulating layer is provided on the lower layer, the insulating layer extending across the cell array region and the peripheral region and also including a flat outer surface from the cell array region to the peripheral region. A flat stopper layer is provided on the flat outer surface of the insulating layer and extending across the cell array region and the peripheral region. Finally, an array of memory cell capacitor storage nodes is provided in the cell array region that extend beyond the flat stopper layer and that penetrate through the flat stopper layer and the insulating layer. Related methods are also provided. | 02-16-2012 |
| 20120037971 | NONVOLATILE MEMORY DEVICE AND METHOD OF FORMING THE SAME - A nonvolatile memory device has a first active region and a second active region defined in a substrate by a device isolation layer, a Metal Oxide Silicon Field-Effect Transistor (MOSFET) disposed on the first active region and including a first electrode pattern, and a Metal Oxide Silicon (MOS) capacitor disposed on the second active region and including a second electrode pattern, and in which the first electrode pattern is narrower in the widthwise direction of the channel of the MOSFET than the first active region. | 02-16-2012 |
| 20120043595 | CAPACITOR DEVICE AND METHOD OF FABRICATING THE SAME - A capacitor device includes a substrate including a first well having a first conductivity type and a first voltage applied thereto and a second well having a second conductivity type and a second voltage applied thereto; and a gate electrode disposed on an upper portion of the first well or an upper portion of the second well in such a way that the gate electrode is insulated from the first well or the second well, wherein capacitances of the capacitor device include a first capacitance between the first well and the second well and a second capacitance between the first well or the second well and the gate electrode. | 02-23-2012 |
| 20120043596 | SEMICONDUCTOR DEVICES AND STRUCTURES INCLUDING AT LEAST PARTIALLY FORMED CONTAINER CAPACITORS - Semiconductor device structures include an at least partially formed container capacitor having a generally cylindrical first conductive member with at least one inner sidewall surface, a lattice material at least partially laterally surrounding an upper end portion of the first conductive member, an anchor material, and at least one aperture extending through the lattice material between the at least partially formed container capacitor and an adjacent at least partially formed container capacitor. Other structures include an at least partially formed container capacitor, a lattice material, and an anchor material disposed over a surface of the lattice material and at least a portion of an end surface of the first conductive member and forming a chemical barrier over at least a portion of an interface between the lattice material and the upper end portion of the first conductive member. | 02-23-2012 |
| 20120043597 | SEA-OF-FINS STRUCTURE ON A SEMICONDUCTOR SUBSTRATE AND METHOD OF FABRICATION - A semiconductor device and a method of fabricating a semiconductor device, wherein the method comprises forming, on a substrate, a plurality of planarized fin bodies to be used for customized fin field effect transistor (FinFET) device formation; forming a nitride spacer around each of the plurality of fin bodies; forming an isolation region in between each of the fin bodies; and coating the plurality of fin bodies, the nitride spacers, and the isolation regions with a protective film. The fabricated semiconductor device is used in customized applications as a customized semiconductor device. | 02-23-2012 |
| 20120056255 | Semiconductor device and method of fabricating the same - A semiconductor device includes a device formation region including a plurality of unit regions arranged in series to each other, each unit region comprising first and second active regions alternately arranged in series to each other. The first active region extends in a first direction. The second active region extends obliquely to the first direction. A plurality of first semiconductor pillars is arranged in the first direction and in each of the first active regions. A second semiconductor pillar is in each of the second active regions. A first bit line includes a first diffusion layer in the device formation region. The first diffusion layer extends under the plurality of first semiconductor pillars and the second semiconductor pillar. The first bit line connects the plurality of first semiconductor pillars and the second semiconductor pillar. A second bit line is electrically connected to the second semiconductor pillar. | 03-08-2012 |
| 20120056256 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device includes a first semiconductor pillar, a second semiconductor pillar, and a first wiring. The first semiconductor pillar includes a first diffusion region. The second semiconductor pillar is adjacent to the first semiconductor pillar. The first wiring is positioned between the first and second semiconductor pillars. The first wiring has a first metal surface. The first metal surface has an ohmic contact with the first diffusion region. | 03-08-2012 |
| 20120061739 | METHOD FOR FABRICATING CAPACITOR AND SEMICONDUCTOR DEVICE USING THE SAME - Provided are a method for fabricating a capacitor and a semiconductor device using the same. The semiconductor device includes a MOS transistor capacitor, first and second plate capacitors, and a metal interconnection. The MOS transistor capacitor is arranged between a power supply and a ground. The first and second plate capacitors are arranged between the power supply and the ground. The metal interconnection is configured to connect the first and second plate capacitors. | 03-15-2012 |
| 20120061740 | SUBRESOLUTION SILICON FEATURES AND METHODS FOR FORMING THE SAME - Novel etch techniques are provided for shaping silicon features below the photolithographic resolution limits. FinFET devices are defined by recessing oxide and exposing a silicon protrusion to an isotropic etch, at least in the channel region. In one implementation, the protrusion is contoured by a dry isotropic etch having excellent selectivity, using a downstream microwave plasma etch. | 03-15-2012 |
| 20120068237 | SELF-ALIGNED STRAP FOR EMBEDDED CAPACITOR AND REPLACEMENT GATE DEVICES - After forming a planarization dielectric layer in a replacement gate integration scheme, disposable gate structures are removed and a stack of a gate dielectric layer and a gate electrode layer is formed within recessed gate regions. Each gate electrode structure is then recessed below a topmost surface of the gate dielectric layer. A dielectric metal oxide portion is formed above each gate electrode by planarization. The dielectric metal oxide portions and gate spacers are employed as a self-aligning etch mask in combination with a patterned photoresist to expose and metalize semiconductor surfaces of a source region and an inner electrode in each embedded memory cell structure. The metalized semiconductor portions form metal semiconductor alloy straps that provide a conductive path between the inner electrode of a capacitor and the source of an access transistor. | 03-22-2012 |
| 20120068238 | LOW IMPEDANCE TRANSMISSON LINE - Transmission lines employing transmission line units or elements within integrated circuits (ICs) are well-known. Typically, different heights for these transmission line units can vary the characteristics of the cell (and transmission line), and there is typically a tradeoff between impedance and space (layout) specifications. Here, a transmission line is provided, which is generally comprised of elements of the same general width, but having differing or tapered heights that allow for impedance adjustments for high frequency applications (i.e., 160 GHz). For example, a transmission line that is coupled to a balun, with the transmission line units decreasing in height near the balun's center tap to adjust the impedance of the transmission line for the balun, is shown. | 03-22-2012 |
| 20120068239 | SEMICONDUCTOR MEMORY DEVICE HAVING A FLOATING BODY CAPACITOR, MEMORY CELL ARRAY HAVING THE SAME AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device having a floating body capacitor. The semiconductor memory device can perform a memory operation using the floating body capacitor. The semiconductor memory device includes an SOI substrate having a staked structure in which a base substrate having a conducting surface, a buried insulating layer and a device-forming layer are staked, a transistor formed in a portion of the device-forming layer, having a gate, a source region and a drain region, and a capacitor formed by the buried insulating layer, the conducting surface of the base substrate, and accumulated holes generated in the device-forming layer when the transistor is driven. | 03-22-2012 |
| 20120074477 | SEMICONDUCTOR DEVICE HAVING RAISED SOURCE AND DRAIN OF DIFFERING HEIGHTS - This semiconductor device has an MOS transistor equipped with a gate electrode formed on a semiconductor substrate, a source region next to one side of the gate electrode, and a drain region next to another side of the gate electrode, wherein an upper end of the source region and an upper end of the drain region are at positions where are higher than a top surface of the semiconductor substrate, and the height of the upper end of the drain region differs from the height of the upper end of the source region. | 03-29-2012 |
| 20120080734 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell portion and a peripheral circuit portion. The memory cell portion includes a pillar capacitor with a lower electrode, a dielectric film, and an upper electrode sequentially formed on a side surface of a first insulating portion which is parallel to a predetermined direction, and a transistor electrically connected to the lower electrode. The peripheral circuit portion includes a plate electrode, a cylinder capacitor with an upper electrode, a dielectric film, and a lower electrode sequentially formed on a side surface of the plate electrode which is parallel to the predetermined direction, and a transistor electrically connected to the lower electrode. | 04-05-2012 |
| 20120080735 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In the semiconductor device composing MOS transistor on which impurities are added from the surface of a P-type substrate, the region of immediate below a gate layer is the P-type substrate on which the impurities are not added, and first and second MOS devices, having an N-type diffusion layer are provided on the surface region of the P-type substrate circumscribing the gate layer. The gate layer of the first MOS device, and the N-type diffusion layer of the second MOS device are connected, and the N-type diffusion layer of the first MOS device and the gate layer of the second MOS device are connected, and thereby a first capacitive element is composed. | 04-05-2012 |
| 20120086060 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a semiconductor substrate, a gate electrode, a dummy gate electrode, and a first impurity diffusion region. The semiconductor substrate has first and second grooves. The gate electrode is in the first groove. The dummy gate electrode is in the second groove. The dummy gate electrode has a first top surface. The first impurity diffusion region in the semiconductor substrate is positioned between the first and second grooves. The first top surface is positioned at a lower level than a bottom of the first impurity diffusion region. | 04-12-2012 |
| 20120086061 | Semiconductor Device - A semiconductor device with a transistor for supplying a current to a pixel comprising an EL element, that can supply an accurate current without the influence of variations even when a small signal current, is provided. A precharge voltage is supplied in advance for the current supply to a pixel and subsequently, the signal writing is completed quickly. The precharge voltage is outputted from a circuit for supplying voltage and current that supplies a current to a current source circuit for supplying a current to the pixel. As the precharge voltage, a gate voltage of a transistor for supplying a current to the current source circuit is supplied to the pixel. Optimum precharge voltage can be supplied in the case where W/L of a transistor in the pixel and W/L of a transistor for supplying current in the circuit for supplying voltage and current are approximately equivalent to each other. | 04-12-2012 |
| 20120091516 | Lateral Floating Coupled Capacitor Device Termination Structures - Voltage termination structures include one or more capacitively coupled trenches, which can be similar to the trenches in the drift regions of the active transistor. The capacitively coupled trenches in the termination regions are arranged with an orientation that is either parallel or perpendicular to the trenches in the active device drift region. The Voltage termination structures can also include capacitively segmented trench structures having dielectric lined regions filled with conducting material and completely surrounded by a silicon mesa region. The Voltage termination structures can further include continuous regions composed entirely of an electrically insulating layer extending a finite distance vertically from the device surface. | 04-19-2012 |
| 20120091517 | SCRATCH PROTECTION FOR DIRECT CONTACT SENSORS - In capacitive sensor circuits where physical contact is required and excess pressure may be inadvertently applied to the sensor surface, aluminum is not sufficiently hard to provide “scratch” protection and may delaminate, causing circuit failure, even if passivation integrity remains intact. Because hard passivation layers alone provide insufficient scratch resistance, at least the capacitive electrodes and preferably all metallization levels within the sensor circuit in the region of the capacitive electrodes between the surface and the active regions of the substrate are formed of a conductive material having a hardness greater than that of aluminum, and at least as great as the lowest hardness for any interlevel dielectric or passivation material employed. | 04-19-2012 |
| 20120091518 | SEMICONDUCTOR DEVICE, METHOD FOR FORMING THE SAME, AND DATA PROCESSING SYSTEM - A semiconductor device includes a semiconductor substrate having a first groove, a word line in the first groove, and a buried insulating film in the first groove. The buried insulating film covers the word line. The buried insulating film comprises a silicon nitride film. | 04-19-2012 |
| 20120098045 | Zero Temperature Coefficient Capacitor - A zero temperature coefficient (ZTC) capacitor including a silicon dioxide dielectric layer with a phosphorus density between 1.7×10 | 04-26-2012 |
| 20120098046 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An ESD protection device is provided. The ESD protection device includes a first group of electrostatic discharge protection devices connected to a first terminal and including at least one of an LORGGR and an HORGGR, and a second group of electrostatic discharge protection devices connected in series to the first group of electrostatic discharge protection devices and a second terminal and including at least one of a GGNMOS, a GGPMOS and a diode. | 04-26-2012 |
| 20120104480 | STORAGE DEVICE - A storage device in which stored data can be held even when power is not supplied, and stored data can be read at high speed without turning on a transistor included in a storage element is provided. In the storage device, a memory cell having a transistor including an oxide semiconductor layer as a channel region and a storage capacitor is electrically connected to a capacitor to form a node. The voltage of the node is boosted up in accordance with stored data by capacitive coupling through a storage capacitor and the potential is read with an amplifier circuit to distinguish data. | 05-03-2012 |
| 20120104481 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor substrate including a DRAM portion and a logic portion thereon, an interlayer film covering the DRAM portion and logic portion of the semiconductor substrate, and plural contact plugs formed in the interlayer film in the DRAM portion and the logic portion, the plural contact plugs being in contact with a metal suicide layer on a highly-doped region of source and drain regions of first, second and third transistors in the DRAM portion and the logic portion, an interface between the plural contact plugs and the metal silicide layer being formed at a main surface in the DRAM portion and the logic portion. | 05-03-2012 |
| 20120112256 | Control gate structure and method of forming a control gate structure - Semiconductor devices and methods of fabricating the devices are provided. An example device may include a substrate and a gate structure on the substrate. The gate structure includes a control gate having at least three distinct gate regions. First and second control gate regions are configured as a first field type, such as a high-gate or low-gate type. A third control gate region configured as a second field type (different from the first field type) is at least partially disposed between the first and second control gate regions. | 05-10-2012 |
| 20120112257 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device with a novel structure in which stored data can be retained even when power is not supplied, and which does not have a limitation on the number of writing. The semiconductor device includes both a memory circuit including a transistor including an oxide semiconductor (in a broader sense, a transistor whose off-state current is sufficiently small), and a peripheral circuit such as a driver circuit including a transistor including a material other than an oxide semiconductor (that is, a transistor capable of operating at sufficiently high speed). Further, the peripheral circuit is provided in a lower portion and the memory circuit is provided in an upper portion, so that the area and size of the semiconductor device can be decreased. | 05-10-2012 |
| 20120112258 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes the following elements. A semiconductor substrate has a device formation region. The device formation region is defined by first and second device isolation regions which extend in first and second directions, respectively. The device formation region has a first gate groove which extends in the second direction. A first gate insulating film is disposed in a lower portion of the first gate groove. A first gate electrode is disposed on the first gate insulating film. The first gate electrode is disposed in the lower portion of the first gate groove. A buried insulating film is disposed over the first gate electrode. The buried insulating film is disposed in an upper portion of the first gate groove. | 05-10-2012 |
| 20120112259 | INTEGRATED CIRCUIT WITH PROTECTION FROM COPPER EXTRUSION - An integrated circuit may include an element placed in an insulating region adjacent to a copper metallization level and including a barrier layer in contact with a metallization level. The element may be electrically connected to and spaced away from a copper line of the metallization level by way of an electrical link passing through the barrier layer and including an electrically conductive material different from copper in direct contact with the copper line. | 05-10-2012 |
| 20120119275 | BURIED DECOUPLING CAPACITORS, DEVICES AND SYSTEMS INCLUDING SAME, AND METHODS OF FABRICATION - A buried decoupling capacitor apparatus and method are provided. According to various embodiments, a buried decoupling capacitor apparatus includes a semiconductor-on-insulator substrate having a buried insulator region and top semiconductor region on the buried insulator region. The apparatus embodiment also includes a first capacitor plate having a doped region in the top semiconductor region in the semiconductor-on-insulator substrate. The apparatus embodiment further includes a dielectric material on the first capacitor plate, and a second capacitor plate on the dielectric material. According to various embodiments, the first capacitor plate, the dielectric material and the second capacitor plate form a decoupling capacitor for use in an integrated circuit. | 05-17-2012 |
| 20120126299 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate; a gate insulating film formed above the semiconductor substrate; a charge storage layer formed above the gate insulating film; a multilayered interelectrode insulating film formed in a first region above an upper surface portion of the element isolation insulating film, a second region above a sidewall portion of the charge storage layer and a third region above an upper surface portion of the charge storage layer, the interelectrode insulating film including a stack of an upper silicon oxide film, a middle silicon nitride film, and a lower silicon oxide film; a control gate electrode formed above the interelectrode insulating film; wherein the middle silicon nitride film is thinner in the third region than in the second region and the upper silicon oxide film is thicker in the third region than in the second region. | 05-24-2012 |
| 20120126300 | CAPACITORS, SEMICONDUCTOR DEVICES INCLUDING THE SAME AND METHODS OF MANUFACTURING THE SEMICONDUCTOR DEVICES - A capacitor includes a first electrode, a first dielectric layer disposed on the first electrode, the first dielectric layer having a tetragonal crystal structure and including a first metal oxide layer doped with a first impurity, a second dielectric layer disposed on the first metal oxide layer, the second dielectric layer having a tetragonal crystal structure and including a second metal oxide layer doped with a second impurity, and a second electrode disposed on the second dielectric layer. The first dielectric layer has a lower crystallization temperature and a substantially higher dielectric constant than the second dielectric layer. | 05-24-2012 |
| 20120132968 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed. The method for manufacturing a semiconductor device includes forming a device isolation film defining an active region over a semiconductor substrate including a periphery region, forming a gate pattern over the active region, forming a contact plug coupled to each of the gate pattern and the active region, forming a line coupled to the contact plug and a first reservoir capacitor over the same layer as in the line, and forming a second storage capacitor coupled to the first storage capacitor. The semiconductor device sufficiently endures a high bias not only using a line electrode and a dielectric film of a periphery region but also using a MOS-type storage capacitor of an upper electrode, and couples a cylindrical storage capacitor in series to a MOS-type capacitor so that it can be used in a small region. | 05-31-2012 |
| 20120132969 | COMPENSATION NETWORK FOR RF TRANSISTOR - A compensation network for a radiofrequency transistor is disclosed. The compensation network comprises first and second bonding bars for coupling to a first terminal of the RF transistor and a compensation capacitor respectively; one or more bond wires coupling the first and second bonding bars together; and a compensation capacitor formed from a first set of conductive elements coupled to the second bonding bar, the first set of conductive elements interdigitating with a second set of conductive elements coupled to a second terminal of the RF transistor. | 05-31-2012 |
| 20120132970 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - Provided are semiconductor devices and methods of manufacturing the same. The semiconductor device may include a substrate provided with a transistor, an insulating layer disposed on the substrate, the insulating layer including a contact hole exposing a portion of the transistor, a spacer disposed on an inner sidewall of the contact hole, and a contact plug disposed in the contact hole. Here, a space defined by the spacer may increase in width from a bottom side thereof to a top side thereof. | 05-31-2012 |
| 20120132971 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a semiconductor substrate having a first gate groove having first and second side walls facing to each other. A first gate insulating film covers the first and second side walls. A first gate electrode is disposed on the first gate insulating film and in a lower portion of the first gate groove. A first burying insulating film buries the first gate groove and covers the first gate electrode. A first diffusion region is adjacent to a first upper portion of the first gate insulating film. The first upper portion is positioned on an upper portion of the first side wall of the first gate groove. A second diffusion region is in contact with an upper portion of the second side wall of the first gate groove. | 05-31-2012 |
| 20120132972 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device with active regions formed in the shape of a band in a substrate; a plurality of word lines arranged at equal intervals that intersect the active regions; cell contacts that includes first cell contacts in the active regions in the center portions in a longitudinal direction, and second cell contacts at both ends in the longitudinal direction; bit line contacts on the first cell contacts; bit lines that pass over the bit line contacts; storage node contacts on the second cell contacts; storage node contact pads on the storage node contacts; and storage capacitors on the storage node contact pads. The center positions of the storage node contacts are offset from the center positions of the second cell contacts. The center positions of the storage node contact pads are offset from the center positions of the storage node contacts. | 05-31-2012 |
| 20120132973 | PACKAGE CONFIGURATIONS FOR LOW EMI CIRCUITS - An electronic component includes a high voltage switching transistor encased in a package. The high voltage switching transistor comprises a source electrode, a gate electrode, and a drain electrode all on a first side of the high voltage switching transistor. The source electrode is electrically connected to a conducting structural portion of the package. Assemblies using the abovementioned transistor with another transistor can be formed, where the source of one transistor can be electrically connected to a conducting structural portion of a package containing the transistor and a drain of the second transistor is electrically connected to the second conductive structural portion of a package that houses the second transistor. Alternatively, the source of the second transistor is electrically isolated from its conductive structural portion, and the drain of the second transistor is electrically isolated from its conductive structural portion. | 05-31-2012 |
| 20120139020 | METHOD AND STRUCTURE FOR HIGH Q VARACTOR - A method for forming a variable capacitor includes providing a semiconductor substrate of a first conductivity type and forming an active region of a second conductivity type within the substrate. The method forms a first dielectric layer overlying the active region. The method provides a conductive gate layer over the first dielectric layer and selectively patterns the conductive gate layer to form a plurality of holes in the conductive gate layer. A perimeter of the holes and a spacing between a first and a second holes are selective to provide a high quality factor (Q) of the capacitor. The method implants impurities of the second conductivity type into the active region through the plurality of holes in the conductive layer. The method also includes providing a second dielectric layer and patterning the second dielectric layer to form contacts to the active region and the gate. | 06-07-2012 |
| 20120139021 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor memory device includes a transistor having a channel region buried in a substrate and source/drain regions formed to provide low contact resistance. A field isolation structure is formed in the substrate to define active structures. The field isolation structure includes a gap-fill pattern, a first material layer surrounding the gap-fill pattern, and a second material layer surrounding at least a portion of the first material layer. Each active structure includes a first active pattern having a top surface located beneath the level of the top surface of the field isolation structure, and a second active pattern disposed on the first active pattern and whose top is located above the level of the top surface of the field isolation structure. | 06-07-2012 |
| 20120146118 | NON-VOLATILE MEMORY DEVICE WITH HIGH SPEED OPERATION AND LOWER POWER CONSUMPTION - A semiconductor memory device has a memory cell region and a peripheral region. The device includes low voltage transistors at the peripheral region having gate insulation films with different thicknesses. For example, a gate insulation film of a low voltage transistor used in an input/output circuit of the memory device may be thinner than the gate insulation film of a low voltage transistor used in a core circuit for the memory device. Since low voltage transistors used at an input/output circuit are formed to be different from low voltage transistors used at a core circuit or a high voltage pump circuit, high speed operation and low power consumption characteristics of a non-volatile memory device may be. | 06-14-2012 |
| 20120146119 | Semiconductor Device - A semiconductor device to improve layout uniformity may include an active region formed in a substrate, a dummy active region formed in the substrate and separated from the active region, a word line crossing over the active region, and a dummy word line. The dummy word line is formed over the dummy active region to overlap at least part of the dummy active region and may have an end positioned within the dummy active region. | 06-14-2012 |
| 20120153369 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral circuit region, and an active region defined by a device isolation film, at least one dummy gate formed over the active region to expose a center part and both ends of the active region, a bit line contact plug formed between the dummy gates so as to be coupled to the center part of the active region, and a storage node contact plug that is spaced apart from the bit line contact plug by the dummy gate and is coupled to both ends of the active region. As a result, the problem that the storage node contact hole is not open in the semiconductor device can be solved, resulting in improved semiconductor device characteristics. | 06-21-2012 |
| 20120153370 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor integrated circuit device, includes a first electrode including a first semiconductor layer formed on a substrate, a side surface insulating film formed on at least a part of a side surface of the first electrode, an upper surface insulating film formed on the first electrode and the side surface insulating film, a second electrode which covers the side surface insulating film and the upper surface insulating film, and a fin-type field effect transistor. The first electrode, the side surface insulating film, and the second electrode constitute a capacitor element. A thickness of the upper surface insulating film between the first electrode and the second electrode is larger than a thickness of the side surface insulating film between the first electrode and the second electrode, and the fin-type field effect transistor includes a second semiconductor layer which protrudes with respect to the plane of the substrate. | 06-21-2012 |
| 20120161215 | RECTANGULAR CAPACITORS FOR DYNAMIC RANDOM ACCESS MEMORY (DRAM) AND DUAL-PASS LITHOGRAPHY METHODS TO FORM THE SAME - A rectangular capacitor for dynamic random access memory (DRAM) and a dual-pass lithography method to form the same are described. For example, a capacitor includes a trench disposed in a first dielectric layer disposed above a substrate. A cup-shaped metal plate is disposed along the bottom and sidewalls of the trench. A second dielectric layer is disposed on and conformal with the cup-shaped metal plate. A trench-fill metal plate is disposed on the second dielectric layer. The second dielectric layer isolates the trench-fill metal plate from the cup-shaped metal plate. The capacitor has a rectangular or near-rectangular shape from a top-down perspective. | 06-28-2012 |
| 20120161216 | ESD Protection Circuit - One embodiment of the disclosure provides an electrostatic discharge protection circuit, including a first resistor, a p-type field effect transistor, a capacitance device and an n-type field effect transistor. The first resistor has a first terminal coupled to a first rail and a second terminal coupled to a first node. The p-type field effect transistor has a source coupled to the first rail, a gate coupled to the first node and a drain coupled to a second node. The capacitance device has a first terminal coupled to a second rail or the second node and a second terminal coupled to the first node. The n-type field effect transistor has a source coupled to the second rail, a gate coupled to the second node and a drain coupled to the first node. | 06-28-2012 |
| 20120161217 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a semiconductor chip which includes a semiconductor integrated circuit provided in an insulator, a first pad a pad having an upper surface of which is exposed via an opening formed in the insulator, and capacitors provided in a capacitor region of the semiconductor chip under the pad. The capacitors are provided in the capacitor region to satisfy a rule of a coverage. And contacts respectively connected to two electrodes of the capacitors are provided at positions that do not vertically overlap the opening. | 06-28-2012 |
| 20120161218 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a first method for manufacturing a semiconductor device, an opening is formed in a substrate. A tungsten film is formed on the substrate so as to fill up inside the opening, and then the tungsten film is annealed. The tungsten film is etched back so that the tungsten film remains inside the opening. In a second method for manufacturing a semiconductor device, a laminate body comprising a tungsten film and an insulating film on the tungsten film is formed on a substrate. The laminate body is annealed, and then the laminate body is etched back. | 06-28-2012 |
| 20120161219 | SEMICONDUCTOR DEVICE - a semiconductor device is provided, which includes an N well having a peak concentration of 2E+17 atom/cm | 06-28-2012 |
| 20120161220 | SEMICONDUCTOR DEVICE - The degree of integration of a semiconductor device is enhanced and the storage capacity per unit area is increased. The semiconductor device includes a first transistor provided in a semiconductor substrate and a second transistor provided over the first transistor. In addition, an upper portion of a semiconductor layer of the second transistor is in contact with a wiring, and a lower portion thereof is in contact with a gate electrode of the first transistor. With such a structure, the wiring and the gate electrode of the first transistor can serve as a source electrode and a drain electrode of the second transistor, respectively. Accordingly, the area occupied by the semiconductor device can be reduced. | 06-28-2012 |
| 20120168839 | POWER DEVICE PACKAGE STRUCTURE - The disclosure relates to a power device package structure. By employing the metal substrate of the power device package structure serve as a bottom electrode of a capacitor, the capacitor is integrated into the power device package structure. A dielectric material layer and a upper metal layer sequentially disposed on the metal substrate. | 07-05-2012 |
| 20120168840 | RF-POWER DEVICE - An RF-power device includes a semiconductor substrate having a plurality of active regions arranged in an array. Each active region includes one or more RF-power transistors. The active regions are interspersed with inactive regions for reducing mutual heating of the RF-power transistors in separate active regions. The devices also includes at least one impedance matching component located in one of the inactive regions of the substrate. | 07-05-2012 |
| 20120175692 | Interconnection Wiring Structure of a Semiconductor Device - A method for manufacturing an interconnection wiring structure of a semiconductor device includes forming an isolation region, which arranges active regions in a diagonal direction, in a semiconductor substrate; forming first damascene trenches, which open upper portions of a bit line contacts, by selectively etching a second interlayer insulation layer; forming bit lines which fill the first damascene trenches; forming second damascene trenches, which expose portions of the active region, by selectively etching the portion of a second interlayer insulation layer between the bit lines and the portion of the first interlayer insulation layer thereunder; attaching trench spacer on side walls of the second damascene trench; and forming storage node contact lines which fill the second damascene trenches. | 07-12-2012 |
| 20120175693 | SEMICONDUCTOR DEVICE ENABLING FURTHER MICROFABRICATION - A semiconductor device includes a plurality of MOS transistors and wiring connected to a source electrode or a drain electrode of the plurality of MOS transistors and, the wiring being provided in the same layer as the source electrode and the drain electrode in a substrate, or in a position deeper than a surface of the substrate. | 07-12-2012 |
| 20120193694 | WIRELESS CHIP AND ELECTRONIC APPLIANCE HAVING THE SAME - The present invention provides a wireless chip having high mechanical strength. Moreover, the present invention also provides a wireless chip which can prevent an electric wave from being blocked. In a wireless chip of the present invention, a layer having a thin film transistor formed over an insulating substrate is fixed to an antenna by an anisotropic conductive adhesive, and the thin film transistor is connected to the antenna. The antenna has a dielectric layer, a first conductive layer, and a second conductive layer; the first conductive layer and the second conductive layer has the dielectric layer therebetween; the first conductive layer serves as a radiating electrode; and the second electrode serves as a ground contact body. | 08-02-2012 |
| 20120199896 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE FOR SUPPRESSING DETERIORATION IN JUNCTION BREAKDOWN VOLTAGE AND SURFACE BREAKDOWN VOLTAGE OF TRANSISTOR - According to one embodiment, a non-volatile semiconductor memory device includes a plurality of memory cells and a transistor. The transistor includes a gate insulating film, a gate electrode on the gate insulating film, a sidewall insulating film on both side surfaces of the gate electrode, a source diffusion layer corresponding to the sidewall insulating film, a first hollow formed in a position at a height less than a bottom surface of the gate insulating film directly below an outer side surface of the sidewall insulating film of another side of the gate electrode, a second hollow formed in the first hollow at a position at a height less than the first hollow, and a drain diffusion layer corresponding to another side of the gate electrode and including a low-concentration drain region formed on a bottom surface of the second hollow and a high-concentration drain region. | 08-09-2012 |
| 20120211812 | HIGH-SPEED HIGH-POWER SEMICONDUCTOR DEVICES - High-speed high-power semiconductor devices are disclosed. In an exemplary design, a high-speed high-power semiconductor device includes a source, a drain to provide an output signal, and an active gate to receive an input signal. The semiconductor device further includes at least one field gate located between the active gate and the drain, at least one shallow trench isolation (STI) strip formed transverse to the at least one field gate, and at least one drain active strip formed parallel to, and alternating with, the at least one STI strip. The semiconductor device may be modeled by a combination of an active FET and a MOS varactor. The active gate controls the active FET, and the at least one field gate controls the MOS varactor. The semiconductor device has a low on resistance and can handle a high voltage. | 08-23-2012 |
| 20120211813 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a semiconductor device may include, but is not limited to, a semiconductor substrate, an isolation electrode, a gate electrode, a gate insulating film, and a first insulating film. The semiconductor substrate has a first groove and a second groove. An isolation electrode is positioned in the first groove. The gate electrode is positioned in the second groove. The gate insulating film is adjacent to the gate electrode. The first insulating film is adjacent to the isolation electrode. The isolation electrode is greater in threshold voltage than the gate electrode. | 08-23-2012 |
| 20120217559 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes an active region protruding from a substrate. The active region includes first and second doped regions therein and a trench therein separating the first and second doped regions. A buried gate structure extends in a first direction along the trench between first and second opposing sidewalls thereof. A conductive interconnection plug is provided on the first doped region adjacent the first sidewall of the trench, and a conductive landing pad is provided on the second doped region adjacent the second sidewall of the trench. The landing pad has a width greater than that of the second doped region of the active region along the first direction. A conductive storage node contact plug is provided on the landing pad opposite the second doped region. The storage node contact plug has a narrower width than the landing pad along the first direction. | 08-30-2012 |
| 20120217560 | Semiconductor Memory Devices Including Support Patterns - A capacitor dielectric can be between the storage node and the electrode layer. A supporting pattern can be connected to the storage node, where the supporting pattern can include at least one first pattern and at least one second pattern layered on one another, where the first pattern can include a material having an etch selectivity with respect to the second pattern. | 08-30-2012 |
| 20120223375 | SEMICONDUCTOR DEVICE - To improve a performance of a semiconductor device having a capacitance element. An MIM type capacitance element, an electrode of which is formed with comb-shaped metal patterns composed of the wirings, is formed over a semiconductor substrate. A conductor pattern, which is a dummy gate pattern for preventing dishing in a CMP process, and an active region, which is a dummy active region, are disposed below the capacitance element, and these are coupled to shielding metal patterns composed of the wirings and then connected to a fixed potential. Then, the conductor pattern and the active region are disposed so as not to overlap the comb-shaped metal patterns in the wirings in a planar manner. | 09-06-2012 |
| 20120228686 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device including, on the same semiconductor substrate, a transistor element, a capacitor, and a resistor. The capacitor is formed on an active region, and the resistor is formed on an element isolation region, both formed of the same polysilicon film. By CMP or etch-back, the surface is ground down while planarizing the surface until a resistor has a desired thickness. Owing to a difference in height between the active region and the element isolation region, a thin resistor and a thick upper electrode of the capacitor are formed to prevent passing through of a contact. | 09-13-2012 |
| 20120228687 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a semiconductor film; a first gate insulating film covering the semiconductor film; a first gate electrode provided over the semiconductor film with the first gate insulating film interposed therebetween; a first conductive film which is provided over the first gate insulating film; an insulating film which is provided over the first gate insulating film, exposes top surfaces of the first gate electrode and the first conductive film, and has a groove portion between the first gate electrode and the first conductive film; an oxide semiconductor film which is provided over the insulating film and is in contact with the first gate electrode, the first conductive film, and the groove portion; a second gate insulating film covering the oxide semiconductor film; and a second gate electrode provided over the oxide semiconductor film and the groove portion with the second gate insulating film interposed therebetween. | 09-13-2012 |
| 20120228688 | MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A memory device that is as small in area as possible and has an extremely long data retention period. A transistor with extremely low leakage current is used as a cell transistor of a memory element in a memory device. Moreover, in order to reduce the area of a memory cell, the transistor is formed so that its source and drain are stacked in the vertical direction in a region where a bit line and a word line intersect each other. Further, a capacitor is stacked above the transistor. | 09-13-2012 |
| 20120235217 | Semiconductor Constructions - Some embodiments include methods in which a pair of spaced-apart adjacent features is formed over a substrate. The features have silicon dioxide surfaces. Silicon nitride is deposited between the features. A first region of the silicon nitride is protected with a mask while a second region is not. The second region is removed to form an opening between the features. Some embodiments include semiconductor constructions that contain a pair of spaced-apart adjacent features. The features are lines extending along a first direction, and are spaced from one another by a trench. Alternating plugs and intervening materials are within the trench, with the plugs and intervening materials alternating along the first direction. The intervening materials consist of silicon nitride, and the plugs have lateral peripheries that directly contact silicon dioxide of the features, and that directly contact silicon nitride of the intervening regions. | 09-20-2012 |
| 20120241829 | Low Leakage Capacitor for Analog Floating-Gate Integrated Circuits - An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad. | 09-27-2012 |
| 20120241830 | SEMICONDUCTOR DEVICE HAVING CELL CAPACITORS - A semiconductor device including: a bit line being arranged on top surfaces of first and second contact plugs via a first insulation layer and extending in a direction connecting a first impurity diffusion layer and a second impurity diffusion layer; a bit line contact plug being formed through the first insulation layer and electrically connecting the bit line to the first contact plug; a first cell capacitor having a first lower electrode beside one of side surfaces of the bit line; a first insulation film insulating the bit line and the first lower electrode from each other; and a first contact conductor electrically connecting a bottom end of the first lower electrode to a side surface of the second contact plug. | 09-27-2012 |
| 20120241831 | Methods of Forming Vertical Field Effect Transistors, Vertical Field Effect Transistors, and DRAM Cells - A method of forming a vertical field effect transistor includes etching an opening into semiconductor material. Sidewalls and radially outermost portions of the opening base are lined with masking material. A semiconductive material pillar is epitaxially grown to within the opening adjacent the masking material from the semiconductor material at the opening base. At least some of the masking material is removed from the opening. A gate dielectric is formed radially about the pillar. Conductive gate material is formed radially about the gate dielectric. An upper portion of the pillar is formed to comprise one source/drain region of the vertical transistor. Semiconductive material of the pillar received below the upper portion is formed to comprise a channel region of the vertical transistor. Semiconductor material adjacent the opening is formed to comprise another source/drain region of the vertical transistor. Other aspects and implementations are contemplated. | 09-27-2012 |
| 20120248518 | ISOLATION STRUCTURE AND DEVICE STRUCTURE INCLUDING THE SAME - An isolation structure is described, including a doped semiconductor layer disposed in a trench in a semiconductor substrate and having the same conductivity type as the substrate, gate dielectric between the doped semiconductor layer and the substrate, and a diffusion region in the substrate formed by dopant diffusion through the gate dielectric from the doped semiconductor layer. A device structure is also described, including the isolation structure and a vertical transistor in the substrate beside the isolation structure. The vertical transistor includes a first S/D region beside the diffusion region and a second S/D region over the first S/D region both having a conductivity type different from that of the doped semiconductor layer. | 10-04-2012 |
| 20120248519 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a semiconductor substrate having a groove; a gate insulator; a first diffusion region; a gate electrode; a hydrogen-containing insulator; and a fluorine-containing insulator. The gate insulator covers inside surfaces of the groove. The first diffusion region is formed in the substrate. The first diffusion region has a first contact surface that contacts the gate insulator. The gate electrode is formed on the gate insulator and in the groove. The hydrogen-containing insulator is formed over the gate electrode and in the groove. The hydrogen-containing insulator is adjacent to the gate insulator. The fluorine-containing insulator is formed on the hydrogen-containing insulator and in the groove. The first contact surface includes Si—H bonds and Si—F bonds. | 10-04-2012 |
| 20120248520 | SEMICONDUCTOR MEMORY DEVICE HAVING PLURAL CELL CAPACITORS STACKED ONE ANOTHER AND MANUFACTURING METHOD THEREOF - Disclosed herein is a device that includes a semiconductor substrate having a first area, a plurality of cell transistors arranged on the first area of the semiconductor substrate, and a plurality of cell capacitors each coupled to an associated one of the cell transistors, the cell capacitors being provided so as to overlap with one another on the first area. | 10-04-2012 |
| 20120256242 | SEMICONDUCTOR NANOWIRE STRUCTURE REUSING SUSPENSION PADS - An integrated circuit apparatus is provided and includes first and second silicon-on-insulator (SOI) pads formed on an insulator substrate, each of the first and second SOI pads including an active area formed thereon, a nanowire suspended between the first and second SOI pads over the insulator substrate, one or more field effect transistors (FETs) operably disposed along the nanowire and a planar device operably disposed on at least one of the respective active areas formed on each of the first and second SOI pads. | 10-11-2012 |
| 20120256243 | SEMICONDUCTOR DEVICE FOR REDUCING INTERCONNECT PITCH - A semiconductor device includes a plurality of transistors formed on a semiconductor substrate, a first local wiring which is electrically connected to at least one of the plurality of transistors and extending in a first direction, a second local wiring which is formed above the first local wiring and which electrically connects to at least one of the plurality of transistors and extends in a second direction, a plurality of first wirings which are formed above the second local wiring and which extend in a third direction, at least each of the plurality of first wirings being electrically connected to the first local wiring and the second local wiring, respectively, and a second wiring which is formed above the first wiring and which electrically connects to at least one of the plurality of first wirings and extends in a fourth direction. | 10-11-2012 |
| 20120256244 | Methods of Forming Field Effect Transistors, Pluralities of Field Effect Transistors, and DRAM Circuitry Comprising a Plurality of Individual Memory Cells - A method of forming a field effect transistor includes forming trench isolation material within a semiconductor substrate and on opposing sides of a semiconductor material channel region along a length of the channel region. The trench isolation material is formed to comprise opposing insulative projections extending toward one another partially under the channel region along the channel length and with semiconductor material being received over the projections. The trench isolation material is etched to expose opposing sides of the semiconductor material along the channel length. The exposed opposing sides of the semiconductor material are etched along the channel length to form a channel fin projecting upwardly relative to the projections. A gate is formed over a top and opposing sides of the fin along the channel length. Other methods and structures are disclosed. | 10-11-2012 |
| 20120261733 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device comprises a trench isolation. The trench isolation is formed in a surface of a semiconductor substrate to define an active region a well region, and a bottom of the trench isolation is positioned within the well region. The trench isolation includes a conductive wiring electrically connected to the well region and an insulating film which buries the conductive wiring in the bottom of the trench isolation. Semiconductor elements are disposed in the active region. | 10-18-2012 |
| 20120261734 | SEMICONDUCTOR MEMORY DEVICE - In the semiconductor memory device, one of a source and a drain of a first transistor is connected to one of a source and a drain of a second transistor, a gate of the first transistor is connected to one of a source and a drain of a third transistor and one of a pair of capacitor electrodes included in a capacitor, the other of the source and the drain of the first transistor and the other of the source and the drain of the third transistor are connected to a bit line, the other of the pair of capacitor electrodes included in the capacitor is connected to a common wiring, and the common wiring is grounded (GND). The common wiring has a net shape when seen from the above, and the third transistor is provided in a mesh formed by the common wiring. | 10-18-2012 |
| 20120261735 | SEMICONDUCTOR DEVICE HAVING A THIN FILM CAPACITOR AND METHOD FOR FABRICATING THE SAME - In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO.sub.2, HfO.sub.2, (Zr.sub.x, Hf.sub.1−x)O.sub.2 (0| 10-18-2012 | |
| 20120267696 | SEMICONDUCTOR DEVICE - Stable electric characteristics and high reliability are provided to a miniaturized and integrated semiconductor device including an oxide semiconductor. In a transistor (a semiconductor device) including an oxide semiconductor film, the oxide semiconductor film is provided along a trench (groove) formed in an insulating layer. The trench includes a lower end corner portion having a curved shape with a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm, and the oxide semiconductor film is provided in contact with a bottom surface, the lower end corner portion, and an inner wall surface of the trench. The oxide semiconductor film includes a crystal having a c-axis substantially perpendicular to a surface at least over the lower end corner portion. | 10-25-2012 |
| 20120273857 | SEMICONDUCTOR DEVICE STRUCTURE AS A CAPACITOR - A capacitor structure includes a conductive region; a first dielectric layer over the conductive region; a conductive material within the first dielectric layer, wherein the conductive material is on the conductive region and forms a first plate electrode of the capacitor structure; an insulating layer within the first dielectric layer and surrounding the conductive material; a first conductive layer within the first dielectric layer and surrounding the insulating layer, wherein the first conductive layer forms a second plate electrode of the capacitor structure; a second conductive layer laterally extending from the first conductive layer at a top surface of the first dielectric layer; a second dielectric layer over the first dielectric layer; and a third conductive layer within the second dielectric layer and on the conductive material. | 11-01-2012 |
| 20120273858 | SEMICONDUCTOR MEMORY DEVICE - An object is to provide a semiconductor memory device that enables low power consumption of a memory cell of a CAM including a nonvolatile memory device. Another object is to provide a semiconductor memory device without degradation due to repeated data writing. Still another object is to provide a nonvolatile memory device that enables high density of memory cells. A semiconductor memory device is provided which includes a memory circuit including a first transistor including an oxide semiconductor in a semiconductor layer, and a capacitor in which a potential corresponding to written data can be retained by turning off the first transistor; and a reference circuit for referring the written potential. The semiconductor memory device enables a high-speed search function by obtaining the address of data generated by detecting the conducting state of a second transistor in the reference circuit. | 11-01-2012 |
| 20120273859 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device may include, but is not limited to, a semiconductor substrate having a first gate groove; a first fin structure underneath the first gate groove; a first diffusion region in the semiconductor substrate, the first diffusion region covering an upper portion of a first side of the first gate groove; and a second diffusion region in the semiconductor substrate. The second diffusion region covers a second side of the first gate groove. The second diffusion region has a bottom which is deeper than a top of the first fin structure. | 11-01-2012 |
| 20120273860 | NON-VOLATILE MEMORY UNIT CELL WITH IMPROVED SENSING MARGIN AND RELIABILITY - An only-one-polysilicon layer non-volatile memory unit cell includes a first P-type transistor, a second P-type transistor, a N-type transistor pair, a first and second coupling capacitors is provided. The N-type transistor pair has a third transistor and a fourth transistor that are connected. The third transistor and the fourth transistor have a first floating polysilicon gate and a second floating polysilicon gate to serve as charge storage mediums, respectively. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage. | 11-01-2012 |
| 20120280296 | Semiconductor Device with DRAM Bit Lines Made From Same Material as Gate Electrodes in Non-Memory Regions of the Device, and Methods of Making Same - Generally, the present disclosure is directed to a semiconductor device with DRAM bit lines made from the same material as the gate electrodes in non-memory regions of the device, and methods of making the same. One illustrative method disclosed herein comprises forming a semiconductor device including a memory array and a logic region. The method further comprises forming a buried word line in the memory array and, after forming the buried word line, performing a first common process operation to form at least a portion of a conductive gate electrode in the logic region and to form at least a portion of a conductive bit line in the memory array. | 11-08-2012 |
| 20120280297 | DRAM WITH DOPANT STOP LAYER AND METHOD OF FABRICATING THE SAME - A DRAM with dopant stop layer includes a substrate, a trench-type transistor and a capacitor electrically connected to the trench-type transistor. The trench-type transistor includes a gate structure embedded in the substrate. A source doping region and a drain doping region are disposed in the substrate at two sides of the gate structure. A boron doping region is disposed under the source doping region. A dopant stop layer is disposed within the boron doping region or below the boron doping region. The dopant stop layer includes a dopant selected from the group consisting of C, Si, Ge, Sn, Cl, F and Br. | 11-08-2012 |
| 20120286341 | Adding Decoupling Function for TAP Cells - A tap cell includes a well region and a well pickup region on the well region; a VDD power rail; and a VSS power rail. A MOS capacitor includes a gate electrode line acting as a first capacitor plate, and the well pickup region acting as a part of a second capacitor plate. A first one of the first and second capacitor plates is coupled to the VDD power rail, and a second one of the first and second capacitor plates is coupled to the VSS power rail. | 11-15-2012 |
| 20120286342 | SEMICONDUCTOR DEVICE - A semiconductor device having a transistor gate length greatly reduced as a result of promotion of semiconductor integrated circuit miniaturization where leakage current generation in a gate insulating film can be inhibited to enhance the transistor function. The semiconductor device includes: a semiconductor substrate having a main surface; a pair of source/drain regions formed over the main surface of the semiconductor substrate; a gate insulating film formed, over a region between the pair of source/drain regions, to be in contact with the main surface; and a gate electrode formed to be in contact with the upper surface of the gate insulating film. In the semiconductor device, the gate electrode has a length of less than 45 nm in a direction from a first one of the pair of source/drain regions to a second one of the pair of source/drain regions, and the gate insulating film has an antiferroelectric film. | 11-15-2012 |
| 20120286343 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A memory device includes a MISFET on a semiconductor substrate of a first conductivity type, and a MIS capacitor on a first well of a second conductivity type. The MISFET includes a gate insulating film on the semiconductor substrate, a gate electrode, and a source/drain located at both sides of the gate electrode. The MIS capacitor includes a capacitor insulating film on the first well serving as a first electrode, a second electrode, and a first impurity layer of the first conductivity type. The gate electrode and the second electrode are electrically connected together, and form a floating gate. The gate insulating film and the capacitor insulating film are made of a same material, and have a same thickness. | 11-15-2012 |
| 20120292678 | BI-DIRECTIONAL SELF-ALIGNED FET CAPACITOR - A method of forming a field effect transistor (FET) capacitor includes forming a channel region; forming a gate stack over the channel region; forming a first extension region on a first side of the gate stack, the first extension region being formed by implanting a first doping material at a first angle such that a shadow region exists on a second side of the gate stack; and forming a second extension region on the second side of the gate stack, the second extension region being formed by implanting a second doping material at a second angle such that a shadow region exists on the first side of the gate stack. | 11-22-2012 |
| 20120299072 | SEMICONDUCTOR DEVICE HAVING METAL PLUG AND METHOD OF FORMING THE SAME - Provided is a semiconductor device including first, second and third source/drain regions. A first conductive plug in contact with the first source/drain regions, having a first width and a first height, and including a first material is provided. An interlayer insulating layer covering the first conductive plug and the substrate is disposed. A second conductive plug vertically penetrating the interlayer insulating layer to be in contact with the second source/drain regions, having a second width and a second height, and including a second material is provided. A third conductive plug vertically penetrating the interlayer insulating layer to be in contact with the third source/drain regions, having a third width and a third height, and including a third material is disposed. The second material includes a noble metal, a noble metal oxide or a perovskite-based conductive oxide. | 11-29-2012 |
| 20120299073 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a semiconductor substrate having a first gate groove having first and second sides opposite to each other; a first diffusion region underneath the first gate groove; a second diffusion region in the semiconductor substrate, the second diffusion region covering an upper portion of the first side of the first gate groove; and a third diffusion region in the semiconductor substrate. The third diffusion region covers the second side of the first gate groove. The third diffusion region is coupled to the first diffusion region. The third diffusion region has a bottom which is deeper than a bottom of the first gate groove. The bottom of the third diffusion region is different in level from the bottom of the first diffusion region. | 11-29-2012 |
| 20120305996 | SEMICONDUCTOR DEVICE - An area occupied by a circuit element having at least a capacitor and a transistor is reduced in a semiconductor device. In a semiconductor device including a first transistor, a second transistor, and a capacitor, the first transistor and the capacitor are provided over the second transistor. Then, a common electrode, which serves as one of a source and a drain of the first transistor and one electrode of the capacitor, is provided. In addition, the other electrode of the capacitor is provided over the common electrode. | 12-06-2012 |
| 20120305997 | Semiconductor Devices Having Recessed Channels - A semiconductor device includes a substrate, a gate insulation layer, a gate structure, a gate spacer, and first and second impurity regions. The substrate has an active region defined by an isolation layer. The active region has a gate trench thereon. The gate insulation layer is formed on an inner wall of the gate trench. The gate structure is formed on the gate insulation layer to fill the gate trench. The gate structure has a width smaller than that of the gate trench, and has a recess at a first portion thereof. The gate spacer is formed on sidewalls of the gate structure. The first and second impurity regions are formed at upper portions of the active region adjacent to the gate structure. The first impurity region is closer to the recess than the second impurity region. Related methods are also provided. | 12-06-2012 |
| 20120313156 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of forming a semiconductor device includes the following processes. A pillar is formed which stands on a semiconductor substrate. A first insulating film is formed which covers a side surface of the pillar. An upper portion of the first insulating film is removed to expose a side surface of an upper portion of the pillar. A contact plug is formed, which contacts the side surface of the upper portion of the pillar and a top surface of the pillar. | 12-13-2012 |
| 20120326218 | 6F2 DRAM Cell | 12-27-2012 |
| 20120326219 | DYNAMIC MEMORY STRUCTURE - A dynamic memory structure includes a strip semiconductor material disposed on a substrate, a gate standing astride the strip semiconductor material and dividing the strip semiconductor material into a source terminal, a drain terminal and a channel region wherein a source width of the source terminal is larger than or equal to a channel width, a dielectric layer sandwiched between the gate and the strip semiconductor material, and a capacitor unit disposed on the substrate and including the source terminal serving as a lower electrode. | 12-27-2012 |
| 20130001662 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor element; a divider connected with an input portion of the semiconductor element; and a combiner connected with an output portion of the semiconductor element. The divider is disposed on a substrate and has a first divider portion including a first transmission line and a second transmission line, a second divider portion including a third transmission line and a fourth transmission line, and a first resistance and a second resistance respectively connected to both the first transmission line and the third transmission line. The first resistance is disposed in the space between the first and third transmission lines, the second resistance is disposed in the space between the first and third transmission lines, and the first resistance is disposed between the second resistance and the semiconductor element. | 01-03-2013 |
| 20130001663 | DRAM Layout with Vertical FETS and Method of Formation - DRAM cell arrays having a cell area of about 4F | 01-03-2013 |
| 20130009225 | MONOLITHICALLY INTEGRATED ACTIVE SNUBBER - A semiconductor device containing an extended drain MOS transistor with an integrated snubber formed by forming a drain drift region of the MOS transistor, forming a snubber capacitor including a capacitor dielectric layer and capacitor plate over the extended drain, and forming a snubber resistor over a gate of the MOS transistor so that the resistor is connected in series between the capacitor plate and a source of the MOS transistor. | 01-10-2013 |
| 20130009226 | DRAM DEVICES AND METHODS OF MANUFACTURING THE SAME - A DRAM device includes a substrate including an active region having an island shape and a buried gate pattern. A mask pattern is over an upper surface portion of the substrate between portions of the buried gate pattern. A capping insulating layer fills a gap between portions of the mask pattern. A first pad contact penetrates the capping insulating layer and the mask pattern, and contacts a first portion of the substrate in the active region. Second pad contacts are under the capping insulating layer, and contact a second portion of the substrate in the active region positioned at both sides of the first pad contact. A spacer is between the first and second pad contacts to insulate the first and second pad contacts. A bit line configured to electrically connect with the first pad contact, and a capacitor configured to electrically connect with the second pad contacts, are provided. | 01-10-2013 |
| 20130020622 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device comprises a semiconductor substrate, a first transistor including a gate insulating film and a gate electrode sequentially formed on the semiconductor substrate, a sidewall, an interlayer insulating film formed on the semiconductor substrate, and a contact plug which penetrates through the interlayer insulating film and reaches the semiconductor substrate. The sidewall is formed on a side surface of the gate electrode, and includes a first insulating film and a second insulating film formed on the first insulating film and containing a metal oxide different from the first insulating film. | 01-24-2013 |
| 20130026549 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING CAPACITOR FOR PROVIDING STABLE POWER AND METHOD OF MANUFACTURING THE SAME - A capacitor and a method of manufacturing the same are provided. A dummy capacitor group is formed in the peripheral circuit area and includes a dummy storage node contact unit, a dielectric, and a dummy plate electrode. A metal oxide semiconductor (MOS) capacitor is formed in the peripheral circuit area and connected to the dummy capacitor group in parallel. Capacitance of the dummy capacitor group may be greater than that of the MOS capacitor. | 01-31-2013 |
| 20130026550 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a first conduction-type semiconductor region, a second conduction-type first impurity region, and a guard ring formed using a first conduction-type second impurity region so as to form a protection device of an electrostatic protection circuit. The first impurity region is formed inside the semiconductor region to have a rectangular planar structure with long and short sides. The guard ring is formed inside the semiconductor region to surround the periphery of the first impurity region. A weak spot is formed on the short side of the rectangular planar structure of the first impurity region. A plurality of electrical contacts are formed in a first portion of the guard ring which faces the long side of the rectangle. A plurality of electrical contracts are not formed in a second portion of the guard ring which faces the weak spot formed on the short side of the rectangle. | 01-31-2013 |
| 20130026551 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING RESERVOIR CAPACITOR - A semiconductor integrated circuit including a large capacity reservoir capacitor to provide suitable power is provided. The semiconductor integrated circuit includes a semiconductor substrate in which a cell area and a peripheral circuit area are defined, a MOS capacitor formed on the semiconductor substrate corresponding to the peripheral circuit area, and a dummy capacitor group formed on the peripheral circuit area to overlap the MOS capacitor. One electrode of the MOS capacitor and one electrode of the dummy capacitor group are connected to each other and the other electrode of the MOS capacitor and the other electrode of the dummy capacitor group are connected to difference voltage sources from each other. | 01-31-2013 |
| 20130032867 | SIGNAL LINE DRIVING CIRCUIT AND LIGHT EMITTING DEVICE - The invention relates to a signal line driving circuit having a first and a second current source circuits, a shift register, and a constant current source for video signal, in which the first current source circuit is disposed in a first latch and the second current source circuit is disposed in a second latch. The first current source circuit includes capacitive means for converting the current supplied from the constant current source for video signal into a voltage, according to a sampling pulse supplied from the shift register, and supplying means for supplying the current corresponding to the converted voltage. | 02-07-2013 |
| 20130037873 | FILM FORMING METHOD, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE USING THE SAME, FILM FORMING APPARATUS, AND SEMICONDUCTOR DEVICE - Provided is a semiconductor device capable of preventing destruction of an electrode having a pillar shape and densely arranged. The semiconductor device having a field-effect transistor and a capacitor having a pillar shape, the semiconductor device includes: a first electrode having a pillar shape and electrically connected to an impurity diffusion region of the field-effect transistor; a dielectric film formed at least on a side of the first electrode; a second electrode formed on the dielectric film; and a support film extending in a direction crossing a length direction of the first electrode having the pillar shape, and formed by a boron-added silicon nitride film connected to the first electrode by penetrating through at least a part of the second electrode. | 02-14-2013 |
| 20130043519 | SEMICONDUCTOR DEVICES USING SHAPED GATE ELECTRODES - A device includes a semiconductor substrate and a gate insulation film lining a trench in an active region of the substrate. A gate electrode pattern is recessed in the trench on the gate insulation film and has an upper surface that has a nonuniform height. A dielectric pattern may be disposed on the gate electrode pattern in the trench. | 02-21-2013 |
| 20130043520 | Raised Source/Drain Field Effect Transistor - In one exemplary embodiment of the invention, a semiconductor structure includes: a substrate; and a plurality of devices at least partially overlying the substrate, where the plurality of devices include a first device coupled to a second device via a first raised source/drain having a first length, where the first device is further coupled to a second raised source/drain having a second length, where the first device comprises a transistor, where the first raised source/drain and the second raised source/drain at least partially overly the substrate, where the second raised source/drain comprises a terminal electrical contact, where the second length is greater than the first length. | 02-21-2013 |
| 20130056813 | CAPACITOR STRUCTURE APPLIED TO INTEGRATED CIRCUIT - A capacitor structure applied to an integrated circuit (IC) is provided. The capacitor structure includes a metal-oxide semiconductor (MOS) capacitor and two metal structures with different structures. The MOS capacitor has a first terminal and a second terminal. The two metal capacitors are formed above the MOS capacitor and respectively coupled between the first terminal and the second terminal. Subject to the confined chip area, the capacitance of the above-mentioned capacitor structure can still reach the design value, and the above-mentioned capacitor structure is further characterized by a large amount of current flow. | 03-07-2013 |
| 20130062675 | PILLARS FOR VERTICAL TRANSISTORS - In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide layer and a nitride layer are used as masks to define trenches, pillars, and active areas in a substrate. Preferably, two substrate etch processes use the masks to form three levels of bulk silicon. | 03-14-2013 |
| 20130069131 | INTEGRATED CIRCUIT DECOUPLING CAPACITOR ARRANGEMENT - A decoupling capacitor arrangement is provided for an integrated circuit. The apparatus includes a plurality of decoupling capacitor arrays electrically connected in parallel with one another. Each of the arrays includes a plurality of decoupling capacitors and a current limiting element. The decoupling capacitors of each array are electrically connected in parallel with one another. The current limiting element is connected in series with the plurality of decoupling capacitors. | 03-21-2013 |
| 20130075798 | SEMICONDUCTOR DEVICE - A semiconductor device comprises: a MOS transistor connected between a power supply terminal and a ground terminal; a first diode connected between a drain and a gate of the MOS transistor; a second diode connected between the drain and the gate of the MOS transistor, in series with the first diode, and having a forward direction which is opposite to that of the first diode; and a capacitor connected between the drain and the gate of the MOS transistor, in series with the first diode and the second diode. | 03-28-2013 |
| 20130075799 | ELECTRO-OPTICAL DEVICE AND ELECTRONIC APPARATUS - Disclosed is a pixel electrode which is electrically connected to a scanning line electrically connected to a gate electrode, a data line electrically connected to a data line side source and drain region, and a pixel electrode side source and drain region; and a capacitance element which has a first capacitance electrode which is electrically connected to a capacitance line, a second capacitance electrode which is provided to oppose the first capacitance electrode, and a dielectric layer which is interposed between the first capacitance electrode and the second capacitance electrode, where the first capacitance electrode is arranged to be covered with the dielectric layer and the second capacitance electrode between a layer where the transistor, the scanning line, and the data line are provided and a layer where the pixel electrode is provided. | 03-28-2013 |
| 20130075800 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS - A semiconductor device manufacturing method includes loading a substrate to a processing chamber, a gate insulating film or a capacitor insulating film being formed on a surface of the substrate; forming an electrode, which includes a conductive oxide film and to which an additive that modulates a work function of the conductive oxide film is added, on the substrate; and unloading the substrate, on which the electrode is formed, from the processing chamber. | 03-28-2013 |
| 20130087839 | DYNAMIC MEMORY STRUCTURE - A DRAM memory structure at least includes a strip semiconductive material disposed on a substrate and extending along a first direction, a split gate disposed on the substrate and extending along a second direction, a dielectric layer at least sandwiched between the split gate and the substrate, a gate dielectric layer at least sandwiched between the split gate and the strip semiconductive material, and a capacitor unit. The split gate independently includes a first block and a second block to divide the strip semiconductive material into a source terminal, a drain terminal and a channel. The capacitor unit is electrically connected to the source terminal. | 04-11-2013 |
| 20130092989 | Embedded Transistor - An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate on opposing sides of the trench. In an embodiment, one of the source/drain regions is coupled to a storage node and the other source/drain region is coupled to a bit line. In this embodiment, the gate electrode may be coupled to a word line to form a DRAM memory cell. | 04-18-2013 |
| 20130092990 | SEMICONDUCTOR DEVICE, DISPLAY DEVICE AND ELECTRONIC DEVICE - When writing a signal current from a current source to a current source circuit, noise occurs in some cases in a wiring through which a current flows, which may cause a potential of the wiring to be outside the normal range. As the potential does not turn back within the normal range easily at this time, writing to the current source circuit is delayed. According to the invention, when the potential becomes outside the normal range due to noise occurring in a wiring through which a current flows when writing a signal current from a current source to a current source circuit, a current is supplied from other than the current source, thereby the potential of the wiring can turn back within the normal range rapidly. | 04-18-2013 |
| 20130099297 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge protection device electrically connected between a pad and an internal circuit is provided and includes a capacitor, a first resistor, a voltage-drop element and an NMOS transistor. A first end of the capacitor is electrically connected to the pad. A first end of the first resistor is electrically connected to a second end of the capacitor, and a second end of the first resistor is electrically connected to ground. The NMOS transistor and the voltage-drop element are connected in series between the pad and the ground, a gate of the NMOS transistor is electrically connected to the second end of the capacitor, and a bulk of the NMOS transistor is electrically connected to the ground. | 04-25-2013 |
| 20130099298 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device comprises a buried gate formed in a mat and in an adjacent dummy region. A space larger than is conventional is formed in a dummy region of a mat edge where the buried gate is to be created. This larger space inhibits shortening of an end of a buried gate and reduction in pattern size attributable to lithographic distortion arising between patterned (mat) and unpatterned (dummy) regions. Device reliability is thereby improved by avoiding gap-fill defects of a gate material. | 04-25-2013 |
| 20130099299 | Semiconductor Device - An object is to provide a semiconductor device with a novel structure in which stored data can be retained even when power is not supplied, and does not have a limitation on the number of times of writing operations. A semiconductor device includes a source-bit line, a first signal line, a second signal line, a word line, and a memory cell connected between the source-bit lines. The memory cell includes a first transistor, a second transistor, and a capacitor. The second transistor is formed including an oxide semiconductor material. A gate electrode of the first transistor, one of a source and drain electrodes, and one of electrodes of the capacitor are electrically connected to one another. The source-bit line and a source electrode of the first transistor are electrically connected to each other. Another source-bit line adjacent to the above source-bit line and a drain electrode of the first transistor are electrically connected to each other. | 04-25-2013 |
| 20130105872 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME | 05-02-2013 |
| 20130105873 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME | 05-02-2013 |
| 20130113029 | SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNEL TRANSISTOR AND METHODS OF FABRICATING THE SAME - A semiconductor memory device includes a first pair of pillars extending from a substrate to form vertical channel regions, the first pair of pillars having a first pillar and a second pillar adjacent to each other, the first pillar and the second pillar arranged in a first direction, a first bit line disposed on a bottom surface of a first trench formed between | 05-09-2013 |
| 20130119448 | MEMORY LAYOUT STRUCTURE AND MEMORY STRUCTURE - A memory array layout includes an active region array having a plurality of active regions, wherein the active regions are arranged alternatively along a second direction and parts of the side of the adjacent active regions are overlapped along a second direction; a plurality of first doped region, wherein each first doped region is disposed in a middle region; a plurality of second doped region, wherein each second doped region is disposed in a distal end region respectively; a plurality of recessed gate structures; a plurality of word lines electrically connected to each recessed gate structure respectively; a plurality of digit lines electrically connected to the first doped region respectively; and a plurality of capacitors electrically connected to each second doped region respectively. | 05-16-2013 |
| 20130126954 | Dynamic Random Access Memory Array and Method of Making - The present invention is related to microelectronic technologies, and discloses specifically a dynamic random access memory (DRAM) array and methods of making the same. The DRAM array uses vertical MOS field effect transistors as array devices for the DRAM, and a buried metal silicide layer as buried bit lines for connecting multiple consecutive vertical MOS field effect transistor array devices. Each of the vertical MOS field-effect-transistor array devices includes a double gate structure with a buried layer of metal, which acts at the same time as buried word lines for the DRAM array. The DRAM array according to the present invention provides increased DRAM integration density, reduced buried bit line resistivity, and improved memory performance of the array devices. The present invention also provides a method of making a DRAM array. | 05-23-2013 |
| 20130126955 | Methods and Apparatus for Hybrid MOS Capacitors in Replacement Gate Process - Methods and apparatus for hybrid MOS capacitors in replacement gate process. A method is disclosed including patterning a gate dielectric layer and a polysilicon gate layer to form a polysilicon gate region over a substrate; forming an inter-level dielectric layer over the substrate and surrounding the polysilicon gate region; defining polysilicon resistor regions each containing at least one portion of the polysilicon gate region and not containing at least one other portion of the polysilicon gate region, forming dummy gate regions removing the dummy gate regions and the gate dielectric layer underneath the dummy gate regions to leave trenches; and forming high-k metal gate devices in the trenches. A capacitor region including a high-k metal gate and a polysilicon gate next to the high-k metal gate is disclosed. Additional hybrid capacitor apparatuses are disclosed. | 05-23-2013 |
| 20130140616 | Integrated Circuit Including a Power Transistor and an Auxiliary Transistor - In one embodiment of an integrated circuit, the integrated circuit includes a power transistor with a power control terminal, a first power load terminal and a second power load terminal. The integrated circuit further includes an auxiliary transistor with an auxiliary control terminal, a first auxiliary load terminal and a second auxiliary load terminal. The first auxiliary load terminal is electrically coupled to the power control terminal. The integrated circuit further includes a capacitor with a first capacitor electrode, a second capacitor electrode and a capacitor dielectric layer. The capacitor dielectric layer includes at least one of a ferroelectric material and a paraelectric material. The first capacitor electrode is electrically coupled to the auxiliary control terminal. | 06-06-2013 |
| 20130140617 | SEMICONDUCTOR DEVICE - A semiconductor device capable of high-speed operation. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is supplied with a first signal. One of a source and a drain of the second transistor is supplied with a first potential. A gate of the second transistor is supplied with a second signal. A first electrode of the capacitor is electrically connected to the other of the source and the drain of the first transistor. A second electrode of the capacitor is electrically connected to the other of the source and the drain of the second transistor. In a first period, the first signal is low and the second signal is high. In a second period, the first signal is high and the second signal is either low or high. | 06-06-2013 |
| 20130140618 | VERTICAL TRANSISTORS - A semiconductor structure having U-shaped transistors includes source/drain regions at the tops of pairs of pillars defined by crossing trenches in the substrate. One pillar is connected to the other pillar in the pair by a ridge that extends above the surrounding trenches. The ridge and lower portions of the pillars define U-shaped channels on opposite sides of the U-shaped structure, facing a gate structure in the trenches on those opposite sides, forming a two sided surround transistor. Optionally, the space between the pillars of a pair is also filled with gate electrode material to define a three-sided surround gate transistor. One of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. Methods of forming semiconductor structures are also disclosed. | 06-06-2013 |
| 20130146952 | ON-CHIP CAPACITORS IN COMBINATION WITH CMOS DEVICES ON EXTREMELY THIN SEMICONDUCTOR ON INSULATOR (ETSOI) SUBSTRATES - A device including a semiconductor on insulator (SOI) substrate including a semiconductor device region and a capacitor device region. A semiconductor device present in the semiconductor device region. The semiconductor device including a gate structure present on a semiconductor on insulator (SOI) layer of the SOI substrate, extension source and drain regions present in the SOI layer on opposing sides of the gate structure, and raised source and drain regions composed of a first portion of an epitaxial semiconductor material on the SOI layer. A capacitor is present in the capacitor device region, said capacitor including a first electrode comprised of a second portion of the epitaxial semiconductor material that has a same composition and crystal structure as the first portion of the epitaxial semiconductor material, a node dielectric layer present on the second portion of the epitaxial semiconductor material, and a second electrode comprised of a conductive material. | 06-13-2013 |
| 20130146953 | Method and Structure For Forming ETSOI Capacitors, Diodes, Resistors and Back Gate Contacts - An ETSOI transistor and a combination of capacitors, junction diodes, bank end contacts and resistors are respectively formed in a transistor and capacitor region thereof by etching through an ETSOI and BOX layers in a replacement gate HK/MG flow. The capacitor and other devices formation are compatible with an ETSOI replacement gate CMOS flow. A low resistance capacitor electrode makes it possible to obtain a high quality capacitor, and devices. The lack of topography during dummy gate patterning are achieved by lithography in combination accompanied with appropriate etch. | 06-13-2013 |
| 20130146954 | Method Of Memory Array And Structure Form - The present invention provides a memory array including a substrate, an isolation region, a plurality of active regions, a plurality of buried bit lines, a plurality of word lines, a plurality of drain regions and a plurality of capacitors. The isolation region and the active regions are disposed in the substrate and the active regions are encompassed and isolated by the isolation region. The buried bit lines are disposed in the substrate and extend in the second direction. The word lines are disposed in the substrate extend in the first direction. The drain regions are disposed in the active region not covered by the word lines. The capacitors are disposed on the substrate and electrically connected to the drain regions. | 06-13-2013 |
| 20130146955 | ELECTRONIC CHIP HAVING CHANNELS THROUGH WHICH A HEAT TRANSPORT COOLANT CAN FLOW, ELECTRONIC COMPONENTS AND COMMUNICATION ARM INCORPORATING SAID CHIP - The invention relates to an electronic chip, comprising: a semiconductor substrate ( | 06-13-2013 |
| 20130161710 | SEMICONDUCTOR DEVICE HAVING BURIED BIT LINE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes: forming an insulation layer over a semiconductor substrate; forming a first conductive layer over the insulation layer; forming a plurality of buried bit lines and insulation layer patterns isolated by a plurality of trenches, wherein the plurality of trenches are formed by etching the first conductive layer and the insulation layer; forming a sacrificial layer to gap-fill the trenches; forming a second conductive layer over the buried bit lines and the sacrificial layer; and forming a plurality of pillars over each of the buried bit lines by etching the second conductive layer. | 06-27-2013 |
| 20130161711 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate including an active region having an isolated shape and a field region. A gate insulation layer is provided on an upper surface of the active region of the substrate. A gate electrode is provided on the gate insulation layer and spaced apart from the boundary of the active region to cover the middle portion of the active region. An impurity region is provided under a surface of the active region that is exposed by the gate electrode. | 06-27-2013 |
| 20130161712 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor circuit and a capacitor, the capacitor including: a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, the second semiconductor region being provided on the first semiconductor region of the first conductivity type and having a higher concentration of a first conductivity type impurity than the first semiconductor region of the first conductivity type, a semiconductor region of a second conductivity type provided on the second semiconductor region of the first conductivity type, a dielectric film provided on the semiconductor region of the second conductivity type, an upper electrode provided on the dielectric film, a first interconnection provided above the semiconductor region of the second conductivity type and electrically connected to the semiconductor region of the second conductivity type, and a second interconnection electrically connected to the upper electrode. | 06-27-2013 |
| 20130161713 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device which includes a memory cell including two or more sub memory cells is provided. The sub memory cells each including a word line, a bit line, a first capacitor, a second capacitor, and a transistor. In the semiconductor device, the sub memory cells are stacked in the memory cell; a first gate and a second gate are formed with a semiconductor film provided therebetween in the transistor; the first gate and the second gate are connected to the word line; one of a source and a drain of the transistor is connected to the bit line; the other of the source and the drain of the transistor is connected to the first capacitor and the second capacitor; and the first gate and the second gate of the transistor in each sub memory cell overlap with each other and are connected to each other. | 06-27-2013 |
| 20130161714 | SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device capable of accurate data retention even with a memory element including a depletion mode transistor. A gate terminal of a transistor for controlling input of a signal to a signal holding portion is negatively charged in advance. The connection to a power supply is physically broken, whereby negative charge is held at the gate terminal. Further, a capacitor having terminals one of which is electrically connected to the gate terminal of the transistor is provided, and thus switching operation of the transistor is controlled with the capacitor. | 06-27-2013 |
| 20130168751 | HIGH-K METAL GATE RANDOM ACCESS MEMORY - The instant disclosure relates to a high-k metal gate random access memory. The memory includes a substrate, a plurality of bit line units, source regions, gate structures, drain regions, word line units, and capacitance units. The substrate has a plurality of trenches, and the bit line units are arranged on the substrate. The source regions are disposed on the bit line units, and the gate structures are disposed on the source regions. Each gate structure has a metal gate and a channel area formed therein. The gate structures are topped with the drain regions. The word lines units are arranged between the source and drain regions The capacitance units are disposed on the drain regions. Another memory is also disclosed, where each drain region and a portion of each gate structure are disposed in the respective capacitance unit, with the drain region being a lower electrode layer. | 07-04-2013 |
| 20130175589 | DECOUPLING CAPACITOR AND METHOD OF MAKING SAME - A semiconductor substrate has at least two active regions, each having at least one active device that includes a gate electrode layer, and a shallow trench isolation (STI) region between the active regions. A decoupling capacitor comprises first and second dummy conductive patterns formed in the same gate electrode layer over the STI region. The first and second dummy conductive regions are unconnected to any of the at least one active device. The first dummy conductive pattern is connected to a source of a first potential. The second dummy conductive pattern is connected to a source of a second potential. A dielectric material is provided between the first and second dummy conductive patterns. | 07-11-2013 |
| 20130175590 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM, AND METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE - A semiconductor device includes: an element isolation region formed in a substrate that defines an active region, a conductive layer formed on the active region, a first insulating film formed between the active region and the conductive layer and having a first thickness, and a second insulating film formed between the active region and the conductive layer and spans at least part of a boundary between the active region and the element isolation region and having a second thickness which is greater than the first thickness. | 07-11-2013 |
| 20130175591 | CAPACITIVE DEVICE, SEMICONDUCTOR UNIT, AND ELECTRONIC APPARATUS - A capacitive device includes: a first capacitive element including a first well region having a first conduction type, a first gate electrode, and first semiconductor layers each formed of an impurity layer having a second conduction type opposite to a conduction type of the first well region; and a second capacitive element electrically connected in parallel to the first capacitive element, the second capacitive element including a second well region having the first conduction type, a second gate electrode, and second semiconductor layers each formed of an impurity layer having the same first conductive type as a conduction type of the second well region. | 07-11-2013 |
| 20130175592 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes, a semiconductor substrate, a plurality of memory cells being provided on the semiconductor substrate in a memory cell region. Each of the plurality of memory cells having a first gate electrode disposed on the semiconductor substrate with a first gate insulating film, and the first gate electrode having a first charge storage layer, a first inter-electrode insulating film and a first control gate electrode film, and a cavity is interposed between an upper surface of the charge storage layer and the inter-electrode insulating film. | 07-11-2013 |
| 20130181269 | DECOUPLING CAPACITOR AND METHOD OF MAKING SAME - A device comprises a semiconductor substrate having first and second implant regions and an electrode above and between the first and second implant regions of a first dopant type. A contact structure is in direct contact with the first and second implant regions and the electrode. A third implant region has a second dopant type different from the first dopant type. A bulk contact is provided on the third implant. | 07-18-2013 |
| 20130181270 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a capacitor, the capacitor includes: a first semiconductor region of a first conductivity type; a second semiconductor region of the first conductivity type disposed on the first semiconductor region, the second semiconductor region having a higher first-conductivity-type impurity concentration than the first semiconductor region; a third semiconductor region of the first conductivity type disposed on the second semiconductor region, the third semiconductor region including a contact region and having a higher first-conductivity-type impurity concentration than the second semiconductor region; a dielectric film disposed on the third semiconductor region; and an upper electrode disposed on the dielectric film beside the contact region. | 07-18-2013 |
| 20130181271 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device capable of increasing ON current while reducing channel resistance and allowing transistors to operate independently and stably, having a fin formed to protrude from the bottom of a gate electrode trench, a gate insulating film covering the surfaces of the gate electrode trench and the fin, a gate electrode embedded in a lower part of the gate electrode trench and formed to stride over the fin via the gate insulating film, a first impurity diffusion region arranged on a first side face, and a second impurity diffusion region arranged on a second side face. | 07-18-2013 |
| 20130193498 | Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor - A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s. | 08-01-2013 |
| 20130193499 | DECOUPLING CAPACITOR AND LAYOUT FOR THE CAPACITOR - A device comprises a semiconductor substrate having first and second implant regions of a first dopant type. A gate insulating layer and a gate electrode are provided above a resistor region between the first and second implant regions. A first dielectric layer is on the first implant region. A contact structure is provided, including a first contact portion conductively contacting the gate electrode, at least part of the first contact portion directly on the gate electrode. A second contact portion directly contacts the first contact portion and is formed directly on the first dielectric layer. A third contact portion is formed on the second implant region. | 08-01-2013 |
| 20130193500 | DECOUPLING FINFET CAPACITORS - A semiconductor device including field-effect transistors (finFETs) and fin capacitors are formed on a silicon substrate. The fin capacitors include silicon fins, one or more electrical conductors between the silicon fins, and insulating material between the silicon fins and the one or more electrical conductors. The fin capacitors may also include insulating material between the one or more electrical conductors and underlying semiconductor material. | 08-01-2013 |
| 20130200447 | Adjustable Meander Line Resistor - An adjustable meander line resistor comprises a plurality of series circuits. Each series circuit comprises a first resistor formed on a first doped region of a transistor, a second resistor formed on a second doped region of the transistor and a connector coupled between the first resistor and the second resistor. A control circuit is employed to control the on and off of the transistor so as to achieve the adjustable meander line resistor. | 08-08-2013 |
| 20130200448 | Meander Line Resistor Structure - A meander line resistor structure comprises a first resistor formed on a first active region, wherein the first resistor is formed by a plurality of first vias connected in series, a second resistor formed on a second active region, wherein the second resistor is formed by a plurality of second vias connected in series and a third resistor formed on the second active region, wherein the third resistor is formed by a plurality of third vias connected in series. The meander line resistor further comprises a first connector coupled between the first resistor and the second resistor. | 08-08-2013 |
| 20130200449 | FINFET STRUCTURE WITH NOVEL EDGE FINS - A semiconductor device including field-effect transistors (finFETs) formed on a silicon substrate. The device includes a number of active areas each having a number of equally-spaced fins separated into regular fins and at least one edge fin, a gate structure over the regular fins, and a drain region as well as a source region electrically connected to the regular fins and disconnected to the at least one edge fin. The edge fins may be floating, connected to a potential source, or serve as a part of a decoupling capacitor. | 08-08-2013 |
| 20130207170 | PROGRAMMABLE LOGIC DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - To provide a programmable logic device in which the number of elements per bit in a memory array can be reduced and with which power consumption or operation frequency can be estimated accurately at a testing stage. Provided is a programmable logic device including a plurality of programmable logic elements and a memory array which stores configuration data that determines logic operation executed in the plurality of programmable logic elements. The memory array includes a plurality of memory elements. The memory element includes a node which establishes electrical connection between the programmable logic element and the memory array, a switch for supplying charge whose amount is determined by the configuration data to the node, holding the charge in the node, or releasing the charge from the node, and a plurality of wirings. Capacitance is formed between the node and the wiring. | 08-15-2013 |
| 20130214338 | SEMICONDUCTOR DEVICE - A semiconductor device comprises a convex portion, a concave portion provided so as to cover upper and side surfaces of the convex portion, a gate electrode provided so as to be opposed to the convex portion with a gate insulating film interposed between the gate electrode and the convex portion, a pair of diffusion layers provided within the convex portion so as to sandwich the gate electrode, and a contact plug provided on the concave portion, so as to be electrically connected to at least one of the diffusion layers. | 08-22-2013 |
| 20130214339 | SEMICONDUCTOR DEVICE COMPRISING CAPACITOR AND METHOD OF FABRICATING THE SAME - A semiconductor device, including a memory cell region and a peripheral circuit region, comprises an insulating film, having an upper surface formed on a major surface of a semiconductor substrate to extend from a memory cell region to a peripheral circuit region thereof. A capacitor lower electrode is formed in the memory cell region to upwardly extend beyond the upper surface of the insulating film on the major surface of the semiconductor substrate. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface. The upper surface of the insulating film is located between the top and bottom surfaces of the capacitor lower electrode part. | 08-22-2013 |
| 20130221418 | Analog Floating-Gate Memory Manufacturing Process Implementing N-Channel and P-Channel MOS Transistors - An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, doped n-type throughout its length, and includes portions serving as gate electrodes of n-channel and p-channel MOS transistors; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. The p-channel MOS transistor includes a buried channel region, formed by way of ion implantation, disposed between its source and drain regions. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad. | 08-29-2013 |
| 20130221419 | Memcapacitor Devices, Field Effect Transistor Devices, And Non-Volatile Memory Arrays - A memcapacitor device includes a pair of opposing conductive electrodes. A semiconductive material including mobile dopants within a dielectric and a mobile dopant barrier dielectric material are received between the pair of opposing conductive electrodes. The semiconductive material and the barrier dielectric material are of different composition relative one another which is at least characterized by at least one different atomic element. One of the semiconductive material and the barrier dielectric material is closer to one of the pair of electrodes than is the other of the semiconductive material and the barrier dielectric material. The other of the semiconductive material and the barrier dielectric material is closer to the other of the pair of electrodes than is the one of the semiconductive material and the barrier dielectric material. Other implementations are disclosed, including field effect transistors, memory arrays, and methods. | 08-29-2013 |
| 20130221420 | STRUCTURE COMPRISING A RUTHENIUM METAL MATERIAL - A method for forming a ruthenium metal layer comprises combining a ruthenium precursor with a measured amount of oxygen to form a ruthenium oxide layer. The ruthenium oxide is annealed in the presence of a hydrogen-rich gas to react the oxygen in the ruthenium oxide with hydrogen, which results in a ruthenium metal layer. By varying the oxygen flow rate during the formation of ruthenium oxide, a ruthenium metal layer having various degrees of smooth and rough textures can be formed. | 08-29-2013 |
| 20130228837 | SEMICONDUCTOR DEVICE - A semiconductor device according to this invention includes a support film that supports a lower electrode of a capacitor at an upper portion, and the support film includes a first insulating material having a stress within a range of +700 MPa to −700 MPa. Use of such a support film prevents a phenomenon in which the capacitor lower electrode is twisted. Preferably, the support film has a rate etched by hydrofluoric acid of 1.0 nm/sec or less and more preferably, the support film includes a silicon carbon nitride film. | 09-05-2013 |
| 20130228838 | SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF - A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential. | 09-05-2013 |
| 20130234221 | MOS Transconductance Gain Boosting Techniques in Millimeter-Wave Range - The present disclosure relates to a semiconductor device, such as a transistor. The device includes a gate terminal, a source terminal, a drain terminal, a transconductance component, and a boost component. The gate terminal is configured to receive a bias voltage. The drain terminal is coupled to the boost component. The transconductance component is coupled to the gate terminal, the source terminal and the drain terminal and provides an output current proportional to the bias voltage. The boost component is coupled to the transconductance component and boosts the output current at a selected frequency range. | 09-12-2013 |
| 20130240965 | SEMICONDUCTOR DEVICE HAVING BURIED BIT LINE, AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming at least one body having two sidewalls by vertically etching a semiconductor substrate, forming a protective layer having open parts that expose portions of the both sidewalls of the body, forming a buffer layer that fills the open parts, and forming a buried bit line in the body by siliciding the buffer layer and a portion of the body between the buffer layer. | 09-19-2013 |
| 20130240966 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor body including a first upper surface with a first side surface extending downwardly therefrom, a second upper surface with a second side surface extending downwardly therefrom, and a bottom surface interfacing first and second side surfaces. The first and second side surfaces and the bottom surface together define a groove. A conductive film partially fills the groove with an intervention of an insulating film therebetween so the conductive film terminates at a first intermediate portion of the first side surface between the first upper surface and the bottom surface and at a second intermediate portion of the second side surface between the second upper surface and the bottom surface. A distance between the first intermediate portion of the first side surface and the first upper surface exceeds a distance between the second intermediate portion of the second side surface and the second upper surface. | 09-19-2013 |
| 20130248956 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device may include active patterns of pillar-shapes disposed on a substrate and spaced apart from each other in one direction; a gate electrode extending in the one direction and overlapped with sidewalls of the active patterns; a gate insulating layer disposed between the gate electrode and the active patterns; bit lines connected to bottom surfaces of respective active patterns; and/or capacitors connected to top surfaces of the respective active patterns. Each of the active patterns may have no p-type/n-type (PN) junctions. A semiconductor device may include a substrate; active patterns on the substrate that are spaced apart from each other; a gate electrode configured to overlap sidewalls of the active patterns; and/or gate insulating layers between the gate electrode and respective active patterns. The active patterns may be doped with dopants of a same conductivity type. | 09-26-2013 |
| 20130248957 | DECOUPLING CAPACITOR CELL, CELL-BASED IC, CELL-BASED IC LAYOUT SYSTEM AND METHOD, AND PORTABLE DEVICE - A decoupling capacitor cell includes: a first decoupling capacitor formed by only a pMOS transistor; and a second decoupling capacitor formed by two metal layers. The decoupling capacitor cell is arranged in an unused region not occupied by basic cells in a cell-based IC and is connected to a power wiring and a ground wiring. | 09-26-2013 |
| 20130256769 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include storage node pads disposed adjacent to each other between word lines but spaced apart from each other by an isolation pattern. Accordingly, it is possible to prevent a bridge problem from being caused by a mask misalignment. This enables to improve reliability of the semiconductor device. | 10-03-2013 |
| 20130256770 | TRANSISTOR, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR MODULE INCLUDING THE SAME - A semiconductor device including a buried cell array transistor and an electronic device including the same are provided. The device includes a field region in a substrate and the filed region defines an active region. A first source/drain region and a second source/drain region are in the active region. A gate trench is between the first and second source/drain regions, and in the active region and the field region. A gate structure is within the gate trench. The gate structure includes a gate electrode, an insulating gate capping pattern on the gate electrode, a gate dielectric between the gate electrode and the active region, and an insulating metal-containing material layer between the insulating gate capping pattern and the active region. | 10-03-2013 |
| 20130256771 | SEMICONDUCTOR DEVICE - The semiconductor device includes a source line, a bit line, a signal line, a word line, memory cells connected in parallel between the source line and the bit line, a first driver circuit electrically connected to the source line and the bit line through switching elements, a second driver circuit electrically connected to the source line through a switching element, a third driver circuit electrically connected to the signal line, and a fourth driver circuit electrically connected to the word line. The memory cell includes a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, a second transistor including a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor. The second transistor includes an oxide semiconductor material. | 10-03-2013 |
| 20130264621 | SEMICONDUCTOR DEVICE HAVING FIN-SHAPED FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF - Disclosed is a semiconductor device including: an active region defined by an element isolation region; a gate trench going across the active region to define source/drain regions on both sides thereof, respectively, and to define, between the source/drain regions, the channel region having a first, second, and third protruding portions which are arranged in a gate width direction; and a gate electrode formed in the gate trench so as to cover the channel region through a gate insulating film. | 10-10-2013 |
| 20130270620 | STRUCTURE AND METHOD FOR FINFET INTEGRATED WITH CAPACITOR - The present disclosure provides one embodiment of a semiconductor structure that includes a semiconductor substrate having a first region and a second region; a shallow trench isolation (STI) feature formed in the semiconductor substrate. The STI feature includes a first portion disposed in the first region and having a first thickness T | 10-17-2013 |
| 20130277723 | DRAM Cells and Methods of Forming Silicon Dioxide - Some embodiments include methods of forming silicon dioxide in which silicon dioxide is formed across silicon utilizing a first treatment temperature of no greater than about 1000° C., and in which an interface between the silicon dioxide and the silicon is annealed utilizing a second treatment temperature which is at least about 1050° C. Some embodiments include methods of forming transistors in which a trench is formed to extend into monocrystalline silicon. Silicon dioxide is formed along multiple crystallographic planes along an interior of the trench utilizing a first treatment temperature of no greater than about 1000° C., and an interface between the silicon dioxide and the monocrystalline silicon is annealed utilizing a second treatment temperature which is at least about 1050° C. A transistor gate is formed within the trench, and a pair of source/drain regions is formed within the monocrystalline silicon adjacent the transistor gate. Some embodiments include DRAM cells. | 10-24-2013 |
| 20130277724 | CAPACITORS AND SEMICONDUCTOR DEVICES INCLUDING THE SAME - A capacitor includes a lower electrode having a curved surface, a first seed on a sidewall of the lower electrode, which the first seed includes a metal silicide and has a shape corresponding to the curved surface of the lower electrode, a dielectric layer on the lower electrode, the dielectric layer covering the first seed, and an upper electrode on the dielectric layer. | 10-24-2013 |
| 20130285132 | Semiconductor Module With a Semiconductor Chip and a Passive Component and Method for Producing the Same - A semiconductor module includes a semiconductor chip and a passive discrete component. The semiconductor chip includes on its top side and/or on the back side one or more contacts, which in its two-dimensional extent takes up the top side and/or the back side of the semiconductor chip virtually completely. The passive component, arranged in a package, is stacked on one of the contacts. The electrode of the passive component is electrically connected with one of the contacts. The counter electrode of the passive component is operatively connected with a control or signal electrode of the semiconductor chip or an electrode of a further semiconductor chip. | 10-31-2013 |
| 20130292752 | Semiconductor Cells, Arrays, Devices and Systems Having a Buried Conductive Line and Methods for Forming the Same - Semiconductor arrays including a plurality of access devices disposed on a buried conductive line and methods for forming the same are provided. The access devices each include a transistor having a source region and drain region spaced apart by a channel region of opposite dopant type and an access line associated with the transistor. The access line may be electrically coupled with one or more of the transistors and may be operably coupled to a voltage source. The access devices may be formed in an array on one or more conductive lines. A system may be formed by integrating the semiconductor devices with one or more memory semiconductor arrays or conventional logic devices, such as a complementary metal-oxide-semiconductor (CMOS) device. | 11-07-2013 |
| 20130299889 | ON-CHIP CAPACITORS IN COMBINATION WITH CMOS DEVICES ON EXTREMELY THIN SEMICONDUCTOR ON INSULATOR (ETSOI) SUBSTRATES - A device including a semiconductor on insulator (SOI) substrate including a semiconductor device region and a capacitor device region. A semiconductor device present in the semiconductor device region. The semiconductor device including a gate structure present on a semiconductor on insulator (SOI) layer of the SOI substrate, extension source and drain regions present in the SOI layer on opposing sides of the gate structure, and raised source and drain regions composed of a first portion of an epitaxial semiconductor material on the SOI layer. A capacitor is present in the capacitor device region, said capacitor including a first electrode comprised of a second portion of the epitaxial semiconductor material that has a same composition and crystal structure as the first portion of the epitaxial semiconductor material, a node dielectric layer present on the second portion of the epitaxial semiconductor material, and a second electrode comprised of a conductive material. | 11-14-2013 |
| 20130307042 | Floating Body Cell Structures, Devices Including Same, and Methods for Forming Same - Floating body cell structures including an array of floating body cells disposed on a back gate and source regions and drain regions of the floating body cells spaced apart from the back gate. The floating body cells may each include a volume of semiconductive material having a channel region extending between pillars, which may be separated by a void, such as a U-shaped trench. The floating body cells of the array may be electrically coupled to another gate, which may be disposed on sidewalls of the volume of semiconductive material or within the void therein. Methods of forming the floating body cell devices are also disclosed. | 11-21-2013 |
| 20130320421 | METAL-OXIDE-SEMICONDUCTOR CAPACITOR - A MOS capacitor includes a substrate, a p-type MOS (pMOS) transistor positioned on the substrate, and an n-type MOS (nMOS) transistor positioned on the substrate. More important, the pMOS transistor and the nMOS transistor are electrically connected in parallel. The MOS transistor further includes a deep n-well that encompassing the pMOS transistor and the nMOS transistor. | 12-05-2013 |
| 20130334582 | DRAM DEVICE - A DRAM device includes plural N-channel MIS transistors arranged in a matrix over a P well, and a plurality of capacitors formed corresponding to the plurality of N-channel MIS transistors, and plural word lines formed corresponding to each row of the plurality of N-channel MIS transistors, and a plurality of bit lines formed corresponding to each column of the plurality of N-channel MIS transistors, and a P | 12-19-2013 |
| 20130341695 | MANUFACTURING PROCESS FOR ZERO-CAPACITOR RANDOM ACCESS MEMORY CIRCUITS - Embodiments of a manufacturing process flow for producing standalone memory devices that can achieve bit cell sizes on the order of 4F2 or 5F2, and that can be applied to common source/drain, separate source/drain, or common source only or common drain only transistor arrays. Active area and word line patterns are formed as perpendicularly-arranged straight lines on a Silicon-on-Insulator substrate. The intersections of the active area and spaces between word lines define contact areas for the connection of vias and metal line layers. Insulative spacers are used to provide an etch mask pattern that allows the selective etching of contact areas as a series of linear trenches, thus facilitating straight line lithography techniques. Embodiments of the manufacturing process remove first layer metal (metal-1) islands and form elongated vias, in a succession of processing steps to build dense memory arrays. | 12-26-2013 |
| 20140001526 | Analog Floating-Gate Capacitor with Improved Data Retention in a Silicided Integrated Circuit | 01-02-2014 |
| 20140001527 | SEMICONDUCTOR DEVICE HAVING BURIED BIT LINES AND METHOD FOR FABRICATING THE SAME | 01-02-2014 |
| 20140015027 | SEMICONDUCTOR DEVICE HAVING GATE ELECTRODE EMBEDDED IN GATE TRENCH - Disclosed herein is a device that includes: a substrate having a gate trench; a gate electrode embedded in the gate trench with an intervention of a gate insulation film; and an embedded insulation film embedded in the gate trench. The substrate includes a first impurity diffusion region in contact with the embedded insulation film and a second impurity diffusion region in contact with the gate insulation film. The gate trench including a first trench portion extending in a first direction and second and third trench portions branching from the first trench portion and extending in a second direction that crosses the first direction. The gate electrode including first, second and third electrode portions embedded in the first, second and third trench portions of the gate trench, respectively. The first impurity diffusion region being sandwiched between the second and third electrode portions. | 01-16-2014 |
| 20140015028 | MICROELECTRONIC MEMORY DEVICES HAVING FLAT STOPPER LAYERS - Memory devices comprise a lower layer that extends across a cell array region and across a peripheral region and that includes a flat outer surface from the cell array region to the peripheral region. A signal transfer conductor layer extends in the cell array region beneath the flat outer surface of the lower layer and extends in the peripheral region above the flat outer surface of the lower layer. An insulating layer is provided on the lower layer, including a flat outer surface from the cell array region to the peripheral region. A flat stopper layer is provided on the flat outer surface of the insulating layer and extending across the cell array region and the peripheral region. Related methods are also provided. | 01-16-2014 |
| 20140021521 | MOS CAPACITOR, METHOD OF FABRICATING THE SAME, AND SEMICONDUCTOR DEVICE USING THE SAME - A MOS capacitor, a method of fabricating the same, and a semiconductor device using the same are provided. The MOS capacitor is arranged in an outermost cell block of the semiconductor device employing an open bit line structure. The MOS capacitor includes a first electrode arranged in a semiconductor substrate, a dielectric layer arranged on a semiconductor substrate, and a second electrode arranged on the dielectric layer and including a dummy bit line. | 01-23-2014 |
| 20140035014 | OTP MEMORY CELL AND FABRICATING METHOD THEREOF - A one-time programmable (OTP) memory cell is provided, which includes: a well of a first conductivity type; a gate insulating layer formed on the well and including first and second fuse regions; a gate electrode of a second conductivity type formed on the gate insulating layer, the second conductivity type being opposite in electric charge to the first conductivity type; a junction region of the second conductivity type formed in the well and arranged to surround the first and second fuse regions; and an isolation layer formed in the well between the first fuse region and the second fuse region. | 02-06-2014 |
| 20140035015 | APPARATUS RELATING TO A MEMORY CELL HAVING A FLOATING BODY - An apparatus is disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer, the transistor including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source and the drain, a second region positioned remote from each of the source and drain, and a passage extending through the insulation layer and coupling the first region to the second region. Additionally, the memory cell may include a bias gate at least partially surrounding the second region and configured for operably coupling to a bias voltage. Furthermore, the memory cell may include a plurality of dielectric layers, wherein each outer vertical surface of the second region has a dielectric layer of the plurality adjacent thereto. | 02-06-2014 |
| 20140035016 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device including, on the same semiconductor substrate, a transistor element, a capacitor, and a resistor. The capacitor is formed on an active region, and the resistor is formed on an element isolation region, both formed of the same polysilicon film. By CMP or etch-back, the surface is ground down while planarizing the surface until a resistor has a desired thickness. Owing to a difference in height between the active region and the element isolation region, a thin resistor and a thick upper electrode of the capacitor are formed to prevent passing through of a contact. | 02-06-2014 |
| 20140035017 | NONVOLATILE MEMORY DEVICE AND METHOD OF FORMING THE SAME - A nonvolatile memory device has a first active region and a second active region defined in a substrate by a device isolation layer, a Metal Oxide Silicon Field-Effect Transistor (MOSFET) disposed on the first active region and including a first electrode pattern, and a Metal Oxide Silicon (MOS) capacitor disposed on the second active region and including a second electrode pattern, and in which the first electrode pattern is narrower in the widthwise direction of the channel of the MOSFET than the first active region. | 02-06-2014 |
| 20140042509 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - Provided are semiconductor devices and methods of manufacturing the same. The semiconductor device may include a substrate provided with a transistor, an insulating layer disposed on the substrate, the insulating layer including a contact hole exposing a portion of the transistor, a spacer disposed on an inner sidewall of the contact hole, and a contact plug disposed in the contact hole. Here, a space defined by the spacer may increase in width from a bottom side thereof to a top side thereof. | 02-13-2014 |
| 20140048859 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - Disclosed is a semiconductor device including: a titanium nitride film formed over a semiconductor substrate and a tungsten film formed over the titanium nitride film. The titanium nitride film contains carbon and the tungsten film contains boron. A tungsten hexafluoride gas and a diborane gas are used in formation of the tungsten film. | 02-20-2014 |
| 20140048860 | SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR PILLAR - Disclosed herein is a device that includes: first to fourth conductive lines embedded in a semiconductor substrate; a first semiconductor pillar located between the first and second conductive lines; a second semiconductor pillar located between the second and third conductive lines; a third semiconductor pillar located between the third and fourth conductive lines; a first storage element connected to an upper portion of the first semiconductor pillar; a second storage element connected to an upper portion of the third semiconductor pillar; and a bit line embedded in the semiconductor substrate connected to lower portions of the first to third semiconductor pillars. At least one of the first and second conductive lines and at least one of the third and fourth conductive lines being supplied with a potential so as to form channels in the first and third semiconductor pillars. | 02-20-2014 |
| 20140048861 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - A multi-gate structure is used and a width (d1) of a high concentration impurity region sandwiched by two channel forming regions in a channel length direction is set to be shorter than a width (d2) of low concentration impurity regions in the channel length direction. Thus, a resistance of the entire semiconductor layer of a TFT which is in an on state is reduced to increase an on current. In addition, a carrier life time due to photoexcitation produced in the high concentration impurity region can be shortened to reduce light sensitivity. | 02-20-2014 |
| 20140061740 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An ESD protection device is described, including a substrate of a first conductivity, a well of a second conductivity, a transistor including a first doped region of the second conductivity located in the substrate and extending into the well, a second doped region of the first conductivity and a gate over the substrate between the two doped regions, a third doped region of the second conductivity and a fourth doped region of the first conductivity disposed in the substrate in sequence from an outer side of the second doped region and coupled to ground, and a fifth doped region of the first conductivity and a sixth doped region of the second conductivity disposed in the well in sequence from an outer side of the first doped region and coupled to a bonding pad. When an ESD voltage is applied to the bonding pad, it is coupled to the gate. | 03-06-2014 |
| 20140061741 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device comprises a bit line formed over a semiconductor substrate. The bit line has an upper portion and a lower portion, and the upper portion is narrower than the lower portion. An barrier film is formed over sidewalls of the bit line, and a storage node contact plug is obtained by filling a space between the bit lines so that an upper portion of the storage node contact is wider than a lower portion of the storage node contact. As a result, the process can be simplified and a short between the storage node contact plug and the bit line can be prevented. | 03-06-2014 |
| 20140061742 | SEMICONDUCTOR DEVICE - A semiconductor device comprises an isolation region, an active region, a first gate trench extending continuously from the active region to the isolation region, first and second insulating films, a first conductive layer, and a cap insulating film. The first insulating film covers an inner surface of the first gate trench. The second insulating film interposes between the first insulating film and the inner surface of the first gate trench at the active region. The first conductive layer buries a lower portion of the first gate trench so as to cover at least a part of the first insulating film. The cap insulating film covers the upper surface of the first conductive layer and buries an upper portion of the first gate trench | 03-06-2014 |
| 20140061743 | SEMICONDUCTOR DEVICES AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a substrate, a device isolation layer defining one or more active regions at the substrate, and one or more gate lines buried in the substrate. Each of the gate lines comprises a first portion on the device isolation layer and a second portion on an active region of the active regions. A top surface of the first portion is lower than a top surface of the second portion. | 03-06-2014 |
| 20140070291 | SEMICONDUCTOR DEVICES INCLUDING A GATE STRUCTURE BETWEEN ACTIVE REGIONS, AND METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING A GATE STRUCTURE BETWEEN ACTIVE REGIONS - Semiconductor devices are provided. The semiconductor devices may include an isolation pattern and first, second, and third active regions of a substrate. The first active region may be spaced apart from the second active region by a first width of the isolation pattern in a direction. A gate structure may be between the first and second active regions and may include a second width wider than the first width of the isolation pattern in the direction. Related methods of forming semiconductor devices are also provided. | 03-13-2014 |
| 20140103414 | Vertical Super-Thin Body Semiconductor on Dielectric Wall Devices and Methods of Their Fabrication - The present invention is a semiconductor device comprising a semiconducting low doped vertical super-thin body (VSTB) formed on Dielectric Body Wall (such as STI-wall as isolating substrate) having the body connection to bulk semiconductor wafer on the bottom side, isolation on the top side, and the channel, gate dielectric, and gate electrode on opposite to STI side surface. The body is made self-aligned to STI hard mask edge allowing tight control of body thickness. Source and Drain are made by etching holes vertically in STI at STI side of the body and filling with high doped crystalline or poly-Si appropriately doped with any appropriate silicides/metal contacts or with Schottky barrier Source/Drain. Gate first or Gate last approaches can be implemented. Many devices can be fabricated in single active area with body isolation between the devices by iso-plugs combined with gate electrode isolation by iso-trenches. The body can be made as an isolated nano-plate or set nano-wire MOSFET's on the STI wall to form VSTB SOI devices. | 04-17-2014 |
| 20140110772 | INTEGRATED CIRCUIT DECOUPLING CAPACITOR ARRANGEMENT - A decoupling capacitor arrangement is provided for an integrated circuit. The apparatus includes a plurality of decoupling capacitor arrays electrically connected in parallel with one another. Each of the arrays includes a plurality of decoupling capacitors and a current limiting element. The decoupling capacitors of each array are electrically connected in parallel with one another. The current limiting element is connected in series with the plurality of decoupling capacitors. | 04-24-2014 |
| 20140117430 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a first substrate, a plurality of memory chips horizontally disposed on the first substrate, and having one surfaces which face the first substrate, other surfaces which face away from the one surfaces, and first bumps formed on the other surfaces, a second substrate disposed on the plurality of memory chips and electrically connected, a sub-substrate horizontally disposed on the first substrate together with the plurality of memory chips and electrically connecting the first substrate and the second substrate, and a driving chip having second bumps on one surface thereof and mounted to the second substrate such that the second bumps are electrically connected with the second substrate. | 05-01-2014 |
| 20140124844 | SEMICONDUCTOR LAYOUT STRUCTURE - A semiconductor layout structure includes multiple active blocks which are disposed on a substrate, parallel with one another and extending along a first direction, multiple first shallow trench isolations which are disposed on a substrate, parallel with one another and respectively disposed on the multiple active blocks, and multiple second shallow trench isolations which are disposed on a substrate, cutting through multiple active blocks and extending along a second direction. The first direction has an angle about 1 degree to about 53 degrees to the second direction. | 05-08-2014 |
| 20140167125 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device capable of increasing ON current while reducing channel resistance and allowing transistors to operate independently and stably, having a fin formed to protrude from the bottom of a gate electrode trench, a gate insulating film covering the surfaces of the gate electrode trench and the fin, a gate electrode embedded in a lower part of the gate electrode trench and formed to stride over the fin via the gate insulating film, a first impurity diffusion region arranged on a first side face, and a second impurity diffusion region arranged on a second side face. | 06-19-2014 |
| 20140167126 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate and a PIP capacitor located. The PIP capacitor includes a first polysilicon layer, a metallic silicide layer, a protective layer, a dielectric layer, and a second polysilicon layer, which have a lower conductive plate pattern and are successively arranged. The method includes: providing a substrate; successively forming a first polysilicon layer, a metallic silicide, and a protective layer on the substrate; transferring a lower conductive plate pattern into the first polysilicon layer, the metallic silicide layer, and the protective layer, thus forming the first polysilicon layer, the metallic silicide layer, and the protective layer having the lower conductive plate pattern; successively forming a dielectric layer and a second polysilicon layer having a lower conductive plate pattern on the protective layer. The capacitance and reliability of the PIP capacitor are improved. | 06-19-2014 |
| 20140197469 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICES WITH CURRENT PATH SELECTION STRUCTURE AND METHODS OF OPERATING THE SAME - Provided are three-dimensional semiconductor devices and methods of operating the same. The three-dimensional semiconductor devices may include active patterns arranged on a substrate to have a multi-layered and multi-column structure and drain patterns connected to respective columns of the active patterns. The methods may include a layer-selection step connecting a selected one of layers of the active patterns selectively to the drain patterns. For example, the layer-selection step may be performed in such a way that widths of depletion regions to be formed in end-portions of the active patterns are differently controlled depending on to a height from the substrate. | 07-17-2014 |
| 20140209987 | MEMORY DEVICE - It is an object to provide a memory device where an area occupied by a memory cell is small, and moreover, a memory device where an area occupied by a memory cell is small and a data holding period is long. A memory device includes a bit line, a capacitor, a first insulating layer provided over the bit line and including a groove portion, a semiconductor layer, a second insulating layer in contact with the semiconductor layer, and a word line in contact with the second insulating layer. Part of the semiconductor layer is electrically connected to the bit line in a bottom portion of the groove portion, and another part of the semiconductor layer is electrically connected to one electrode of the capacitor in a top surface of the first insulating layer. | 07-31-2014 |
| 20140231890 | MIM CAPACITOR IN FINFET STRUCTURE - A method of forming a FinFET structure having a metal-insulator-metal capacitor. Silicon fins are formed on a semiconductor substrate followed by formation of the metal-insulator-metal capacitor on the silicon fins by depositing sequential layers of a first layer of titanium nitride, a dielectric layer and a second layer of titanium nitride. A polysilicon layer is deposited over the metal-insulator-metal capacitor followed by etching back the polysilicon layer and the metal-insulator-metal capacitor layers from ends of the silicon fins so that the first and second ends of the silicon fins protrude from the polysilicon layer. A spacer may be formed on surfaces facing the ends of the silicon fins followed by the formation of epitaxial silicon over the ends of the silicon fins. Also disclosed is a FinFET structure having a metal-insulator-metal capacitor. | 08-21-2014 |
| 20140231891 | MIM CAPACITOR IN FINFET STRUCTURE - A FinFET structure which includes: silicon fins on a semiconductor substrate, each silicon fin having two sides and a horizontal surface; sequential layers of a first layer of titanium nitride, a dielectric layer and a second layer of titanium nitride on the sides and horizontal surface of the silicon fins; a polysilicon gate layer over the second layer of titanium nitride on the silicon fins and over the semiconductor substrate such that first and second ends of the silicon fins protrude from the polysilicon layer; spacers adjacent to the polysilicon gate layer; epitaxial silicon over the first and second ends of the silicon fins to form sources and drains, wherein the combination of the first layer of titanium nitride, dielectric layer and second layer of titanium nitride forms a metal-insulator-metal capacitor situated between each silicon fin and the polysilicon layer. | 08-21-2014 |
| 20140231892 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - First dopant regions and second dopant regions are provided at both sides of the gate structures. Conductive lines cross over the gate structures and are connected to the first dopant regions. Each of the conductive lines includes a conductive pattern and a capping pattern disposed on the conductive pattern. Contact structures are provided between the conductive lines and are connected to the second dopant regions. Each of the contact structures includes a lower contact pattern disposed on the second dopant region and an upper contact pattern disposed on the lower contact pattern. A bottom surface of the upper contact pattern is lower than a top surface of the conductive pattern. | 08-21-2014 |
| 20140252440 | SEMICONDUCTOR DEVICES INCLUDING CONDUCTIVE PLUG - Semiconductor devices include a substrate having a target connection region; a conductive line having a first side wall spaced apart from the substrate by at least an insulating layer, and a conductive plug structure electrically connecting the conductive line to the target connection region, wherein the conductive plug includes a first conductive plug having a first side wall, a bottom surface contacting the target connection region of the substrate, and a second side wall facing the first side wall of the conductive line, and a second conductive plug between the conductive line and the first conductive plug. The second conductive plug contacts both the first side wall of the conductive line and the second side wall of the first conductive plug. | 09-11-2014 |
| 20140264517 | SEMICONDUCTOR DEVICES HAVING A SILICON-GERMANIUM CHANNEL LAYER AND METHODS OF FORMING THE SAME - Semiconductor devices having a silicon-germanium channel layer and methods of forming the semiconductor devices are provided. The methods may include forming a silicon-germanium channel layer on a substrate in a peripheral circuit region and sequentially forming a first insulating layer and a second insulating layer on the silicon-germanium channel layer. The methods may also include forming a conductive layer on the substrate, which includes a cell array region and the peripheral circuit region, and patterning the conductive layer to form a conductive line in the cell array region and a gate electrode in the peripheral circuit region. The first insulating layer may be formed at a first temperature and the second insulating layer may be formed at a second temperature higher than the first temperature. | 09-18-2014 |
| 20140264518 | SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device which can store data even after the application of power supply voltage is stopped, a manufacturing method thereof, or a driving method thereof. Data stored in a first circuit portion is transmitted to a second circuit portion, the data is stored in the second circuit portion in a period during which the application of power supply voltage is stopped, and data corresponding to the data is transmitted to the first circuit portion at the time of applying power supply voltage again. With such a configuration, a semiconductor device can store data even in a period during which the application of the power supply voltage is stopped. In particular, the second circuit portion includes a transistor including an oxide semiconductor, whereby the data can be accurately stored. | 09-18-2014 |
| 20140284671 | SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF - A semiconductor structure includes a metal gate, a second dielectric layer and a contact plug. The metal gate is located on a substrate and in a first dielectric layer, wherein the metal gate includes a work function metal layer having a U-shaped cross- sectional profile and a low resistivity material located on the work function metal layer. The second dielectric layer is located on the metal gate and the first dielectric layer. The contact plug is located on the second dielectric layer and in a third dielectric layer, thereby a capacitor is formed. Moreover, the present invention also provides a semiconductor process forming said semiconductor structure. | 09-25-2014 |
| 20140284672 | MEMORY DEVICE COMPRISING AN ARRAY PORTION AND A LOGIC PORTION - In an embodiment of the present invention, a method comprises patterning a first plurality of semiconductor structures in an array portion of a semiconductor substrate using a first photolithographic mask. The method further comprises patterning a second plurality of semiconductor structures over a logic portion of a semiconductor substrate using a second photolithographic mask. The method further comprises patterning a sacrificial layer over the first plurality of semiconductor structures using the second photolithographic mask. The sacrificial layer is patterned simultaneously with the second plurality of semiconductor structures. | 09-25-2014 |
| 20140284673 | Memory Device And Electronic Device - A selection operation is performed for individual memory cells. A device includes a first memory cell and a second memory cell provided in the same row as the first memory cell, each of which includes a field-effect transistor having a first gate and a second gate. The field-effect transistor controls at least data writing and data holding in the memory cell by being turned on or off. The device further includes a row selection line electrically connected to the first gates of the field-effect transistors included in the first memory cell and the second memory cell, a first column selection line electrically connected to the second gate of the field-effect transistor included in the first memory cell, and a second column selection line electrically connected to the second gate of the field-effect transistor included in the second memory cell. | 09-25-2014 |
| 20140299926 | Semiconductor Device and Method for Manufacturing the Same - A method for manufacturing a semiconductor device comprises forming a first layer on an impurity diffusion region in a semiconductor substrate by a selective epitaxial growth method, forming a second layer on the first layer by the selective epitaxial growth method, forming a contact hole penetrating an interlayer insulating film in a thickness direction thereof and reaching the second layer, and filling a conductive material into the contact hole to form a contact plug including the first and second layers and the conductive material. | 10-09-2014 |
| 20140312401 | MEMORY CELL HAVING A RECESSED GATE AND MANUFACTURING METHOD THEREOF - A memory cell with a recessed gate includes a semiconductor substrate, a shallow trench isolation, an active region, a gate electrode, a halogen-doped dielectric layer and at least a capacitor. The shallow trench isolation is disposed in the semiconductor substrate in order to define the active region. A source region and a drain region are respectively disposed on each end of the active region along a first direction. A gate trench is formed in the semiconductor substrate between the source region and the drain region, wherein the gate trench includes a sidewall portion and a curved-bottom surface. The curved-bottom surface has a convex profile when viewed from a cross-sectional view taken along a second direction perpendicular to the first direction. The gate electrode is disposed in the gate trench and the halogen-doped dielectric layer is disposed between the gate electrode and the semiconductor substrate. | 10-23-2014 |
| 20140312402 | SEMICONDUCTOR MEMORY DEVICE - In the semiconductor memory device, one of a source and a drain of a first transistor is connected to one of a source and a drain of a second transistor, a gate of the first transistor is connected to one of a source and a drain of a third transistor and one of a pair of capacitor electrodes included in a capacitor, the other of the source and the drain of the first transistor and the other of the source and the drain of the third transistor are connected to a bit line, the other of the pair of capacitor electrodes included in the capacitor is connected to a common wiring, and the common wiring is grounded (GND). The common wiring has a net shape when seen from the above, and the third transistor is provided in a mesh formed by the common wiring. | 10-23-2014 |
| 20140319591 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In an interlayer insulating film in which contact plugs are embedded, a capacitor element is formed which has electrodes each formed of a metal. Over a substrate, the interlayer insulating film is formed. The interlayer insulating film includes a first insulating film and a second insulating film. In the second insulating film, the first and second contact plugs are formed. The first and second contact plugs extend through the second insulating film to reach first and second gate electrodes. In a surface of the substrate, an isolation film is formed. Within a region overlapping the isolation film in planar view, the capacitor element is formed. The capacitor element includes the lower and upper electrodes. Each of the lower and upper electrodes contains a metal. The lower and upper electrodes of the capacitor element are formed over the first insulating film to be embedded in the second insulating film. | 10-30-2014 |
| 20140327062 | ELECTRONIC DEVICES INCLUDING OXIDE DIELECTRIC AND INTERFACE LAYERS - An electronic device may include a substrate, an oxide dielectric layer on the substrate, an interface layer on the oxide dielectric layer, and an electrode on the interface layer. The oxide dielectric layer may include an aluminum oxide layer between first and second zirconium oxide layers. The interface layer may have a first formation enthalpy, and the oxide dielectric layer may be between the substrate and the interface layer. The electrode may have a second formation enthalpy higher than the first formation enthalpy, and the interface layer may be between the oxide dielectric layer and the electrode. | 11-06-2014 |
| 20140327063 | SEMICONDUCTOR DEVICE HAVING LANDING PADS - A semiconductor device including a substrate, the substrate including active regions; a pair of conductive lines spaced apart from the substrate such that an insulating layer is between the substrate and the pair of conductive lines; insulating spacers covering side walls of each of the pair of conductive lines such that contact holes having first widths in a first direction are defined between the pair of conductive lines; upper insulating patterns on the pair of conductive lines, the upper insulating patterns defining landing pad holes connected to the contact holes such that the landing pad holes have second widths in the first direction that are greater than the first widths; contact structures including contact plugs connected to the active regions by passing through the insulating layer, and first landing pads connected to the contact plugs, the first landing pads being in the landing pads holes such that the first landing pads vertically overlap with one of the pair of conductive lines; and capacitor lower electrodes connected to the contact structures. | 11-06-2014 |
| 20140332871 | SEMICONDUCTOR DEVICE HAVING JUMPER PATTERN AND BLOCKING PATTERN - A semiconductor device includes a substrate having a transistor area, a gate structure disposed on the transistor area of the substrate, a first interlayer insulating layer covering the gate structure, a blocking pattern disposed on the first interlayer insulating layer, and a jumper pattern disposed on the blocking pattern. The jumper pattern includes jumper contact plugs vertically penetrating the first interlayer insulating layer to be in contact with the substrate exposed at both sides of the gate structure, and a jumper section configured to electrically connect the jumper contact plugs. | 11-13-2014 |
| 20140332872 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device includes a semiconductor substrate including a pad region and a peripheral region, a first buffer layer formed to include a capacitor over the semiconductor substrate in the pad region, a second buffer layer formed to include a first contact pad over the first buffer layer, and a third buffer layer formed to include a second contact pad over the first contact pad. The semiconductor device, by additionally forming a buffer layer at a lower part in the pad region, reduces a stress caused by wire bonding. Thus, an applied stress to a lower structure in the pad region is also reduced. As a result, the buffer layer prevents formation of an electrical bridge between the pad region and the peripheral region. | 11-13-2014 |
| 20140339618 | CIRCUIT HAVING CAPACITOR COUPLED WITH MEMORY ELEMENT - A circuit includes a capacitor and a memory element. The capacitor includes a first conductive layer, a first terminal, and a second terminal. The first conductive layer includes a first plurality of bars extending along a first direction and parallel to one another, where two adjacent bars of the first plurality of bars have a first capacitance therebetween. The first terminal is coupled with a first bar of the two adjacent bars, and the second terminal is coupled with a second bar of the two adjacent bars. The memory element has an input coupled with the first terminal and an output coupled with the second terminal. The capacitor is configured to inhibit changing a logic state at the input of the memory element. | 11-20-2014 |
| 20140346580 | SEMICONDUCTOR DEVICES CAPABLE OF SELF-CURING - A semiconductor device includes a plurality of first signal lines crossing a plurality of second signal lines. At least one of the first signal lines has a first end to receive a first voltage and a second end to receive a second voltage. The first and second voltages are applied simultaneously to respective ones of the first and second ends. A difference between the first and second voltages causes joule heating in the at least one first signal line. The joule heating may correct one or more defects in the semiconductor device. | 11-27-2014 |
| 20140367755 | SEMICONDUCTOR MEMORY DEVICES INCLUDING SUPPORT PATTERNS - A capacitor dielectric can be between the storage node and the electrode layer. A supporting pattern can be connected to the storage node, where the supporting pattern can include at least one first pattern and at least one second pattern layered on one another, where the first pattern can include a material having an etch selectivity with respect to the second pattern. | 12-18-2014 |
| 20140374809 | PADS INCLUDING CURVED SIDES AND RELATED ELECTRONIC DEVICES, STRUCTURES, AND METHODS - An electronic device may include a substrate, and a plurality of spaced apart pads on the substrate. Each of the pads may includes first, second, third, and fourth sides, the first and third sides may be opposite sides that are substantially straight, and the second and fourth sides may be opposite sides that are curved. Related methods, devices, and structures are also discussed. | 12-25-2014 |
| 20150008495 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a method for fabricating the same are provided to prevent a floating body effect and reduce coupling capacitance between buried bit lines. The semiconductor device comprises a first pillar disposed over a semiconductor substrate and including a vertical channel region, a bit line located in the lower portion of the vertical channel region inside the first pillar and a semiconductor layer extended from the semiconductor substrate to one sidewall of the first pillar. | 01-08-2015 |
| 20150014758 | MEMORY CELLS HAVING A FOLDED DIGIT LINE ARCHITECTURE - Memory arrays having folded architectures and methods of making the same. Specifically, memory arrays having a portion of the transistors in a row that are reciprocated and shifted with respect to other transistors in the same row. Trenches formed between the rows may form a weave pattern throughout the array, in a direction of the row. Trenches formed between legs of the transistors may also form a weave pattern throughout the array in a direction of the row. | 01-15-2015 |
| 20150021676 | HIGH VOLTAGE METAL-OXIDE-METAL (HV-MOM) DEVICE, HV-MOM LAYOUT AND METHOD OF MAKING THE HV-MOM DEVICE - A high voltage metal-oxide-metal (HV-MOM) device includes a substrate, a deep well in the substrate and at least one high voltage well in the substrate over the deep well. The HV-MOM device further includes a dielectric layer over each high voltage well of the at least one high voltage well and a gate structure over the dielectric layer. The HV-MOM device further includes an inter-layer dielectric (ILD) layer over the substrate, the ILD layer surrounding the gate structure. The HV-MOM device further includes a first inter-metal dielectric (IMD) layer over the ILD layer and a first metal feature in the first IMD layer, wherein the first metal feature is part of a MOM capacitor. | 01-22-2015 |
| 20150021677 | Embedded Transistor - An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate on opposing sides of the trench. In an embodiment, one of the source/drain regions is coupled to a storage node and the other source/drain region is coupled to a bit line. In this embodiment, the gate electrode may be coupled to a word line to form a DRAM memory cell. | 01-22-2015 |
| 20150028406 | Arrays Of Recessed Access Gate Lines, Arrays Of Conductive Lines, Arrays Of Recessed Access Gate Lines And Conductive Lines, Memory Circuitry, Methods Of Forming An Array Of Recessed Access Gate Lines, Methods Of Forming An Array Of Conductive Lines, And Methods Of Forming An Array Of Recessed Access Gate Lines And An Array Of Conductive Lines - An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric projections. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Other arrays are disclosed, as are methods. | 01-29-2015 |
| 20150035033 | LIGHT EMITTING DEVICE - A light emitting device is provided which can prevent a change in gate voltage due to leakage or other causes and at the same time can prevent the aperture ratio from lowering. A capacitor storage is formed from a connection wiring line, an insulating film, and a capacitance wiring line. The connection wiring line is formed over a gate electrode and an active layer of a TFT of a pixel, and is connected to the active layer. The insulating film is formed on the connection wiring line. The capacitance wiring line is formed on the insulating film. This structure enables the capacitor storage to overlap the TFT, thereby increasing the capacity of the capacitor storage while keeping the aperture ratio from lowering. Accordingly, a change in gate voltage due to leakage or other causes can be avoided to prevent a change in luminance of an OLED and flickering of screen in analog driving. | 02-05-2015 |
| 20150048432 | Meander Line Resistor Structure - A system comprises a first transistor comprising a first active region and a second active region, a first resistor comprising a plurality of first vias connected in series, wherein the first resistor is over the first active region, a second resistor comprising a plurality of second vias connected in series, wherein the second resistor is over the second active region, a second transistor comprising a third active region and a fourth active region, a capacitor having a terminal electrically coupled to the fourth active region and a bit line electrically coupled to the third active region. | 02-19-2015 |
| 20150060970 | Semiconductor Device Including Contact Plugs And Conductive Layers Thereon - Disclosed herein is a device that includes: a semiconductor substrate; a first insulating layer over a surface of the semiconductor substrate; first and second contact plugs each including side and upper surfaces, the side surfaces of the first and second contact plugs being surrounded by the first insulating film, the upper surfaces of the first and second contact plugs being substantially on the same plane with an upper surface of the first insulating layer; a second insulating layer over the first insulating layer; a first conductive layer including a bottom portion on the first contact plug and a side portion surrounded by the second insulating layer; a third insulating layer over the first conductive layer; and a second conductive layer on the second contact plug, apart of a side surface of the second conductive layer being surrounded by both the second and third insulating layers. | 03-05-2015 |
| 20150069482 | DRAM Arrays, Semiconductor Constructions and DRAM Array Layouts - Some embodiments include a DRAM array layout. Wordlines extend along a first direction, and bitlines extend along a second direction that crosses the first direction. Cell active material structures are at intersections of the wordlines and bitlines. The cell active material structures have a first side coupled to a bitline and a second side coupled to a capacitor. The second side is on an opposite side of a wordline passing through a cell active material structure relative to the first side. Each cell active material structure has a connection to a bitline which is not shared with any other cell active material structures. Some embodiments include DRAM arrays and semiconductor constructions. | 03-12-2015 |
| 20150076575 | METHOD AND APPARATUS FOR FORMING AN INTEGRATED CIRCUIT WITH A METALIZED COUPLING CAPACITOR - An integrated circuit includes a plurality of metal layers of bit cells of a memory cell array disposed in a first metal layer and extending in a first direction, a plurality of word lines of the memory cell array disposed in a second metal layer and extending in a second direction that is different from the first direction, and at least two conductive traces disposed in a third metal layer substantially adjacent to each other and extending at least partially across the memory cell array, a first one of the at least two conductive traces coupled to a driving source node of a write assist circuit, and a second conductive trace of the at least two conductive traces coupled to an enable input of the write-assist circuit, where the at least two conductive traces form at least one embedded capacitor having a capacitive coupling to the bit line. | 03-19-2015 |
| 20150076576 | DISPLAY DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME - It is an object to decrease the number of transistors connected to a capacitor. In a structure, a capacitor and one transistor are included, one electrode of the capacitor is connected to a wiring, and the other electrode of the capacitor is connected to a gate of the transistor. Since a clock signal is input to the wiring, the clock signal is input to the gate of the transistor through the capacitor. Then, on/off of the transistor is controlled by a signal which synchronizes with the clock signal, so that a period when the transistor is on and a period when the transistor is off are repeated. In this manner, deterioration of the transistor can be suppressed. | 03-19-2015 |
| 20150097220 | FIN-SHAPED FIELD EFFECT TRANSISTOR AND CAPACITOR STRUCTURES - A fin-shaped field-effect transistor device is provided. The fin-shaped field effect transistor device may include a semiconductor substrate having a top and a bottom surface. The fin-shaped field effect transistor device may also include a fin structure disposed on the top surface of the semiconductor substrate, where the fin structure includes a first sidewall and a second sidewall opposite of the first sidewall. The first sidewall is adjacent to a first region of the top surface of the semiconductor substrate and the second sidewall is adjacent to a second region of the top surface of the semiconductor substrate. The fin-shaped field effect transistor device may also include an insulation layer disposed above the fin structure and the first and second regions of the top surface. The fin-shaped field effect transistor device may also include a conductor structure disposed above and adjacent to the insulation layer. | 04-09-2015 |
| 20150097221 | POWER FET WITH A RESONANT TRANSISTOR GATE - A semiconductor FET provides a resonant gate and source and drain electrodes, wherein the resonant gate is electromagnetically resonant at one or more predetermined frequencies. | 04-09-2015 |
| 20150102394 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge (ESD) protection device includes a substrate including a plurality of active fins and a plurality of grooves. The ESD protection device includes an insulation layer on the active fins and the grooves, and a gate electrode on the active fins. The ESD protection device includes a first impurity region adjacent to a first side of the gate electrode, and a second impurity region adjacent to a second side of the gate electrode. The second side of the gate electrode may be arranged opposite to the first side. The ESD protection device includes an electrode pattern of a capacitor overlapping the first impurity region, a resistor overlapping the second impurity region, and a connection structure electrically connecting the electrode pattern, the gate electrode, and the resistor to each other. | 04-16-2015 |
| 20150115342 | Semiconductor Device - Provided is a semiconductor device including a substrate of a first conductivity type, a first circuit region, a separation region, a second circuit region, and a rectifying element. The rectifying element has a second conductivity type layer, a first high concentration second conductivity type region, a second high concentration second conductivity type region, an element isolation film, a first insulation layer, and a first conductive film. A first contact is coupled to the first high concentration second conductivity type region, and a second contact is coupled to the second high concentration second conductivity type region. A third contact is coupled to the first conductive film. The first contact, the second contact and the third contact are separated from each other. | 04-30-2015 |
| 20150115343 | TRANSISTOR ARRANGEMENT - A transistor arrangement comprising an electrically conductive substrate; a semiconductor body including a transistor structure, the transistor structure including a source terminal connected to said substrate; a bond pad providing a connection to the transistor structure configured to receive a bond wire; wherein the semiconductor body includes an RF-return current path for carrying return current associated with said bond wire, said RF-return current path comprising a strip of metal arranged on said body, said strip configured such that it extends beneath said bond pad and is connected to said source terminal of the transistor structure. | 04-30-2015 |
| 20150137201 | HIGH DENSITY LINEAR CAPACITOR - A methods for fabricating a capacitor structure includes fabricating polysilicon structures on a semiconductor substrate. The method further includes fabricating M1 to diffusion (MD) interconnects on the semiconductor substrate. The polysilicon structures are disposed in an interleaved arrangement with the MD interconnects. The method also includes selectively connecting the interleaved arrangement of the MD interconnects and/or the polysilicon structures as the capacitor structure. | 05-21-2015 |
| 20150137202 | CELL-BASED IC LAYOUT SYSTEM AND CELL-BASED IC LAYOUT METHOD - A decoupling capacitor cell includes: a first decoupling capacitor formed by only a pMOS transistor; and a second decoupling capacitor formed by two metal layers. The decoupling capacitor cell is arranged in an unused region not occupied by basic cells in a cell-based IC and is connected to a power wiring and a ground wiring. | 05-21-2015 |
| 20150145008 | FIN CAPACITOR EMPLOYING SIDEWALL IMAGE TRANSFER - Spacer structures are formed around an array of disposable mandrel structures and above a doped semiconductor material portion. A sidewall image transfer process is employed to pattern an upper portion of the doped semiconductor material portion into an array of doped semiconductor fins. After formation of a dielectric material layer on the top surfaces and sidewall surfaces of the doped semiconductor fins, gate-level mandrel structures are formed to straddle multiple semiconductor fins. A conductive hole-containing structure is formed to laterally surround a plurality of gate-level mandrel structures, which is subsequently removed. A contact-level dielectric layer is formed over the conductive hole-containing structure and the plurality of doped semiconductor fins. The semiconductor fins function as a lower electrode of a fin capacitor, and the conductive hole-containing structure functions as an upper electrode of the fin capacitor. | 05-28-2015 |
| 20150145009 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD THEREOF - In order to achieve high-speed operation of an eDRAM, the eDRAM includes: a selection MISFET having a gate electrode that serves as a word line, a source region, and a drain region; a source plug electrode coupled to the source region; and a drain plug electrode coupled to the drain region DR | 05-28-2015 |
| 20150303200 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device comprising: a silicon substrate; an embedded gate electrode groove provided in the silicon substrate; a gate insulating film provided on the wall inside the embedded gate electrode groove; an embedded gate electrode provided on the gate insulating film so as to be installed inside the embedded gate electrode groove, the embedded gate electrode, having a first portion having a titanium nitride film and a first metal film thereon, and a second portion having a single-layer titanium nitride film; and a contact plug electrically connected to the first metal film constituting the first portion of the embedded gate electrode. | 10-22-2015 |
| 20150311220 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To enhance the write speed of a nonvolatile memory. A charge injection/emission part of a nonvolatile memory cell includes an active region having an upper face, a side wall, and a shoulder part connecting the upper face and the side wall, a conductor film covering the upper face and the shoulder part of the active region, and a capacitance insulating film provided between the conductor film and the active region. Furthermore, the active region has a protrusion part constituted of a first concave part with respect to the upper face and a second concave part with respect to the side wall, in the shoulder part. | 10-29-2015 |
| 20150311307 | HIGH-K DIELECTRICS WITH A LOW-K INTERFACE FOR SOLUTION PROCESSED DEVICES - A device, including a substrate, an electronically active component on the substrate, an interface dielectric on the semiconductor, and a relaxor dielectric on the interface dielectric. The relaxor dielectric includes a surfactant that is solid at room temperature. | 10-29-2015 |
| 20150318234 | SWITCH CIRCUIT PACKAGE MODULE - A switch circuit package module includes at least a semiconductor switch unit and at least a first capacitor unit. The semiconductor switch unit includes a first semiconductor switch element and a second semiconductor switch element. The first semiconductor switch element and the second semiconductor switch element include a plurality of sub micro-switch elements. The capacitor unit includes a plurality of capacitors configured to cooperate with the sub micro-switch elements. The capacitors are arranged in a symmetrical distribution surrounded the semiconductor switch unit, such that impedances of any two symmetrical commutation loops each of which mainly consists of one capacitor and two sub micro-switch elements from the first semiconductor switch element and second semiconductor switch element respectively are close to or the same with each other. | 11-05-2015 |
| 20150318242 | SWITCH CIRCUIT PACKAGE MODULE - A switch circuit package module includes a semiconductor switch unit and a capacitor unit. The semiconductor switch unit includes a first semiconductor switch element and a second semiconductor switch element. The first semiconductor switch element includes sub micro-switch elements, each sub micro-switch element configured with a drain electrode and a source electrode. The second semiconductor switch element includes sub micro-switch elements, each sub micro-switch element configured with a drain electrode and a source electrode. The capacitor unit includes a plurality of capacitors. The semiconductor switch unit includes a plurality of common electrodes, each common electrode connects the source electrode of one sub micro-switch element in the first semiconductor switch element with the drain of one sub micro-switch element in the second semiconductor switch element and is disposed adjacent to at least one drain electrode from the first semiconductor switch element or one source electrode from the second semiconductor switch element. | 11-05-2015 |
| 20150318273 | ANTENNA EFFECT DISCHARGE CIRCUIT AND MANUFACTURING METHOD - An antenna effect discharge circuit is described for a device having patterned conductor layers, which may be exposed to charge inducing environments during a manufacturing process. The antenna effect discharge circuit has a terminal that is connected to a node on the device to be protected from charge accumulation and a gate, such as the gate of a field effect transistor in the circuit, and a terminal through which accumulated charge can be discharged to the substrate. A capacitor couples the gate in the antenna effect discharge circuit to the substrate. A voltage supply circuit is configured to provide voltage sufficient to bias the antenna effect discharge circuit in an off condition during operation of the device. A patterned conductor in the upper layer, and preferably the uppermost layer, of the device links the gate in the antenna effect discharge circuit to the voltage supply circuit. | 11-05-2015 |
| 20150318287 | SEMICONDUCTOR DEVICE, AND MANUFACTURING FOR SAME - A semiconductor device comprising: a semiconductor substrate; a first wiring having, in this order, on a first region of a semiconductor substrate, a second silicon film containing impurity, and a conductive film; and a second wiring having, in this order, on a second region of a semiconductor substrate, a first silicon film containing impurity, an etching stop film, a second silicon film containing impurity, and a conductive film. | 11-05-2015 |
| 20150318296 | NON-VOLATILE MEMORY DEVICES WITH VERTICALLY INTEGRATED CAPACITOR ELECTRODES - Provided is a vertical non-volatile memory device in which a capacitor constituting a peripheral circuit region is formed as a vertical type so that an area occupied by the capacitor in the entire device can be reduced as compared with a planar capacitor. Thus, a non-volatile memory device may be highly integrated and have a high capacity. The device includes a substrate having a cell region and a peripheral circuit region, a memory cell string including a plurality of vertical memory cells formed in the cell region and channel holes formed to penetrate the vertical memory cells in a first direction vertical to the substrate, an insulating layer formed in the peripheral circuit region on the substrates at substantially the same level as an upper surface of the memory cell string, and a plurality of capacitor electrodes formed on the peripheral circuit region to penetrate at least a portion of the insulating layer in the first direction, the plurality of capacitor electrodes extending parallel to the channel holes. The plurality of capacitor electrodes are spaced apart from one another in a second direction parallel to the substrate, and the insulating layer is interposed between a pair of adjacent capacitor electrodes from among the plurality of capacitor electrodes. | 11-05-2015 |
| 20150318407 | Adding Decoupling Function for TAP Cells - A circuit includes a tap cell. The tap cell includes a well region, a first well pickup region in the well region, a VDD power rail and a VSS power rail spaced apart from the VDD power rail. The tap cell also includes a first jog extending from the VDD power rail toward the VSS power rail and forming a continuous region with the VDD power rail. The tap cell further comprises a first capacitor including a first gate electrode line acting as a first capacitor plate, and the first well pickup region acting as a part of a second capacitor plate. A first one of the first and second capacitor plates is overlapped by and connected to the first jog, and a second one of the first and second capacitor plates is coupled to the VSS power rail. | 11-05-2015 |
| 20150333054 | DECOUPLING CAPACITOR AND METHOD OF MAKING SAME - A semiconductor substrate has at least two active regions, each having at least one active device that includes a gate electrode layer, and a shallow trench isolation (STI) region between the active regions. A decoupling capacitor comprises first and second dummy conductive patterns formed in the same gate electrode layer over the STI region. The first and second dummy conductive regions are unconnected to any of the at least one active device. The first dummy conductive pattern is connected to a source of a first potential. The second dummy conductive pattern is connected to a source of a second potential. A dielectric material is provided between the first and second dummy conductive patterns. | 11-19-2015 |
| 20150340426 | COMPONENT, FOR EXAMPLE NMOS TRANSISTOR, WITH AN ACTIVE REGION UNDER RELAXED COMPRESSIVE STRESS, AND ASSOCIATED DECOUPLING CAPACITOR - An integrated circuit includes a substrate and a circuit component (such as a MOS device or resistance) disposed at least partially within an active region of the substrate limited by an insulating region. A capacitive structure including a first electrode (for connection to a first potential such as ground) and a second electrode (for connection to a second potential such as a supply voltage) is provided in connection with the insulating region. One of the first and second electrodes is situated at least in part within the insulating region. The capacitive structure is thus configured in order to allow a reduction in compressive stresses within the active region. | 11-26-2015 |
| 20150348976 | SEMICONDUCTOR DEVICE HAVING JUNCTIONLESS VERTICAL GATE TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A junctionless vertical gate transistor includes an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region and a third impurity region sequentially formed over the first impurity region; gate electrodes coupled to sidewalls of the second impurity region; and bit lines arranged in a direction of intersecting with the gate electrodes and each contacting the first impurity region. The first to the third impurity regions include impurities of the same polarity. | 12-03-2015 |
| 20150357335 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Dishing of a plate of a capacitor is suppressed in a structure where the top of the plate is flush with a top of an interconnection. Double interlayer dielectric films are used to form a first recess and a second recess. The second recess has an opening on the bottom of the first recess. The first and second recesses are used to form a capacitor. The lower electrode of the capacitor has a bottom part along the bottom of the first recess. The lower electrode further includes a sidewall part having an upper end that projects along a side face of the second recess from the opening of the second recess up to a position between the opening of the second recess and a top of the upper interlayer dielectric film (the upper one of the double interlayer dielectric films). | 12-10-2015 |
| 20150357336 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - This semiconductor device is provided with: a silicon pillar that is provided by digging from a main surface of a semiconductor substrate; a first diffusion layer that is provided above the silicon pillar; a second diffusion layer, that is provided from a bottom portion of the silicon pillar to one region of the semiconductor substrate, said one region being continuous to the silicon pillar; a gate electrode in contact with at least a first side surface of the silicon pillar with a gate insulating film therebetween; a first embedding insulating film that surrounds the gate electrode; a second embedding insulating film in contact with a second side surface of the silicon pillar, said second side surface facing the first side surface of the silicon pillar; and a conductive layer, which is electrically connected to the second diffusion layer, and which is in contact with the second embedding insulating film at a position separated from the silicon pillar. | 12-10-2015 |
| 20150357337 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR - One semiconductor device includes first to third gate electrodes arranged inside a first active region and embedded in first to third trenches extending in a first direction, a first semiconductor pillar positioned between the first and second trenches, a second semiconductor pillar positioned between the second and third trenches, a first vertical transistor having the first and second gate electrodes as the double gate electrodes therefor, and a second vertical transistor having the second and third gate electrodes as the double gate electrodes therefor. The second gate electrode is shared by the first vertical transistor and the second vertical transistor. | 12-10-2015 |
| 20150357477 | BACKSIDE SOURCE-DRAIN CONTACT FOR INTEGRATED CIRCUIT TRANSISTOR DEVICES AND METHOD OF MAKING SAME - An integrated circuit transistor is formed on and in a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region epitaxially grown above the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate is preferably of the silicon on insulator (SOI) type. | 12-10-2015 |
| 20150372137 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device which is provided with: a gate insulating film which contains a high dielectric constant insulating material and has a first width; a lower gate electrode which has a second width that is narrower than the first width; an upper gate electrode which has a third width; and a first spacer layer which covers the lateral part of the upper gate electrode, a part of the lower part of the upper gate electrode, a part of the lower gate electrode, a part of the upper surface of the gate insulating film, said part of the upper surface being out of contact with the lower gate electrode, and the lateral surface of the gate insulating film. | 12-24-2015 |
| 20150380480 | SEMICONDUCTOR DEVICE - A semiconductor device having a capacitor which includes a first electrode electrically coupled to a transistor and a second electrode separate from the first electrode and covered with an interlayer insulating film, in which a plurality of coupling holes are formed in the interlayer insulating film and are in contact with the second electrode at the lower ends; and, when the capacitance of the second electrode is represented by C [nF] and the total area of the lower ends of the coupling holes is represented by A [μm | 12-31-2015 |
| 20160005742 | Semiconductor Constructions, and Semiconductor Processing Methods - Some embodiments include methods in which a pair of spaced-apart adjacent features is formed over a substrate. The features have silicon dioxide surfaces. Silicon nitride is deposited between the features. A first region of the silicon nitride is protected with a mask while a second region is not. The second region is removed to form an opening between the features. Some embodiments include semiconductor constructions that contain a pair of spaced-apart adjacent features. The features are lines extending along a first direction, and are spaced from one another by a trench. Alternating plugs and intervening materials are within the trench, with the plugs and intervening materials alternating along the first direction. The intervening materials consist of silicon nitride, and the plugs have lateral peripheries that directly contact silicon dioxide of the features, and that directly contact silicon nitride of the intervening regions. | 01-07-2016 |
| 20160013180 | FinFET CIRCUIT | 01-14-2016 |
| 20160020270 | METAL-INSULATOR-METAL CAPACITOR, ELECTRONIC DEVICE INCLUDING THE SAME, AND METHOD OF FABRICATING THE SAME - A metal-insulator-metal (MIM) capacitor that includes an insulation pattern on an underlying structure having a capacitor region and a peripheral region surrounding the capacitor region, the insulation pattern having a plurality contact holes that expose portions of the underlying structure in the capacitor region; a lower metal pattern in the capacitor region to cover a top surface of the insulation pattern, sidewalls of the insulation pattern corresponding to sidewalls of the contact holes, and the portions of the underlying structure exposed by the contact holes; a dielectric pattern that covers the lower metal pattern in the capacitor region and a top surface of the insulation pattern in the peripheral region; and an upper metal pattern on the dielectric pattern in the capacitor region and the peripheral region. | 01-21-2016 |
| 20160027786 | SEMICONDUCTOR DEVICES HAVING SELF-ALIGNED CONTACT PADS - A semiconductor device includes a substrate having a field area that defines active areas, gate trenches in the substrate and extending in a first direction, a buried gate in a respective gate trench, gate capping fences in a respective gate trench over a respective buried gate, the gate capping fences protruding from top surfaces of the active areas and extending in the first direction, bit line trenches in the gate capping fences, a respective bit line trench crossing the gate capping fences and extending in a second direction perpendicular to the first direction, an insulator structure on inner walls of a respective bit line trench, bit lines and bit line capping patterns stacked on the insulator structures in a respective bit line trench, contact pads self-aligned with the gate capping fences and on the substrate between the adjacent bit lines, and a lower electrode of a capacitor on a respective contact pad. | 01-28-2016 |
| 20160027814 | BACKPLANE FOR DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE BACKPLANE - A backplane for a display apparatus includes a substrate including a display area and a non-display area; a first transistor formed on the display area; and a second transistor formed on the non-display area, wherein a first active layer includes a first channel area, a first source area disposed on one side of the first channel area, a first drain area disposed on the other side of the first channel area, and a low-density doped area and a halo doped area that are adjacent to both ends of the first gate electrode, and the second active layer includes a second channel area, a second source area disposed on one side of the second channel area, and a second drain area disposed on the other side of the second channel area. | 01-28-2016 |
| 20160035729 | Meander Line Resistor Structure - A system comprises a first transistor comprising a first drain/source region and a second drain/source region, a second transistor comprising a third drain/source region and a fourth drain/source region, wherein the first transistor and the second transistor are separated by an isolation region, a first resistor formed by at least two vias, wherein a bottom via of the first resistor is in direct contact with the first drain/source region, a second resistor formed by at least two vias, wherein a bottom via of the second resistor is in direct contact with the second drain/source region, a bit line connected to the third drain/source region through a plurality of bit line contacts and a capacitor connected to the fourth drain/source region through a capacitor contact. | 02-04-2016 |
| 20160043069 | SWITCH CELL - A radio-frequency (RF) switch circuit is configured to maintain a disconnection or a connection between a node and an antenna terminal. The RF switch circuit comprises one or more switch cells. A switch cell comprises one or more transistors. The switch cell comprises one or more gate-drain capacitors. The switch cell comprises one or more source-drain capacitors. A gate-drain capacitor is coupled between a gate of a transistor and a drain of the transistor. A source-drain capacitor is coupled between a source of a transistor and a drain of the transistor. | 02-11-2016 |
| 20160043070 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - A semiconductor device in which a circuit and a power storage element are efficiently placed is provided. The semiconductor device includes a first transistor, a second transistor, and an electric double-layer capacitor. The first transistor, the second transistor, and the electric double-layer capacitor are provided over one substrate. A band gap of a semiconductor constituting a channel region of the second transistor is wider than a band gap of a semiconductor constituting a channel region of the first transistor. The electric double-layer capacitor includes a solid electrolyte. | 02-11-2016 |
| 20160043090 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided is a semiconductor device in which a voltage does not need to be applied to an element-isolating region that self-aligns with word lines (WL). This method for manufacturing said semiconductor device has the following steps: a step in which provisional active regions that are shaped such that active regions ( | 02-11-2016 |
| 20160043135 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a semiconductor memory device including a memory cell array and peripheral region includes a magnetoresistive element provided in the memory cell array, first contact under the magnetoresistive element and second contact in the peripheral region. A material of the first contact differs from that of the second contact. | 02-11-2016 |
| 20160064383 | SEMICONDUCTOR DEVICE - A semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limitation on the number of times of writing. In the semiconductor device, a plurality of memory cells each including a first transistor, a second transistor, and a capacitor is provided in matrix and a wiring (also called a bit line) for connecting one memory cell to another memory cell and a source or drain electrode of the first transistor are electrically connected to each other through a source or drain electrode of the second transistor. Accordingly, the number of wirings can be smaller than that in the case where the source or drain electrode of the first transistor and the source or drain electrode of the second transistor are connected to different wirings. Thus, the degree of integration of the semiconductor device can be increased. | 03-03-2016 |
| 20160071946 | ELECTRODE STRUCTURE, METHOD OF FABRICATING THE SAME, AND SEMICONDUCTOR DEVICE INCLUDING THE ELECTRODE STRUCTURE - An electrode structure is disclosed. The electrode structure includes a first polysilicon layer doped with resistance adjustment impurities; a second polysilicon layer for adjusting grains, formed in the first polysilicon layer and doped with grain adjustment impurities; an ohmic metal layer formed on the first and second polysilicon layers; a barrier metal layer formed on the ohmic metal layer; and a metal layer formed on the barrier metal layer. | 03-10-2016 |
| 20160079445 | CIRCUIT ARRANGEMENT AND METHOD OF FORMING A CIRCUIT ARRANGEMENT - A circuit arrangement may be provided. The circuit arrangement may include a semiconductor substrate including a first surface, a second surface opposite the first surface, and a first doped region of a first conductivity type extending from the first surface into the semiconductor substrate. The circuit arrangement may include at least one capacitor including a first electrode including a doped region of the first conductivity type extending from the second surface into the semiconductor substrate, a dielectric layer formed over the first electrode extending from the second surface away from the semiconductor substrate, and a second electrode formed over the dielectric layer opposite the first electrode. The circuit arrangement may further include at least one semiconductor device monolithically integrated in the semiconductor substrate. The first doped region of the first conductivity type may extend from the first surface into the semiconductor substrate to form an electrically conductive connection with the first electrode. | 03-17-2016 |
| 20160079446 | PUMPING CAPACITOR - A pumping capacitor is provided. The pumping capacitor includes a substrate, a P-type gate layer on the substrate, and a gate dielectric layer between the substrate and the P-type gate layer. The substrate includes an N-type well region and an N-type doping region in the N-type well region. | 03-17-2016 |
| 20160086937 | Integrated Switch Devices - Various aspects of the technology include an integrated circuit device comprising a compound semiconductor layer and a plurality of input, switch, and ground ohmic metal fingers fabricated on the compound semiconductor layer in a repeating sequence. A control gate may be disposed between each input finger and adjacent switch finger, and a sync gate may be disposed between each ground finger and adjacent switch finger. A sync gate and a control gate may be disposed adjacent each switch finger. The device further includes a plurality of control gate pads, each control gate pad at an end of two control gates, and a control gate pad at opposite ends of each control gate, and a plurality of sync gate pads, each sync gate pad at an end of two sync gates, and a sync gate pad at opposite ends of each sync gate. | 03-24-2016 |
| 20160086956 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - One semiconductor device has a groove formed on one surface of a semiconductor substrate, a gate electrode formed on the lower part of the groove with a gate insulation film interposed there between, a side wall insulation film made of a nitride film formed on the inner wall of the groove above the gate electrode, and an embedded insulation film formed in the groove enclosed by the side wall insulation film above the gate electrode. The side wall insulation film is shaped so that the width increases closer the bottom part of the groove. | 03-24-2016 |
| 20160093628 | MEMORY DEVICE, MEMORY CELL AND MEMORY CELL LAYOUT - A memory device includes at least one memory cell. The memory cell includes first and second transistors, and first and second capacitors. The first transistor is coupled to a source line. The second transistor is coupled to the first transistor and a bit line. The first capacitor is coupled to a word line and the second transistor. The second capacitor is coupled to the second transistor and an erase gate. | 03-31-2016 |
| 20160093709 | Transistor-Containing Constructions and Memory Arrays - Some embodiments include transistor-containing constructions having gate material within an opening in a semiconductor material and spaced from the semiconductor material by gate dielectric material. The opening has a wide lower region beneath a narrow upper region. A saddle region of the gate dielectric material extends outwardly from a bottom of the opening and is along the semiconductor material beneath the opening. A saddle region of the gate material extends outwardly from the bottom of the opening and is along the gate dielectric material beneath the opening. Source/drain regions are within the semiconductor material along sides of the gate material. Some embodiments include memory arrays. | 03-31-2016 |
| 20160099248 | SEMICONDUCTOR MEMORY DEVICE WITH IMPROVED ACTIVE AREA/WORD LINE LAYOUT - One semiconductor device includes a bit line extending in a straight line in an X direction, a first and a second horizontal active region extending in the X direction, and a sloped active region arranged between the first and the second horizontal regions and inclined with respect to the X direction, an active region arranged at the center of a bit line impurity diffusion region, a first word line arranged in the first horizontal active region segment, a second word line arranged in the second horizontal active region segment, and a third and a fourth word line arranged in the sloped active region segment next to each other with the bit line impurity diffusion region interposed therebetween. | 04-07-2016 |
| 20160111412 | ESD PROTECTION CIRCUIT - An electrostatic discharge (ESD) protection circuit may include an n-channel metal oxide semiconductor (NMOS) having a drain connected to a power terminal and a source and a gate connected to a ground terminal, a capacitor connected to the drain and a bulk terminal of the NMOS in parallel, and a plurality of series-connected diodes having anodes of one ends thereof connected to the bulk terminal and cathodes of the other ends thereof connected to the ground terminal. | 04-21-2016 |
| 20160111418 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, a transistor, a conductive contact and a capacitor. The transistor is formed on the semiconductor substrate, and the transistor includes a gate, a source and a drain. The conductive contact is formed on and in contact with at least one of the source and the drain. The capacitor includes a first electrode and a second electrode spaced apart from first electrode. At least one of the first and second electrodes extends on substantially the same level as the conductive contact or the gate. A method of forming the semiconductor device is provided as well. | 04-21-2016 |
| 20160126235 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A capacitive component region is formed below a temperature detecting diode or below a protective diode. In addition, the capacitive component region is formed below an anode metal wiring line connecting the temperature detecting diode and an anode electrode pad and below a cathode metal wiring line connecting the temperature detecting diode and a cathode electrode pad. The capacitive component region is an insulating film interposed between polysilicon layers. Specifically, a first insulating film, a polysilicon conductive layer, and a second insulating film are sequentially formed on a first main surface of a semiconductor substrate, and the temperature detecting diode, the protective diode, the anode metal wiring line, or the cathode metal wiring line is formed on the upper surface of the second insulating film. Therefore, it is possible to improve the static electricity resistance of the temperature detecting diode or the protective diode. | 05-05-2016 |
| 20160126246 | INTEGRATED CIRCUIT DEVICES HAVING METAL-INSULATOR-SILICON CONTACT AND METHODS OF FABRICATING THE SAME - Integrated circuit devices and methods of forming the devices are provided. The devices may include an active area, a gate electrode in the active area and a source/drain area adjacent a side of the gate electrode in the active area. The source/drain area may include a doped semiconductor material. The devices may also include an interlayer insulating layer on the active area, and the interlayer insulating layer may include a recess exposing an upper surface of the source/drain area. The devices may further include a conductive plug that is in the recess and includes a first metal and an insulating layer that is in the recess and includes a second metal. The insulating layer may be between the upper surface of the source/drain area and a lower surface of the conductive plug and may contact the doped semiconductor material. | 05-05-2016 |
| 20160133559 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a substrate comprising a plurality of layers formed thereon, at least a first device formed in one of the layers formed thereon, a drawn region enclosing the first device, and a plurality of dummy structures in another layer. The dummy structures are formed in a first region correspondingly outside of the drawing region and in a second region correspondingly inside of the drawing region. | 05-12-2016 |
| 20160148937 | SEMICONDUCTOR DEVICE - A semiconductor device includes a bit line structure on a substrate, the bit line structure having a polysilicon layer pattern doped with impurities, and a metal layer pattern on the polysilicon layer pattern, a first spacer surrounding and contacting a sidewall of the bit line structure, the first spacer having a constant thickness, and a capacitor contact structure on the substrate, an air gap being defined between the capacitor contact structure and the first spacer. | 05-26-2016 |
| 20160149057 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate including a first impurity diffusion region having a first doping concentration and at least one second impurity diffusion region having a second doping concentration different from the first doping concentration, the at least one second impurity region being surrounded by the first impurity diffusion region; at least one electrode facing the first impurity diffusion region and the at least one second impurity diffusion region; and at least one insulating layer between the first impurity diffusion region and the at least one electrode, and between the at least one second impurity diffusion region and the at least one electrode. | 05-26-2016 |
| 20160155744 | MEMORY DEVICE WITH MANUFACTURABLE CYLINDRICAL STORAGE NODE | 06-02-2016 |
| 20160155745 | Arrays Of Recessed Access Gate Lines, Arrays Of Conductive Lines,Arrays Of Recessed Access Gate Lines And Conductive Lines, And Memory Circuitry | 06-02-2016 |
| 20160155805 | SECONDARY USE OF ASPECT RATIO TRAPPING HOLES AS eDRAM STRUCTURE | 06-02-2016 |
| 20160172363 | Method of Forming Contacts for a Memory Device | 06-16-2016 |
| 20160190122 | Method for FinFET Integrated with Capacitor - A semiconductor structure comprises a semiconductor substrate and a shallow trench isolation (STI) feature over the substrate. The STI feature includes first and second portions. A top surface of the first portion is lower than a top surface of the second portion. The semiconductor structure further comprises fin active regions; conductive features on the fin active regions and the STI feature; and dielectric features separating the conductive features from the fin active regions. The semiconductor structure further comprises a first gate stack having a first one of the dielectric features and a first one of the conductive features overlying the first one of the dielectric features; and a second gate stack having a second one of the dielectric features and a second one of the conductive features overlying the second one of the dielectric features. | 06-30-2016 |
| 20160197082 | Low Leakage Non-Planar Access Transistor for Embedded Dynamic Random Access Memory (eDRAM) | 07-07-2016 |
| 20160204128 | COINTEGRATION OF BULK AND SOI SEMICONDUCTOR DEVICES | 07-14-2016 |
| 20190148360 | METHOD AND APPARATUS OF FORMING HIGH VOLTAGE VARACTOR AND VERTICAL TRANSISTOR ON A SUBSTRATE | 05-16-2019 |
| 20190148362 | METHOD AND APPARATUS OF FORMING HIGH VOLTAGE VARACTOR AND VERTICAL TRANSISTOR ON A SUBSTRATE | 05-16-2019 |
| 20190148368 | ISOLATION STRUCTURE FOR SEMICONDUCTOR DEVICE HAVING SELF-BIASING BURIED LAYER AND METHOD THEREFOR | 05-16-2019 |
| 20190148513 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | 05-16-2019 |
| 20220139836 | SEMICONDUCTOR MEMORY DEVICE INCLUDING WIRING CONTACT PLUGS - A semiconductor memory device includes a substrate including a cell area and a peripheral area, a plurality of capacitors including a plurality of lower electrodes arranged in the cell area, a plurality of capacitor dielectric layers covering the plurality of lower electrodes, and an upper electrode on the plurality of capacitor dielectric layers, an etch stop layer covering the upper electrode, a filling insulation layer covering the etch stop layer and arranged in the cell area and the peripheral area, a plurality of wiring lines on the filling insulation layer, and a first wiring contact plug electrically connecting at least one of the plurality of wiring lines to the upper electrode. The upper electrode includes a first upper electrode layer covering the plurality of capacitor dielectric layers and including a semiconductor material and a second upper electrode layer covering the first upper electrode layer and including a metallic material. | 05-05-2022 |
| 20220139902 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a substrate, a gate dielectric layer and a conductive layer that are stacked, and the gate dielectric layer is located between the substrate and the conductive layer. The substrate includes a semiconductor substrate and an insulating substrate which are arranged on the same layer. The conductive layer includes: a gate conductor layer, a projection of which on the substrate covers the semiconductor substrate, and an external connecting layer, a projection of which on the substrate covers the insulating substrate. A groove is formed on a bottom surface, towards the substrate, of the external connecting layer and the groove is filled with an insulator. | 05-05-2022 |
| 20220139918 | Novel Three-Dimensional DRAM Structures - Novel three-dimensional DRAM structures are disclosed, together with methods of making the same. Each DRAM cell comprises a vertical transistor and a storage capacitor stacked vertically. Storage capacitors are arranged in a rectangular pattern in the array of DRAM cells. This arrangement improves the area efficiency of storage capacitors over honeycomb type. A first embodiment of the present disclosure uses cup-shaped storage capacitors. The exterior of the cup as well as the interior may contribute to the capacitance. In a second embodiment, a single capacitor pillar forms the internal electrode of each storage capacitor. A third embodiment employs double-pillar storage capacitors. Common to all embodiments are options to dispose contact plugs between vertical transistors and storage capacitors, dispose an etch-stop layer over the gate of vertical transistors, dispose one or more mesh layers for storage capacitors, and widen semiconductor pillars within available space in bit-line direction. | 05-05-2022 |
| 20220139927 | SEMICONDUCTOR MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - The present disclosure provides a semiconductor memory device capable of improving reliability and performance. The semiconductor memory device comprises a substrate including a cell region and a peripheral region around the cell region, a cell region isolation film which defines the cell region, a bit line structure in the cell region, a first peripheral gate structure on the peripheral region of the substrate, the first peripheral gate structure comprising a first peripheral gate conduction film and a first peripheral capping film on the first peripheral gate conduction film, a peripheral interlayer insulating film around the first peripheral gate structure and an insertion interlayer insulating film on the peripheral interlayer insulating film and the first peripheral gate structure, and including a material different from the peripheral interlayer insulating film. An upper face of the peripheral interlayer insulating film is lower than an upper face of the first peripheral capping film. | 05-05-2022 |
