| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257133000 |
Combined with field effect transistor
| 861 |
| 257173000 |
Device protection (e.g., from overvoltage)
| 104 |
| 257119000 |
Bidirectional rectifier with control electrode (gate) (e.g., Triac)
| 74 |
| 257109000 |
Having only two terminals and no control electrode (gate), e.g., Shockley diode
| 44 |
| 257146000 |
Combined with other solid-state active device in integrated structure
| 17 |
| 257147000 |
With extended latchup current level (e.g., gate turn off "GTO" device)
| 15 |
| 257168000 |
With means to increase breakdown voltage
| 7 |
| 257132000 |
Five or more layer unidirectional structure
| 7 |
| 257162000 |
Lateral structure
| 7 |
| 257113000 |
With light activation
| 6 |
| 257163000 |
Emitter region feature | 4 |
| 20100052012 | SEMICONDUCTOR DEVICE - The first base electrodes and the first emitter electrodes are all formed like strips, and are alternately arranged in parallel, and the area of the second emitter electrode is expanded to be larger than that of the second base electrode. With this, the number of current paths increases in each of which a current is pulled up almost straight from the emitter region to the second emitter electrode through the first emitter electrodes, thereby preventing the current densities of the entire chip from becoming uneven. | 03-04-2010 |
| 20110127576 | Bipolar Power Semiconductor Component Comprising a P-type Emitter and More Highly Doped Zones in the P-type Emitter, and Production Method - A bipolar power semiconductor component configured as an IGBT includes a semiconductor body, in which a p-doped emitter, an n-doped base, a p-doped base and an n-doped main emitter are arranged successively in a vertical direction. The p-doped emitter has a number of heavily p-doped zones having a locally increased p-type doping. | 06-02-2011 |
| 20130153958 | SEMICONDUCTOR SWITCHING DEVICE - A semiconductor switching device includes a package, and a semiconductor switching element provided in the package and having a collector electrode and an emitter electrode. A main collector terminal and a main emitter terminal reflect voltage drop generated during application of current by a floating component in the package. A second collector terminal and a second emitter terminal detect a voltage between the collector electrode and the emitter electrode without reflecting the voltage drop. A third emitter terminal is arranged close to the second emitter terminal, and detects the voltage drop generated between the main emitter terminal and the second emitter terminal. | 06-20-2013 |
| 20160064484 | LATERAL BIPOLAR JUNCTION TRANSISTORS ON A SILICON-ON-INSULATOR SUBSTRATE WITH A THIN DEVICE LAYER THICKNESS - Methods of forming bipolar device structures and bipolar device structures. An opening may be formed in a device layer of a silicon-on-insulator substrate that extends to a buried insulator layer of the silicon-on-insulator substrate. An intrinsic base layer may be grown within the device layer opening by lateral growth on opposite first and second sidewalls of the device layer bordering the opening. A first collector of a first bipolar junction transistor of the device structure may be formed at a first spacing from the first sidewall. A second collector of a second bipolar junction transistor of the device structure may be formed at a second spacing from the second sidewall. An emitter, which is shared by the first bipolar junction transistor and the second bipolar transistor, is formed inside the opening. Portions of the intrinsic base layer may supply respective intrinsic bases for the first and second bipolar junction transistors. | 03-03-2016 |
| 257155000 |
With switching speed enhancement means (e.g., Schottky contact) | 4 |
| 20110147793 | SiGe HETEROJUNCTION BIPOLAR TRANSISTOR MULTI-FINGER STRUCTURE - The present invention provides a multi-finger structure of a SiGe heterojunction bipolar transistor (HBT). It is consisted of plural SiGe HBT single cells. The multi-finger structure is in a form of C/BEBC/BEBC/.../C, wherein, C, B, E respectively stands for collector, base and emitter; CBEBC stands for a SiGe HBT single cell. The collector region is consisted of an n type ion implanted layer inside the active region. The bottom of the implanted layer is connected to two n type pseudo buried layers. The two pseudo buried layers are formed through implantation to the bottom of the shallow trenches that surround the collector active region. Two collectors are picked up by deep trench contact through the field oxide above the two pseudo buried layers. The present invention can reduce junction capacitance, decrease collector electrode output resistance, and improve device frequency characteristics. | 06-23-2011 |
| 20130082302 | SEMICONDUCTOR DEVICE - A semiconductor device comprises: a substrate having a first and second surface; trenches provided on the second surface; a gate electrode provided in each trench; a first-conductive-type emitter layer provided on the second surface and contacting with the trenches; and an emitter electrode provided on the second surface to extend in a longitudinal direction of the trenches, the emitter electrode having a non-contact portion partially provided in the first-conductive-type emitter layer. | 04-04-2013 |
| 20130161691 | SEMICONDUCTOR DEVICE - A semiconductor device contains a semiconductor substrate, a cathode, an anode, and a gate electrode. The semiconductor device has a cathode segment disposed in a portion corresponding to at least the cathode, an anode segment disposed in a portion corresponding to the anode, a plurality of embedded segments disposed in a portion closer to the cathode segment than to the anode segment, a takeoff segment disposed between the gate electrode and the embedded segments to electrically connect the gate electrode to the embedded segments, and a channel segment disposed between the adjacent embedded segments. | 06-27-2013 |
| 20140209973 | Reverse Blocking Semiconductor Device, Semiconductor Device with Local Emitter Efficiency Modification and Method of Manufacturing a Reverse Blocking Semiconductor Device - A reverse blocking semiconductor device includes a base region of a first conductivity type and a body region of a second, complementary conductivity type, wherein the base and body regions form a pn junction. Between the base region and a collector electrode an emitter layer is arranged that includes emitter zones of the second conductivity type and at least one channel of the first conductivity type. The channels extend through the emitter layer between the base region and the collector electrode and reduce the leakage current in a forward blocking state. | 07-31-2014 |
| 257157000 |
With integrated trigger signal amplification means (e.g., amplified gate, "pilot thyristor", etc.) | 3 |
| 20090057714 | THYRISTOR AND METHODS FOR PRODUCING A THYRISTOR - A thyristor having a semiconductor body in which a p-doped emitter, an n-doped base, a p-doped base and an n-doped main emitter are arranged successively in a vertical direction starting from a rear face toward a front face. For buffering of the transient heating, a metallization is applied to the front face and/or to the rear face and includes at least one first section which has an area-specific heat capacity of more than 50 J·K | 03-05-2009 |
| 20120043583 | LOW LEAKAGE, LOW CAPACITANCE ELECTROSTATIC DISCHARGE (ESD) SILICON CONTROLLED RECITIFER (SCR), METHODS OF MANUFACTURE AND DESIGN STRUCTURE - A low leakage, low capacitance diode based triggered electrostatic discharge (ESD) silicon controlled rectifiers (SCR), methods of manufacture and design structure are provided. The method includes providing a silicon film on an insulator layer. The method further includes forming isolation regions which extend from an upper side of the silicon layer to the insulator layer. The method further includes forming one or more diodes in the silicon layer, including a p+ region and an n+ region formed in a well bordered by the isolation regions. The isolation regions isolate the one or more diodes in a vertical direction and the insulator layer isolates the one or more diodes from an underlying P or N type substrate, in a horizontal direction. | 02-23-2012 |
| 20130105857 | PHASE CONTROL THYRISTOR WITH IMPROVED PATTERN OF LOCAL EMITTER SHORTS DOTS | 05-02-2013 |
| 257154000 |
With resistive region connecting separate sections of device | 3 |
| 20110204415 | HIGH HOLDING VOLTAGE DEVICE - A high holding voltage (HV) electrostatic discharge (ESD) protection circuit comprises a silicon controlled rectifier (SCR) device and compensation regions located within the length between the anode and cathode (LAC) of the SCR device which increase the holding voltage of the SCR device. The compensation regions may introduce negative feedback mechanisms into the SCR device which may influence the loop gain of the SCR and cause it to reach regenerative feedback at a higher holding voltage. | 08-25-2011 |
| 20150048415 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate, a first doping region, a first well, a resistor element, and a first, a second, and a third heavily doping regions. The first well and the third heavily doping region are disposed in the first doping region, which is disposed on the substrate. The first heavily doping region and the second heavily doping region, which are separated from each other, are disposed in the first well. The second and the third heavily doping regions are electrically connected via the resistor element. Each of the substrate, the first well, and the second heavily doping region has a first type doping. Each of the first doping region, the first heavily doping region, and the third heavily doping region has a second type doping, complementary to the first type doping. | 02-19-2015 |
| 20150084094 | SCR COMPONENT WITH TEMPERATURE-STABLE CHARACTERISTICS - An SCR-type component of vertical structure has a main upper electrode formed on a silicon region of a first conductivity type which is formed in a silicon layer of a second conductivity type. The silicon region is interrupted in first areas where the material of the silicon layer comes into contact with the upper electrode, and is further interrupted in second areas filled with resistive porous silicon extending between the silicon layer and the main upper electrode. | 03-26-2015 |
| 257175000 |
With means to control triggering (e.g., gate electrode configuration, Zener diode firing, dV/Dt control, transient control by ferrite bead, etc.) | 3 |
| 20120012892 | HIGH DENSITY THYRISTOR RANDOM ACCESS MEMORY DEVICE AND METHOD - Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided allow trace wiring in a memory array to be formed on or near a surface of a memory device. | 01-19-2012 |
| 20130009208 | HIGH DENSITY THYRISTOR RANDOM ACCESS MEMORY DEVICE AND METHOD - Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided allow trace wiring in a memory array to be formed on or near a surface of a memory device. | 01-10-2013 |
| 20130313607 | Silicon Controlled Rectifier With Stress-Enhanced Adjustable Trigger Voltage - Device structures, fabrication methods, operating methods, and design structures for a silicon controlled rectifier. The method includes applying a mechanical stress to a region of a silicon controlled rectifier (SCR) at a level sufficient to modulate a trigger current of the SCR. The device and design structures include a SCR with an anode, a cathode, a first region, and a second region of opposite conductivity type to the first region. The first and second regions of the SCR are disposed in a current-carrying path between the anode and cathode of the SCR. A layer is positioned on a top surface of a semiconductor substrate relative to the first region and configured to cause a mechanical stress in the first region of the SCR at a level sufficient to modulate a trigger current of the SCR. | 11-28-2013 |
| 257172000 |
With means to lower "ON" voltage drop | 2 |
| 20080230801 | TRENCH TYPE POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A method for manufacturing a trench type power semiconductor device is provided. The method includes: forming a first silicon oxide film on a silicon substrate; forming a thermal oxidation-resistant film on the first silicon oxide film; forming an opening in the first silicon oxide film and the thermal oxidation-resistant film; forming a sidewall on an inner side surface of the opening; forming a trench in the silicon substrate by etching the silicon substrate using the first silicon oxide film, the thermal oxidation-resistant film, and the sidewall as a mask; removing the sidewall; forming a second silicon oxide film thicker than the first silicon oxide film on an inner surface of the trench by applying thermal oxidation to the silicon substrate; burying a trench gate electrode in the trench; removing the thermal oxidation-resistant film; and introducing impurities into at least part of a region of the silicon substrate between the trenches. | 09-25-2008 |
| 20130207159 | BIPOLAR NON-PUNCH-THROUGH POWER SEMICONDUCTOR DEVICE - An exemplary bipolar non-punch-through power semiconductor device includes a semiconductor wafer and a first electrical contact on a first main side and a second electrical contact on a second main side. The wafer has an inner region with a wafer thickness and a termination region that surrounds the inner region, such that the wafer thickness is reduced at least on the first main side with a negative bevel. The semiconductor wafer has at least a two-layer structure with layers of different conductivity types, which can include a drift layer of a first conductivity type, a first layer of a second conductivity type at a first layer depth and directly connected to the drift layer on the first main side and contacting the first electrical contact, and a second layer of the second conductivity type arranged in the termination region on the first main side up to a second layer depth. | 08-15-2013 |
| 257108000 |
Controlled by nonelectrical, nonoptical external signal (e.g., magnetic field, pressure, thermal) | 1 |
| 20090114945 | SPINTRONICS COMPONENTS WITHOUT NON-MAGNETIC INTERPLAYERS - A spintronics element comprises two ferromagnetic layers without a non-magnetic interlayer between them. The two ferromagnetic layers may be independently switched by various means such as but not limited to applying one or more external magnetic fields, and/or employing current induced switching, and/or applying optical spin-pumping. | 05-07-2009 |
| 257177000 |
With housing or external electrode | 1 |
| 20090095979 | Power Module - A power module includes a substrate having first and second main substrate surfaces; a semiconductor device disposed on the first main substrate surface, and having a first main surface on which a first main electrode is formed, and a second main surface on which a second main electrode in contact with the first main substrate surface is formed; a heat conduction portion disposed on the first main substrate surface in a residual region of a region on which the semiconductor device is disposed; and an upper cooling portion disposed on the heat conduction portion. | 04-16-2009 |
| Entries |
| Document | Title | Date |
|---|
| 20080308837 | VERTICAL CURRENT CONTROLLED SILICON ON INSULATOR (SOI) DEVICE SUCH AS A SILICON CONTROLLED RECTIFIER AND METHOD OF FORMING VERTICAL SOI CURRENT CONTROLLED DEVICES - A Silicon on Insulator (SOI) Integrated Circuit (IC) chip with devices such as a vertical Silicon Controlled Rectifier (SCR), vertical bipolar transistors, a vertical capacitor, a resistor and/or a vertical pinch resistor and method of making the device(s). The devices are formed in a seed hole through the SOI surface layer and insulator layer to the substrate. A buried diffusion, e.g., N-type, is formed through the seed hole in the substrate. A doped epitaxial layer is formed on the buried diffusion and may include multiple doped layers, e.g., a P-type layer and an N-type layer. Polysilicon, e.g., P-type, may be formed on the doped epitaxial layer. Contacts to the buried diffusion are formed in a contact liner. | 12-18-2008 |
| 20100270584 | Semiconductor Switching Device with Gate Connection - The present disclosure provides a semiconductor switching device including a substrate having deposited thereon a cathode, an anode and a gate of the semiconductor switching device, and a connection means for electrically connecting the cathode in the gate of the semiconductor switching device to an external circuit unit. The connection includes a cathode-gate connection unit having a coaxial structure including a gate conductor and a cathode conductor for electrically connecting the cathode and the gate of the semiconductor switching device to the external circuit unit. | 10-28-2010 |
| 20110316042 | THYRISTOR RANDOM ACCESS MEMORY DEVICE AND METHOD - Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided reduce a need for manufacturing methods such as deep dopant implants. | 12-29-2011 |
| 20120080716 | INITIAL-ON SCR DEVICE FOR ON-CHIP ESD PROTECTION - A semiconductor device for electrostatic discharge (ESD) protection comprises a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor. | 04-05-2012 |
| 20130285111 | DIODE-TRIGGERED SILICON CONTROLLED RECTIFIER WITH AN INTEGRATED DIODE - Device structures, design structures, and fabrication methods for a silicon controlled rectifier. A well of a first conductivity type is formed in a device region, which may be defined from a device layer of a semiconductor-on-insulator substrate. A doped region of a second conductivity type is formed in the well. A cathode of a silicon controlled rectifier and a cathode of a diode are formed in the device region. The silicon controlled rectifier comprises a first portion of the well and an anode comprised of a first portion of the doped region. The diode comprises a second portion of the well and an anode comprised of a second portion of the doped region. | 10-31-2013 |
| 20130320395 | HIGH-VOLTAGE VERTICAL POWER COMPONENT - A vertical power component including: a silicon substrate of a first conductivity type; on the side of a lower surface of the substrate supporting a single electrode, a lower layer of the second conductivity type; and on the side of an upper surface of the substrate supporting a conduction electrode and a gate electrode, an upper region of the second conductivity type, wherein the component periphery includes, on the lower surface side, a porous silicon insulating ring penetrating into the substrate down to a depth greater than that of the lower layer. | 12-05-2013 |
| 20140015001 | THYRISTOR RANDOM ACCESS MEMORY DEVICE AND METHOD - Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided reduce a need for manufacturing methods such as deep dopant implants. | 01-16-2014 |
| 20140110751 | THYRISTOR AND METHOD FOR THE SAME - A thyristor includes a base region, a pair of first doping regions, at least one second doping region, at least one third doping region, and a pair of metal layers. The first doping regions are formed in two opposite sides of the base region and touch the base region. The second doping region is formed between the base region and one of the first doping regions. The second doping region touches the base region and the first doping region. The third doping region is formed in one of the first doping regions and touches the first doping region. The type of the first doping region is different from the types of the second doping region, the third doping region, and the base region. The metal layers touch the first doping regions respectively. The first doping regions and the third doping region are located between the metal layers. | 04-24-2014 |
| 20140145238 | SEMICONDUCTOR DEVICES AND FABRICATION METHODS - Methods of fabricating vertical devices are described, along with apparatuses and systems that include them. In one such method, a vertical device is formed at least partially in a void in a first dielectric material and a second dielectric material. Additional embodiments are also described. | 05-29-2014 |
| 20150333068 | THYRISTOR RANDOM ACCESS MEMORY - Devices and methods for forming a device are presented. The device includes a substrate having a well of a first polarity type and a thyristor-based memory cell. The thyristor-based memory cell includes at least a first region of a second polarity type adjacent to the well, a gate which serves as a second word line disposed on the substrate, at least a first layer of the first polarity type disposed adjacent to the first region of the second polarity type and adjacent to the gate, and at least a heavily doped first layer of the second polarity type disposed on the first layer of the first polarity type and adjacent to the gate. At least the heavily doped first layer of the second polarity type is self-aligned with side of the gate. | 11-19-2015 |
| 20160141416 | SEMICONDUCTOR DEVICES AND FABRICATION METHODS - Methods of fabricating vertical devices are described, along with apparatuses and systems that include them. In one such method, a vertical device is formed at least partially in a void in a first dielectric material and a second dielectric material. Additional embodiments are also described. | 05-19-2016 |
