Class / Patent application number | Description | Number of patent applications / Date published |
257147000 | With extended latchup current level (e.g., gate turn off "GTO" device) | 15 |
20090152587 | DEEP GUARD REGIONS FOR REDUCING LATCH-UP IN ELECTRONICS DEVICES - An embodiment of an integrated circuit includes a semiconductor layer, a well, first and second source/drain regions, and a guard region. The semiconductor layer has a first conductivity, and the well is disposed in the layer and has a second conductivity. The first source/drain region is formed in the well and has the first conductivity, and the second source/drain region is formed in the layer outside of the well and has the second conductivity. The guard region is disposed in the layer between the well and the second source/drain region and has the second conductivity. The guard region may prevent latch up by inhibiting the triggering of a silicon-controlled rectifier (SCR) having one of the first and second source/drain regions as an anode and the other of the first and second source/drain regions as a cathode. | 06-18-2009 |
20090309132 | INTEGRATED LATCH-UP FREE INSULATED GATE BIPOLAR TRANSISTOR - A lateral Insulated Gate Bipolar Transistor (LIGBT) includes a semiconductor substrate and an anode region in the semiconductor substrate. A cathode region of a first conductivity type in the substrate is laterally spaced from the anode region, and a cathode region of a second conductivity type in the substrate is located proximate to and on a side of the cathode region of the first conductivity type opposite from the anode region. A drift region in the semiconductor substrate extends between the anode region and the cathode region of the first conductivity type. An insulated gate is operatively coupled to the cathode region of the first conductivity type and is located on a side of the cathode region of the first conductivity type opposite from the anode region. An insulating spacer overlies the cathode region of the second conductivity type. The lateral dimensions of the insulating spacer and the cathode region of the second conductivity type are substantially equal and substantially smaller than the lateral dimension of the cathode region of the first conductivity type. | 12-17-2009 |
20110018029 | SEMICONDUCTOR DEVICE HAVING A FLOATING SEMICONDUCTOR ZONE - A semiconductor device includes a first trench and a second trench extending into a semiconductor body from a surface. A body region of a first conductivity type adjoins a first sidewall of the first trench and a first sidewall of the second trench, the body region including a channel portion adjoining to a source structure and being configured to be controlled in its conductivity by a gate structure. The channel portion is formed at the first sidewall of the second trench and is not formed at the first sidewall of the first trench. An electrically floating semiconductor zone of the first conductivity type adjoins the first trench and has a bottom side located deeper within the semiconductor body than the bottom side of the body region. | 01-27-2011 |
20110049564 | Integrated schottky diode in high voltage semiconductor device - This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area. The method comprises the steps of a) growing and patterning a field oxide layer in the termination area and also in the active cell area on a top surface of the semiconductor substrate b) depositing and patterning a polysilicon layer on the top surface of the semiconductor substrate at a gap distance away from the field oxide layer; c) performing a blank body dopant implant to form body dopant regions in the semiconductor substrate substantially aligned with the gap area followed by diffusing the body dopant regions into body regions in the semiconductor substrate; d) implanting high concentration body-dopant regions encompassed in and having a higher dopant concentration than the body regions and e) applying a source mask to implant source regions having a conductivity opposite to the body region with the source regions encompassed in the body regions and surrounded by the high concentration body-dopant regions. | 03-03-2011 |
20110073906 | High voltage MOSFET diode reverse recovery by minimizing P-body charges - This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area. The method comprises the steps of a) growing and patterning a field oxide layer in the termination area and also in the active cell area on a top surface of the semiconductor substrate b) depositing and patterning a polysilicon layer on the top surface of the semiconductor substrate at a gap distance away from the field oxide layer; c) performing a blank body dopant implant to form body dopant regions in the semiconductor substrate substantially aligned with the gap area followed by diffusing the body dopant regions into body regions in the semiconductor substrate; d) implanting high concentration body-dopant regions encompassed in and having a higher dopant concentration than the body regions e) applying a source mask to implant source regions having a conductivity opposite to the body region with the source regions encompassed in the body regions and surrounded by the high concentration body-dopant regions; and f) etching contact trenches into the source, body contact, and body regions. | 03-31-2011 |
20130001640 | SEMICONDUCTOR DEVICE HAVING A FLOATING SEMICONDUCTOR ZONE - A semiconductor device includes a first trench and a second trench extending into a semiconductor body from a surface. A body region of a first conductivity type adjoins a first sidewall of the first trench and a first sidewall of the second trench, the body region including a channel portion adjoining to a source structure and being configured to be controlled in its conductivity by a gate structure. The channel portion is formed at the first sidewall of the second trench and is not formed at the first sidewall of the first trench. An electrically floating semiconductor zone of the first conductivity type adjoins the first trench and has a bottom side located deeper within the semiconductor body than the bottom side of the body region. | 01-03-2013 |
20130153957 | SILICON-CONTROLLED-RECTIFIER WITH ADJUSTABLE HOLDING VOLTAGE - A silicon-controlled-rectifier (SCR) with adjustable holding voltage is disclosed, which comprises a heavily doped semiconductor layer and an epitaxial layer formed on the heavily doped semiconductor layer. A first N-well having a first P-heavily doped area is formed in the epitaxial layer. A second N-well or a first P-well is formed in the epitaxial layer. When the second N-well is formed in the epitaxial layer, a P-doped area is located between the first N-well and the second N-well. Besides, a first N-heavily doped area is formed in the second N-well or the first P-well. At least one deep isolation trench is formed in the epitaxial layer and located between the first P-heavily doped area and the first N-heavily doped area. A distance between the deep isolation trench and the heavily doped semiconductor layer is larger than zero. | 06-20-2013 |
20130161690 | SEMICONDUCTOR DEVICE - A semiconductor device contains a first conductive type semiconductor substrate, at least one cathode formed on one surface of the semiconductor substrate, an anode formed on the other surface of the semiconductor substrate, and a gate electrode electrically insulated from the cathode, formed on the one surface of the semiconductor substrate to control current conduction between the cathode and the anode. The semiconductor substrate has a thickness of less than 460 rm. | 06-27-2013 |
20130320398 | LATCH-UP ROBUST SCR-BASED DEVICES - An approach for providing a latch-up robust silicon control rectifier (SCR) is disclosed. Embodiments include providing a first N+ region and a first P+ region in a substrate for a SCR; providing first and second n-well regions in the substrate proximate the first N+ and P+ regions; providing a second N+ region in the first n-well region, and a second P+ region in the second n-well region; and coupling the first N+ and P+ regions to a ground rail, the second N+ region to a power rail, and the second P+ region to an I/O pad. | 12-05-2013 |
20130341675 | LATCH-UP FREE ESD PROTECTION - An ESD module having a first portion (FP) and a second portion (SP) in a substrate is presented. The FP includes a FP well of a second polarity type and first and second FP contact regions. The first FP contact region is of a first polarity type and the second FP contact region is of a second polarity type. The SP includes a SP well of a first polarity type and first and second SP contact regions. The first SP contact region is of a first polarity type and the second SP contact region is of a second polarity type. An intermediate portion (IP) is disposed in the substrate between the FP and SP in the substrate. The IP includes a well of the second polarity type. The IP increases trigger current and holding voltage of the module to prevent latch up during normal device operation. | 12-26-2013 |
20150340481 | LATCH-UP ROBUST SCR-BASED DEVICES - An approach for providing a latch-up robust silicon control rectifier (SCR) is disclosed. Embodiments include providing a first N+ region and a first P+ region in a substrate for a SCR; providing first and second n-well regions in the substrate proximate the first N+ and P+ regions; providing a second N+ region in the first n-well region, and a second P+ region in the second n-well region; and coupling the first N+ and P+ regions to a ground rail, the second N+ region to a power rail, and the second P+ region to an I/O pad. | 11-26-2015 |
257148000 | Having impurity doping for gain reduction | 3 |
20130341676 | Methods and Apparatus for Increased Holding Voltage in Silicon Controlled Rectifiers for ESD Protection - Methods and apparatus for increased holding voltage SCRs. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of the first conductivity type; a second well of a second conductivity type adjacent to the first well, an intersection of the first well and the second well forming a p-n junction; a first diffused region of the first conductivity type formed at the first well and coupled to a ground terminal; a first diffused region of the second conductivity type formed at the first well; a second diffused region of the first conductivity type formed at the second well and coupled to a pad terminal; a second diffused region of the second conductivity type formed in the second well; and a Schottky junction formed adjacent to the first diffused region of the second conductivity type coupled to a ground terminal. Methods for forming devices are disclosed. | 12-26-2013 |
20150294967 | ESD PROTECTION CIRCUIT WITH ISOLATED SCR FOR NEGATIVE VOLTAGE OPERATION - A semiconductor controlled rectifier (FIG. | 10-15-2015 |
20160013302 | REVERSE-CONDUCTING POWER SEMICONDUCTOR DEVICE | 01-14-2016 |
257150000 | With specified housing or external terminal | 1 |
20120326208 | PRESSURE CONTACT SEMICONDUCTOR DEVICE - A pressure contact semiconductor device includes a cathode post electrode and a gate electrode formed on a top surface of a substrate, an anode post electrode formed on a bottom surface thereof, a circuit substrate, a cathode flange overlapping the cathode post electrode and connected to the circuit substrate, a cathode fin electrode overlapping the cathode flange, an anode fin electrode underlapping and the anode post electrode, a gate flange connected to both the gate electrode and the circuit substrate, a securing member having a parallel portion parallel to the circuit substrate and a perpendicular portion perpendicular to the circuit substrate, the perpendicular portion being secured to a side of the cathode fin electrode, and a spacer formed from plate material and secured at the top to the parallel portion of the securing member and at the bottom to the circuit substrate. | 12-27-2012 |