Class / Patent application number | Description | Number of patent applications / Date published |
216018000 | Filling or coating of groove or through hole with a conductor to form an electrical interconnection | 49 |
20080264899 | INTERCONNECT STRUCTURE WITH STRESS BUFFERING ABILITY AND THE MANUFACTURING METHOD THEREOF - An interconnect structure with stress buffering ability is disclosed, which comprises: a first surface, connected to a device selected form the group consisting of a substrate and an electronic device; a second surface, connected to a device selected form the group consisting of the substrate and the electronic device; a supporting part, sandwiched between and interconnecting the first and the second surfaces while enabling the areas of the two ends of the supporting part to be small than those of the first and the second surfaces in respective; and a buffer, arranged surrounding the supporting part for absorbing and buffering stresses. | 10-30-2008 |
20080283491 | Fabrication method of printed circuit board and printed circuit board machining apparatus - There is provided a printed circuit board whose peel strength is large and a printed circuit board fabrication method and a printed circuit board machining apparatus that allow a fabrication time and a fabrication cost to be reduced. The fabrication method of the printed circuit board comprises steps of forming a resist layer on a surface of the printed circuit board whose surface is made of an insulator, of forming a hole that is connected from the surface of the resist layer to a conductor pattern of an inner layer and a hole and grooves having a depth not connected with the conductor layer of the inner layer by irradiating lasers, of filling a conductive material into the holes and the grooves to form a conductor pattern and of removing the resist layer to project a portion of the conductor pattern out of the surface of the insulating layer. | 11-20-2008 |
20080296253 | Method and apparatus to change solder pad size using a differential pad plating - A method of manufacturing an interposer is provided, including the steps of providing a sheet with a copper layer and polyimide layer, laser drilling holes in the polyimide layer down to the copper layer, filling the holes with copper and extending the copper above the polyimide layer to define caps, removing portions of the copper layer to form conductive pads, and filling gaps between the conductive pads with an insulator, wherein individual conductive pads are in electrical contact with corresponding individual caps. | 12-04-2008 |
20080314867 | METHOD OF MAKING DEMOUNTABLE INTERCONNECT STRUCTURE - A method for making an interconnect structure includes applying a first metal layer to an electronic device, wherein the electronic device comprises at least one I/O contact and the first metal layer is located on a surface of the I/O contact; applying a removable layer to the electronic device. The removable layer is adjacent to the first metal layer. An adhesive layer is applied to the electronic device or to a base insulative layer. The electronic device is secured to the base insulative layer using the adhesive layer. The first metal layer and removable layer are disposed between the electronic device and the base insulative layer. | 12-25-2008 |
20090014411 | Fabricating method for multilayer printed circuit board - A fabrication method for a multilayer printed circuit board includes: forming a first circuit-forming pattern and a first insulation layer, into which the first circuit-forming pattern is inserted, on a first carrier; forming inner circuit patterns and inner insulation layers over the first insulation layer, and forming inner vias connecting the inner circuit patterns positioned on different insulation layers; forming a second circuit-forming pattern on a second carrier and inserting the second circuit-forming pattern into a second insulation layer on an outermost side; removing the first carrier and the second carrier; forming circuit-forming grooves by removing the first circuit-forming pattern and the second circuit-forming pattern, and forming via-forming indentations connected with the circuit-forming grooves; and forming outer circuit patterns and outer vias by filling the circuit-forming grooves and the via-forming indentations with a conductive material. This can provide a thin printed circuit board having high reliability and fine-lined circuits. | 01-15-2009 |
20090026169 | Printed circuit board manufacturing system and manufacturing method thereof - A printed circuit board manufacturing system and a manufacturing method thereof are disclosed. A method of manufacturing printed circuit board, comprising: providing a substrate that comprises a pad and an insulation layer covering the pad; acquiring an image of the substrate; acquiring location information of the pad by analyzing the image of the substrate; forming a via hole by removing a part of the insulation layer that corresponds the location information of the pad; and forming a via by filling the via hole with a conductive material, provides improved process conformity, even if the substrate has partial or nonlinear deformation, by considering the location information of the pad in the via hole forming. The improved conformity may allow more flexibility to substrate design and more integrity for circuitries on printed circuit board. | 01-29-2009 |
20090057265 | Method of manufacturing multilayer printed circuit board - In a method of manufacturing a multilayer printed circuit board, a plurality of insulating substrates each having a first surface and a second surface is prepared. A circuit pattern is formed on each of the first surfaces of the insulating substrates. A plurality of via holes is provided so as to extend through respective ones of the insulating substrates from a side of the second surfaces in such a manner that the via holes reach corresponding ones of the circuit patterns. Ones of a plurality of sintered bodies made of conductive particles is inserted into corresponding ones of the via holes and is fixed in the via holes. The insulating substrates are stacked so that the circuit patterns are electrically coupled through the sintered bodies. | 03-05-2009 |
20090084755 | METHOD FOR FORMING MICRO-VIAS ON A SUBSTRATE - A method for forming at least one micro-via on a substrate is disclosed. The method comprises drilling at least one hole in a substrate by using a first laser beam. The first laser beam has an energy distribution, which is more at edges of the first laser beam than at the center of the first laser beam. The method further comprises forming at least one blank pattern on a top surface of the substrate and around an outer periphery of the at least one hole by removing at least a portion of the substrate by using a second laser beam. At least one blank pattern of the plurality of blank pattern corresponds to pad of the at least one micro-via. Thereafter, the method comprises filling the plurality of blank patterns and the at least one micro-via with a conductive material to form at least micro-via. | 04-02-2009 |
20090090692 | Methods of Processing Substrates and Methods of Forming Conductive Connections to Substrates - Embodiments disclosed include methods of processing substrates, including methods of forming conductive connections to substrates. In one embodiment, a method of processing a substrate includes forming a material to be etched over a first material of a substrate. The material to be etched and the first material are of different compositions. The material to be etched is etched in a dry etch chamber to expose the first material. After the etching, the first material is contacted with a non-oxygen-containing gas in situ within the dry etch chamber effective to form a second material physically contacting onto the first material. The second material comprises a component of the first material and a component of the gas. In one embodiment, the first material is contacted with a gas that may or may not include oxygen in situ within the dry etch chamber effective to form a conductive second material. | 04-09-2009 |
20090159561 | INTEGRATED DEVICE TECHNOLOGY USING A BURIED POWER BUSS FOR MAJOR DEVICE AND CIRCUIT ADVANTAGES - A method for providing an improved integrated circuit device is disclosed. The method comprises the steps of providing active and passive areas in the substrate, providing a plurality of slots in the substrate after providing the active and passive areas, and oxidizing the plurality of slots. The method further comprises providing metal in each of the plurality of slots, providing a dielectric coating over the slots, and providing etched contacts in select areas remote from the location of the slots. Additionally, the method provides an additional layer of metal that interconnects the contacts and the buried metal in select areas where contacts were etched, resulting in metal of three levels; and provides one level of the metal is surface and two levels of the metal that comprise a buried power buss (BPB). | 06-25-2009 |
20090242507 | MANUFACTURING PROCESS OF ELECTRODE - A resist layer is formed over one surface of a current-collector material, while a resist layer having a predetermined pattern is formed on the other surface of the current-collector material. Through-holes are formed on the current-collector material through an etching process. An electrode slurry is applied onto the current-collector material formed with the through-holes without removing the resist layers. Specifically, since the through-holes are closed by the resist layer, the electrode slurry does not pass through the through-holes to leak out. Therefore, the current-collector material can be conveyed in the horizontal direction, whereby the productivity of an electrode can be enhanced. The resist layers are made of PVdF, and the resist layers are removed in a heating and drying step in which the PVdF is dissolved. | 10-01-2009 |
20100116782 | METHOD FOR MANUFACTURING MULTILAYER WIRING BOARD - Disclosed are a multilayer wiring board, which has a high degree of freedom of wiring design and can realize high-density wiring, and a method which can simply manufacture the multilayer wiring board. The multilayer wiring board comprises a core substrate and two or more wiring layers provided on the core substrate through an electrical insulating layer. The core substrate has a plurality of throughholes filled with an electroconductive material, and the front side and back side of the core substrate have been electrically conducted to each other by the electroconductive material. The throughholes have an opening diameter in the range of 10 to 100 μm. An insulation layer and an electroconductive material diffusion barrier layer are also provided, and the electroconductive material is filled into the throughholes through the insulation layer. A first wiring layer provided through an electrical insulating layer on the core substrate is connected to the electroconductive material filled into the throughhole through via. | 05-13-2010 |
20100294740 | Directed self-assembly of block copolymers using segmented prepatterns - An opening in a substrate is formed, e.g., using optical lithography, with the opening having sidewalls whose cross section is given by segments that are contoured and convex. The cross section of the opening may be given by overlapping circular regions, for example. The sidewalls adjoin at various points, where they define protrusions. A layer of polymer including a block copolymer is applied over the opening and the substrate, and allowed to self-assemble. Discrete, segregated domains form in the opening, which are removed to form holes, which can be transferred into the underlying substrate. The positions of these domains and their corresponding holes are directed to predetermined positions by the sidewalls and their associated protrusions. The distances separating these holes may be greater or less than what they would be if the block copolymer (and any additives) were to self-assemble in the absence of any sidewalls. | 11-25-2010 |
20100301005 | Method of Manufacturing an Electrical Circuit on a Substrate - Electrical components, e.g., radiators, are made by a method comprising the steps of (1) providing a substrate, e.g., a polymeric film, having a first facial side that has a metal coating, e.g., copper, and a second facial side that does not have a metal coating; (2) applying an etch-resist to the metal coating to define a trace; (3) etching from the substrate the metal coating not covered by the etch-resist; (4) removing the etch-resist from the metal coating; and (5) plating, e.g., electroless plating, the uncovered metal coating with a plating material comprising at least one of silver, gold, and nickel. | 12-02-2010 |
20110011829 | Device Mounting Board - A device mounting board on which a device is mounted is provided with a substrate and an insulating film provided on one surface of the substrate. The substrate and the insulating film include glass fiber impregnated with epoxy resin. The epoxy resin impregnation ratio of the glass fiber included in the insulating resin film is higher than that of the glass fiber included in the substrate. | 01-20-2011 |
20110114597 | BARRIER INTEGRATION SCHEME FOR HIGH-RELIABILITY VIAS - Disclosed is a method of fabricating an integrated circuit comprising patterning a dielectric layer to form a hole having a sidewall and a bottom. The hole can expose an underlying material of an electrically conducting material. The method also includes exposing the sidewall and the exposed underlying material to a plasma etch, depositing a barrier layer on the bottom and the sidewall of the hole after the plasma etch clean, forming a counter-sunk cone in the underlying material by etching through the barrier layer at the bottom of the hole into the conducting metal underneath, flash depositing a thin layer of the barrier material into the hole, and finally depositing a metal seed layer in the hole covering the sidewalls and the bottom of the hole including the cone at the bottom. The hole is finally filled by depositing a metal layer in the hole. | 05-19-2011 |
20110226730 | DIE STACKING WITH AN ANNULAR VIA HAVING A RECESSED SOCKET - A die stack including a die having an annular via with a recessed conductive socket and methods of forming the die stack provide a structure for use in a variety of electronic systems. In an embodiment, a die stack includes a conductive pillar on the top of a die inserted into the recessed conductive socket of another die. | 09-22-2011 |
20110303636 | Method of manufacturing mounting substrate - A method of manufacturing a mounting substrate, the method including: providing an insulation layer, the insulation layer having a circuit pattern formed in one side thereof; forming at least one bonding pad in the other side of the insulation layer, the bonding pad electrically connected with the circuit pattern; and etching the bonding pad such that a surface of the bonding pad is recessed from a surface of the insulation layer by a predetermined depth. | 12-15-2011 |
20120012553 | METHOD OF FORMING FIBROUS LAMINATE CHIP CARRIER STRUCTURES - A method for making a leadless chip carrier (LCC) for use in electronic packages having a core layer stripped of copper cladding, containing drilled clearance holes within, a layer of resin coated copper (RCC) placed on the upper surface of the core layer and a second layer of RCC placed on the lower surface of the core layer. The layers are laminated together with the RCC filling the clearance holes during lamination. A pattern is etched on the RCC and vias are drilled through the filled clearance holes and pre-plated with seed copper layers. The seed copper layers in the vias are then covered by a layer of copper plating to meet the requirements of the core buildup layer, and resin inhibiting conductive anodic filament (CAF) growth within the structure. | 01-19-2012 |
20120074094 | Manufacturing Method for Forming Circuit Structure on Non-Conductive Carrier - A manufacturing method of forming an electrical circuit on a non-conductive carrier comprises following steps. After providing an electrically non-conductive carrier, catalysts are dispersed on or in the electrically non-conductive carrier. A predetermined track structure is formed on the electrically non-conductive carrier to expose the catalysts on the surface of the predetermined track structure. The surface of the predetermined track structure containing the catalysts is metalized to form a conductor track. | 03-29-2012 |
20120145665 | METHOD OF MANUFACTURING PRINTED CIRCUIT BOARD - A method of manufacturing a printed circuit board includes forming a through hole | 06-14-2012 |
20120175340 | METHOD FOR MANUFACTURING WIRING BOARD - In order to provide a method for manufacturing a wiring board free from contact fault, a method of the present invention, which manufactures a wiring board ( | 07-12-2012 |
20120175341 | METHODS FOR FORMING CONDUCTIVE ELEMENTS AND VIAS ON SUBSTRATES - Methods of forming conductive elements on and in a substrate include forming a layer of conductive material over a surface of a substrate prior to forming a plurality of vias through the substrate from an opposing surface of the substrate to the layer of conductive material. In some embodiments, a temporary carrier may be secured to the layer of conductive material on a side thereof opposite the substrate prior to forming the vias. Structures, including workpieces formed using such methods, are also disclosed. | 07-12-2012 |
20130048598 | PLATING METHOD OF CIRCUIT SUBSTRATE, PRODUCTION METHOD OF PLATED CIRCUIT SUBSTRATE, AND SILVER ETCHING LIQUID - Provided is a plating method of a circuit substrate comprising a conductive pattern in which a metal layer containing at least silver and copper is exposed on an outer surface. The plating method comprises: step (A) of treating the circuit substrate with a first liquid agent containing an oxidizing agent; step (B) of treating the circuit substrate after the step (A) with a second liquid agent which dissolves copper oxide, and thereby removing copper oxide from the conductive pattern's surface; step (C) of treating the circuit substrate after the step (B) with a third liquid agent whose rate of dissolving silver oxide (I) at 25° C. is 1000 times or more faster than its rate of dissolving copper (0) at 25° C., and thereby removing silver oxide from the conductive pattern's surface; and step (D) of performing electroless plating on the conductive pattern of the circuit substrate after the step (C). | 02-28-2013 |
20130087527 | LITHOGRAPHY METHOD FOR DOUBLED PITCH - Lithography method for etching very dense patterns on a substrate, based on a combination of several less dense partial patterns; a sacrificial layer is formed on a substrate and is etched according to a first partial pattern; spacers are formed on edges of elements of the sacrificial layer, the spacers defining a second partial pattern; then the sacrificial layer is removed leaving only the spacers remaining A layer sensitive to an electron beam is subsequently deposited between the spacers to a thickness less than or equal to the height of the spacers, and this sensitive layer is exposed using an electron beam according to a third partial pattern such that there remains on the substrate a final pattern of regions lacking spacers and a sensitive layer, this pattern resulting from the combination of the second and third partial patterns and having higher density than each of the partial patterns. | 04-11-2013 |
20140001150 | CIRCUIT BOARD MULTI-FUNCTIONAL HOLE SYSTEM AND METHOD | 01-02-2014 |
20140034602 | OPTICAL WAVEGUIDE DEVICE, MANUFACTURING METHOD THEREFOR, OPTICAL MODULATOR, POLARIZATION MODE DISPERSION COMPENSATOR, AND OPTICAL SWITCH - An optical waveguide device includes: a substrate which has an electro-optical effect; an optical waveguide which is formed on the substrate and/or inside the substrate; and an in-substrate electrode which is formed of a metal and provided inside the substrate. | 02-06-2014 |
20140042122 | METHOD OF MANUFACTURING PRINTED CIRCUIT BOARD - Disclosed herein is a method of manufacturing a printed circuit board, the method including: preparing a base substrate having an insulating layer and a connection pad formed in the insulating layer; forming a photosensitive resist on the insulating layer; forming an opening part of which a side surface has a foot shape by patterning the photosensitive resist; forming a via hole exposing the connection pad by etching the insulating layer exposed by the opening part; and forming a via by filling the via hole. | 02-13-2014 |
20140054262 | PIEZOELECTRIC MICRO ENERGY HARVESTER AND MANUFACTURING METHOD THEREOF - Disclosed is a piezoelectric micro energy harvester and manufacturing method thereof, the method including: forming an insulation film on a substrate; patterning the insulation film and forming an electrode pad pattern, a center electrode pattern, and a side electrode pattern; forming an open cavity at an inside of the substrate for suspension of the center electrode pattern and the side electrode pattern; disposing a conductive film on the electrode pad pattern, the center electrode pattern, and the side electrode pattern and forming electrode pads, a center electrode, and a side electrode; and forming a piezoelectric film so as to cover a space between the center electrode and the side electrode and upper surfaces of the center electrode and the side electrode. | 02-27-2014 |
20140076844 | Method for Making a Biocompatible Hermetic Housing Including Hermetic Electrical Feedthroughs - A method for fabricating a biocompatible hermetic housing including electrical feedthroughs, the method comprises providing a ceramic sheet having an upper surface and a lower surface, forming at least one via hole in said ceramic sheet extending from said upper surface to said lower surface, inserting a conductive thick film paste into said via hole, laminating the ceramic sheet with paste filled via hole between an upper ceramic sheet and a lower ceramic sheet to foam a laminated ceramic substrate, firing the laminated ceramic substrate to a temperature to sinter the laminated ceramic substrate and cause the paste filled via hole to form metalized via and cause the laminated ceramic substrate to form a hermetic seal around said metalized via, and removing the upper ceramic sheet and the lower ceramic sheet material from the fired laminated ceramic substrate to expose an upper and a lower surface of the metalized via. | 03-20-2014 |
20140091053 | ELECTRICAL DEVICE WITH TEETH JOINING LAYERS AND METHOD FOR MAKING THE SAME - A multilayer electrical device, such as a printed circuit board, having a tooth structure including a metal layer set in a dielectric. The device includes a base; a conductive layer adjacent to the base; a dielectric material adjacent to conductive layer; a tooth structure including a metal layer set in the dielectric material to join the dielectric material to the metal layer; and wherein the metal layer forms a portion of circuitry. | 04-03-2014 |
20140124475 | METHOD OF MANUFACTURING PRINTED CIRCUIT BOARD - The present invention relates to a method of manufacturing a printed circuit board. The method of manufacturing a printed circuit board including: preparing two copper clad laminates, each consisting of an insulating layer and copper foil layers laminated on upper and lower surfaces of the insulating layer; bonding the two copper clad laminates after disposing the lower copper foil layers of the copper clad laminates to face each other; processing a via hole passing through the upper copper foil layer and the insulating layer of each copper clad laminate; fill-plating a via electrode inside the via hole and forming a circuit layer on an outer layer of the copper clad laminate; separating the bonded copper clad laminates; and patterning the lower copper foil layer of the separated copper clad laminate is provided. | 05-08-2014 |
20140138345 | METHODS OF FORMING CONDUCTIVE PATTERNS USING INKJET PRINTING METHODS - A method of forming a conductive pattern includes forming a first partition and a second partition which are spaced apart from each other on a substrate, the first and second partitions defining a trench. The method includes discharging ink into the trench to form ink droplets pinned in a boundary region of the first and second partitions. The method further includes the boundary region including a region between a top side and an outer side of the first and second partitions, the ink including conductive particles. The method includes performing drying and sintering processes to form the conductive pattern in the trench, the conductive pattern including the conductive particles. | 05-22-2014 |
20140175046 | METHOD FOR FORMING COPPER WIRING - In a Cu wiring forming method for forming a Cu wiring by filling Cu in a recess which is formed in a substrate in a predetermined pattern, a barrier film formed of a TaAlN film is formed at least on the surface of the recess by thermal ALD or thermal CVD. Then a Cu film is formed to fill the recess with the Cu film. Further, the Cu wiring is formed in the recess by polishing the entire surface of the substrate by CMP. | 06-26-2014 |
20140175047 | METHOD OF MANUFACTURING A PRINTED CIRCUIT BOARD - A method of manufacturing a printed circuit board, according to one embodiment, includes forming a circuit pattern and a via pad, which is disposed by being spaced apart from the circuit pattern and has concavo-convex patterns, on a first insulating layer; forming a second insulating layer on the circuit pattern and the via pad having the concavo-convex patterns formed thereon; forming a via hole by etching a portion of the second insulating layer on the via pad; and forming a copper foil layer on the second insulating layer having the via hole formed therein. | 06-26-2014 |
20140263168 | METHOD FOR MANUFACTURING PACKAGE SUBSTRATE - A method for manufacturing a package substrate is provided, including etching a substrate to form trenches each having a buffer portion, and forming a circuit in each of the trenches. The trenches are formed by etching instead of excimer laser to increase the aspect ratio of the trench, thereby solving the problem that the metallic layer is not thick enough and achieving a high yield of the circuit and a good process capability index. | 09-18-2014 |
20140326697 | CONDUCTIVE TRANSPARENT FILM AND METHOD FOR MAKING SAME - A method for the production of a transparent conductor deposit on a substrate, the method comprising:
| 11-06-2014 |
20140326698 | INTERCONNECT STRUCTURE AND METHOD OF MAKING SAME - An interconnect structure and method of fabricating the same is provided. More specifically, the interconnect structure is a defect free capped interconnect structure. The structure includes a conductive material formed in a trench of a planarized dielectric layer which is devoid of cap material. The structure further includes the cap material formed on the conductive material to prevent migration. The method of forming a structure includes selectively depositing a sacrificial material over a dielectric material and providing a metal capping layer over a conductive layer within a trench of the dielectric material. The method further includes removing the sacrificial material with any unwanted deposited or nucleated metal capping layer thereon. | 11-06-2014 |
20150041428 | METHODS OF MANUFACTURING PRINTED CIRCUIT BOARDS WITH STACKED MICRO VIAS - A method of manufacturing at least a portion of a printed circuit board. The method includes: applying a lamination adhesive on a first plural-layer substrate that includes a plurality of circuit layers with at least one first metal pad on a first side of the first plural-layer substrate; applying a protective film on the lamination adhesive; forming at least one via into the lamination adhesive to expose the at least one metal pad on the first side of the first plural-layer substrate; filling at least one conductive paste into the at least one via formed in the lamination adhesive; removing the protective film to expose the lamination adhesive on the first plural-layer substrate; and attaching the first plural-layer substrate with a second plural-layer substrate that includes a plurality of circuit layers with at least one second metal pad on a second side of the second plural-layer substrate. | 02-12-2015 |
20150076107 | METHOD FOR MANUFACTURING MULTILAYER WIRING BOARD - A multilayer wiring board has a high degree of freedom of wiring design and can realize high-density wiring, and a method to simply manufacture the multilayer wiring board. A core substrate with two or more wiring layers provided thereon through an electrical insulating layer. The core substrate has a plurality of throughholes filled with an electroconductive material, and the front side and back side of the core substrate have been electrically conducted to each other by the electroconductive material. The throughholes have an opening diameter in the range of 10 to 100 μm. An insulation layer and an electroconductive material diffusion barrier layer are also provided, and the electroconductive material is filled into the throughholes through the insulation layer. A first wiring layer provided through an electrical insulating layer on the core substrate is connected to the electroconductive material filled into the throughhole through via. | 03-19-2015 |
20150318187 | ETCH BACK PROCESSES OF BONDING MATERIAL FOR THE MANUFACTURE OF THROUGH-GLASS VIAS - A method for manufacturing vias in a glass substrate includes bonding, through a bonding layer, a first face of the glass substrate including a plurality of holes to a first face of a glass carrier. The bonding layer has a thickness t between the first face of the glass substrate and the first face of the glass carrier and extends into at least some of the plurality of holes to a depth h from the first face of the glass substrate. The method includes etching back the bonding layer to a depth d through the plurality of holes in the glass substrate. The depth d is less than the sum of the thickness t and the depth h. The method can include filling the plurality of holes with an electrically conductive material, and de-bonding the glass substrate from the bonding layer and the glass carrier. | 11-05-2015 |
20150326146 | Flexible Micro-Electro-Mechanical Transducer - A method as disclosed makes a capacitive micromachined ultrasonic transducer (cMUT). The method forms a pattern of standing features on a substrate to serve as support walls in the cMUT being made, and further makes a patterned trench from the front side into the substrate at selected locations where separation boundaries of neighboring elements of the cMUT are located. In the process of completing the transducer elements of the cMUT, the method forms a covering layer over the patterned trench to at least temporarily cover the patterned trench. The covering layer seals the patterned trench to prevent other materials from entering during at least a part of the fabrication process. | 11-12-2015 |
20150371854 | METHODS FOR FABRICATING REFINED GRAPHITE-BASED STRUCTURES AND DEVICES MADE THEREFROM - Graphite-based devices with a reduced characteristic dimension and methods for forming such devices are provided. One or more thin films are deposited onto a substrate and undesired portions of the deposited thin film or thin films are removed to produce processed elements with reduced characteristic dimensions. Graphene layers are generated on selected processed elements or exposed portions of the substrate after removal of the processed elements. Multiple sets of graphene layers can be generated, each with a different physical characteristic, thereby producing a graphite-based device with multiple functionalities in the same device. | 12-24-2015 |
20160050769 | METHOD FOR MANUFACTURING MULTILAYER WIRING SUBSTRATE - To provide a method for manufacturing a multilayer wiring substrate, in which an insulating layer and a metal foil provided thereon are integrally laminated on an inner layer material having a wiring formed thereon, in which a hole for via hole is formed in the metal foil and the insulating layer, and in which the hole for via hole is filled with an electrolytic filled plating layer after a base electroless plating layer is formed, the method being featured in that, after the base electroless plating layer is formed, first, an electrolysis filled plating layer is formed to the extent that the hole for via hole is not completely filled, and then, after the surface of the electrolytic filled plating layer is etched, the hole for via hole is completely filled by an electrolytic filled plating layer. | 02-18-2016 |
20160073505 | MANUFACTURING METHOD OF MULTILAYER FLEXIBLE CIRCUIT STRUCTURE - A manufacturing method of multilayer flexible circuit structure including the following steps is provided. Two first flexible substrates are correspondingly bonded on two sides of a release film, and two conductive materials are correspondingly formed on the two first flexible substrates. The two conductive materials are patterned to form two first inner-layer circuits. Two outer build-up structures are bonded on the two corresponding first flexible substrates. The release film is removed, so as to separate the two first flexible substrates. An outer-layer circuit is formed on each of the first flexible substrates and the corresponding outer build-up structure, wherein the outer-layer circuit is connected to the corresponding first inner-layer circuit, and each of the first flexible substrates, the corresponding first inner-layer circuit, the outer build-up structure and the outer-layer circuit correspondingly form a multilayer flexible circuit structure. Another manufacturing method of multilayer flexible circuit structure is also provided. | 03-10-2016 |
20160132141 | METHOD FOR MANUFACTURING HYBRID TRANSPARENT ELECTRODE AND HYBRID TRANSPARENT ELECTRODE - Provided herein is a method for producing a hybrid transparent electrode, the method including filling grooves of a substrate with a conductive metal ink composition; filling the grooves with residue conductive metal ink composition that remains on a surface of the substrate as the grooves are being filled with the conductive metal ink composition to form an electrode pattern; and forming a conductive layer including a conductive material on the electrode pattern. | 05-12-2016 |
20160147087 | ELECTRO-OPTICAL MODULATOR WITH A VERTICAL CAPACITOR STRUCTURE - An optical modulator may include a leftmost waveguide, a rightmost waveguide, and a dielectric layer disposed therebetween. In one embodiment, the waveguides may be disposed on the same plane. When a voltage potential is created between the rightmost and leftmost waveguides, these layers form a silicon-insulator-silicon capacitor (also referred to as SISCAP) structure that provides efficient, high-speed optical modulation of an optical signal passing through the modulator. As opposed to a horizontal SISCAP structure where the dielectric layer is disposed between upper and lower waveguides, arranging the dielectric layer between waveguides disposed on the same plane results in a vertical SISCAP structure. In one embodiment, the leftmost and rightmost waveguide are both made from crystalline silicon. | 05-26-2016 |
20160186058 | Etchant Solutions and Method of Use Thereof - Etching compositions and method of using the etching compositions comprising potassium hydroxide; one or more than one additional alkaline compounds selected from the group consisting of TEAH, TMAF and NH | 06-30-2016 |
20160202404 | METHOD FOR MANUFACTURING POLARIZING FILM | 07-14-2016 |