Entries |
Document | Title | Date |
20080210661 | Method For Forming Via Hole in Substrate For Flexible Printed Circuit Board - There is provided a method for forming a via hole ( | 09-04-2008 |
20080230512 | Printed Circuit Board and Method for Processing Printed Circuit Board - The invention is to provide a printed circuit board in which advance of packaging density of the printed circuit board and reduction in production cost can be attained while processing quality can be made uniform, a method for processing the printed circuit board and a method for producing the printed circuit board. | 09-25-2008 |
20080251496 | Optoelectric composite substrate and method of manufacturing the same - An optoelectric composite substrate of the present invention includes an insulating film, an optical waveguide embedded in the insulating film in a state that an upper surface is exposed from the insulating film, a via hole formed to pass through the insulating film, a conductor formed in the via hole, and a connection terminal on which an optical device is mounted and which is connected to an upper end side of the conductor, wherein the connection terminal is embedded in an upper-side portion of the via hole or is projected from the insulating film. | 10-16-2008 |
20080277375 | Method for manufacturing flexible display substrate and flexible display device - A method for manufacturing a flexible electrophoretic display device, including: providing a metal mother substrate having a first thickness, including a unit display panel region and a non-display region adjacent the unit display panel region; forming a display element in the unit display panel region; forming a groove in the non-display region of the mother substrate; cutting the mother substrate along the groove to separate the unit display panel region from the mother substrate; thinning the substrate of the separated unit display panel region; and forming an electrophoretic film on the unit display panel region. | 11-13-2008 |
20080302760 | Method of forming a metal layer pattern having a nanogap and method of manufacturing a molecule-sized device using the same - A method of patterning a metal layer includes forming a first mask on a surface of the metal layer, the first mask having an opening through the first mask that exposes the metal layer, and forming a nanogap in the exposed metal layer using an ion beam directed through the opening. The first mask limits a lateral extent of the ion beam, and the nanogap has a width that is less than a width of the opening. | 12-11-2008 |
20080314865 | Method for Providing Hermetic Electrical Feedthrough - A method for fabricating the hermetic electrical feedthrough. The method comprises providing a ceramic sheet having an upper surface and a lower surface, forming at least one via hole in said ceramic sheet extending from said upper surface to said lower surface, inserting a conductive thickfilm paste into said via hole, laminating the ceramic sheet with paste filled via hole between an upper ceramic sheet and a lower ceramic sheet to form a laminated ceramic substrate, firing the laminated ceramic substrate to a temperature to sinter the laminated ceramic substrate and cause the paste filled via hole to form metalized via and cause the laminated ceramic substrate to form a hermetic seal around said metalized via, and removing the upper ceramic sheet and the lower ceramic sheet material from the fired laminated ceramic substrate to expose an upper and a lower surface of the metalized via. | 12-25-2008 |
20080314866 | MIRROR AND MIRROR LAYER FOR OPTICAL MODULATOR AND METHOD - Described herein are systems, devices, and methods relating to packaging electronic devices, for example, microelectromechanical systems (MEMS) devices, including optical modulators such as interferometric optical modulators. The interferometric modulator disclosed herein comprises a movable mirror. Some embodiments of the disclosed movable mirror exhibit a combination of improved properties compared to known mirrors, including reduced moving mass, improved mechanical properties, and reduced etch times. | 12-25-2008 |
20090014410 | Producing method of suspension board with circuit - A producing method of a suspension board with circuit includes simultaneously forming a conductive pattern formed on an insulating layer formed on a metal supporting board and having a terminal portion for connecting to an electronic component, and a mark formed on the metal supporting board, or on the insulating layer and having an opening for forming a reference hole for mounting the electronic component, and forming the reference hole by etching the metal supporting board disposed in the opening of the mark, or the insulating layer and the metal supporting board each disposed in the opening of the mark. | 01-15-2009 |
20090020501 | METHOD OF FORMING PASSAGE IN SUBSTRATE FOR MEMS MODULE - A method of forming a passage in a substrate for a MEMS module is disclosed to include the steps of respectively forming a first support layer and a second support layer in a first space and a second space, which are respectively formed in a bottom side and a top side of a substrate by etching, by injection molding to define a sacrifice portion between the first and second support layers, and removing the sacrifice portion from the substrate by etching to form a passage defined between the first support layer and the second support layer in the substrate with two ends in communication with ambient atmosphere. | 01-22-2009 |
20090026168 | METHOD FOR MANUFACTURING A RIGID-FLEX CIRCUIT BOARD - A method for manufacturing a rigid-flex board is disclosed. After the formation of each layer of the rigid-flex board, a laser-etched groove is formed at the interface between a rigid part and a bending area of the rigid-flex board. After the laser etching process, a circuit-board routing process is performed to remove materials along the sideward perimeter of the bending area. The exposed copper layer is then removed from inside the laser-etched groove. Thereafter, a redundancy rigid structure within the bending area is readily removed to expose the flex board within the bending area. | 01-29-2009 |
20090032493 | Method For Manufacturing Predetermined Pattern - A method for manufacturing a predetermined pattern is generally used to manufacture a predetermined pattern on PCBs. The method comprises a step of etching an insulating substrate of the PCB with a laser beam instead of chemical solutions to produce the predetermined pattern according to the layout of the predetermined patterns. The method may further comprise a step of applying metallization treatment on the predetermined pattern, thereby forming a desired trace. The laser etching has the advantages such as high precision and no chemical wastewater. The laser etching also overcomes the disadvantages of conventional manufacturing methods, such as uneven thickness and imprecision. | 02-05-2009 |
20090050602 | METHOD FOR FORMING HOLES IN MAKING PRINTED CIRCUIT BOARD - A method for forming holes in making a printed circuit board includes the step of: providing a copper clad laminate including an insulation layer and a copper layer laminated on the insulation layer; forming a carbon nano-material on the copper layer of the copper clad laminate; and applying a laser beam onto a portion of the carbon nano-material to define a hole in the copper clad laminate beneath the portion of the carbon nano-material. | 02-26-2009 |
20090071934 | Crystalline aluminum oxide layers having increased energy band gap, charge trap layer devices including crystalline aluminum oxide layers, and methods of manufacturing the same - Crystalline aluminum oxide layers having increased energy band gap, charge trap memory devices including crystalline aluminum oxide layers and methods of manufacturing the same are provided. A method of forming an aluminum oxide layer having an increased energy band gap includes forming an amorphous aluminum oxide layer on a lower film, introducing hydrogen (H) or hydroxyl group (OH) into the amorphous aluminum oxide layer, and crystallizing the amorphous aluminum oxide layer including the H or OH. | 03-19-2009 |
20090159559 | METHOD OF MANUFACTURING MULTILAYER PRINTED CIRCUIT BOARD HAVING BURIED HOLES - A method for manufacturing a multilayer printed circuit board includes the following steps. A number of laminate units are provided. Each of the laminate units includes an electrically conductive layer with a circuit pattern defined therein, and a release layer releasably attached to the electrically conductive layer. A number of insulation layers are provided. Each of the insulation layers definies a metalized through hole therein. The electrically conductive layers and the insulation layers are stacked alternately one on another such that adjacent electrically conductive layers are insulated by one insulation layer and the metalized through holes electrically connects the circuit patterns of the adjacent electrically conductive layers. In the stacking step, the release layer is removed from the laminate unit after the electrically conductive layer is stacked onto the respective insulation layer, thereby obtaining a pre-laminated multilayer printed circuit board. The stacked electrically conductive layers and the insulation layers are laminated together to achieve a multilayer printed circuit board. | 06-25-2009 |
20090159560 | SELECTIVE ETCH CHEMISTRIES FOR FORMING HIGH ASPECT RATIO FEATURES AND ASSOCIATED STRUCTURES - An interlevel dielectric layer, such as a silicon oxide layer, is selectively etched using a plasma etch chemistry including a silicon species and a halide species and also preferably a carbon species and an oxygen species. The silicon species can be generated from a silicon compound, such as Si | 06-25-2009 |
20090166320 | SELECTIVE ELECTROLESS PLATING FOR ELECTRONIC SUBSTRATES - In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including forming a film on a surface of a substrate, the film designed to prevent the seeding of an electroless plating catalyst, laser ablating the surface of the substrate through the film to form trenches, and seeding the surface of the substrate with an electroless plating catalyst. Other embodiments are also disclosed and claimed. | 07-02-2009 |
20090188890 | SOLDER VOID REDUCTION ON CIRCUIT BOARDS - There is disclosed a method, system, and screen for reducing solder voids on circuit boards. In an embodiment, there is provided a method of reducing solder voids on a circuit board, comprising: locating via holes provided at a conductive landing pad; and covering at least some of the via holes with a coating, whereby gases from the covered via holes are prevented from expanding and forming voids. In another embodiment, the method further comprises covering the location of at least some of the via holes in a pattern of strips, whereby more of the via holes may be covered by the coating while reducing areas of the conductive landing pad covered by the coating. In another embodiment, the coating and removal process may be performed at the same time as when all other areas of the circuit board are coated and removed, such that a separate manufacturing step is not required. | 07-30-2009 |
20090266788 | METHOD FOR FABRICATING CONDUCTIVE PATTERN ON FLEXIBLE SUBSTRATE AND PROTECTIVE INK USED THEREIN - The invention discloses a method for fabricating a conductive pattern on a flexible substrate. A flexible substrate having a conductive layer thereon is provided. A protective ink is screen printed on the conductive layer, wherein a portion of the conductive layer is exposed through the protective ink. The exposed portion of the conductive layer is removed by etching using the protective ink as a mask. The protective ink is then removed, thus providing a conductive pattern with a minimum line width of not greater than 150 μm. The invention also discloses a composition for the protective ink. | 10-29-2009 |
20090272715 | NANOFABRICATION BASED ON SAM GROWTH - The present invention relates to a process of nano fabrication based on nucleated SAM growth, to patterned substrates prepared thereby, to a nano wire or grid of nanowires prepared thereby and to electronic devices including the same. In particular, there is provided a process which comprises applying a first SAM-forming molecular species to a first surface region of the substrate surface, so as to provide a first SAM defining a scaffold pattern on the first surface region; and applying a second SAM-forming molecular species to at least a second surface region of said substrate surface which is not covered by the first SAM, whereby a second replica SAM comprising the second SAM-forming molecular species selectively forms on substrate surface adjacent to at least one edge of said first SAM. | 11-05-2009 |
20090277869 | SOLID STATE MEMBRANE CHANNEL DEVICE FOR THE MEASUREMENT AND CHARACTERIZATION OF ATOMIC AND MOLECULAR SIZED SAMPLES - A solid state device is formed through thin film deposition techniques which results in a self-supporting thin film layer that can have a precisely defined channel bored therethrough. The device is useful in the chacterization of polymer molecules by measuring changes in various electrical characteristics as molecules pass through the channel. To form the device, a thin film layer having various patterns of electrically conductive leads are formed on a silicon substrate. Using standard lithography techniques, a relatively large or micro-scale aperture is bored through the silicon substrate which in turn exposes a portion of the thin film layer. This process does not affect the thin film. Subsequently, a high precision material removal process is used (such as a TEM) to bore a precise nano-scale aperture through the thin film layer that coincides with the removed section of the silicon substrate. | 11-12-2009 |
20090289030 | METHOD OF FABRICATING PRINTED WIRING BOARD - A method of fabricating a printed wiring board that is capable of forming a minute via hole with high accuracy is provided. This method of fabricating a printed wiring board | 11-26-2009 |
20090301997 | FABRICATING PROCESS OF STRUCTURE WITH EMBEDDED CIRCUIT - A fabricating process of a structure with an embedded circuit is described as follows. Firstly, a substrate having an upper surface and a lower surface opposite to the upper surface is provided. Afterward, a dielectric layer is formed on the upper surface of the substrate. Next, a plating-resistant layer is formed on the dielectric layer. Then, the plating-resistant layer and the dielectric layer are patterned for forming an recess pattern on the dielectric layer. Subsequently, a conductive base layer is formed in the recess pattern by using a chemical method, and the plating-resistant layer is exposed by the conductive base layer. After that, the plating-resistant layer is removed. | 12-10-2009 |
20100051578 | METHOD FOR FABRICATING AN INTEGRATED CIRCUIT - A method for fabricating an integrated circuit includes providing a substrate having thereon a material layer; forming trenches in the material layer; forming damascened wires in the trenches; covering the damascened wires and the material layer with a cap layer; forming a through hole in the cap layer that exposes a portion of the material layer; and removing the material layer thereby forming an air gap between the damascened wires. | 03-04-2010 |
20100084371 | METHODS FOR FABRICATION OF MICROFLUIDIC SYSTEMS ON PRINTED CIRCUIT BOARDS - Methods for fabrication of microfluidic systems on printed circuit boards (PCB) are described. The PCB contains layers of insulating material and a layer or layers of metal buried within layers of insulating material. The metal layers are etched away, leaving fully enclosed microfluidic channels buried within the layers of insulating material. | 04-08-2010 |
20100147790 | SUPPORT STRUCTURE FOR MEMS DEVICE AND METHODS THEREFOR - A microelectromechanical systems device having support structures formed of sacrificial material surrounded by a protective material. The microelectromechanical systems device includes a substrate having an electrode formed thereon. Another electrode is separated from the first electrode by a cavity and forms a movable layer, which is supported by support structures formed of a sacrificial material. | 06-17-2010 |
20100181285 | Method of manufacturing capacitor device - A method of manufacturing a capacitor device includes forming at least one through-hole in a capacitor laminate formed with laminated multiple capacitors, conducting a dry desmear treatment in the at least one through-hole after forming the at least one through-hole, and forming seed metal through dry processing in the at least one through-hole after conducting the dry desmear treatment. | 07-22-2010 |
20100200540 | Large substrate structural vias - An electronic package and methods by which the package reduces thermal fatigue failure of conductors in the electronic package. The electronic package includes a carrier substrate having first and second surfaces and a plurality of anchor vias having a via material extending from the first surface toward the second surface. The electronic package includes a first conducting layer having a length and a width extending laterally in two dimensions across a major part of the first surface of the carrier substrate. The anchor vias have plural attachments along the length and the width of the first conducting layer to secure the first conducting layer to the carrier substrate. | 08-12-2010 |
20100213162 | PLASMA ETCHING METHOD, PLASMA ETCHING APPARATUS AND STORAGE MEDIUM - There is provided a plasma etching method capable of achieving a sufficient organic film modifying effect by high-velocity electrons. In forming a hole in an etching target film by plasma etching, a first condition of generating plasma within a processing chamber by way of turning on a plasma-generating high frequency power application unit and a second condition of not generating the plasma within the processing chamber by way of turning off the plasma-generating high frequency power application unit are repeated alternately. Further, a negative DC voltage is applied from a first DC power supply such that an absolute value of the applied negative DC voltage during a period of the second condition is greater than an absolute value of the applied negative DC voltage during a period of the first condition. | 08-26-2010 |
20100224588 | METHODS OF FORMING METAL-INSULATOR-METAL (MIM) CAPACITORS WITH PASSIVATION LAYERS ON DIELECTRIC LAYERS - Methods of forming a dielectric layer of a MIM capacitor can include forming a passivation layer on a dielectric layer of a MIM capacitor to separate the dielectric layer from direct contact with an overlying photo-resist pattern. Related capacitor structures are also disclosed. | 09-09-2010 |
20100237039 | METHOD OF ACCURATELY SPACING Z-AXIS ELECTRODE - A method of forming a device with a controlled electrode gap width includes providing a substrate, forming a functional layer on top of a surface of the substrate, forming a sacrificial layer above the functional layer, exposing a first portion of the functional layer through the sacrificial layer, forming a first spacer layer on the exposed first portion of the functional layer, forming an encapsulation layer above the first spacer layer, and vapor etching the encapsulated first spacer layer to form a first gap between the functional layer and the encapsulation layer. | 09-23-2010 |
20110017703 | SELECTIVE PLANARIZATION METHOD AND DEVICES FABRICATED ON PLANARIZED STRUCTURES - A method and system for treating a surface structure of a workpiece. The method provides a carrier-gel to the surface structure of the workpiece. The carrier-gel includes an etchant for selectively etching a first material of the surface structure and has a gel particle size larger than the surface structure. The method etches the first material from the surface structure by a reaction of the etchant included in the carrier-gel with the first material of the surface structure in order to remove a part of the first material from the surface structure for subsequent device fabrication. The system includes a chemical reactor supporting the workpiece. The chemical reactor is configured to flow the carrier-gel noted to the surface structure of the workpiece in order to remove the first material from the surface structure. | 01-27-2011 |
20110036808 | ULTRASONIC TRANSDUCER, ULTRASONIC TRANSDUCER FABRICATION METHOD, AND ULTRASONIC ENDOSCOPE - An ultrasonic transducer according to the present invention includes: two or more ultrasonic transducer cells, each of which has a lower electrode, a first insulating layer placed on the lower electrode, a cavity placed on the first insulating layer, a second insulating layer placed on the cavity, and an upper electrode placed above the second insulating layer; channels which communicate the cavities with each other; the second insulating layer placed on the channels; holes formed in the second insulating layer placed on the channels; and sealing portions which seal the holes, where that part of the sealing portions which enters the channels is the same in cross-sectional shape as the holes. | 02-17-2011 |
20110089138 | METHOD OF MANUFACTURING PRINTED CIRCUIT BOARD - Disclosed is a method of manufacturing a printed circuit board, including (A) forming a first circuit layer on a base substrate and forming a first insulating layer thereon, (B) forming trenches including dummy trenches and wiring trenches on the first insulating layer and plating the trenches, thus providing a trench circuit layer including a dummy circuit pattern and a wiring circuit pattern, (C) removing the dummy circuit pattern of the trench circuit layer, and (D) forming a second insulating layer on the trench circuit layer from which the dummy circuit pattern was removed. The method reduces deviation of plating thickness and thus realizes the design density of a trench circuit layer. | 04-21-2011 |
20110132867 | METHOD AND SYSTEM FOR IMPRINT LITHOGRAPHY - A method and apparatus of imprint lithography wherein the method includes depositing a material on a patterned surface of a conductive substrate, and pressing a transparent substrate and the conductive substrate together, wherein the pressing causes the material to conform to the patterned surface. Energy is applied to the material to form patterned material from the material. The transparent substrate and the conductive substrate are separated, wherein the patterned material adheres to the transparent substrate. | 06-09-2011 |
20110147342 | METHOD FOR FABRICATING WIRING STRUCTURE OF WIRING BOARD - A method for fabricating a wiring structure of a wiring board is provided. First, a substrate including an insulation layer and a film disposed on the insulation layer is provided. Next, an intaglio pattern exposing the insulation layer is formed on an outer surface of the film. The intaglio pattern is formed by removing a portion of the insulation layer and a portion of the film. Next, an activated layer is formed on the outer surface and in the intaglio pattern. The activated layer completely covers the outer surface and all surfaces of the intaglio pattern. Then, the film and the activated layer on the outer surface are removed, and the activated layer in the intaglio pattern is remained. After the film and the activated layer on the outer surface are removed, a conductive material is formed in the intaglio pattern by chemical deposition method. | 06-23-2011 |
20110215069 | METHOD FOR MANUFACTURING PRINTED CIRCUIT BOARD WITH THICK TRACES - A method for manufacturing printed circuit board includes steps below. A first electrically conductive layer including a first surface and a second surface at an opposite side thereof to the first surface is provided. A number of first traces directly formed on the second surface. A first insulating layer is formed on the second surface of the first electrically conductive layer and the surface of the first traces. The electrically conductive layer is etched to form a number of second traces, the second traces superpose the first traces, the first traces and the second traces constitute a circuit pattern. | 09-08-2011 |
20110266252 | HIGH-TEMPERATURE SELECTIVE DRY ETCH HAVING REDUCED POST-ETCH SOLID RESIDUE - Methods of dry etching silicon-containing dielectric films are described. The methods include maintaining a relatively high temperature of the dielectric films while etching in order to achieve reduced solid residue on the etched surface. Partially or completely avoiding the accumulation of solid residue increases the etch rate. | 11-03-2011 |
20120031873 | ETCHING DEVICE AND METHOD FOR MANUFACTURING PRINTED CIRCUIT BOARD USING SAME - In a method for manufacturing a printed circuit board, a substrate, including a number of plated through holes (PTHs) is provided. Each of the PTHs has an electrically conductive layer plated on its inner wall and includes an electrically connecting portion and a stub. A protective layer is formed on a surface of the substrate adjacent to the stub. An etching device, including an upper plate and a number of spray tubes corresponding to the PTHs, is provided. Each of the spray tubes includes a protruding portion beyond the upper plate. The substrate is arranged in such a manner that the protective layer is in contact with the upper plate and the protruding portions are received in the stubs. After that, the protruding portions spray an etchant to etch and remove the electrically conductive layer of the stubs, and the protective layer is removed. | 02-09-2012 |
20120061347 | PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING PRINTED WIRING BOARD - A method for manufacturing a printed wiring board including preparing a carrier, forming a metal layer on the carrier, forming an etching resist on the metal layer, forming a metal film from the metal layer underneath the resist by removing portion of the metal layer exposed through the resist and part of the metal layer contiguous to the portion of the metal layer and underneath the resist, forming a coating layer on side surface of the film and the carrier, forming a pad on the coating layer, removing the resist, forming a resin insulation layer on the film and surface of the pad, forming an opening reaching the surface of the pad in the insulation layer, forming a conductive circuit on the insulation layer, forming a via conductor connecting the circuit and the pad in the opening, removing the carrier from the film and coating layer, and removing the film. | 03-15-2012 |
20120061348 | Large Scale Patterned Growth of Aligned One-Dimensional Nanostructures - A method of making nanostructures using a self-assembled monolayer of organic spheres is disclosed. The nanostructures include bowl-shaped structures and patterned elongated nanostructures. A bowl-shaped nanostructure with a nanorod grown from a conductive substrate through the bowl-shaped nanostructure may be configured as a field emitter or a vertical field effect transistor. A method of separating nanoparticles of a desired size employs an array of bowl-shaped structures. | 03-15-2012 |
20120080400 | MULTILAYER PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING MULTILAYER PRINTED WIRING BOARD - A multilayer printed wiring board including a first interlayer resin insulation layer, a pad formed on the first interlayer resin insulation layer, a solder resist layer formed on the first interlayer resin insulation layer and the pad, a protective film formed on a portion of the pad exposed by an opening of the solder resist layer, and a coating layer formed between the pad and the solder resist layer. The pad mounts an electronic component. The coating layer has a metal layer and a coating film. The metal layer is formed on the surface of the pad and the coating film is formed on the metal layer. | 04-05-2012 |
20120111825 | AIR GAP INTERCONNECT STRUCTURES AND METHODS FOR FORMING THE SAME - A metal interconnect structure includes at least a pair of metal lines, a cavity therebetween, and a dielectric metal-diffusion barrier layer located on at least one portion of walls of the cavity. After formation of a cavity between the pair of metal lines, the dielectric metal-diffusion barrier layer is formed on the exposed surfaces of the cavity. A dielectric material layer is formed above the pair of metal lines to encapsulate the cavity. The dielectric metal-diffusion barrier layer prevents diffusion of metal and impurities from one metal line to another metal line and vice versa, thereby preventing electrical shorts between the pair of metal lines. | 05-10-2012 |
20120118852 | Method for manufacturing quartz crystal unit, quartz crystal oscillator and electronic apparatus - In a method for manufacturing a quartz crystal unit, a metal film is formed on a quartz crystal wafer which is then etched to form a quartz crystal tuning fork resonator having first and second tines vibratable in flexural and fundamental modes. A groove is chemically etched in a first main surface of both tines such that a first surface of the groove is opposite a first side surface of the corresponding tine. The width of the groove is greater than a distance in the width direction from the groove first surface to the first side surface of the corresponding tine. An electrode is formed on each groove first surface and on the first side surface of both tines with the electrode on the groove first surface of the first tine having the same electrical polarity as the electrode on the first side surface of the second tine. | 05-17-2012 |
20120125882 | METHOD OF MAKING TOUCH-SENSITIVE DEVICE WITH ELECTRODES HAVING LOCATION PATTERN INCLUDED THEREIN - A method of patterning a conductor on a substrate, the conductor including a unique location indicia that may be sensed with a sensing device, and the location on the substrate determined therefrom. | 05-24-2012 |
20120132614 | FLEXIBLE ELECTRICAL SUBSTRATE - A flexible substrate layer haying metallic bus-lines and connecting stitches is formed. A trace layer haying electrical traces and thermal vias is also formed. The substrate layer and the trace layer are bonded together by way of respective thermal pathways and electrically interconnected. The resulting layer-wise assembly is configured to support and electrically interconnect an array of photovoltaic cells and to channel away heat during operation. | 05-31-2012 |
20120152890 | METHODS FOR MANUFACTURING RADIO FREQUENCY (RF) POWDER - The present disclosure provides methods for manufacturing a radio frequency (RF) powder including a plurality of RF particles, each of which includes a circuit element. A plurality of circuit elements, each corresponding to a different RF particle, may be formed on a first surface of a substrate. Grooves may be etched into the first surface of the substrate between the plurality of circuit elements. A protection film may be formed on each of the plurality of circuit elements and a portion of the substrate between a second, opposite surface of the substrate and bottoms of the grooves may be removed so that each of the plurality of circuit elements is associated with the remaining portion of the substrate. | 06-21-2012 |
20120187077 | MICRO-ELECTROMECHANICAL SYSTEMS (MEMS) MICROPHONE AND METHOD OF MANUFACTURING THE SAME - Provided are a micro-electromechanical systems (MEMS) microphone and a method of manufacturing the same. A manufacturing process is simplified compared to a conventional art using both upper and lower substrate processes. Since defects which may occur during manufacturing are reduced due to the simplified manufacturing process, the manufacturing throughput is improved, and since durability of the MEMS microphone is improved, system stability against the external environment is improved. | 07-26-2012 |
20120279942 | METHOD FOR PREPARING NANOTUBES OF PIEZOELECTRIC MATERIAL AND NANOTUBES OF PIEZOELECTRIC MATERIAL OBTAINED THEREBY - A method for preparing nanotubes by providing nanorods of a piezoelectric material having an asymmetric crystal structure and by further providing hydroxide ions to the nanorods to etch inner parts of the nanorods to form the nanotubes. | 11-08-2012 |
20130026130 | METHOD OF MANUFACTURING LIQUID EJECTION HEAD SUBSTRATE - A liquid ejection head substrate is manufactured by forming a wiring pattern on one surface of a substrate, forming an etching mask layer on the other surface of the substrate, forming a positioning reference mark on the etching mask layer by means of a laser, forming an opening pattern groove running through the etching mask layer and having a bottom in the inside of the silicon substrate, using the positioning reference mark, and forming a liquid supply port running through the silicon substrate by etching the silicon substrate from the opening pattern groove to the one surface by means of crystal anisotropic etching. | 01-31-2013 |
20130032569 | Method of Fabricating Cliche - Disclosed herein is a method of fabricating a cliché capable of preventing a printing roller from touching a bottom surface of the cliché. The method of fabricating the cliché includes forming a mask thin film pattern having a multilayer structure and a photoresist pattern on a base substrate, forming a resistant reinforcement inducing layer to cover the photoresist pattern, thereby transforming the photoresist pattern into a resistant reinforced photoresist pattern, and forming groove patterns having different depths from each other by etching the base substrate using the resistant reinforced photoresist pattern and the mask thin film pattern having the multilayer structure as masks. | 02-07-2013 |
20130126467 | METHOD FOR MANUFACTURING CONDUCTIVE LINES WITH SMALL LINE-TO-LINE SPACE - The present invention discloses a method for manufacturing conductive lines with small line-to-line space. The method for manufacturing conductive lines is to coat photoresist on a conductor layer firstly, after exposure and development treatments, then further perform an ashing treatment to completely remove the corresponding part of the photoresist that is corresponding to the exposure area, and then perform an etching step for the conductor layer to form the required conductive lines. The method provided by the present invention can manufacture wire patterns that meet the requirement of small line-to-line space under a condition that the exposure apparatus has limited exposure accuracy. | 05-23-2013 |
20130168349 | METHOD OF FORMING VIA HOLE IN CIRCUIT BOARD - A method of forming a via hole in a circuit board including an insulating layer and a metal layer disposed on each of top and bottom surfaces of the insulating layer, the method including: selectively removing a portion of each of the metal layers where the via hole is to be formed thereby exposing the insulating layer; and removing the exposed insulating layer, wherein the removing of the exposed insulating layer includes chemically swelling the exposed insulating layer and removing the swollen insulating layer. | 07-04-2013 |
20130200040 | TITANIUM NITRIDE REMOVAL - A chemical solution that removes undesired metal hard mask yet remains selective to the device wiring metallurgy and dielectric materials. The present disclosure decreases aspect ratio by selective removal of the metal hard mask before the metallization of the receiving structures without adverse damage to any existing metal or dielectric materials required to define the semiconductor device, e.g. copper metallurgy or device dielectric. Thus, an improved aspect ratio for metal fill without introducing any excessive trapezoidal cross-sectional character to the defined metal receiving structures of the device will result. | 08-08-2013 |
20130277330 | METHODS OF PATTERNING A CONDUCTOR ON A SUBSTRATE - A method of patterning a conductor on a substrate includes providing an inked elastomeric stamp inked with self-assembled monolayer-forming molecules and having a relief pattern with raised features. Then the raised features of the inked stamp contact a metal-coated visible light transparent substrate. Then the metal is etched to form an electrically conductive micropattern corresponding to the raised features of the inked stamp on the visible light transparent substrate. | 10-24-2013 |
20130299451 | METHOD OF PRODUCING A SUSPENSION BOARD WITH CIRCUIT - A suspension board with circuit includes a metal supporting board, an insulating layer formed on the metal supporting board, and a conductive pattern formed on the insulating layer and having a terminal portion connected to connecting terminals of a magnetic head mounted on a slider. A slider mounting region where the slider is disposed is defined, and a plurality of the terminal portions are spaced apart from each other in the slider mounting region, and in the metal supporting board, an opening which opens so as to expose the insulating layer where the terminal portions are disposed is formed at the slider mounting region. | 11-14-2013 |
20130306592 | PLASTIC CAPACITIVE TOUCH SCREEN AND METHOD OF MANUFACTURING SAME - A method of removing portions of a conductive layer comprising a transparent conductive material and/or a metallic material disposed on a plastic substrate used for capacitive touchscreen devices includes providing a plastic substrate having a conductive layer disposed on a surface thereof and removing portions of the conductive layer at the surface of the plastic substrate to establish a pattern of electrically isolated conductive portions on the surface of the plastic substrate. The conductive portions or traces are electrically connected to a touchscreen controller, which is operable to determine a location of a touch or proximity of an object at or near the surface of the plastic substrate responsive to a detected change in capacitance. The removal process may comprise etching or laser ablating portions of the conductive layer at the surface of the plastic substrate. | 11-21-2013 |
20130319972 | Method of Manufacturing a Flexible Circuit Electrode Array - Polymer materials make useful materials as electrode array bodies for neural stimulation. They are particularly useful for retinal stimulation to create artificial vision. Regardless of which polymer is used, the basic construction method is the same. A layer of polymer is laid down. A layer of metal is applied to the polymer and patterned to create electrodes and leads for those electrodes. A second layer of polymer is applied over the metal layer and patterned to leave openings for the electrodes, or openings are created later by means such as laser ablation. Hence the array and its supply cable are formed of a single body. | 12-05-2013 |
20140001149 | Crossed slit structure for nanopores | 01-02-2014 |
20140021163 | GRAPHENE WINDOWS, METHODS FOR MAKING SAME, AND DEVICES CONTAINING SAME - The present invention relates to graphene windows and methods for making same. One method comprises selecting a high purity metal foil, growing a layer of graphene on a first face of the metal foil, patterning the second face of the graphene-modified foil with a polymer, wherein the second face of the graphene-modified foil has an exposed region and etching the second face of the graphene-modified foil in the exposed region until exposing the first layer of graphene. | 01-23-2014 |
20140021164 | METHOD FOR MANUFACTURING A MULTILAYER RIGID FLEXIBLE PRINTED CIRCUIT BOARD - A method for manufacturing a multilayer rigid flexible printed circuit board that includes a flexible region including a flexible film having a circuit pattern formed on one or both surfaces thereof and a laser blocking layer formed on the circuit pattern; and a rigid region formed adjacent to the flexible region and including a plurality of pattern layers on one or both surfaces of extended portions extended to both sides of the flexible film of the flexible region. | 01-23-2014 |
20140021165 | GRAPHENE WINDOWS, METHODS FOR MAKING SAME, AND DEVICES CONTAINING SAME - The present invention relates to graphene windows and methods for making same. The present invention further relates to devices that include such graphene windows. | 01-23-2014 |
20140054261 | MICRO-DEVICE ON GLASS - A method of fabricating a micro-device having micro-features on glass is presented. The method includes the steps of preparing a first glass substrate, fabricating a metallic pattern on the first glass substrate, preparing a second glass substrate and providing one or more apertures on the second glass substrate, heating the first glass substrate and the second glass substrate with a controlled temperature raise, bonding the first glass substrate and the second glass substrate by applying pressure to form a bonded substrate, wherein the metallic pattern is embedded within the bonded substrate, cooling the bonded substrate with a controlled temperature drop and thereafter maintaining the bonded substrate at a temperature suitable for etching, etching the metallic pattern within the bonded substrate, wherein an etchant has access to the metallic pattern via the apertures, forming a void within the bonded substrate, wherein the void comprises micro-features. | 02-27-2014 |
20140076843 | METHOD OF FABRICATING IN-PLANE SWITCHING (IPS) SCREEN ELECTRODE - A method of fabricating an In-Plane Switching (IPS) screen electrode is disclosed. In the method, a first ITO layer is etched, and the etched first ITO layer is annealed. Subsequently, a second ITO layer is etched, and the etched first ITO layer and the etched second ITO layer are concurrently annealed. With this method, the etched first ITO layer is annealed after the first ITO layer is etched, subsequent etching of the second ITO layer will have no influence upon the annealed first ITO layer, thus making it possible to ensure the line widths of the two ITO layers and a spacing between the respective ITO layers to thereby effectively avoid the problem of a short circuit due to a too small spacing between the respective ITO layers. | 03-20-2014 |
20140131307 | Method and Apparatus for Converting Commerical Off-The-Shelf (COTS) Thin Small-Outline Package (TSOP) Components Into Rugged Off-The-Shelf (ROTS) Components - An embodiment of the invention generally relates to a method of converting a commercial off-the-shelf electrical lead to a rugged off-the-shelf electrical lead by laser machining a portion of the electrical lead. The method includes ablating material from the electrical lead of the commercial off-the-shelf component to reduce the moment of inertia or increase the flexibility of the electrical lead. | 05-15-2014 |
20140151326 | LIGHT-TRANSMITTING METAL ELECTRODE AND PROCESS FOR PRODUCTION THEREOF - The present invention provides a light-transmitting metal electrode including a substrate and a metal electrode layer having plural openings. The metal electrode layer also has such a continuous metal part that any pair of point-positions in the part is continuously connected without breaks. The openings in the metal electrode layer are periodically arranged to form plural microdomains. The plural microdomains are so placed that the in-plane arranging directions thereof are oriented independently of each other. The thickness of the metal electrode layer is in the range of 10 to 200 nm. | 06-05-2014 |
20140190932 | SELF-FORMED NANOMETER CHANNEL AT WAFER SCALE - A mechanism is provided for fabricating nanochannels for a nanodevice. Insulating film is deposited on a substrate. A nanowire is patterned on the film. Insulating material is deposited on the nanowire and film. A first circular hole is formed in the insulating material as an inlet, over a first tip of the nanowire to expose the first tip. A second circular hole is formed as an outlet, over a second tip of the nanowire opposite the first tip to expose the second tip. A nanochannel connects the first and second holes by etching away the nanowire via an etchant in the first and the second holes. A first reservoir is attached over the first hole in connection with the nanochannel at a previous location of the first tip. A second reservoir is attached over the second hole in connection with the nanochannel at a previous location of the second tip. | 07-10-2014 |
20140190933 | METHOD OF MANUFACTURING A MAGNETORESISTIVE DEVICE - A method of manufacturing a magnetoresistive-based device includes a metal hard mask that is inert to a top electrode etch chemistry and that has low sputter yield during a magnetic stack sputter. The metal hard mask is patterned by the photo resist and the photo mask is then stripped and the top electrode (overlying magnetic materials of the magnetoresistive-based device) is patterned by the metal hard mask. | 07-10-2014 |
20140197131 | FLUID OSCILLATIONS ON STRUCTURED SURFACES - A device comprising a substrate having a surface that comprises a conductive base layer. The device also comprises fluid-support-structures on the conductive base layer. Each of the fluid-support-structures has at least one dimension of about 1 millimeter or less. Each of the fluid-support-structures is coated with an electrical insulator. The device is configured to oscillate a fluid locatable between tops of the fluid-support-structures and the conductive base layer when a voltage is applied between the conductive base layer and the fluid. | 07-17-2014 |
20140231381 | Methods of Continuously Wet Etching A Patterned Substrate - Metalized web substrate is wet etched in a reaction vessel by contacting with oxidizing and metal complexing agent to remove metal from unpatterned region. Following etching, substrate is rinsed, and rinse is at least partly recycled. Concentrations of oxidizing and metal complexing agents in the etchant bath are maintained by delivering replenishment feeds of each. Concentration of metal in the etchant bath is maintained by discharging some of the etchant bath. Replenishment rates of oxidizing and metal complexing agents and etchant removal rate are determined based at least in part on rate that metal etched from the substrate enters the etchant bath. | 08-21-2014 |
20140231382 | PIEZOELECTRIC DEVICE AND METHOD FOR MANUFACTURING PIEZOELECTRIC DEVICE - A piezoelectric device prevents damage to a piezoelectric thin film caused by etching and the manufacturing cost of the piezoelectric device is reduced. On a surface of a support layer formed on a support substrate, an etching adjustment layer is formed. An etchant flows through etching windows to simultaneously form a through hole through which a portion of a sacrificial layer is exposed to a side of a piezoelectric thin film and an opening through which the etching adjustment layer, which is conductive with a lower electrode, is exposed to the side of the piezoelectric thin film. By making an etchant flow through the through hole, the sacrificial layer is removed. A lead-out wiring is formed between an upper electrode and a bump pad and a lead-out wiring is formed between the conductive etching adjustment layer, which is conductive with the lower electrode, and a bump pad. | 08-21-2014 |
20140238953 | ETCHING AGENT FOR COPPER OR COPPER ALLOY - Object is to provide an etching solution which generates less foam and can etch copper or copper alloy at high selectivity when used in a step of etching copper or copper alloy in an electronic substrate having both of copper or copper alloy and nickel. | 08-28-2014 |
20140251947 | METHOD AND APPARATUS FOR LIGHT INDUCED ETCHING OF GLASS SUBSTRATES IN THE FABRICATION OF ELECTRONIC CIRCUITS - A method of etching a glass substrate using an etchant that is reversibly activated to etch only in precise locations in which such etching is desired and is deactivated when outside of these locations. The method involves exposing a first side of the glass substrate to a mixture of chemical substances that includes a neutralized etchant that is photosensitive. The neutralized etchant is formed by reacting a neutralizer with an etchant. The method also includes transmitting light from a direction of a second side of the glass into the mixture of chemical substances. In response to exposure to this light, the etchant is reversibly released from a bond to the neutralizer to form the etchant on predetermined areas of the first side of the glass, wherein the predetermined areas are defined by the dimension of the light. | 09-11-2014 |
20140299571 | PLASMA PROCESSING METHOD AND PLASMA PROCESSING APPARATUS - Disclosed are a plasma processing method and a plasma processing apparatus which collectively perform etching under the same etching conditions while suppressing a shape abnormality. The multilayer film material has a polysilicon layer, a first metal layer formed on the polysilicon layer, and a hard mask layer which contains a tungsten layer formed on the first metal layer. In the method, plasma is generated by a mixed gas of a chloride-containing gas which contains a compound containing chlorine and silicon, a compound containing chlorine and boron, or a compound containing chlorine and hydrogen, a chlorine-containing gas which contains chlorine, and a processing gas which contains carbon and fluorine, and the hard mask layer is used as an etching mask so as to perform the etching from a top surface of the first metal layer to a bottom surface of the polysilicon layer. | 10-09-2014 |
20140299572 | COMPLIANT MICRO DEVICE TRANSFER HEAD WITH INTEGRATED ELECTRODE LEADS - A compliant micro device transfer head and head array are disclosed. In an embodiment a micro device transfer head includes a spring arm having integrated electrode leads that is deflectable into a space between a base substrate and the spring arm. | 10-09-2014 |
20140312002 | FABRICATION OF TUNNELING JUNCTION FOR NANOPORE DNA SEQUENCING - A mechanism is provided for forming a nanodevice. A reservoir is filled with a conductive fluid, and a membrane is formed to separate the reservoir in the nanodevice. The membrane includes an electrode layer having a tunneling junction formed therein. The membrane is formed to have a nanopore formed through one or more other layers of the membrane such that the nanopore is aligned with the tunneling junction of the electrode layer. The tunneling junction of the electrode layer is narrowed to a narrowed size by electroplating or electroless deposition. When a voltage is applied to the electrode layer, a tunneling current is generated by a base in the tunneling junction to be measured as a current signature for distinguishing the base. When an organic coating is formed on an inside surface of the tunneling junction, transient bonds are formed between the electrode layer and the base. | 10-23-2014 |
20140312003 | FABRICATION OF TUNNELING JUNCTION FOR NANOPORE DNA SEQUENCING - A mechanism is provided for forming a nanodevice. A reservoir is filled with a conductive fluid, and a membrane is formed to separate the reservoir in the nanodevice. The membrane includes an electrode layer having a tunneling junction formed therein. The membrane is formed to have a nanopore formed through one or more other layers of the membrane such that the nanopore is aligned with the tunneling junction of the electrode layer. The tunneling junction of the electrode layer is narrowed to a narrowed size by electroplating or electroless deposition. When a voltage is applied to the electrode layer, a tunneling current is generated by a base in the tunneling junction to be measured as a current signature for distinguishing the base. When an organic coating is formed on an inside surface of the tunneling junction, transient bonds are formed between the electrode layer and the base. | 10-23-2014 |
20150027980 | MANUFACTURING METHOD OF AN APPARATUS FOR THE PROCESSING OF SINGLE MOLECULES - The invention relates to a method for manufacturing an apparatus for the processing of single molecules. According to this method, a self-assembling resist ( | 01-29-2015 |
20150034589 | SYSTEM AND METHOD FOR FORMING PATTERNED COPPER LINES THROUGH ELECTROLESS COPPER PLATING - A method for forming copper on a substrate including inputting a copper source solution into a mixer, inputting a reducing solution into the mixer, mixing copper source solution and the reducing solution to form a plating solution having a pH of greater than about 6.5 and applying the plating solution to a substrate, the substrate including a catalytic layer wherein applying the plating solution to the substrate includes forming a catalytic layer, maintaining the catalytic layer in a controlled environment and forming copper on the catalytic layer. A system for forming copper structures is also disclosed. | 02-05-2015 |
20150083688 | SYSTEM FOR MANUFACTURING ELECTROSURGICAL SEAL PLATES - A system for the manufacture of an end effector assembly which is configured for use with an electrosurgical instrument configured for performing an electrosurgical procedure is provided. The system includes a photolithography module that is configured to etch one or more pockets on a seal surface of the seal plate. A vacuum module is configured to raise, transfer and lower a spacer from a location remote from the pocket(s) on the seal plate to the pocket on the seal plate(s). An adhesive dispensing module is configured to dispense an adhesive into the pocket on the seal plate. An optical module is configured to monitor a volume of the adhesive dispensed within the pocket and monitor placement of the spacer within the pocket. | 03-26-2015 |
20150114926 | ANODE FOILS FOR ELECTROLYTIC CAPACITORS AND METHODS FOR MAKING SAME - Anode foils suitable for use in electrolytic capacitors, including those having multiple anode configurations, have improved strength, reduced brittleness, and increased capacitance compared to conventional anode foils for electrolytic capacitors. Exemplary methods of manufacturing an anode foil suitable for use in an electrolytic capacitor include disposing a resist material in a predetermined pattern on an exposed surface of an anode foil substrate such that a first portion of the exposed surface of the anode foil substrate is covered by the resist material, and a second portion of the exposed surface remains uncovered; polymerizing the resist material; exposing at least the second portion of the exposed surface to one or more etchants so as to form a plurality of tunnels; stripping the polymerized resist material; and widening at least a portion of the plurality of tunnels. The resist material may be deposited, for example, by ink-jet printing, stamping or screen printing. | 04-30-2015 |
20150122771 | Display Device with Touch Panel - A manufacturing method of a touch panel includes the steps of providing a substrate, forming a first conductive film on the substrate, forming a first mask on the first conductive film, etching the first conductive film to form electrode portions and lower intersect portions of the touch panel, forming an insulating film made of a negative resist on the first conductive film, and forming a contact hole above the electrode portion by removing the insulating film. The steps further include forming a second conductive film on the insulating film, forming a second mask on the second conductive film, etching the second conductive film to form an upper intersect portion connected between two adjacent electrode portions via the contact hole and intersecting with the lower intersect portion, and forming protective film on the second conductive film. | 05-07-2015 |
20150136729 | METHOD FOR PRODUCING PIEZOELECTRIC ACTUATOR AND METHOD FOR PRODUCING LIQUID TRANSPORT APPARATUS - A vibration layer is formed by the AD method on a cavity plate before forming pressure chambers, a common electrode is formed on the vibration layer, and a piezoelectric layer is formed on the common electrode by the AD method. Subsequently, the pressure chambers are formed in the cavity plate by the etching. After that, individual electrodes are formed on the piezoelectric layer. Subsequently, the stack of the cavity plate, the vibration layer, the common electrode, the piezoelectric layer, and the individual electrodes is heated at about 850° C. to simultaneously perform the annealing of the piezoelectric layer and the sintering of the individual electrodes and the common electrode. Accordingly, the atoms of the cavity plate are suppressed from being diffused into the driving portions of the piezoelectric layer. | 05-21-2015 |
20150296628 | Biocompatible Bonding Method and Electronics Package Suitable for Implantation - The invention is directed to a method of bonding a hermetically sealed electronics package to an electrode or a flexible circuit and the resulting electronics package, that is suitable for implantation in living tissue, such as for a retinal or cortical electrode array to enable restoration of sight to certain non-sighted individuals. The hermetically sealed electronics package is directly bonded to the flex circuit or electrode by electroplating a biocompatible material, such as platinum or gold, effectively forming a plated rivet-shaped connection, which bonds the flex circuit to the electronics package. The resulting electronic device is biocompatible and is suitable for long-term implantation in living tissue. | 10-15-2015 |
20150325862 | MASK-LESS FABRICATION OF VERTICAL THIN FILM BATTERIES - A method of fabricating a thin film battery may comprise: depositing a first stack of blanket layers on a substrate, the first stack comprising a cathode current collector, a cathode, an electrolyte, an anode and an anode current collector; laser die patterning the first stack to form one or more second stacks, each second stack forming the core of a separate thin film battery; blanket depositing an encapsulation layer over the one or more second stacks; laser patterning the encapsulation layer to open up contact areas to the anode current collectors on each of the one or more second stacks; blanket depositing a metal pad layer over the encapsulation layer and the contact areas; and laser patterning the metal pad layer to electrically isolate the anode current collectors of each of the one or more thin film batteries. For electrically non-conductive substrates, cathode contact areas are opened-up through the substrate. | 11-12-2015 |
20150364293 | METHOD OF MAKING TRANSMISSION ELECTRON MICROSCOPE MICRO-GRID - A method of making a transmission electron microscope micro-grid includes following steps. A carbon nanotube layer is provided, and the carbon nanotube layer includes a first surface and a second surface opposite to each other. A first metal layer is electroplated on the first surface and a second metal layer is electroplated on the second surface. A number of first through holes are formed by etching the first metal layer, and a number of second through holes are formed by etching the second metal layer, wherein the carbon nanotube layer is exposed through the number of first through holes and the number of second through holes. | 12-17-2015 |
20160064647 | SIZE-CONTROLLABLE OPENING AND METHOD OF MAKING SAME - A support structure includes an internal cavity. An elastic membrane extends to divide the internal cavity into a first chamber and a second chamber. The elastic membrane includes a nanometric-sized pin hole extending there through to interconnect the first chamber to the second chamber. The elastic membrane is formed of a first electrode film and a second electrode film separated by a piezo insulating film. Electrical connection leads are provided to support application of a bias current to the first and second electrode films of the elastic membrane. In response to an applied bias current, the elastic membrane deforms by bending in a direction towards one of the first and second chambers so as to produce an increase in a diameter of the pin hole. | 03-03-2016 |
20160118270 | CARRIER AND A METHOD FOR PROCESSING A CARRIER - According to various embodiments, a carrier may include: a hollow chamber spaced apart from a surface of the carrier; and at least one support structure within the hollow chamber connecting a first region of the carrier disposed over the hollow chamber with a second region of the carrier disposed below the hollow chamber, wherein at least a part of a surface of the at least one support structure is spaced apart from an inner surface of the hollow chamber, and wherein the at least one support structure includes an electrically insulating material. | 04-28-2016 |
20160170140 | OPTOELECTRONIC STRUCTURES HAVING MULTI-LEVEL OPTICAL WAVEGUIDES AND METHODS OF FORMING THE STRUCTURES | 06-16-2016 |
20160184819 | SELF-ALIGNED NANOGAP FABRICATION - Disclosed herein is a method comprising: depositing a second electrode of each of a plurality of electrode pairs onto a substrate, through an opening of one or more resist layers; depositing a strip of a sacrificial layer directly on the second electrode through the same opening of the one or more resist layer; depositing a first electrode of each of the plurality of electrode pairs directly on the strip of the sacrificial layer through the same opening of the one or more resist layer; and forming a nanogap channel by removing the strip of the sacrificial layer; wherein the strip of the sacrificial layer is sandwiched between and in direct contact with the first electrode and the second electrode before the strip is removed, and wherein at least a portion of the first electrode directly faces at least a portion of the second electrode. | 06-30-2016 |