Class / Patent application number | Description | Number of patent applications / Date published |
257526000 | With bipolar transistor structure | 38 |
20080230869 | ULTRA-THIN SOI VERTICAL BIPOLAR TRANSISTORS WITH AN INVERSION COLLECTOR ON THIN-BURIED OXIDE (BOX) FOR LOW SUBSTRATE-BIAS OPERATION AND METHODS THEREOF - The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS. | 09-25-2008 |
20090160016 | SEMICONDUCTOR DEVICE - A semiconductor device having a bipolar transistor improved with heat dissipation. A semiconductor device having bipolar transistors formed in a plurality of device forming regions electrically isolated from each other by device isolation trenches traversing the semiconductor layer, in which a device isolation trench for each of unit bipolar transistors connected in parallel is removed and the plurality of unit bipolar transistors connected in series are entirely surrounded with one device isolation trench. | 06-25-2009 |
20090250785 | METHODS OF FORMING A SHALLOW BASE REGION OF A BIPOLAR TRANSISTOR - The disclosed subject matter provides a method of forming a bipolar transistor. The method includes depositing a first insulating layer over a first layer of material that is doped with a dopant of a first type. The first layer is formed over a substrate. The method also includes modifying a thickness of the first oxide layer based on a target dopant profile and implanting a dopant of the first type in the first layer. The dopant is implanted at an energy selected based on the modified thickness of the first insulating layer and the target dopant profile. | 10-08-2009 |
20100001369 | DEVICE LAYOUT FOR GATE LAST PROCESS - A semiconductor device is provided that includes a semiconductor substrate having a first region and a second region, transistors having metal gates formed in the first region, an isolation structure formed in the second region, at least one junction device formed proximate the isolation structure in the second region, and a stopping structure formed overlying the isolation structure in the second region. | 01-07-2010 |
20100025808 | Bipolar Transistor And Method Of Fabricating The Same - The invention provides a bipolar transistor with a reduced collector series resistance integrated in a trench ( | 02-04-2010 |
20100025809 | Integrated Circuit and Method of Forming Sealed Trench Junction Termination - An integrated circuit having a substrate with a first conductivity type of semiconductor material. A buried layer is formed in the substrate. The buried layer has a second conductivity type of semiconductor material. A first semiconductor layer is formed over the buried layer. The first semiconductor layer has the second conductivity type of semiconductor material. A trench is formed through the first semiconductor layer and buried layer and extends into the substrate. The trench is lined with an insulating layer and filled with an insulating material. A second semiconductor layer is formed in the first semiconductor layer. The second semiconductor layer has the first conductivity type of semiconductor material. A third semiconductor layer is formed in the second semiconductor layer. The third semiconductor layer has the second conductivity type of semiconductor material. The first, second, and third semiconductor layers form the collector, base, and emitter of a bipolar transistor. | 02-04-2010 |
20110057289 | Ultrashallow Emitter Formation Using ALD and High Temperature Short Time Annealing - An integrated circuit containing a bipolar transistor including an emitter diffused region with a peak doping density higher than 1·10 | 03-10-2011 |
20110140233 | Parasitic vertical PNP bipolar transistor and its fabrication method in BiCMOS process - A parasitic vertical PNP bipolar transistor in BiCMOS process comprises a collector, a base and an emitter. The collector is formed by active region with p-type ion implanting layer (P type well in NMOS). It connects a P-type conductive region, which formed in the bottom region of shallow trench isolation (STI). The collector terminal connection is through the P-type buried layer and the adjacent active region. The base is formed by N type ion implanting layer above the collector which shares a N-type lightly doped drain (NLDD) implanting of NMOS. Its connection is through the N-type poly on the base region. The emitter is formed by the P-type epitaxy layer on the base region with heavy p-type doped, and connected by the extrinsic base region of NPN bipolar transistor device. This invention also includes the fabrication method of this parasitic vertical PNP bipolar transistor in BiCMOS process. And this PNP bipolar transistor can be used as the I/O (input/output) device in high speed, high current and power gain BiCMOS circuits. It also provides a device option with low cost. | 06-16-2011 |
20110156202 | Parasitic Vertical PNP Bipolar Transistor in BICMOS Process - A parasitic vertical PNP device in one type of BiCMOS process with shallow trench isolation (STI) comprises a collector formed by a p type impurity ion implantation layer inside active area, the bottom of collector connects to a p type buried layer, the p type pseudo buried layer is formed in bottom of shallow trench at both sides of collector active region through ion implantation, deep contacts through field oxide to connect pseudo buried layers and to pick up the collector; a base, formed by n type impurity ion implantation layer which sits on top of above stated collector; an emitter, a p type epitaxy layer lies above base and is connected out directly by a metal contact. Part of the p type epitaxy layer is converted into n type, which serves as connection path of base. Present invented PNP can be used as output device of BiCMOS high frequency circuit. It has a small device area and conduction resistance. | 06-30-2011 |
20110254120 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: a substrate of a first conductivity type; a first diffusion layer of a second conductivity type formed on the substrate; a second diffusion layer of the first conductivity type formed in an upper part of the first diffusion layer; a third diffusion layer of the second conductivity type formed in an upper part of the second diffusion layer; a fourth diffusion layer of the second conductivity type formed in the upper part of the first diffusion layer; and a fifth diffusion layer of the first conductivity type formed below the third diffusion layer. A sum of a shortest distance from the third diffusion layer to the fifth diffusion layer and a shortest distance from the fifth diffusion layer or the lower end of the first diffusion layer to the fourth diffusion layer is smaller than a shortest distance from the third diffusion layer to the fourth diffusion layer. | 10-20-2011 |
20110309471 | TRANSISTOR STRUCTURE WITH A SIDEWALL-DEFINED INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION AND METHOD OF FORMING THE STRUCTURE - Disclosed are embodiments of an improved transistor structure (e.g., a bipolar transistor (BT) structure or heterojunction bipolar transistor (HBT) structure) and a method of forming the transistor structure. The structure embodiments can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance C | 12-22-2011 |
20120313216 | COMPLEMENTARY BIPOLAR INVERTER - An example embodiment is a complementary transistor inverter circuit. The circuit includes a semiconductor-on-insulator (SOI) substrate, a lateral PNP bipolar transistor fabricated on the SOI substrate, and a lateral NPN bipolar transistor fabricated on the SOI substrate. The lateral PNP bipolar transistor includes a PNP base, a PNP emitter, and a PNP collector. The lateral NPN bipolar transistor includes a NPN base, a NPN emitter, and a NPN collector. The PNP base, the PNP emitter, the PNP collector, the NPN base, the NPN emitter, and the NPN collector abut the buried insulator of the SOI substrate. | 12-13-2012 |
20130099351 | BIPOLAR TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A bipolar transistor is disclosed, which includes a collector region, a base region, an emitter region and field plates. Each field plate is present in a structure of a flat sidewall covering one side face of the active region so that it also covers the collector region from one side. The field plate has its surface parallel to the side face of the active region and is isolated from the side face of the active region by a pad oxide layer. The field plate has its top lower than the surface of the active region. The bipolar transistor is capable of improving the breakdown voltage of the device without increasing the collector resistance or deteriorating the frequency characteristic. A method of manufacturing bipolar transistor is also disclosed. | 04-25-2013 |
20130134550 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to the present invention includes a p-type semiconductor substrate, a first n-type collector diffusion layer formed in the p-type semiconductor substrate, a deep trench formed in the p-type semiconductor substrate so as to surround the first n-type collector diffusion layer, a p-type channel stopper layer formed beneath the deep trench, and an n-type diffusion layer formed between a sidewall of the deep trench and the first n-type collector diffusion layer. | 05-30-2013 |
20130328162 | HOMO-JUNCTION DIODE STRUCTURES USING FIN FIELD EFFECT TRANSISTOR PROCESSING - Diodes and bipolar junction transistors (BJTs) are formed in IC devices that include fin field-effect transistors (FinFETs) by utilizing various process steps in the FinFET formation process. The diode or BJT includes an isolated fin area and fin array area having n-wells having different depths and a p-well in a portion of the fin array area that surrounds the n-well in the isolated fin area. The n-wells and p-well for the diodes and BJTs are implanted together with the FinFET n-wells and p-wells. | 12-12-2013 |
20140008758 | COMPLEMENTARY BIPOLAR INVERTER - An example embodiment is a complementary transistor inverter circuit. The circuit includes a semiconductor-on-insulator (SOI) substrate, a lateral PNP bipolar transistor fabricated on the SOI substrate, and a lateral NPN bipolar transistor fabricated on the SOI substrate. The lateral PNP bipolar transistor includes a PNP base, a PNP emitter, and a PNP collector. The lateral NPN bipolar transistor includes a NPN base, a NPN emitter, and a NPN collector. The PNP base, the PNP emitter, the PNP collector, the NPN base, the NPN emitter, and the NPN collector abut the buried insulator of the SOI substrate. | 01-09-2014 |
20140117493 | ISOLATION SCHEME FOR BIPOLAR TRANSISTORS IN BICMOS TECHNOLOGY - Methods for fabricating a device structure, as well as device structures and design structures for a bipolar junction transistor. The device structure includes a collector region in a substrate, a plurality of isolation structures extending into the substrate and comprised of an electrical insulator, and an isolation region in the substrate. The isolation structures have a length and are arranged with a pitch transverse to the length such that each adjacent pair of the isolation structures is separated by a respective section of the substrate. The isolation region is laterally separated from at least one of the isolation structures by a first portion of the collector region. The isolation region laterally separates a second portion of the collector region from the first portion of the collector region. The device structure further includes an intrinsic base on the second portion of the collector region and an emitter on the intrinsic base. The emitter has a length transversely oriented relative to the length of the isolation structures. | 05-01-2014 |
20140159195 | DECOUPLING CAPACITOR AND METHOD OF MAKING SAME - A semiconductor substrate has at least two active regions, each having at least one active device that includes a gate electrode layer, and a shallow trench isolation (STI) region between the active regions. A decoupling capacitor comprises first and second dummy conductive patterns formed in the same gate electrode layer over the STI region. The first and second dummy conductive regions are unconnected to any of the at least one active device. The first dummy conductive pattern is connected to a source of a first potential. The second dummy conductive pattern is connected to a source of a second potential. A dielectric material is provided between the first and second dummy conductive patterns. | 06-12-2014 |
20140319648 | INTEGRATED CIRCUIT ON SOI COMPRISING A TRANSISTOR PROTECTING FROM ELECTROSTATIC DISCHARGES - An integrated circuit includes first and second electronic components, a buried UTBOX insulating layer, first and second ground planes plumb with the first and second electronic components, first and second wells, first and second biasing electrodes making contact with the first and second wells and with the first and second ground planes, a third electrode making contact with the first well, a first trench isolation separating the first and third electrodes and extending through the buried insulating layer as far as into the first well, and a second trench isolation that isolates the first electrode from the first component, and that does not extend as far as the interface between the first ground plane and the first well. | 10-30-2014 |
20140327106 | BIPOLAR JUNCTION TRANSISTORS WITH SELF-ALIGNED TERMINALS - Device structures, fabrication methods, and design structures for a bipolar junction transistor. A semiconductor material layer is formed on a substrate and a mask layer is formed on the semiconductor material layer. The mask layer is patterned to form a plurality of openings to the semiconductor material layer. After the mask layer is formed and patterned, the semiconductor material layer is etched at respective locations of the openings to define a first trench, a second trench separated from the first trench by a first section of the semiconductor material layer defining a terminal of the bipolar junction transistor, and a third trench separated from the first trench by a second section of the semiconductor material layer defining an isolation pedestal. A trench isolation region is formed at a location in the substrate that is determined at least in part using the isolation pedestal as a positional reference. | 11-06-2014 |
20150008558 | SELF-ALIGNED BIPOLAR JUNCTION TRANSISTORS - Device structures and design structures for a bipolar junction transistor. An intrinsic base is formed on the substrate, a terminal is formed on the intrinsic base, and an extrinsic base is formed that is arranged in juxtaposition with the intrinsic base on the substrate. The intrinsic base and terminal are respectively comprised of first and second semiconductor materials. | 01-08-2015 |
20150008559 | BIPOLAR JUNCTION TRANSISTOR WITH MULTIPLE EMITTER FINGERS - Bipolar junction transistors and design structures for a bipolar junction transistor. The bipolar junction transistor may include a plurality of emitters that are arranged in distinct emitter fingers. A silicide layer is formed that covers an extrinsic base layer of the bipolar junction transistor and that fills the gaps between adjacent emitters. Non-conductive spacers on the emitter sidewalls electrically insulate the emitters from the silicide layer. The emitters extend through the extrinsic base layer and the silicide layer to contact the intrinsic base layer. The emitters may be formed using sacrificial emitter pedestals in a replacement-type process. | 01-08-2015 |
20150048478 | TRENCH ISOLATION FOR BIPOLAR JUNCTION TRANSISTORS IN BICMOS TECHNOLOGY - Device structures and design structures for a bipolar junction transistor. A first isolation structure is formed in a substrate to define a boundary for a device region. A collector is formed in the device region, and a second isolation structure is formed in the device region. The second isolation structure defines a boundary for the collector. The second isolation structure is laterally positioned relative to the first isolation structure to define a section of the device region between the first and second isolation structures. | 02-19-2015 |
20150054123 | SELF-ALIGNED EMITTER-BASE REGION - Aspects of the invention provide a method of forming a bipolar junction transistor. The method includes: providing a semiconductor substrate including a uniform silicon nitride layer over an emitter pedestal, and a base layer below the emitter pedestal; applying a photomask at a first end and a second end of a base region; and performing a silicon nitride etch with the photomask to simultaneously form silicon nitride spacers adjacent to the emitter pedestal and exposing the base region of the bipolar junction transistor. The silicon nitride etch may be an end-pointed etch. | 02-26-2015 |
20150097265 | Semiconductor Device with Buried Conduction Path - A device includes a semiconductor substrate, emitter and collector regions disposed in the semiconductor substrate, having a first conductivity type, and laterally spaced from one another, and a composite base region disposed in the semiconductor substrate, having a second conductivity type, and including a base contact region, a buried region through which a buried conduction path between the emitter and collector regions is formed during operation, and a base link region electrically connecting the base contact region and the buried region. The base link region has a dopant concentration level higher than the buried region and is disposed laterally between the emitter and collector regions. | 04-09-2015 |
20150115399 | BIPOLAR JUNCTION TRANSISTORS WITH SELF-ALIGNED TERMINALS - Device structures, fabrication methods, and design structures for a bipolar junction transistor. A semiconductor material layer is formed on a substrate and a mask layer is formed on the semiconductor material layer. The mask layer is patterned to form a plurality of openings to the semiconductor material layer. After the mask layer is formed and patterned, the semiconductor material layer is etched at respective locations of the openings to define a first trench, a second trench separated from the first trench by a first section of the semiconductor material layer defining a terminal of the bipolar junction transistor, and a third trench separated from the first trench by a second section of the semiconductor material layer defining an isolation pedestal. A trench isolation region is formed at a location in the substrate that is determined at least in part using the isolation pedestal as a positional reference. | 04-30-2015 |
20160005843 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - By using an SOI substrate in which a front surface-side semiconductor layer, an insulating layer, and a back surface-side semiconductor layer are laminated in this order, vertical semiconductor devices are mass-produced. A process to be executed on a front surface of the SOI substrate is executed on the front surface. A back surface of the SOI substrate is etched so that the back surface-side semiconductor layer and the insulating layer are removed and a back surface of the front surface-side semiconductor layer is exposed. A process to be executed on the exposed back surface of the front surface-side semiconductor layer is executed on the back surface. A thickness of the front surface-side semiconductor layer of the SOI substrate can be accurately controlled, and the semiconductor devices having a semiconductor layer with the same thickness as the thickness of the front surface-side semiconductor layer are mass-produced. | 01-07-2016 |
20160013177 | ESD PROTECTION DEVICE AND RELATED FABRICATION METHODS | 01-14-2016 |
20160043202 | SELF-ALIGNED BIPOLAR JUNCTION TRANSISTOR HAVING SELF-PLANARIZING ISOLATION RAISED BASE STRUCTURES - A collector region is formed between insulating shallow trench isolation regions within a substrate. A base material is epitaxially grown on the collector region and the shallow trench isolation regions. The base material forms a base region on the collector region and extrinsic base regions on the shallow trench isolation regions. Further, a sacrificial emitter structure is patterned on the base region and sidewall spacers are formed on the sacrificial emitter structure. Planar raised base structures are epitaxially grown on the base region and the extrinsic base regions, and the upper layer of the raised base structures is oxidized. The sacrificial emitter structure is removed to leave an open space between the sidewall spacers and an emitter is formed within the open space between the sidewall spacers. The upper layer of the raised base structures comprises a planar insulator electrically insulating the emitter from the raised base structures. | 02-11-2016 |
20160049492 | VERTICAL P-TYPE, N-TYPE, P-TYPE (PNP) JUNCTION INTEGRATED CIRCUIT (IC) STRUCTURE, AND METHODS OF FORMING - Various particular embodiments include a method of amorphizing a portion of silicon underneath the N+ base section of a PNP transistor structure. After amorphizing, the method can include selectively etching that implant-amorphized silicon to trim the collector-base area and collector-base junction. The selective etching is enhanced because the unimplanted silicon region etches at a distinct rate than the implant-amorphized silicon, allowing for control over the trimming of the collector-base junction. | 02-18-2016 |
20160049501 | Method to build vertical PNP in a BICMOS technology with improved speed - Various particular embodiments include an integrated circuit (IC) structure including: a stack region; and a silicon substrate underlying and contacting the stack region, the silicon substrate including: a silicon region including a doped subcollector region; a set of isolation regions overlying the silicon region; a base region between the set of isolation regions and below the stack region, the base region including an intrinsic base contacting the stack region, an extrinsic base contacting the intrinsic base and the stack region, and an amorphized extrinsic base contact region contacting the extrinsic base; a collector region between the set of isolation regions; an undercut collector-base region between the set of isolation regions and below the base region; and a collector contact region contacting the collector region under the intrinsic base and the collector-base region via the doped subcollector region. | 02-18-2016 |
20160086934 | LIL ENHANCED ESD-PNP IN A BCD - Disclosed is a PNP ESD integrated circuit, including a substrate, an active region formed within the substrate, the active region including at least one base region of a second conductivity type, a plurality of collector regions of a first conductivity type formed within the active region, a plurality of emitter regions of the first conductivity type formed within the active region, and a local interconnect layer (LIL) contacting the plurality of emitter regions and the plurality of collector regions, the LIL including cooling fin contacts formed on the collector regions to enhance the current handling capacity of the collector regions. | 03-24-2016 |
20160087068 | LATERAL BIPOLAR TRANSISTOR WITH BASE EXTENSION REGION - A method of forming a base extension region for a lateral bipolar transistor. The base extension region may include forming an extrinsic base on an intrinsic base layer, the intrinsic base layer is on an insulator layer, a top portion of the intrinsic base layer is exposed on opposite sides of the extrinsic base; forming a base extension region by recessing the exposed top portion of the intrinsic base layer to a recessed surface, the recessed surface is above a top surface of the insulator layer, the base extension region is a region of the intrinsic base layer remaining above the recessed surface; and forming an emitter/collector in the intrinsic base layer, an intrinsic base is a portion of the intrinsic base layer between the emitter/collector, the emitter/collector is a distance from the extrinsic base of no less than a thickness of the base extension region. | 03-24-2016 |
20160111411 | STRUCTURE AND METHOD FOR ENHANCING ROBUSTNESS OF ESD DEVICE - A method and structure of improving the robustness of an electrostatic discharge (ESD) protection device is disclosed. One aspect of the instant disclosure provides a semiconductor structure that comprises: a first well structure; a second well structure arranged adjacent to the isolation structure in the substrate, a diffusion region respectively disposed in the first and the second well structures; an isolation structure arranged between the well structures and laterally separating the diffusion regions; and a partition structure arranged in the isolation structure. The partition structure affects a steeper slope on a lateral surface of the isolation structure bordering at least one of the diffusion regions, thereby modifying a ballasting characteristic of the isolation structure. | 04-21-2016 |
20160190292 | BIPOLAR TRANSISTOR WITH EXTRINSIC BASE REGION AND METHODS OF FABRICATION - The present disclosure relates to integrated circuit (IC) structures and methods of forming the same. An IC structure according to the present disclosure can include: a doped substrate region adjacent to an insulating region; a crystalline base structure including: an intrinsic base region located on and contacting the doped substrate region, the intrinsic base region having a first thickness; an extrinsic base region adjacent to the insulating region, wherein the extrinsic base region has a second thickness greater than the first thickness; a semiconductor layer located on the intrinsic base region of the crystalline base structure; and a doped semiconductor layer located on the semiconductor layer. | 06-30-2016 |
20160197167 | Vertical P-Type, N-Type, P-Type (PNP) Junction Integrated Circuit (IC) Structure | 07-07-2016 |
20160204233 | INTEGRATED CIRCUIT HEAT DISSIPATION USING NANOSTRUCTURES | 07-14-2016 |
20170236817 | ESD PROTECTION DEVICE | 08-17-2017 |