Entries |
Document | Title | Date |
20080197443 | Semiconductor Substrate Comprising a Pn-Junction and Method For Producing Said Substrate - An SOI substrate comprising a carrier substrate, a dielectric layer and a semiconductor layer. A continuous pn junction is realized in the semiconductor layer, which pn junction can be produced by applying differently doped partial layers on the SOI substrate. In this way, it is possible to use an SOI substrate for producing semiconductor components and, in particular, rear side diodes. | 08-21-2008 |
20080197444 | INTEGRATED CIRCUIT AND METHOD INCLUDING AN ISOLATION ARRANGEMENT - An integrated circuit and method including an isolation arrangement. One embodiment provides a substrate having trenches and mesa regions and also auxiliary structures on the mesa regions. A first isolation structure covers side walls and a bottom region of the trenches and at least partially side walls of the auxiliary structure. A liner on the first isolation structure fills the trenches and gaps between the auxiliary structures with a second isolation structure; and the second isolation structure is pulled back, wherein upper sections of the liner are uncovered. | 08-21-2008 |
20080197445 | Isolation and termination structures for semiconductor die - Various integrated circuit devices, including a lateral DMOS transistor, a quasi-vertical DMOS transistor, a junction field-effect transistor (JFET), a depletion-mode MOSFET, and a diode, are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench. Various techniques for terminating the isolation structure by extending the floor isolation region beyond the trench, using a guard ring, and a forming a drift region are described. | 08-21-2008 |
20080197446 | Isolated diode - Various integrated circuit devices, in particular a diode, are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench. Various techniques for terminating the isolation structure by extending the floor isolation region beyond the trench, using a guard ring, and a forming a drift region are described. | 08-21-2008 |
20080203520 | Isolation structure for semiconductor integrated circuit substrate - Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of the isolation structures are coplanar with the surface of the substrate. Field doping regions may be formed beneath the field oxide regions. To meet the demands of different devices, the isolation structures may have varying widths and depths. | 08-28-2008 |
20080211054 | METHODS FOR FORMING GERMANIUM-ON-INSULATOR SEMICONDUCTOR STRUCTURES USING A POROUS LAYER AND SEMICONDUCTOR STRUCTURES FORMED BY THESE METHODS - A semiconductor structure that includes a monocrystalline germanium-containing layer, preferably substantially pure germanium, a substrate, and a buried insulator layer separating the germanium-containing layer from the substrate. A porous layer, which may be porous silicon, is formed on a substrate and a germanium-containing layer is formed on the porous silicon layer. The porous layer may be converted to a layer of oxide, which provides the buried insulator layer. Alternatively, the germanium-containing layer may be transferred from the porous layer to an insulating layer on another substrate. After the transfer, the insulating layer is buried between the latter substrate and the germanium-containing layer. | 09-04-2008 |
20080211055 | Utilizing Sidewall Spacer Features to Form Magnetic Tunnel Junctions in an Integrated Circuit - Novel methods for reliably and reproducibly forming magnetic tunnel junctions in integrated circuits are described. In accordance with aspects of the invention, sidewall spacer features are utilized during the processing of the film stack. Advantageously, these sidewall spacer features create a tapered masking feature which helps to avoid byproduct redeposition during the etching of the MTJ film stack, thereby improving process yield. Moreover, the sidewall spacer features may be used as encapsulating layers during subsequent processing steps and as vertical contacts to higher levels of metallization. | 09-04-2008 |
20080217728 | Fusion bonding process and structure for fabricating silicon-on-insulator (SOI) semiconductor devices - A method of fabricating a semiconductor-on-insulator device including: providing a first semiconductor wafer having an about 200 angstrom thick oxide layer thereover; etching the first semiconductor wafer to raise a pattern therein; doping the raised pattern of the first semiconductor wafer through the about 200 angstrom thick oxide layer; providing a second semiconductor wafer having an oxide thereover; and, bonding the first semiconductor wafer oxide to the second semiconductor wafer oxide at an elevated temperature. | 09-11-2008 |
20080224253 | SEMICONDUCTOR DEVICE - A semiconductor device receiving as input a radio frequency signal having a frequency of 500 MHz or more and a power of 20 dBm or more is provided. The semiconductor device includes: a silicon substrate; a silicon oxide film formed on the silicon substrate; a radio frequency interconnect provided on the silicon oxide film and passing the radio frequency signal; a fixed potential interconnect provided on the silicon oxide film and placed at a fixed potential; and an acceptor-doped layer. The acceptor-doped layer is formed in a region of the silicon substrate. The region is in contact with the silicon oxide film. The acceptor-doped layer is doped with acceptors. | 09-18-2008 |
20080224254 | Glass-based SOI structures - Semiconductor-on-insulator (SOI) structures, including large area SOI structures, are provided which have one or more regions composed of a layer of a substantially single-crystal semiconductor (e.g., doped silicon) attached to a support substrate composed of an oxide glass or an oxide glass-ceramic. The oxide glass or oxide glass-ceramic is preferably transparent and preferably has a strain point of less than 1000° C., a resistivity at 250° C. that is less than or equal to 10 | 09-18-2008 |
20080224255 | SUBGROUND RULE STI FILL FOR HOT STRUCTURE - This invention provides a hybrid orientation (HOT) semiconductor-on-insulator (SOI) structure having an isolation region, e.g. a shallow trench isolation region (STI), and a method for forming the STI structure that is easy to control. The method of forming the isolation region includes an etch of the insulating material, selective to the semiconductor material, followed by an etch of the semiconductor material, selective to the insulating material, and then filling any high aspect ratio gaps with a CVD oxide, and filling the remainder of the STI with an HDP oxide. | 09-18-2008 |
20080224256 | SEMICONDUCTOR-ON-INSULATOR(SOI) STRUCTURES INCLUDING GRADIENT NITRIDED BURIED OXIDE (BOX) - A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer | 09-18-2008 |
20080237778 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device having a silicon-on-insulator region and a bulk region in a same semiconductor substrate, the method includes: (a) etching the semiconductor substrate in the silicon-on-insulator region so as to form a concave; (b) forming a first semiconductor layer and subsequently a second semiconductor layer on the semiconductor substrate in the silicon-on-insulator region, so as to bury the concave; (c) etching the second semiconductor layer and the first semiconductor layer partially, so as to form a trench which exposes a side surface of the first semiconductor substrate in the silicon-on-insulator region; (d) etching the first semiconductor layer through the trench with an etching condition in which the first semiconductor layer is easier to be etched than the second semiconductor layer, so as to form a cavity between the semiconductor substrate and the second semiconductor layer in the silicon-on-insulator region; and (e) forming a buried insulating film inside the cavity. | 10-02-2008 |
20080251878 | STRUCTURE INCORPORATING SEMICONDUCTOR DEVICE STRUCTURES FOR USE IN SRAM DEVICES - Device structures embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes static random access memory (SRAM) devices. The design structure includes a dielectric region disposed between first and second semiconductor regions and a gate conductor structure extending between the first and second semiconductor regions. The gate conductor structure has a first sidewall overlying the first semiconductor region. The design structure further comprises an electrically connective bridge extending across the first semiconductor region. A portion of the electrically connective bridge electrically connects a impurity-doped region in the first semiconductor region with the first sidewall of the gate conductor structure. | 10-16-2008 |
20080251879 | Method for Manufacturing Simox Substrate and Simox Substrate Obtained by this Method - Heavy metal contamination in a device process can be efficiently trapped in a substrate. | 10-16-2008 |
20080251880 | MIXED ORIENTATION AND MIXED MATERIAL SEMICONDUCTOR-ON-INSULATOR WAFER - The present disclosure relates, generally, to a semiconductor substrate with a planarized surface comprising mixed single-crystal orientation regions and/or mixed single-crystal semiconductor material regions, where each region is electrically isolated. In accordance with one embodiment of the disclosure CMOS devices on SOI regions are manufactured on semiconductors having different orientations. According to another embodiment, an SOI device is contemplated as having a plurality of semiconductor regions having at least one of a different semiconductor material, crystalline lattice constant or lattice strain. Methods and processes for fabricating the different embodiments of the invention is also disclosed. | 10-16-2008 |
20080251881 | SEMICONDUCTOR DEVICE WITH DOUBLE BARRIER FILM - A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has a bottom in the second barrier film. The bottom has a width greater than a trench made in the first insulation layer, as measured in a direction crossing the widthwise direction of the trench. The lower contact hole penetrates the first insulation layer and first barrier film, communicates with the first contact hole via the trench and is provided on the diffusion layer. The upper portion of the lower contact hole has the same width as the trench. The contact plug is provided in the upper contact hole and lower contact hole. | 10-16-2008 |
20080277755 | Filling of Insulation Trenches Using Cmos-Standard Processes for Creating Dielectrically Insulated Areas on a Soi Disk - Insulating trenches isolate regions of a semiconductor layer and include hermetically sealed voids. After forming a trench, a first fill of SiO | 11-13-2008 |
20080283958 | Semiconductor device and method for manufacturing the same - It is an object to achieve high performance of a semiconductor integrated circuit depending on not only a microfabrication technique but also another way and to achieve low power consumption of a semiconductor integrated circuit. A semiconductor device is provided in which a crystal orientation or a crystal axis of a single-crystalline semiconductor layer for a MISFET having a first conductivity type is different from that of a single-crystalline semiconductor layer for a MISFET having a second conductivity type. A crystal orientation or a crystal axis is such that mobility of carriers traveling in a channel length direction is increased in each MISFET. With such a structure, mobility of carriers flowing in a channel of a MISFET is increased, and a semiconductor integrated circuit can be operated at higher speed. Further, low voltage driving becomes possible, and low power consumption can be achieved. | 11-20-2008 |
20080290445 | Method for manufacturing a semiconductor body with a trench and semiconductor body with a trench - A method for manufacturing a semiconductor body with a trench comprises the steps of etching the trench ( | 11-27-2008 |
20080296724 | Semiconductor substrate and manufacturing method of semiconductor device - To provide a semiconductor substrate including a crystalline semiconductor layer which is suitable for practical use, even if a material different from that of the semiconductor layer is used for a supporting substrate, and a semiconductor device using the semiconductor substrate. The semiconductor substrate includes a bonding layer which forms a bonding plane, a barrier layer formed of an insulating material containing nitrogen, a relief layer which is formed of an insulating material that includes nitrogen at less than 20 at. % and hydrogen at 1 at. % to 20 at. %, and an insulating layer containing a halogen, between a supporting substrate and a single-crystal semiconductor layer. The semiconductor device includes the above-described structure at least partially, and a gate insulating layer formed by a microwave plasma CVD method using SiH | 12-04-2008 |
20080303115 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor memory device includes a semiconductor substrate having a dummy cell region adjacent to a memory cell region, a plurality of memory cell transistors, a selective gate transistor, a peripheral circuit transistor, a selective gate line, a contact plug, a dummy contact plug formed in an element forming region of the memory cell region adjacent to the selective gate line, and a spacer insulating film formed on a sidewall of the peripheral circuit transistor. The sidewall of the selective gate electrode is formed with no spacer insulating film, and the selective gate line has a sidewall facing an region of the dummy cell region in which the dummy contact plug is formed, except for the sidewall of the selective gate electrode. The sidewall of the selective gate line is formed with a spacer insulating film. | 12-11-2008 |
20080303116 | SEMICONDUCTOR ON INSULATOR APPARATUS - A method and apparatus for producing a relatively thin, relatively uniform semiconductor layer which has improved carrier mobility. In an embodiment, a lattice-matched insulator layer is formed on a semiconductor substrate, and a lattice-matched semiconductor layer is formed on the insulator layer to form a relatively thin, relatively uniform semiconductor on insulator apparatus. In embodiments of the method and apparatus, energy band characteristics may be used to facilitate the extraction of the well-region minority carriers. | 12-11-2008 |
20080308896 | Integrated circuit device comprising a gate electrode structure and corresponding method of fabrication - The present invention provides an integrated circuit device comprising a semiconductor substrate and a gate electrode structure on the semiconductor substrate having at least one insulating layer of dielectric material on said semiconductor substrate and a metal layer on said at least one insulating layer, said metal layer containing niobium (Nb), vanadium (V), chromium (Cr), tungsten (W) and/or molybdenum (Mo). | 12-18-2008 |
20080315347 | PROVIDING GAPS IN CAPPING LAYER TO REDUCE TENSILE STRESS FOR BEOL FABRICATION OF INTEGRATED CIRCUITS - Fabricating an integrated circuit using a cap layer that includes one or more gaps or voids. The gaps or voids are provided prior to performing deposition and cure for an inter-layer dielectric (ILD) layer adjoining the cap layer. The gaps or voids reduce and prevent tensile stress buildup by allowing for stress relaxation, hence preventing catastrophic failure of the integrated circuit. | 12-25-2008 |
20080315348 | Pitch by Splitting Bottom Metallization Layer - An integrated circuit structure includes a semiconductor substrate; a first bottom metallization (M1) layer over the semiconductor substrate; a second M1 layer over the first M1 layer, wherein metal lines in the first and the second M1 layer have widths of greater than about a minimum feature size; and vias connecting the first and the second M1 layers. | 12-25-2008 |
20080315349 | Method for Manufacturing Bonded Wafer and Bonded Wafer - The present invention provides a method for manufacturing a bonded wafer prepared by bonding a base wafer and a bond wafer, comprising at least a step of etching an oxide film in a terrace region in an outer periphery of the bonded wafer wherein the oxide film in the terrace region is etched by spin-etching with holding and spinning the bonded wafer. Thereby, there is provided a method for manufacturing a bonded wafer in which an oxide film formed in a terrace region of a base wafer is efficiently etched without removing an oxide film on the back surface of the base wafer. | 12-25-2008 |
20080315350 | Method for manufacturing semiconductor substrate, and semiconductor device - It is an object to form single-crystalline semiconductor layers with high mobility over approximately the entire surface of a glass substrate even when the glass substrate is increased in size. A first single-crystalline semiconductor substrate is bonded to a substrate having an insulating surface, the first single-crystalline semiconductor substrate is separated such that a first single-crystalline semiconductor layer is left remaining over the substrate having an insulating surface, a second single-crystalline semiconductor substrate is bonded to the substrate having an insulating surface so as to overlap with at least part of the first single-crystalline semiconductor layer provided over the substrate having an insulating surface, and the second single-crystalline semiconductor substrate is separated such that a second single-crystalline semiconductor layer is left remaining over the substrate having an insulating surface. | 12-25-2008 |
20090001501 | Fiber Soi Substrate, Semiconductor Device Using Same and Method for Manufacturing Same - The present invention provides a SOI substrate that can realize a composite device formed of a MOS integrated circuit and a passive device and can reduce a size and a manufacturing cost of a semiconductor device. | 01-01-2009 |
20090001502 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion of the workpiece. An isolation ring structure is disposed within the top portion of the workpiece extending completely through at least a portion of the buried layer, the isolation ring structure comprising a ring having an interior region. A diffusion confining structure is disposed within the interior region of the isolation ring structure. A conductive region is disposed within the top portion of the workpiece within a portion of the interior of the isolation ring structure, the conductive region comprising at least one dopant element implanted and diffused into the top portion of the workpiece. The diffusion confining structure defines at least one edge of the conductive region, and the conductive region is coupled to the buried layer. | 01-01-2009 |
20090001503 | SEMICONDUCTOR DEVICE HAVING FLOATING BODY ELEMENT AND BULK BODY ELEMENT AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a floating body element and a bulk body element and a manufacturing method thereof are provided. The semiconductor device includes a substrate having a bulk body element region and floating body element regions. An isolation region defining an active region of the bulk body element region of the substrate and defining first buried patterns and first active patterns, which are sequentially stacked on a first element region of the floating body element regions of the substrate is provided. A first buried dielectric layer interposed between the first buried patterns and the substrate and between the first buried patterns and the first active patterns is provided. | 01-01-2009 |
20090014828 | SEMICONDUCTOR MEMORY DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR MEMORY DEVICE - In a method of manufacturing a semiconductor memory device, an opening is made in a part of an insulating film formed on a silicon substrate. An amorphous silicon thin film is formed on the insulating film in which the opening has been made and inside the opening. Then, a monocrystal is solid-phase-grown in the amorphous silicon thin film, with the opening as a seed, thereby forming a monocrystalline silicon layer. Then, the monocrystalline silicon layer is heat-treated in an oxidizing atmosphere, thereby thinning the monocrystalline silicon layer and reducing the defect density. Then, a memory cell array is formed on the monocrystalline silicon layer which has been thinned and whose defect density has been reduced. | 01-15-2009 |
20090020845 | SHALLOW TRENCH ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES INCLUDING DOPED OXIDE FILM LINERS AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a substrate having a trench, a sidewall liner that covers inner walls of the trench, a doped oxide film liner on the sidewall liner in the trench, and a gap-fill insulating film that buries the trench on the doped oxide film liner. In order to form the doped oxide film liner, an oxide film liner is doped with a dopant under a plasma atmosphere. Related methods are also disclosed. | 01-22-2009 |
20090020846 | DIODE FOR ADJUSTING PIN RESISTANCE OF A SEMICONDUCTOR DEVICE - A diode comprises a P-type well formed in a semiconductor substrate, at least one N-type impurity doping area formed in the P-type well, an isolation area formed to surround the N-type impurity doping area, a P-type impurity doping area formed to surround the isolation area, first contacts formed in the N-type impurity doping area in a single row or a plurality of rows, and second contacts formed in the P-type impurity doping area in a single row or a plurality of rows, wherein pin resistance can be adjusted through changing any one of a distance between the N-type impurity doping area and the P-type impurity doping area, a contact pitch between the first contacts, and a contact pitch between the second contacts. | 01-22-2009 |
20090051001 | ISOLATED VERTICAL POWER DEVICE STRUCTURE WITH BOTH N-DOPED AND P-DOPED TRENCHES - A method for manufacturing an isolated vertical power device includes forming, in a back surface of a first conductivity type substrate, back isolation wall trenches that surround a conduction region of the device. In a front surface of the substrate, front isolation wall trenches are formed around the conduction region. Thereafter, a film containing a second type dopant is deposited in the front and back isolation wall trenches. In the conduction region on the back surface, conduction region trenches are formed inside the perimeter of the isolation wall trenches. A first type dopant is deposited in the conduction region trenches. The dopants are diffused from the conduction region trenches and isolation wall trenches to form a first conductivity type conduction region structure and a second conductivity type isolation wall. | 02-26-2009 |
20090057810 | Method of Fabricating an Integrated Circuit - A method of fabricating an integrated circuit includes providing a semiconductor substrate having a doped area; generating a conductive structure towards the doped area, wherein the conductive structure includes an extending section that protrudes from the doped area; generating an electrically isolating layer at a sidewall of the extending section after generating the conductive structure. | 03-05-2009 |
20090057811 | SIMOX WAFER MANUFACTURING METHOD AND SIMOX WAFER - A SIMOX wafer manufacturing method which is capable of providing etching conditions to prevent surface defects (divots) from being spread. The method includes an oxygen implantation process and a high temperature annealing step for forming a BOX layer, a front surface oxide film etching process to treat a front surface of the wafer at an area in which oxygen is implanted, and a rear surface oxide film etching process to treat a rear surface of the wafer, and oxide film etching conditions in the front and rear oxide film etching processes are controlled differently. | 03-05-2009 |
20090057812 | Semiconductor device having multiple element formation regions and manufacturing method thereof - In a manufacturing of a semiconductor device, at least one of elements is formed in each of element formation regions of a substrate having a main side and a rear side, and the substrate is thinned by polished from a rear side of the substrate, and then, multiple trenches are formed on the rear side of the substrate, so that each trench reaches the main side of the substrate. After that, an insulating material is deposited over an inner surface of each trench to form an insulating layer in the trench, so that the element formation regions are isolated. Thereby, generation of cracks and structural steps in the substrate and separation of element formation regions from the substrate can be suppressed. | 03-05-2009 |
20090072341 | BURIED LOW-RESISTANCE METAL WORD LINES FOR CROSS-POINT VARIABLE-RESISTANCE MATERIAL MEMORIES - Variable-resistance material memories include a buried salicide word line disposed below a diode. Variable-resistance material memories include a metal spacer spaced apart and next to the diode. Processes include the formation of one of the buried salicide word line and the metal spacer. Devices include the variable-resistance material memories and one of the buried salicided word line and the spacer word line. | 03-19-2009 |
20090072342 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device includes forming an ion implanted region on a semiconductor substrate in a cell/core region. The semiconductor substrate is selectively etched to form a recess. The recess exposes a boundary of the ion implanted region. The ion implanted region exposed at the bottom of the recess is removed to form an under-cut space in the semiconductor substrate. An insulating film is formed to form a substrate having a silicon-on-insulator (SOI) structure in the cell/core region. The insulating film fills the under-cut space and the recess. | 03-19-2009 |
20090072343 | SEMICONDUCTOR DEVICE AND ELECTRONIC APPLIANCE - A high-performance semiconductor device using an SOI substrate in which a low-heat-resistance substrate is used as a base substrate. Further, a high-performance semiconductor device formed without using chemical polishing. Further, an electronic device using the semiconductor device. An insulating layer over an insulating substrate, a bonding layer over the insulating layer, and a single-crystal semiconductor layer over the bonding layer are included, and the arithmetic-mean roughness of roughness in an upper surface of the single-crystal semiconductor layer is greater than or equal to 1 nm and less than or equal to 7 nm. Alternatively, the root-mean-square roughness of the roughness may be greater than or equal to 1 nm and less than or equal to 10 nm. Alternatively, a maximum difference in height of the roughness may be greater than or equal to 5 nm and less than or equal to 250 nm. | 03-19-2009 |
20090079024 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - To provide a method for manufacturing a large-area semiconductor device, to provide a method for manufacturing a semiconductor device with high efficiency, and to provide a highly-reliable semiconductor device in the case of using a large-area substrate including an impurity element. A plurality of single crystal semiconductor substrates are concurrently processed to manufacture an SOI substrate, so that an area of a semiconductor device can be increased and a semiconductor device can be manufactured with improved efficiency. In specific, a series of processes is performed using a tray with which a plurality of semiconductor substrates can be concurrently processed. Here, the tray is provided with at least one depression for holding single crystal semiconductor substrates. Further, deterioration of characteristics of a manufactured semiconductor element is prevented by providing an insulating layer serving as a barrier layer against an impurity element which may affect characteristics of the semiconductor element. | 03-26-2009 |
20090079025 | SUBSTRATE PROVIDED WITH SEMICONDUCTOR FILMS AND MANUFACTURING METHOD THEREOF - A plurality of single crystal semiconductor substrates having a rectangular shape are disposed on a tray. Depression portions are provided in the tray so that the single crystal semiconductor substrates can fit in. The single crystal semiconductor substrates disposed on the tray are doped with hydrogen ions, so that damaged regions are formed at a desired depth. A bonding layer is formed on surfaces of the single crystal semiconductor substrates. The plurality of single crystal semiconductor substrates in each of which the damaged region is formed and on which the bonding layer is formed are disposed on the tray and bonded to the base substrate. By heat treatment, the single crystal semiconductor substrates are separated at the damaged regions; accordingly, a plurality of single crystal semiconductor layers which are thinned are formed over the base substrate; | 03-26-2009 |
20090090992 | ISOLATION TRENCH STRUCTURE FOR HIGH ELECTRIC STRENGTH - The invention relates to an isolation trench structure and a corresponding layout wherein the insulating properties of isolation trenches ( | 04-09-2009 |
20090096054 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including a semiconductor substrate is provided. The semiconductor substrate includes a substrate having an insulating surface, and a plurality of stacks over the substrate having an insulating surface. Each of the plurality of stacks includes a bonding layer over the substrate having an insulating surface, an insulating layer over the bonding layer, and a single crystal semiconductor layer over the insulating layer. The substrate having an insulating surface has a depression, and the depression is provided between one of the plurality of stacks and another adjacent one of the plurality of stacks. | 04-16-2009 |
20090102008 | SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor substrate having an SOI layer is provided. Between an SOI layer and a glass substrate, a bonding layer is provided which is formed of one layer or a plurality of layers of phosphosilicate glass, borosilicate glass, and/or borophosphosilicate glass, using organosilane as one material by a thermal CVD method at a temperature of 500° C. to 800° C. | 04-23-2009 |
20090102009 | Semiconductor device and method of forming the same - Provided are a semiconductor device and a method of forming the semiconductor device. The semiconductor device includes an active region of which an edge is curved. The semiconductor device includes a gate insulating layer, a floating gate, a gate interlayer dielectric layer and a control gate line on the active region. The semiconductor device includes an oxide pattern having a concave top surface between adjacent floating gates. The control gate may be sufficiently spaced apart from the active region by the oxide pattern. The method can provide a semiconductor device that includes a reoxidation process, an active region having a curved edge and an oxide pattern having a top surface of a curved concave shape. | 04-23-2009 |
20090102010 | SEMICONDUCTOR DEVICE WITH STI AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first structure formed on an area from the active region in the first area to a nearby STI isolation region and having a first height; and a second structure formed on an area from the active region in the second area to a nearby STI isolation region and having a second height, wherein the surface of the said STI isolation region in the first area is lower than the surface of said STI isolation region in the second area. | 04-23-2009 |
20090108394 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device comprises forming a deposition structure including a first substrate, an insulating layer and a second substrate of a SOI substrate; etching the second substrate located in a boundary of cell and core regions and a peripheral region to form a line-type trench; filling an isolating film in the trench; removing the second substrate and the insulating layer of the peripheral region; performing a selective epitaxial growth (SEG) process using the first substrate exposed in the peripheral region to form an epitaxial layer; and performing a chemical mechanical polishing (CMP) process on the epitaxial layer. As a result, the method has a floating body effect to shorten a developing period and improve a process yield. | 04-30-2009 |
20090108395 | SEMICONDUCTOR DEVICE HAVING INCREASED ACTIVE REGION WIDTH AND METHOD FOR MANUFACTURING THE SAME - The disclosed semiconductor device includes a plurality of active patterns including first active patterns which protrude from a semiconductor substrate and have a first width and second active patterns which are connected to upper ends of the respective first active patterns and have a second width greater than the first width. The semiconductor device further includes isolation patterns respectively located between the active patterns to insulate the active patterns from one another. | 04-30-2009 |
20090121309 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a device isolation structure on a semiconductor substrate to define an active region. A hard mask pattern defining a recess region is formed over the semiconductor substrate. The semiconductor substrate is selectively etched using the hard mask pattern to form a recess channel structure. The etching process for the semiconductor substrate is performed by two plasma etching methods under different etching conditions. The hard mask pattern is removed to expose the active region including the recess channel structure. A gate electrode is formed to fill the recess channel structure. | 05-14-2009 |
20090127648 | Hybrid Gap-fill Approach for STI Formation - A method of forming a shallow trench isolation region is provided. The method includes providing a semiconductor substrate comprising a top surface; forming an opening extending from the top surface into the semiconductor substrate; performing a first deposition step to fill a first dielectric material into the opening using a first deposition method. The first deposition method has a bottom deposition rate substantially greater than a sidewall deposition rate. The method further includes isotropically etching the first dielectric material, wherein at least a bottom portion of the first dielectric material remains after the etching; and performing a second deposition step to fill a remaining portion of the opening with a second dielectric material. The first deposition method may be a high-density plasma chemical vapor deposition. The second deposition method may be a high-aspect ratio process. | 05-21-2009 |
20090127649 | Semiconductor device and method for fabricating the same - According to the present invention, a semiconductor device includes a semiconductor layer; a device-isolation region formed in the semiconductor layer; an active region surrounded by the device isolation region; and a gap, formed at boundary between the device isolation region and the active region. The gap is not formed under the active region. The gap is formed on a side wall portion of the active region, which extends in a depth direction. | 05-21-2009 |
20090127650 | TRENCH ISOLATION STRUCTURE IN A SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A trench isolation structure in a semiconductor device is provided. A semiconductor substrate has cell regions and peripheral circuit regions. First trenches have a predetermined depth and are formed in the semiconductor substrate at the cell regions. A first sidewall oxide film is formed overlying the first trenches. A first liner nitride film is formed overlying the first sidewall oxide film. Second trenches have a predetermined depth and are formed in the semiconductor substrate at the peripheral circuit regions. A second sidewall oxide film is formed overlying the second trenches. An oxide film fills the first overlying second trenches. A second liner nitride film formed on the filling oxide film. The second liner nitride film is separated from the sidewalls of the first and second trenches. | 05-21-2009 |
20090127651 | ROBUST SHALLOW TRENCH ISOLATION STRUCTURES AND A METHOD FOR FORMING SHALLOW TRENCH ISOLATION STRUCTURES - In a semiconductor substrate, a shallow trench isolation structure having a dielectric material disposed in voids of a trench-fill material and a method for forming the shallow trench isolation structure. The voids may be formed during a wet clean process after the dielectric material is formed in the trench. A conformal silicon nitride layer is formed over the substrate and in the voids. After removal of the silicon nitride layer, the voids are at least partially filled by the silicon nitride material. | 05-21-2009 |
20090140374 | SEMICONDUCTOR DEVICE WITH IMPROVED CONTROL ABILITY OF A GATE AND METHOD FOR MANUFACTURING THE SAME - Disclosed is a semiconductor device capable of improving a control ability of a gate and enhancing operation characteristics of the gate. The semiconductor device comprises a semiconductor substrate having a recessed active region. An isolation structure is formed to define the recessed active region in the semiconductor substrate and the isolation structure includes a trench, a side wall insulation layer formed over the surface of the trench, and an insulation layer formed over the side wall insulation layer to fill the trench. A portion of the side wall insulation layer adjoining a gate forming area of the recessed active region is removed to form a moat, and a gate is formed over the semiconductor substrate including the moat. | 06-04-2009 |
20090140375 | METHOD OF FORMING ISOLATION LAYER IN SEMICONDUCTOR DEVICE - A semiconductor device can include a semiconductor substrate, a first trench formed in the semiconductor substrate, a second trench formed in the semiconductor substrate, a first device isolation layer formed in the first trench, a second device isolation layer formed in the second trench having a different structure than the first device isolation layer. | 06-04-2009 |
20090140376 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE DEVICE - A method for forming a device isolation layer in a semiconductor substrate by destroying a lattice structure of the semiconductor substrate through a high-energy ion implantation process. | 06-04-2009 |
20090140377 | DIELECTRIC ISOLATION TYPE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A dielectric isolation type semiconductor device includes a dielectric isolation type substrate in which a support substrate, an embedded dielectric layer, and a first conductive type semiconductor substrate of a low impurity concentration are laminated one over another. The semiconductor substrate includes a first semiconductor region of a first conductive type having a high impurity concentration, a second semiconductor region of a second conductive type having a high impurity concentration arranged so as to surround the first semiconductor region, a first main electrode joined to a surface of the first semiconductor region, and a second main electrode joined to a surface of the second semiconductor region. A first dielectric portion is arranged adjacent the embedded dielectric layer so as to surround a region of the support substrate superposed on the first semiconductor region in a direction of lamination thereof, and a wire connected with the first main electrode. | 06-04-2009 |
20090146242 | METAL ION TRANSISTOR AND RELATED METHODS - A metal ion transistor and related methods are disclosed. In one embodiment, the metal ion transistor includes a cell positioned in at least one isolation layer, the cell including a metal ion doped low dielectric constant (low-k) dielectric material sealed from each adjacent isolation layer; a first electrode contacting the cell on a first side; a second electrode contacting the cell on a second side; and a third electrode contacting the cell on a third side, wherein each electrode is isolated from each other electrode. | 06-11-2009 |
20090146243 | Semiconductor Device Having Recessed Channel and Method for Manufacturing the Same - A semiconductor device having a recessed channel and a method for manufacturing the same. The semiconductor device comprises a semiconductor substrate formed with an isolation layer defining an active region including a channel region and a junction region, a recessed trench including a top trench formed within the channel region of the semiconductor substrate and a bottom trench formed from a bottom surface of the top trench with a width narrower than the top trench, and a gate stack overlapping the recessed trench and extending across the active region. | 06-11-2009 |
20090146244 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE - In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes removing a portion of a semiconductor material to form a first protrusion and a cavity having a boundary that is below a surface of the semiconductor material, wherein the first protrusion extends from the boundary of the cavity. The method further includes forming a non-conformal material over a first portion of the first protrusion using an angled deposition of the non-conformal material, wherein the angle of deposition of the non-conformal material is non-perpendicular to the surface of the semiconductor material. Other embodiments are described and claimed. | 06-11-2009 |
20090146245 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE - In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes removing a portion of a semiconductor material to form a cavity that extends at least about one micron or greater below the surface of the semiconductor material, filling the cavity with a sacrificial material, forming a dielectric material over the sacrificial material and over at least a portion of the surface of the semiconductor material, and removing a portion of the dielectric material to form an opening to expose a portion of the sacrificial material, wherein the opening has a width that is substantially less than a width of the cavity and the dielectric material is rigid or substantially rigid. The method further includes removing the sacrificial material. Other embodiments are described and claimed. | 06-11-2009 |
20090152669 | SI TRENCH BETWEEN BITLINE HDP FOR BVDSS IMPROVEMENT - Memory devices having improved BVdss characteristics and methods of making the memory devices are provided. The memory devices contain bitline dielectrics on bitlines of a semiconductor substrate; first spacers adjacent the side surfaces of the bitline dielectrics and on the upper surface of the semiconductor substrate; a trench in the semiconductor substrate between the first spacers; and second spacers adjacent the side surfaces of the trench. By containing the trench and the first and second spacers between the bitlines, the memory device can improve the electrical isolation between the bitlines, thereby preventing and/or mitigating bitline-to-bitline current leakage and increasing BVdss. | 06-18-2009 |
20090152670 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of fabricating the same includes a semiconductor substrate including a first trench; an epitaxial layer disposed on and/or over the semiconductor substrate and including a second trench connected to the first trench; a first insulator disposed in the first trench; and a second insulator disposed in the second trench. | 06-18-2009 |
20090152671 | METHOD FOR MANUFACTURING SIMOX WAFER AND SIMOX WAFER - This method for manufacturing a SIMOX wafer includes: heating a silicon wafer to 300° C. or more and implanting oxygen ions so as to form a high oxygen concentration layer within the silicon wafer; subjecting the silicon wafer to a cooling to less than 300° C. and an implanting of oxygen ions so as to form an amorphous layer; and subjecting the silicon wafer to a heat-treating in a mixed gas atmosphere containing oxygen so as to form a buried oxide layer. In the forming of the buried oxide layer, a starting temperature is less than 1350° C. and a maximum temperature is 1350° C. or more. This SIMOX wafer is manufactured by the above method and includes a BOX layer and a SOI layer on the BOX layer. The BOX layer has a thickness of 1300 Å or more and a breakdown voltage of 7 MV/cm or more, and the surface of the SOI layer and the interface between the SOI layer and the BOX layer have a roughness over a 10-μm square area of 4 Å rms or less. | 06-18-2009 |
20090152672 | Semiconductor Devices and Methods of Manufacture Thereof - Methods of fabricating semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a method of fabricating a semiconductor device includes providing a workpiece having a plurality of trenches formed therein, forming a liner over the workpiece, and forming a layer of photosensitive material over the liner. The layer of photosensitive material is removed from over the workpiece except from over at least a portion of each of the plurality of trenches. The layer of photosensitive material is partially removed from over the workpiece, leaving a portion of the layer of photosensitive material remaining within a lower portion of the plurality of trenches over the liner. | 06-18-2009 |
20090160009 | Semiconductor array and method for manufacturing a semiconductor array - Semiconductor array and method for manufacturing a semiconductor array, wherein
| 06-25-2009 |
20090160010 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE DEVICE - A semiconductor device and a method for manufacturing the device capable of preventing an LDD region and a lower portion of the gate electrode from overlapping each other to achieve desirable device performance are disclosed. Embodiments relate to a semiconductor device and a method for manufacturing the device that may minimize overlap between an LDD region and a lower portion of the gate electrode. Minimizing overlap may maximize device performance and minimize the generation of defects between gate electrodes. | 06-25-2009 |
20090160011 | ISOLATOR AND METHOD OF MANUFACTURING THE SAME - The present invention relates to an isolator and a method of manufacturing the same. An isolator according to the present invention includes a silicon wafer, protective devices formed in predetermined regions of the silicon wafer, and a transformer formed in a predetermined region on the silicon wafer, the transformer having at least two coil patterns spaced apart from each other. According to the present invention, an isolator can be protected from impulses generated by ESD and surge, so that its reliability can be improved, and its size can be considerably decreased. Further, the number of wire bonding times is decreased, so that performance of a chip can be enhanced, and packaging efficiency can be improved, thereby increasing productivity. | 06-25-2009 |
20090166799 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SUCH A SEMICONDUCTOR DEVICE - The invention relates to a method of manufacturing a semiconductor device ( | 07-02-2009 |
20090166800 | INTERLAYER DIELECTRIC MATERIAL IN A SEMICONDUCTOR DEVICE COMPRISING A DOUBLET STRUCTURE OF STRESSED MATERIALS - By forming a buffer material above differently stressed contact etch stop layers followed by the deposition of a further stress-inducing material, enhanced overall device performance may be accomplished, wherein an undesired influence of the additional stress-inducing layer may be reduced in device regions, for instance, by removing the additional material or by performing a relaxation implantation process. Furthermore, process uniformity during a patterning sequence for forming contact openings may be enhanced by partially removing the additional stress-inducing layer at an area at which a contact opening is to be formed. | 07-02-2009 |
20090184390 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is disclosed, which includes a semiconductor substrate including a device region and an isolation region having an isolation trench, a gate electrode formed on the device region through a gate insulating film, a first isolation insulating film formed in the isolation trench, the first isolation insulating film having a recess, a second isolation insulating film formed on the first isolation insulating film to be filled in the recess, the second isolation insulating film having an upper surface higher than the upper surface of the semiconductor substrate, and an impurity region formed in the semiconductor substrate under the first isolation insulating film, the impurity region having a conductivity type the same as a conductivity type of the semiconductor substrate, an impurity concentration higher than an impurity concentration of the semiconductor substrate, and a width of the impurity region smaller than a width of the isolation trench. | 07-23-2009 |
20090189242 | METHOD FOR NON-SELECTIVE SHALLOW TRENCH ISOLATION REACTIVE ION ETCH FOR PATTERNING HYBRID-ORIENTED DEVICES COMPATIBLE WITH HIGH-PERFORMANCE HIGHLY-INTEGRATED LOGIC DEVICES - Disclosed are embodiments of a hybrid-orientation technology (HOT) wafer and a method of forming the HOT wafer with improved shallow trench isolation (STI) structures for patterning devices in both silicon-on-insulator (SOI) regions, having a first crystallographic orientation, and bulk regions, having a second crystallographic orientation. The improved STI structures are formed using a non-selective etch process to ensure that all of the STI structures and, particularly, the STI structures at the SOI-bulk interfaces, each extend to the semiconductor substrate and have an essentially homogeneous (i.e., single material) and planar (i.e., divot-free) bottom surface that is approximately parallel to the top surface of the substrate. Optionally, an additional selective etch process can be used to extend the STI structures a predetermined depth into the substrate. | 07-30-2009 |
20090189243 | SEMICONDUCTOR DEVICE WITH TRENCH ISOLATION STRUCTURE AND METHOD FOR FABRICATING THE SAME - The present invention relates to a semiconductor device with a device isolation structure and a method for fabricating the same. The semiconductor device includes: a substrate provided with a trench formed in the substrate; and at least one device isolation structure including an oxide layer formed on the trench, a nitride layer formed on the oxide layer disposed on sidewalls of the trench and a high density plasma oxide layer formed on the nitride layer to fill the trench. | 07-30-2009 |
20090194842 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes an SOI substrate, a first STI-type isolation region, a second STI-type isolation region, and an alignment mark region. The SOI substrate includes a support substrate, an insulating layer deposited on the support substrate, and a semiconductor layer which includes a thin film region and a thick film region. The thin film region includes a first semiconductor layer deposited on the support substrate, and the thick film region includes the first semiconductor layer and a second semiconductor layer deposited on a part of the first semiconductor layer. The first STI-type isolation region is disposed at the thin film region. The second STI-type isolation region is disposed at the thick film region. The alignment mark region is disposed at the thick film region. An alignment mark to be used for alignment of the second STI-type isolation region is disposed at the alignment mark region. | 08-06-2009 |
20090200635 | Integrated Circuit Having Electrical Isolation Regions, Mask Technology and Method of Manufacturing Same - An integrated circuit device (e.g., a logic or memory device) having a plurality of memory cells each including at least one transistor, wherein transistors of neighboring memory cells are separated by isolation regions. The isolation regions include a first liner layer, a barrier layer disposed on or over the first liner layer, wherein the barrier layer is less than 3 nanometers, and preferably between about 1 nanometer to about 2 nanometers in thickness. The isolation regions further include a second liner layer (comprising, e.g., a silicon nitride material), disposed on or over the barrier layer, and an electrical isolation material, disposed on or over the second liner layer. The barrier layer prohibits, minimizes, reduces, inhibits and/or retards diffusion of nitrogen atoms there through. Also disclosed are methods of manufacturing such integrated circuit devices as well as methods of manufacture of a mask for use in fabrication of integrated circuits, wherein the mask comprises depositing a pad layer, depositing a barrier layer on or over the pad layer wherein the barrier layer includes a thickness of about 1 nanometer to about 2 nanometers, and depositing a hard mask layer on or over the barrier layer which includes a silicon nitride material. The barrier layer prohibits, minimizes, reduces, inhibits and/or retards diffusion of nitrogen atoms there through. | 08-13-2009 |
20090206441 | METHOD OF FORMING COPLANAR ACTIVE AND ISOLATION REGIONS AND STRUCTURES THEREOF - Methods of forming coplanar active regions and isolation regions and structures thereof are disclosed. One embodiment includes shallow-trench-isolation (STI) formation in a semiconductor-on-insulator (SOI) layer on a substrate of a semiconductor structure; and bonding a handle wafer to the STI and SOI layer to form an intermediate structure. The intermediate structure may have a single layer including at least one STI region and at least one SOI region therein disposed between the damaged substrate and the handle wafer. The method may also include cleaving the hydrogen implanted substrate and removing any residual substrate to expose a surface of the at least one STI region and a surface of the at least one SOI region. The exposed surface of the at least one STI region forms an isolation region and the exposed surface of the at least one SOI region forms an active region, which are coplanar to each other. | 08-20-2009 |
20090206442 | METHOD AND STRUCTURE FOR RELIEVING TRANSISTOR PERFORMANCE DEGRADATION DUE TO SHALLOW TRENCH ISOLATION INDUCED STRESS - A method of forming shallow trench isolation (STI) regions for semiconductor devices, the method including defining STI trench openings within a semiconductor substrate; filling the STI trench openings with an initial trench fill material; defining a pattern of nano-scale openings over the substrate, at locations corresponding to the STI trench openings; transferring the pattern of nano-scale openings into the trench fill material so as to define a plurality of vertically oriented nano-scale openings in the trench fill material; and plugging upper portions of the nano-scale openings with additional trench fill material, thereby defining porous STI regions in the substrate. | 08-20-2009 |
20090206443 | DEVICES INCLUDING FIN TRANSISTORS ROBUST TO GATE SHORTS AND METHODS OF MAKING THE SAME - Disclosed are methods, systems and devices, including a method that includes the acts of etching an inter-row trench in a substrate, substantially or entirely filling the inter-row trench with a dielectric material, and forming a fin and a insulating projection at least in part by etching a gate trench in the substrate. In some embodiments, the insulating projection includes at least some of the dielectric material in the inter-row trench. | 08-20-2009 |
20090206444 | INTEGRATED SEMICONDUCTOR DEVICE - An integrated semiconductor device includes a plurality of semiconductor elements having different integrated element circuits or different sizes; an insulating material arranged between the semiconductor elements; an organic insulating film arranged entirely on the semiconductor elements and the insulating material; a fine thin-layer wiring that arranged on the organic insulating film and connects the semiconductor elements; a first input/output electrode arranged on an area of the insulating material; and a first bump electrode formed on the first input/output electrode. | 08-20-2009 |
20090206445 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device may include, but is not limited to, first and second well regions, and a well isolation region isolating the first and second well regions. The first and second well regions each may include an active region, a device isolation groove that defines the active region, and a device isolation insulating film that fills the device isolation groove. The first and second well regions may include first and second well layers, respectively. The well isolation region may include a well isolation groove, a well isolation insulating film that fills the well isolation groove, and a diffusion stopper layer disposed under a bottom of the well isolation groove. The first and second well layers have first and second bottoms respectively, which are deeper in depth than a bottom of the device isolation groove and shallower in depth than the bottom of the well isolation groove. | 08-20-2009 |
20090212387 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A trench is formed on a semiconductor substrate with a first insulation film patterned on the semiconductor substrate as a mask; a second insulation film is embedded in the trench and flattened; an upper portion of the first insulation film is selectively removed, and a part of a side face of the second insulation film is exposed; a part of the second insulation film is isotropically removed; a lower portion of the remaining first insulation film is selectively removed; and then a part of the remaining second insulation film is further isotropically removed so that an upper face of the second insulation film is at a predetermined height from a surface of the semiconductor substrate, a taper having a minimum taper angle of 90° or more is formed on the side face of the second insulation film, and a STI is formed. | 08-27-2009 |
20090212388 | HIGH-Z STRUCTURE AND METHOD FOR CO-ALIGNMENT OF MIXED OPTICAL AND ELECTRON BEAM LITHOGRAPHIC FABRICATION LEVELS - A structure for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target. The structure including a first trench in a semiconductor substrate, the first trench extending from a top surface of the substrate into the substrate a first distance; an electron back-scattering layer in a bottom of the first trench; a dielectric capping layer in the trench over the back-scattering layer; and a second trench in the substrate, the second trench extending from the top surface of the substrate into the substrate a second distance, the second distance less than the first distance. | 08-27-2009 |
20090218654 | Semiconductor Memory Devices Including Extended Memory Elements - A semiconductor memory device may include a semiconductor substrate having an active region thereof, and the active region may have a length and a width, with the length being greater than the width. A field isolation layer may be on the semiconductor substrate surrounding the active region. First and second wordlines may be on the substrate crossing the active region, with the first and second wordlines defining a drain portion of the active region between the first and second wordlines and first and second source portions of the active region at opposite ends of the active region. First and second memory storage elements may be respectively coupled to the first and second source portions of the active region, with the first and second wordlines being between portions of the respective first and second memory storage elements and the active region in a direction perpendicular to a surface of the substrate. | 09-03-2009 |
20090230502 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device includes: forming a first semiconductor layer on a semiconductor substrate; forming a second semiconductor layer on the first semiconductor layer; forming a first groove which penetrates the first and the second semiconductor layers by etching the first and the second semiconductor layers; forming a support in the first groove; forming a second groove so that the first semiconductor layer is exposed by etching the second semiconductor layer; forming a cavity between the second semiconductor layer and the semiconductor substrate by etching the first semiconductor layer through the second groove; and forming an insulating film inside the cavity. In the step of forming the second groove, the second semiconductor layer is formed so as to have a first region, a second region, and a third region in a plan view. The first groove includes a plurality of first grooves. The first region is sandwiched between the first grooves in a first direction in the plan view. The second region is sandwiched between the first grooves in the first direction in the plan view and is provided parallel to the first region along a second direction which intersects with the first direction. The third region links the first and the second regions while being adjacent to the second groove. | 09-17-2009 |
20090230503 | METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE, AND SEMICONDUCTOR DEVICE - Methods for manufacturing a semiconductor substrate and a semiconductor device by which a high-performance semiconductor element can be formed are provided. A single crystal semiconductor substrate including an embrittlement layer and a base substrate are bonded to each other with an insulating layer interposed therebetween, and the single crystal semiconductor substrate is separated along the embrittlement layer by heat treatment to fix a single crystal semiconductor layer over the base substrate. Next, a plurality of regions of a monitor substrate are irradiated with laser light under conditions of different energy densities, and carbon concentration distribution and hydrogen concentration distribution in a depth direction of each region of the single crystal semiconductor layer which has been irradiated with the laser light is measured. Optimal irradiation intensity of laser light is irradiation intensity with which a local maximum of the carbon concentration and a shoulder peak of the hydrogen concentration are observed. A single crystal semiconductor layer is irradiated with optimal laser light at energy density detected by using the monitor substrate, whereby a semiconductor substrate is manufactured. | 09-17-2009 |
20090230504 | HOT process STI in SRAM device and method of manufacturing - A structure and method for forming SRAMs on HOT substrates with STI is described. Logic circuits may also be fabricated on the same chip with some devices on the SOI regions and other devices on the SOI regions. | 09-17-2009 |
20090236682 | LAYER STACK INCLUDING A TUNGSTEN LAYER - A method for producing a layer stack includes providing a tungsten layer, depositing an oxidation barrier layer that immunizes the tungsten layer against oxidation on top of the tungsten layer, and depositing a cap layer on top of the oxidation barrier layer. An integrated circuit is also described. | 09-24-2009 |
20090243029 | METHOD, STRUCTURE AND DESIGN STRUCTURE FOR CUSTOMIZING HISTORY EFFECTS OF SOI CIRCUITS - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a structure which comprises a high-leakage dielectric formed in a divot on each side of a segmented FET comprised of active silicon islands and gate electrodes thereon, and a low-leakage dielectric on the surface of the active silicon islands, adjacent the high-leakage dielectric, wherein the low-leakage dielectric has a lower leakage than the high-leakage dielectric. Also provided is a structure and method of fabricating the structure. | 10-01-2009 |
20090243030 | METHOD OF FORMING SHALLOW TRENCH ISOLATION STRUCTURE - A method of fabricating an isolation structure and the structure thereof is provided. The method is compatible with the embedded memory process and provides the isolation structure with a poly cap thereon to protect the top corners of the isolation structure, without using an extra photomask. | 10-01-2009 |
20090250782 | SUBGROUNDRULE SPACE FOR IMPROVED METAL HIGH-K DEVICE - The present invention provides a semiconducting device including a substrate including at least one semiconducting region and isolation regions; a gate structure atop the substrate having a gate dielectric layer positioned on the semiconducting region and a metal layer atop the gate dielectric layer, the gate structure having a width equal to or greater than the width of the at least one semiconducting region; and a contact structure including a base having a first width equal to the width of the gate structure and an upper surface having a second width, wherein the first width is greater than the second width. In one embodiment, the contact structure includes a polysilicon conductor and dielectric spacers, wherein each spacer of the dielectric spacer abuts a sidewall of the polysilicon conductor. In another embodiment, the contact structure includes a polysilicon conductor having a tapered sidewall. | 10-08-2009 |
20090261448 | METHOD OF FORMING SHALLOW TRENCH ISOLATION STRUCTURES FOR INTEGRATED CIRCUITS - A method of forming shallow trench isolation (STI) structures using a multi-step etch process is disclosed. The first etch step is performed by selectively etching the substrate at a substantially higher etching rate than the mask layer to form preliminary openings having steep taper angles. The second etch step is performed by non-selectively etching the substrate to deepen the preliminary openings to form STI gaps with substantially flat bottoms. | 10-22-2009 |
20090267176 | A METHOD FOR FORMING A MULTI-LAYER SHALLOW TRENCH ISOLATION STRUCTURE IN A SEMICONDUCTOR DEVICE - The disclosure describes a multi-layer shallow trench isolation structure in a semiconductor device. The shallow trench isolation structure may include a first void-free, doped oxide layer in the shallow trench, and a second void-free layer above the first doped oxide layer. The first layer may be formed by vapor deposition of precursors of a source of silicon, a source of oxygen and sources of doping materials and making the layer void-free by reflowing the initial layer by an annealing process. The second layer may be formed by vapor deposition of precursors of silicon and doping materials and making the layer void-free by reflowing the initial layer by an annealing process. Alternatively, the second layer may be a silicon oxide layer that may be formed by an atomic layer deposition method. The processing conditions for forming the two layers are different. | 10-29-2009 |
20090273051 | METHODS OF FORMING ISOLATED ACTIVE AREAS, TRENCHES, AND CONDUCTIVE LINES IN SEMICONDUCTOR STRUCTURES AND SEMICONDUCTOR STRUCTURES INCLUDING THE SAME - Methods of pitch doubling of asymmetric features and semiconductor structures including the same are disclosed. In one embodiment, a single photolithography mask may be used to pitch double three features, for example, of a DRAM array. In one embodiment, two wordlines and a grounded gate over field may be pitch doubled. Semiconductor structures including such features are also disclosed. | 11-05-2009 |
20090273052 | Reducing Device Performance Drift Caused by Large Spacings Between Action Regions - A method of forming an integrated circuit structure includes providing a semiconductor substrate; and forming a first and a second MOS device. The first MOS device includes a first active region in the semiconductor substrate; and a first gate over the first active region. The second MOS device includes a second active region in the semiconductor substrate; and a second gate over the second active region. The method further include forming a dielectric region between the first and the second active regions, wherein the dielectric region has an inherent stress; and implanting the dielectric region to form a stress-released region in the dielectric region, wherein source and drain regions of the first and the second MOS devices are not implanted during the step of implanting. | 11-05-2009 |
20090278223 | Process for Producing Siliceous Film and Substrate With The Siliceous Film Produced by The Process - An objective of the present invention is to provide a process for producing a siliceous film which has a uniform quality independently of sites and in both the inside and outside of the grooves and is free from voids and cracks in the inside of the grooves. A substrate with the siliceous film can be produced by forming an insulating film having a high hydrogen content on a surface of a silicon substrate having concavoconvexes, then coating a composition containing a polysilazane compound on the substrate, and heating the coated substrate to convert the polysilazane compound to a silicon dioxide film. | 11-12-2009 |
20090278224 | METHODS OF FORMING AN AMORPHOUS SILICON THIN FILM - A method for forming an amorphous silicon thin film is disclosed. In some embodiments, a method includes loading a substrate into a reaction chamber; and conducting a plurality of deposition cycles on the substrate. Each of at least two of the cycles includes: supplying a silicon precursor to the reaction chamber during a first time period; applying radio frequency power to the reaction chamber at least partly during the first time period; stopping supplying of the silicon precursor and applying of the radio frequency power during a second time period between the first time period and an immediately subsequent deposition cycle; and supplying hydrogen plasma to the reaction chamber during a third time period between the second time period and the immediately subsequent deposition cycle. The method allows formation of an amorphous silicon film having an excellent step-coverage and a low roughness at a relatively low deposition temperature. | 11-12-2009 |
20090278225 | SEMICONDUCTOR DEVICE AND METHOD FOR ISOLATING THE SAME - The present invention relates to a semiconductor device and a method for isolating the same. The semiconductor device includes: a silicon substrate provided with a trench including at least one silicon pillar at a bottom portion of the trench, wherein the silicon pillar become sidewalls of micro trenches; and a device isolation layer selectively and partially filled into the plurality of micro trenches. | 11-12-2009 |
20090289323 | Apparatus For Implementing Multiple Integrated Circuits Using Different Gate Oxide Thicknesses On A Single Integrated Circuit Die - An apparatus comprising plurality of functional integrated circuit blocks, each manufactured with different oxide thicknesses on a monolithic integrated circuit die, is described. Using different gate oxide thicknesses for different functional integrated circuit blocks provides reduced power consumption and increases performance in processing systems. Several embodiments comprising different combinations of functional integrated circuit blocks, including processor cores and memory elements, are presented. | 11-26-2009 |
20090289324 | MASK OVERHANG REDUCTION OR ELIMINATION AFTER SUBSTRATE ETCH - A method of forming IC devices includes providing a substrate and forming a patterned masking layer including at least one masked region having at least one masking layer, and a feature region bounded by the masking layer. Etching forms an etched feature in the substrate, wherein undercutting during the etching forms at least one mask overhang region over a surface portion of the etched feature that is recessed relative to an outer edge of the masking layer. A pullback etch process exclusive of any additional patterning step laterally etches the masking layer. The conditions for the pullback etch retain at least a portion of the masking layer and reduce a length of the mask overhang region by at least 50%, or eliminate the mask overhang region entirely. The etched feature is then filled after the pullback etch process to form a filled etched feature. | 11-26-2009 |
20090294893 | ISOLATION TRENCH INTERSECTION STRUCTURE WITH REDUCED GAP WIDTH - The invention relates to isolation trenches having a high aspect ratio for trench-insulated smart power technologies in Silicon On Insulator (SOI) silicon wafers. The specific geometric layout of the intersections and junctions of the isolation trenches allows error rate reduction and simplification of manufacture. | 12-03-2009 |
20090294894 | INTEGRATED CIRCUIT HAVING LOCALIZED EMBEDDED SiGe AND METHOD OF MANUFACTURING - An integrated circuit (IC) with localized SiGe embedded in a substrate and a method of manufacturing the IC is provided. The method includes forming recesses in a substrate on each side of a gate structure and remote from a shallow trench isolation structure. The method further includes growing a stress material within the recesses such that the stress material is bounded on its side only by the substrate. | 12-03-2009 |
20090294895 | INTEGRATED CIRCUIT WITH CONDUCTIVE STRUCTURES - An integrated circuit includes an array of transistors and wordlines, where individual wordlines are coupled to a number of the transistors. Conductive structures that are insulated from the wordlines are disposed in a layer beneath the wordlines and are arranged between the transistors. | 12-03-2009 |
20090294896 | SHALLOW TRENCH ISOLATION PROCESS UTILIZING DIFFERENTIAL LINERS - A method of manufacturing an integrated circuit (IC) can utilize a shallow trench isolation (STI) technique. The shallow trench isolation technique can be used in an IC process. Separate liners for the trench are used for NMOS and PMOS regions. The liners can induce strain in the substrate. | 12-03-2009 |
20090302412 | CARRIER MOBILITY ENHANCED CHANNEL DEVICES AND METHOD OF MANUFACTURE - An integrated circuit with stress enhanced channels, a design structure and a method of manufacturing the integrated circuit is provided. The method includes forming a dummy gate structure on a substrate and forming a trench in the dummy gate structure. The method further includes filling a portion of the trench with a strain inducing material and filling a remaining portion of the trench with gate material. | 12-10-2009 |
20090302413 | SEMICONDUCTOR DEVICE AND STI FORMING METHOD THEREFOR - A semiconductor device includes: a semiconductor substrate having a low voltage (LV) region and a high voltage (HV) region; a pad oxide film pattern and a pad nitride film pattern which are formed over the semiconductor substrate. Further, the semiconductor device includes a shallow trench isolation (STI) formed in the LV region and a STI in the HV region, with a step generated therebetween by ions with which the HV region on the semiconductor substrate is doped when an etching process is carried out using the pad oxide film pattern and pad nitride film pattern as a mask. | 12-10-2009 |
20090302414 | TRENCH ISOLATION FOR REDUCED CROSS TALK - A starting substrate in the form of a semiconductor wafer ( | 12-10-2009 |
20090309183 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An object is to provide a method for manufacturing, with high yield, a semiconductor device having a crystalline semiconductor layer even if a substrate with low upper temperature limit. A groove is formed in a part of a semiconductor substrate to form a semiconductor substrate that has a projecting portion, and a bonding layer is formed to cover the projecting portion. In addition, before the bonding layer is formed, a portion of the semiconductor substrate to be the projecting portion is irradiated with accelerated ions to form a brittle layer. After the bonding layer and the supporting substrate are bonded together, heat treatment for separation of the semiconductor substrate is performed to provide a semiconductor layer over the supporting substrate. The semiconductor layer is selectively etched, and a semiconductor element is formed and a semiconductor device is manufactured. | 12-17-2009 |
20090315138 | METHOD AND STRUCTURE FOR SOI BODY CONTACT FET WITH REDUCED PARASITIC CAPACITANCE - In one embodiment, the present invention provides a semiconductor device that includes a substrate including a semiconducting layer positioned overlying an insulating layer the semiconducting layer including a semiconducting body and isolation regions present about a perimeter of the semiconducting body; a gate structure overlying the semiconducting layer of the substrate, the gate structure present on a first portion on an upper surface of the semiconducting body; and a silicide body contact that is in direct physical contact with a second portion of the semiconducting body that is separated from the first portion of the semiconducting body by a non-silicide semiconducting region. | 12-24-2009 |
20090315139 | PATTERNING METHOD AND SEMICONDUCTOR DEVICE - A patterning method includes defining, in the case of an electric current which exceeds an allowable limit flowing between first conduction type well regions arranged in a semiconductor substrate, a first pattern between the first conduction type well regions; defining a second pattern by removing, in the case of a first region in which arrangement is inhibited being in the first pattern, the first region from the first pattern; defining a third pattern by removing, in the case of a second region which exceeds a fabrication limit being in the second pattern, the second region from the second pattern; and using the third pattern as a dummy active region in a second conduction type well region arranged in the semiconductor substrate. | 12-24-2009 |
20090315140 | METHOD OF FORMING A DEVICE WAFER WITH RECYCLABLE SUPPORT - A method for forming a device wafer with a recyclable support by providing a wafer having first and second surfaces, with at least the first surface of the wafer comprising a semiconductor material that is suitable for receiving or forming electronic devices thereon, providing a supporting substrate having upper and lower surfaces, and providing the second surface of the wafer or the upper surface of the supporting substrate with void features in an amount sufficient to enable a connecting bond therebetween to form a construct wherein the bond is formed at an interface between the wafer and the substrate and is suitable to maintain the wafer and supporting substrate in association while forming or applying electronic devices to the first surface of the wafer, but which connecting bond is severable at the interface due to the void features to separate the substrate from the wafer so that the substrate can be reused. | 12-24-2009 |
20090321872 | LOW COST SUBSTRATES AND METHOD OF FORMING SUCH SUBSTRATES - In one embodiment, the invention provides engineered substrates having a support with surface pits, an intermediate layer of amorphous material arranged on the surface of the support so as to at least partially fill the surface pits, and a top layer arranged on the intermediate layer. The invention also provides methods for manufacturing the engineered substrates which deposit an intermediate layer on a pitted surface of a support so as to at least partially fill the surface pits, then anneal the intermediate layer, then assemble a donor substrate with the annealed intermediate layer to form an intermediate structure, and finally reduce the thickness of the donor substrate portion of the intermediate structure in order to form the engineered substrate. | 12-31-2009 |
20090321873 | LOW-COST SUBSTRATES HAVING HIGH-RESISTIVITY PROPERTIES AND METHODS FOR THEIR MANUFACTURE - In one embodiment, the invention provides substrates that are structured so that devices fabricated in a top layer thereof have properties similar to the same devices fabricated in a standard high resistivity substrate. Substrates of the invention include a support having a standard resistivity, a semiconductor layer arranged on the support substrate having a high-resistivity, preferably greater than about 1000 Ohms-cm, an insulating layer arranged on the high-resistivity layer, and a top layer arranged on the insulating layer. The invention also provides methods for manufacturing such substrates. | 12-31-2009 |
20090321874 | EPITAXIAL WAFER AND PRODUCTION METHOD THEREOF - A small amount of oxygen is ion-implanted in a wafer surface layer, and then heat treatment is performed so as to form an incomplete implanted oxide film in the surface layer. Thereby, wafer cost is reduced; a pit is prevented from forming in a surface of an epitaxial film; and a slip is prevented from forming in an external peripheral portion of a wafer. | 12-31-2009 |
20100006973 | STI Structure At SOI/Bulk Transition For HOT Device - A semiconductor device with STIs separating HOT regions is described. Processes for eliminating voids due to misalignments in boundary region STIs are described. | 01-14-2010 |
20100013044 | THREE-DIMENSIONAL SILICON ON OXIDE DEVICE ISOLATION - A silicon-on-insulator wafer ( | 01-21-2010 |
20100025804 | SOI SUBSTRATE AND METHOD FOR MANUFACTURING SOI SUBSTRATE - On the side of a surface (the bonding surface side) of a single crystal Si substrate, a uniform ion implantation layer is formed at a prescribed depth (L) in the vicinity of the surface. The surface of the single crystal Si substrate and a surface of a transparent insulating substrate as bonding surfaces are brought into close contact with each other, and bonding is performed by heating the substrates in this state at a temperature of 350° C. or below. After this bonding process, an Si—Si bond in the ion implantation layer is broken by applying impact from the outside, and a single crystal silicon thin film is mechanically peeled along a crystal surface at a position equivalent to the prescribed depth (L) in the vicinity of the surface of the single crystal Si substrate. | 02-04-2010 |
20100025805 | SEMICONDUCTOR DEVICES WITH EXTENDED ACTIVE REGIONS - A method of making a semiconductor device is achieved in and over a semiconductor layer. A trench is formed adjacent to a first active area. The trench is filled with insulating material. A masking feature is formed over a center portion of the trench to expose a first side of the trench between a first side of the masking feature and the first active area. A step of etching into the first side of the trench leaves a first recess in the trench. A first epitaxial region is grown in the first recess to extend the first active area to include the first recess and thereby form an extended first active region. | 02-04-2010 |
20100025806 | Semiconductor device and method of fabricating the same - In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried in the trenches is formed to form device isolation regions having protruding portions at sidewalls, wherein the device isolation regions decrease a portion of a width of active regions. | 02-04-2010 |
20100044826 | 3D INTEGRATED CIRCUIT DEVICE FABRICATION WITH PRECISELY CONTROLLABLE SUBSTRATE REMOVAL - A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P− layer, and the P− layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P− layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P− layer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure. | 02-25-2010 |
20100044827 | Method for making a substrate structure comprising a film and substrate structure made by same method - A method for manufacturing a substrate structure comprising a film and a substrate structure made by this method are disclosed. The method for manufacturing a substrate structure comprising a film includes the steps of: providing a target substrate; providing an initial substrate; forming an embrittlement-layer on the initial substrate; forming a device layer on the embrittlement-layer; doping with hydrogen ions; bonding the device layer with the target substrate; and separating the device layer from the initial substrate. The hydrogen ions are added into the embrittlement-layer through doping, before an energy treatment is applied to embrittle and break the embrittlement-layer, thereby separating the device layer from the initial substrate. Since the hydrogen ions are added into the embrittlement-layer through doping, a crystal lattice structure of the device layer will not be damaged during the step of doping with hydrogen ions. | 02-25-2010 |
20100044828 | MONOLITHIC INTEGRATED COMPOSITE DEVICE HAVING SILICON INTEGRATED CIRCUIT AND SILICON OPTICAL DEVICE INTEGRATED THEREON, AND FABRICATION METHOD THEREOF - Provided is a monolithic integrated composite device including: a silicon substrate which is partitioned into a silicon integrated circuit forming region and a silicon optical device forming region; a buried oxide layer which is formed locally in the silicon substrate of the silicon optical device forming region and isolates unit devices of the silicon optical device forming region; an overlay layer formed locally on the buried oxide layer; a silicon optical device formed in the silicon optical device forming region using the silicon overlay layer; a silicon integrated circuit formed in the silicon integrated circuit forming region of the silicon substrate; and wiring connecting the silicon integrated circuit and the silicon optical device or connecting the silicon optical devices or connecting the silicon integrated circuits. | 02-25-2010 |
20100044829 | METHOD FOR PRODUCING SOI SUBSTRATE AND SOI SUBSTRATE - The present invention is a method for producing an SOI substrate including the steps of: preparing a bond wafer and a base wafer which are composed of single crystal silicon wafers; forming an oxide film on a surface of at least one of the bond wafer and the base wafer so that a thickness of a buried oxide film after bonding becomes 3 μm or more; bonding the bond wafer and the base wafer via the oxide film; performing a law-temperature heat treatment at a temperature of 400° C. or more and 1000° C. or less to the bonded substrate; thinning the bond wafer to be an SOI layer; and increasing bonding strength by performing a high-temperature heat treatment at a temperature exceeding 1000° C. Thus, a method for producing an SOI substrate by which generation of slip dislocations is suppressed and an SOI substrate having a high-quality SOI layer can be obtained, for producing a SOI layer in which the thickness of a buried oxide film is thick as 3 μm or more by a bonding method, etc. are provided. | 02-25-2010 |
20100044830 | METHOD OF PRODUCING AN SOI STRUCTURE WITH AN INSULATING LAYER OF CONTROLLED THICKNESS - The invention relates to semiconductor-on-insulator structure and its method of manufacture. This structure includes a substrate, a thin, useful surface layer and an insulating layer positioned between the substrate and surface layer. The insulating layer is at least one dielectric layer of a high k material having a permittivity that is higher than that of silicon dioxide and a capacitance that is substantially equivalent to that of a layer of silicon dioxide having a thickness of less than or equal to 30 nm. | 02-25-2010 |
20100052092 | METHOD FOR FABRICATING A SEMICONDUCTOR ON INSULATOR SUBSTRATE WITH REDUCED SECCO DEFECT DENSITY - The invention relates to a method for fabricating a semiconductor on insulator substrate, in particular a silicon on insulator substrate by providing a source substrate, providing a predetermined splitting area inside the source substrate by implanting atomic species, bonding the source substrate to a handle substrate, detaching a remainder of the source substrate from the source-handle component at the predetermined splitting area to thereby transfer a device layer of the source substrate onto the handle substrate, and thinning of the device layer. To obtain semiconductor on insulator substrates with a reduced Secco defect density of less than 100 per cm | 03-04-2010 |
20100052093 | SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A semiconductor substrate is a semiconductor substrate used when an SOI substrate having an SOI structure is manufactured, in which a silicon oxide film and a silicon single crystal layer are formed on the surface of a silicon substrate. A region containing no nitrogen, which is made of a silicon single crystal layer with a thickness of 10 μm or less, is formed in the vicinity of the surface, and the nitrogen concentration of a portion excluding the region, that is, the region containing nitrogen, is in a range of 1×10 | 03-04-2010 |
20100065940 | 3-D INTEGRATED CIRCUIT SYSTEM AND METHOD - A semiconductor fabrication system and method are presented. A three dimensional multilayer integrated circuit fabrication method can include forming a first device layer and forming a second device layer on top of the first device layer with minimal detrimental heat transfer to the first layer by utilizing a controlled laser layer formation annealing process. A controlled laser crystallization process can be utilized and the controlled laser can include creating an amorphous layer; defining a crystallization area in the amorphous layer, where in the crystallization area is defined to promote single crystal growth (i.e. prevent multi-crystalline growth); and applying laser to the crystallization area, wherein the laser is applied in a manner that prevents undesired heat transfer to another layer. | 03-18-2010 |
20100072569 | Method of forming an isolation layer, method of manufacturing a semiconductor device using the same, and semiconductor device having an isolation layer - In a method of forming an isolation layer, a plurality of trenches is formed on a substrate. A liner is formed on inner walls of the trenches. The liner is thermally oxidized to fill up some of the trenches. The other trenches are filled up with an insulation material. As a result, the isolation layer is free of voids. | 03-25-2010 |
20100078757 | SEMICONDUCTOR DEVICE HAVING RECESS GATE AND ISOLATION STRUCTURE AND METHOD FOR FABRICATING THE SAME - Disclosed herein is a semiconductor device including an isolation structure and a recess gate and a method for fabricating the same. The method for fabricating a semiconductor device includes: forming a trench by selectively etching an isolation region of a semiconductor substrate to define an active region; forming a first SOD partially filling the trench; forming a stress shielding layer, which is denser than the first SOD, over the first SOD; forming a second SOD that fills the trench over the first SOD including the stress shielding layer; forming a recess groove by selectively etching a portion of the active region, wherein an upper surface of the first SOD is spaced downwardly from a bottom of the recess groove, and an upper surface of the stress shielding layer is spaced upwardly from the bottom of the recessed groove; and forming a gate of a transistor that fills the recess groove. | 04-01-2010 |
20100084733 | ISOLATION LAYER OF SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A device isolation layer includes a semiconductor substrate defining an upper trench etched to a predetermined depth, a lower trench defined in the semiconductor substrate at a lower part of the upper trench, the lower trench having a smaller width than the upper trench, and an insulating oxide embedded in the upper and lower trenches. Accordingly, since a stepped structure is formed in the trenches, generation voids may be restrained while improving the gap-filling efficiency. | 04-08-2010 |
20100084734 | MANUFACTURING METHOD OF SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR DEVICE - To provide a semiconductor substrate in which a semiconductor element having favorable crystallinity and high performance can be formed. A single crystal semiconductor substrate having an embrittlement layer and a base substrate are bonded with an insulating layer interposed therebetween; the single crystal semiconductor substrate is separated along the embrittlement layer by heat treatment; a single crystal semiconductor layer is fixed to the base substrate; the single crystal semiconductor layer is irradiated with a laser beam; the single crystal semiconductor layer is in a partially melted state to be recrystallized; and crystal defects are repaired. In addition, the energy density of a laser beam with which the best crystallinity of the single crystal semiconductor layer is obtained is detected by a microwave photoconductivity decay method. | 04-08-2010 |
20100096719 | METHODS OF FORMING FINE PATTERNS IN INTEGRATED CIRCUIT DEVICES - A method of fabricating an integrated circuit device includes forming first and second mask structures on respective first and second regions of a feature layer. Each of the first and second mask structures includes a dual mask pattern and an etch mask pattern thereon having an etch selectivity relative to the dual mask pattern. The etch mask patterns of the first and second mask structures are isotropically etched to remove the etch mask pattern from the first mask structure while maintaining at least a portion of the etch mask pattern on the second mask structure. Spacers are formed on opposing sidewalls of the first and second mask structures. The first mask structure is selectively removed from between the spacers in the first region using the portion of the etch mask pattern on the second mask structure as a mask to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region, and a second mask pattern including the opposing sidewall spacers with the second mask structure therebetween in the second region. The feature layer may be patterned using the first mask pattern as a mask to define a first feature on the first region, and using the second mask pattern as a mask to define a second feature on the second region having a greater width than the first feature. | 04-22-2010 |
20100096720 | SOI SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - To provide an SOI substrate having a high mechanical strength, and a method for manufacturing the SOI substrate, a single crystal semiconductor substrate is irradiated with accelerated ions so that an embrittled region is formed in a region at a predetermined depth from a surface of the single crystal semiconductor substrate; the single crystal semiconductor substrate is bonded to a base substrate with an insulating layer interposed therebetween; the single crystal semiconductor substrate is heated to be separated along the embrittled region, so that a semiconductor layer is provided over the base substrate with the insulating layer interposed therebetween; and a surface of the semiconductor layer is irradiated with a laser beam so that at least a superficial part of the semiconductor layer is melted, whereby at least one of nitrogen, oxygen, and carbon is solid-dissolved in the semiconductor layer. | 04-22-2010 |
20100102415 | METHODS FOR SELECTIVE PERMEATION OF SELF-ASSEMBLED BLOCK COPOLYMERS WITH METAL OXIDES, METHODS FOR FORMING METAL OXIDE STRUCTURES, AND SEMICONDUCTOR STRUCTURES INCLUDING SAME - Methods of forming metal oxide structure and methods of forming metal oxide patterns on a substrate using a block copolymer system formulated for self-assembly are disclosed. The metal oxide structures and patterns may be used, for example, as a mask for sublithographic patterning during various stages of semiconductor device fabrication. A block copolymer at least within a trench in the substrate and including at least one soluble block and at least one insoluble block may be annealed to form a self-assembled pattern including a plurality of repeating units of the soluble block laterally aligned with the trench and positioned within a matrix of the insoluble block. The self-assembled pattern may be exposed to a metal oxide precursor which impregnates the soluble block. The metal oxide precursor may be oxidized to form a metal oxide. The self-assembled pattern may be removed to form a pattern of metal oxide lines on the substrate surface. | 04-29-2010 |
20100117188 | METHOD FOR PRODUCING TRENCH ISOLATION IN SILICON CARBIDE AND GALLIUM NITRIDE AND ARTICLES MADE THEREBY - A method for fabricating a trench in a SiC or GaN semiconductor wafer is provided. The method may include filling the trench with a conformal layer of electrically and/or optically isolating material. A device is also provided. | 05-13-2010 |
20100133645 | METHOD FOR STACKING AND INTERCONNECTING INTEGRATED CIRCUITS - A method for stacking and interconnecting integrated circuits includes providing at least two substrates; forming a trench in each substrate; filling the trench with an insulating material; forming, in each substrate, at least one conductive area; thinning each substrate until reaching at least the bottom of the trench, to obtain in each substrate at least one electrically insulated region within the closed perimeter delineated by the trench; bonding the substrates together; making at least one hole through the bonded substrates so that the hole passes at least partially through the conductive areas and passes through the insulated region of each substrate; and filling the hole with an electrically conductive material so as to obtain a conductive column that traverses the isolated region of each substrate and is in lateral electrical contact with the conductive areas. | 06-03-2010 |
20100133646 | SELF-ALIGNED SI RICH NITRIDE CHARGE TRAP LAYER ISOLATION FOR CHARGE TRAP FLASH MEMORY - A method for fabricating a memory device with U-shaped trap layers over rounded active region corners is disclosed. In the present invention, an STI process is performed before the charge-trapping layer is formed. Immediately after the STI process, the sharp corners of the active regions are exposed, making them available for rounding. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, a bottom oxide layer, nitride layer, and sacrificial top oxide layer are formed. An organic bottom antireflective coating applied to the charge trapping layer is planarized. Now the organic bottom antireflective coating, sacrificial top oxide layer, and nitride layer are etched, without etching the sacrificial top oxide layer and nitride layer over the active regions. After the etching the charge trapping layer has a cross-sectional U-shape appearance. U-shaped trap layer edges allow for increased packing density and integration while maintaining isolation between trap layers. | 06-03-2010 |
20100140735 | NANOSTRUCTURES FOR DISLOCATION BLOCKING IN GROUP II-VI SEMICONDUCTOR DEVICES - A compound semiconductor workpiece with reduced defects and greater strength that uses Group II-VI semiconductor nanoislands on a substrate. Additional layers of Group II-VI semiconductor are grown on the nanoislands using MBE until the newly formed layers coalesce to form a uniform layer of a desired thickness. In an alternate embodiment, nanoholes are patterned into a silicon nitride layer to expose an elemental silicon surface of a substrate. Group II-VI semiconductor material is grown in the holes until the layers fill the holes and coalesce to form a uniform layer of a desired thickness. Suitable materials for the substrate include silicon and silicon on insulator materials and cadmium telluride may be used as the Group II-VI semiconductor. | 06-10-2010 |
20100148299 | Method of manufacturing semiconductor device, and semiconductor device - A method of manufacturing a semiconductor device of the present invention include a step of forming, in a substrate, a first trench, and a second trench which crosses the first trench; a step of forming a film over the entire surface of the substrate so as to fill the first trench and the second trench; and a step of removing a portion of the film which resides over the top surface of the substrate, so as to leave the film in the first trench and the second trench; wherein in the step of forming the first trench and the second trench, a projection is formed in a portion of intersection of the first trench and the second trench, so as to extend from one of corners of the portion of intersection towards the center thereof in a plan view. | 06-17-2010 |
20100148300 | ISOLATION TRENCH FILL USING OXIDE LINER AND NITRIDE ETCH BACK TECHNIQUE WITH DUAL TRENCH DEPTH CAPABILITY - An oxide layer is formed over a substrate having a smaller isolation trench and a large isolation trench. A nitride layer is formed over the oxide layer such that it completely fills the smaller isolation trench and lines the larger isolation trench. The nitride layer is etched back to form a recess in the nitride layer in the smaller isolation trench while at least a portion of the nitride layer lining the larger isolation trench is completely removed. A layer of HDP oxide is deposited over the substrate, completely filling the smaller and larger isolation trenches. The HDP oxide layer is planarized to the upper surface of the substrate. The deeper larger isolation trench may be formed by performing an etching step after the nitride layer has been etched back, prior to depositing HDP oxide. | 06-17-2010 |
20100155880 | Back gate doping for SOI substrates - A silicon-on-insulator (SOI) substrate comprises a base silicon substrate having a back gate region, wherein the back gate region has a first dopant concentration that is greater than 1×10 | 06-24-2010 |
20100155881 | Forming Isolation Regions For Integrated Circuits - A substrate may have active areas at different levels separated by a mask. Along the mask may be a shallow trench isolation. Along the shallow trench isolation may be a LOCOS isolation. The shape of a substrate transition region between the levels may be tunably controlled. The shallow trench isolation may reduce the bird's beak effect. | 06-24-2010 |
20100164054 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are provided. The semiconductor device can include a semiconductor substrate including a trench, a first oxide layer in the trench, a second oxide layer filled in the trench to form an insulating layer, and a silicon nitride layer interposed between the first and second oxide layers. The silicon nitride layer can be etched such that the silicon nitride layer is recessed from top surfaces of the semiconductor substrate and the second oxide layer, thereby forming a divot at a top corner of the trench. | 07-01-2010 |
20100176481 | Memory Device and Manufacturing Method Thereof - A memory device and a manufacturing method thereof are provided. The manufacturing method of memory device includes the following steps. Firstly, a substrate having a substrate surface is provided. Next, at least two memory units separated via a space are formed on the substrate. Then, an insulating layer covering the memory units and the substrate surface is formed. After that, a mask layer only covering the bottom of the insulating layer is formed on the insulating layer. Afterwards, the part of the insulating layer partially covered by the mask layer is etched. Then, the mask layer is removed. Next, the part of the insulating layer where the mask layer is removed is etched. Lastly, a protecting layer is formed on the memory units and in the space between the memory units. | 07-15-2010 |
20100176482 | LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH SUBSEQUENT SELF ALIGNED SHALLOW TRENCH ISOLATION - A semiconductor substrate structure for manufacturing integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate, the lower insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; an electrically conductive layer formed on the lower insulating layer; an insulator with etch stop characteristics formed on the electrically conductive layer; an upper insulating layer formed on the etch stop layer; and a semiconductor layer formed on the upper insulating layer. A scheme of subsequently building a dual-depth shallow trench isolation with the deeper STI in the back gate layer self-aligned to the shallower STI in the active region in such a semiconductor substrate is also disclosed. | 07-15-2010 |
20100181639 | SEMICONDUCTOR DEVICES AND FABRICATION METHODS THEREOF - A semiconductor device is provided. The semiconductor device comprises an epitaxial layer disposed on a semiconductor substrate, a plurality of electronic devices disposed on the epitaxial layer and a trench isolation structure disposed between the electric devices. The trench isolation structure comprises a trench in the epitaxial layer and the semiconductor substrate, an oxide liner on the sidewall and bottom of the trench, and a doped polysilicon layer filled in the trench. Moreover, a zero bias voltage can be applied to the doped polysilicon layer. The trench isolation structure can be used for isolating electronic devices having different operation voltages or high-voltage devices. | 07-22-2010 |
20100181640 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device about which the reliability thereof is certainly kept even when a void is generated in a buried film in its trench. A rectangular element formation region is formed in a silicon layer. A trench having a predetermined width is formed to surround the element formation region. A first TEOS film and a second TEOS film are buried in the trench. A protecting film is formed at an L-shaped intersection region of the trench. | 07-22-2010 |
20100187649 | CHARGE RESERVOIR STRUCTURE - The present invention relates to a process for preparing semiconductor on insulator type structures that include a semiconductor layer of a donor substrate, an insulator layer and a receiver substrate. The process includes bonding of the donor substrate onto the receiver substrate, with at least one of the substrates being coated with an insulator layer, and forming at the bonding interface a so-called trapping interface of electrically active traps suitable for retaining charge carriers. The invention also relates to a semiconductor on insulator type structure that includes such a trapping interface. | 07-29-2010 |
20100187650 | INSULATED WELL WITH A LOW STRAY CAPACITANCE FOR ELECTRONIC COMPONENTS - A structure including at least one electronic component formed in a semiconductor stack comprising a heavily-doped buried silicon layer of a first conductivity type extending on a lightly-doped silicon substrate of a second conductivity type and a vertical insulating trench surrounding the component. The trench penetrates, into the silicon substrate, under the silicon layer, down to a depth greater than the thickness of the space charge region in the silicon substrate. | 07-29-2010 |
20100193896 | METHOD FOR NITRIDATION OF SHALLOW TRENCH ISOLATION STRUCTURE TO PREVENT OXYGEN ABSORPTION - A method for forming an isolation structure includes forming a trench in a semiconductor layer. At least a portion of the trench is filled with a dielectric material including oxygen. A region comprising nitrogen is formed in at least an upper portion of the dielectric material. | 08-05-2010 |
20100193897 | SEMICONDUCTOR MATERIAL MANUFACTURE - Electronic apparatus, systems, and methods include a semiconductor layer bonded to a bulk region of a wafer or a substrate, in which the semiconductor layer can be bonded to the bulk region using electromagnetic radiation. Additional apparatus, systems, and methods are disclosed. | 08-05-2010 |
20100193898 | METHOD FOR FORMING TRENCH ISOLATION USING GAS CLUSTER ION BEAM PROCESSING - A method of forming shallow trench isolation on a substrate using a gas cluster ion beam (GCIB) is described. The method comprises generating a GCIB, and irradiating the substrate with the GCIB to form a shallow trench isolation structure by depositing a dielectric layer in at least one region on the substrate. | 08-05-2010 |
20100193899 | PRECISE OXIDE DISSOLUTION - In a Semiconductor-on-Insulator (SeOI) wafer that includes a thin working layer made from one or more semiconductor material(s); a support layer, and a buried oxide (BOX) layer between the working layer and the support layer, a method of decreasing the thickness of the BOX layer by dissolving it at a dissolution rate that is controlled and set to be below 0.06 Å/sec in order to avoid increasing Dit. The Dit after dissolution of the BOX layer is typically below 1E12 cm-2 eV-1. | 08-05-2010 |
20100200946 | Method for forming trench isolation using a gas cluster ion beam growth process - A method of forming shallow trench isolation on a substrate using a gas cluster ion beam (GCIB) is described. The method comprises generating a GCIB, and irradiating the substrate with the GCIB to form a shallow trench isolation structure by growing a dielectric layer in at least one region on the substrate. | 08-12-2010 |
20100207235 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes an isolation structure formed in a semiconductor substrate to delimit an active region. The active region includes a gate forming area. Spacers are formed on the side surfaces of the active region excluding portions of the side surfaces of the active region at the gate forming area, such that side surfaces of the gate forming area of the active region are exposed. A gate is formed to cover the exposed gate forming area of the active region. | 08-19-2010 |
20100207236 | METHOD FOR MAKING A SUBSTRATE OF THE SEMICONDUCTOR ON INSULATOR TYPE WITH AN INTEGRATED GROUND PLANE - A method for making a semiconductor on insulator (SeOI) type substrate that includes an integrated ground plane under the insulating layer wherein the substrate is intended to be used in making electronic components. This method includes implanting atoms or ions of a metal in at least one portion of a semiconducting receiver substrate, carrying out a heat treatment of the receiver substrate in order to obtain an integrated ground plane on or in at least one portion of that receiver substrate, transferring an active layer stemming from a semiconducting donor substrate onto the receiver substrate, with an insulating layer being inserted in between the donor and receiver substrates to obtain the substrate with an integrated ground plane. | 08-19-2010 |
20100219498 | METHOD FOR MANUFACTURING NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE, AND NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - An isolation oxide film whose upper surface is higher than a surface of a substrate is formed in the substrate. A silicon oxide film is formed on the substrate between the isolation oxide films. A self-aligned polysilicon film is formed on the silicon oxide film between the isolation oxide films. After forming a resist pattern covering the peripheral circuitry, the isolation oxide films in the memory cell are etched by a predetermined thickness. An ONO film is formed on the entire surface of the substrate, a second resist pattern covering the memory cell is formed. Then, the ONO film, the polysilicon film | 09-02-2010 |
20100219499 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - An excessive metallic film on a device isolation region is prevented from contributing to silicidation in an end of a source-drain diffusion layer region to thereby form a silicide film with uniform film thickness. There are sequentially conducted a step of forming a device isolation region | 09-02-2010 |
20100219500 | METHOD FOR MANUFACTURING DIRECT BONDED SOI WAFER AND DIRECT BONDED SOI WAFER MANUFACTURED BY THE METHOND - A direct bonded SOI wafer having an entire buried oxide film layer covered and not exposed is manufactured by: (A) forming a laminated body by laminating a semiconductor wafer and a support wafer via an oxide film; and (B) forming a thin-film single crystal silicon layer on the support wafer using a buried oxide film layer by film-thinning the semiconductor wafer to a predetermined thickness. In a process (C) the entire buried oxide film layer is covered by a main surface on the laminating side of the support wafer and the single crystal silicon layer. The covering of the entire buried film layer is carried out by, between process (A) and (B), removing the oxide film formed on the circumferential end edge of the main surface on the laminating side and the chamfered portion to leave the oxide film only on the laminated surface except the circumferential end edge. | 09-02-2010 |
20100224954 | SUBSTRATE COMPOSITIONS AND METHODS FOR FORMING SEMICONDUCTOR ON INSULATOR DEVICES - Methods and apparatus for producing a semiconductor on insulator structure include: subjecting an implantation surface of a donor single crystal semiconductor wafer to an ion implantation process to create an exfoliation layer of the donor semiconductor wafer; bonding the implantation surface of the exfoliation layer to a glass substrate using electrolysis, wherein a liquidus viscosity of the glass substrate is about 100,000 Poise or greater. | 09-09-2010 |
20100230776 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE - Briefly, in accordance with one or more embodiments, a semiconductor structure and method for forming the semiconductor structure are disclosed. The semiconductor structure may comprise a dielectric structure and one or more active areas or one or more field areas, for example, disposed proximate to the dielectric structure along a perimeter thereof. The dielectric structure and the other areas may be separated by one or more trenches or gaps to provide stress relief between the dielectric structure and the other areas. The one or more trenches may include one or more silicon formations formed there between to provide a spring like function and further provide stress relief between the dielectric structure and the other areas. Stress relief of the trenches may be further enhanced via hydrogen annealing to smooth sharp corners or other sharp features of the trenches such as scalloping. | 09-16-2010 |
20100230777 | SELECTIVE STI STRESS RELAXATION THROUGH ION IMPLANTATION - A first example embodiment comprises the following steps and the structure formed therefrom. A trench having opposing sidewalls is formed within a substrate. A stress layer having an inherent stress is formed over the opposing trench sidewalls. The stress layer having stress layer sidewalls over the trench sidewalls. Ions are implanted into one or more portions of the stress layer to form ion-implanted relaxed portions with the portions of the stress layer that are not implanted are un-implanted portions, whereby the inherent stress of the one or more ion-implanted relaxed portions of stress layer portions is relaxed. | 09-16-2010 |
20100244180 | METHOD FOR FABRICATING DEVICE ISOLATION STRUCTURE - A method of a fabricating a semiconductor device includes providing a substrate having a first region and a second region. A pad layer is formed overlying the substrate in both the first region and the second region. A mask layer is then formed overlying the pad layer. Thereafter, the mask layer, the pad layer and the substrate are patterned to form a plurality of first trenches in the first region and a plurality of second trenches in the second region. A trimming process is then performed on the mask layer to remove a portion of the mask layer. An insulation layer is formed over the substrate and fills the plurality of the first trenches and the plurality of the second trenches. Ultimately, a planarization process is performed on the insulation layer. | 09-30-2010 |
20100244181 | Filling Gaps in Integrated Circuit Fabrication - A gap may be filled using deposition and sputtering by forming a liner and a gap fill material in the same deposition chamber in some embodiments. The liner may be made harder than the gap fill so that the liner protects the underlying substrate when sputtering is used during the gap fill. | 09-30-2010 |
20100244182 | METHOD OF MANUFACTURING LAMINATED WAFER BY HIGH TEMPERATURE LAMINATING METHOD - To provide a method of manufacturing a laminated wafer by which a strong coupling is achieved between wafers made of different materials having a large difference in thermal expansion coefficient without lowering a maximum heat treatment temperature as well as in which cracks or chips of the wafer does not occur. A method of manufacturing a laminated wafer | 09-30-2010 |
20100244183 | INTEGRATED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An integrated semiconductor device and method of manufacturing the same includes leaving one part of a semiconductor layer so that an inclined surface is formed on a trench when forming the trench on a SOI wafer. A thick silicon oxide film (second insulation film) is formed along this incline surface. This thick silicon oxide film prevents oxygen entering a boundary surface between an insulation layer and the semiconductor layer of the SOI wafer within the trench. | 09-30-2010 |
20100244184 | Method of Forming an Electrical Contact Between a Support Wafer and the Surface of a Top Silicon Layer of a Silicon-on-Insulator Wafer and an Electrical Device Including Such an Electrical Contact - Method of forming an electrical contact between a support wafer and a surface of a top silicon layer of a silicon-on-insulator wafer. The method comprises etching a cavity into the top silicon layer and the insulator layer. A selective epitaxial step is performed for growing an epitaxial layer of silicon inside the cavity up to the surface of the top silicon layer. An electrical device comprising an electrical contact between a support wafer and a surface of a top silicon layer of a silicon-on-insulator wafer formed according to the inventive method. | 09-30-2010 |
20100252906 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device including a thin film device unit including a TFT, and a peripheral device unit provided around the thin film device unit and including a semiconductor element, includes a first step of preparing a substrate, a second step of bonding the peripheral device unit directly to the substrate, and a third step of forming the thin film device unit on the substrate to which the peripheral device unit is bonded. | 10-07-2010 |
20100264510 | SOI (SILICON ON INSULATOR) STRUCTURE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a SOI structure semiconductor device using a SOI substrate, a lattice distortion layer is formed by implanting Ar ions into a silicon substrate as an active layer. The lattice distortion layer is capable of serving as a gettering site. The dose amount of Ar ions is adjusted in such a manner that tensile stress in the lattice distortion layer is equal to or greater than 11 MPa and equal to or less than 27 MPa. Thus, the lattice distortion layer can prevent occurrence of a leakage current while serving as the gettering site. | 10-21-2010 |
20100270639 | MANUFACTURING METHOD OF SOI SUBSTRATE - There is provided a method of manufacturing an SOI substrate which is practicable even when a supporting substrate having a low allowable temperature limit is used. A separation layer is formed in a region at a certain depth from a surface of a semiconductor substrate, and a first heat treatment is conducted when a semiconductor layer on the separation layer is bonded to the supporting substrate and separated. A second heat treatment is conducted to the supporting substrate to which the semiconductor layer is bonded. The second heat treatment is conducted at a temperature which is equal to or higher than the temperature of the first heat treatment and does not exceed a strain point of the supporting substrate. When the first heat treatment and the second heat treatment are conducted at the same temperature, a treatment time of the second heat treatment may be set to be longer. | 10-28-2010 |
20100283118 | OXIDATION AFTER OXIDE DISSOLUTION - A method for manufacturing a SeOI substrate that includes a thin working layer made from one or more semiconductor material(s); a support layer; and a thin buried oxide layer between the working layer and the support layer. The method includes a manufacturing step of an intermediate SeOI substrate having a buried oxide layer with a thickness greater than a thickness desired for the thin buried oxide layer; and a dissolution step of the buried oxide layer in order to form therewith the thin buried oxide layer. After the dissolution step, an oxidation step of the substrate is conducted for creating an oxidized layer on the substrate, and an oxide migration step for diffusing at least a part of the oxide layer through the working layer in order to increase the electrical interface quality of the substrate and decrease its Dit value. | 11-11-2010 |
20100289113 | FABRICATION PROCESS OF A HYBRID SEMICONDUCTOR SUBSTRATE - The present invention relates to a method for manufacturing a hybrid semiconductor substrate comprising the steps of (a) providing a hybrid semiconductor substrate comprising a semiconductor-on-insulator (SeOI) region, that comprises an insulating layer over a base substrate and a SeOI layer over the insulating layer, and a bulk semiconductor region, wherein the SeOI region and the bulk semiconductor region share the same base substrate; (b) providing a mask layer over the SeOI region; and (c) forming a first impurity level by doping the SeOI region and the bulk semiconductor region simultaneously such that the first impurity level in the SeOI region is contained within the mask. Thereby avoiding higher number of process steps involved in the manufacturing process of hybrid semiconductor substrate. | 11-18-2010 |
20100289114 | SEMICONDUCTOR ELEMENT FORMED IN A CRYSTALLINE SUBSTRATE MATERIAL AND COMPRISING AN EMBEDDED IN SITU DOPED SEMICONDUCTOR MATERIAL - The PN junction of a substrate diode in a sophisticated SOI device may be formed on the basis of an embedded in situ doped semiconductor material, thereby providing superior diode characteristics. For example, a silicon/germanium semiconductor material may be formed in a cavity in the substrate material, wherein the size and shape of the cavity may be selected so as to avoid undue interaction with metal silicide material. | 11-18-2010 |
20100295147 | ISOLATION STRUCTURE AND FORMATION METHOD THEREOF - An isolation structure comprising a substrate is provided. A trench is in the substrate. A sidewall of the trench has a first inclined surface and a second inclined surface. The first inclined surface is located on the second inclined surface. The slope of the first inclined surface is different from the slope of the second inclined surface. A length of the first inclined surface is greater than 15 nanometers. | 11-25-2010 |
20100301446 | IN-LINE STACKING OF TRANSISTORS FOR SOFT ERROR RATE HARDENING - Each one of a pair of CMOS transistors is formed in its own island and a gate terminal for each transistor is formed by a single, in-line conductor connecting both gate terminals together. This type of “in-line” connection achieves nearly a five-time improvement in the reduction of the ability of ionizing radiation particles to strike both transistors at the same time as compared to prior art “side-by-side” transistor stacking through use of a relatively smaller solid angle spanning the two transistors. This results in “hardening” of the transistors and improving their resistance to single event upsets and, thus, improving the soft error rate (SER) of the transistors. | 12-02-2010 |
20100301447 | Epitaxy Silicon On Insulator (ESOI) - Methods and structures for semiconductor devices with STI regions in SOI substrates is provided. A semiconductor structure comprises an SOI epitaxy island formed over a substrate. The structure further comprises an STI structure surrounding the SOI island. The STI structure comprises a second epitaxial layer on the substrate, and a second dielectric layer on the second epitaxial layer. A semiconductor fabrication method comprises forming a dielectric layer over a substrate and surrounding a device fabrication region in the substrate with an isolation trench extending through the dielectric layer. The method also includes filling the isolation trench with a first epitaxial layer and forming a second epitaxial layer over the device fabrication region and over the first epitaxial layer. Then a portion of the first epitaxial layer is replaced with an isolation dielectric, and then a device such as a transistor is formed second epitaxial layer within the device fabrication region. | 12-02-2010 |
20100314711 | 3D INTEGRATED CIRCUIT DEVICE HAVING LOWER-COST ACTIVE CIRCUITRY LAYERS STACKED BEFORE HIGHER-COST ACTIVE CIRCUITRY LAYER - A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer that includes active circuitry is provided, and a first portion of the first active circuitry layer wafer is removed such that a second portion of the first active circuitry layer wafer remains. Another wafer that includes active circuitry is provided, and the other wafer is bonded to the second portion of the first active circuitry layer wafer. The first active circuitry layer wafer is lower-cost than the other wafer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure. | 12-16-2010 |
20100320559 | SEMICONDUCTOR DEVICE INCLUDING INDEPENDENT ACTIVE LAYERS AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate of n-type silicon including, in an upper portion thereof, a first polarity inversion region and a second polarity inversion regions spaced from each other and doped with a p-type impurity. A first HFET including a first active layer and a second HFET including a second active layer both made of a group III-V nitride semiconductor are independently formed on the respective polarity inversion regions in the semiconductor substrate, and the HFETs are electrically connected to each other through interconnects. | 12-23-2010 |
20100320560 | Metallic Bump Structure Without Under Bump Metallurgy And a Manufacturing Method Thereof - The metallic bump is directly formed on a semiconductor wafer's I/O pad without UBM. First, a zinc layer is formed on the I/O pad or an anti-oxidation layer of the I/O pad is selectively etched off. Then, an isolative layer and a copper foil are arranged sequentially in this order above the I/O pad. The isolative layer is originally in a liquid state or in a temporarily solid state and later permanently solidified. Then, a via above the I/O pad is formed by removing part of the isolative layer and the cooper foil. Subsequently, A thin metallic layer connecting the copper foil and the I/O pad is formed in the via and a plating resist on the copper foil is formed. Then, a metallic bump is formed from the via whose height is controlled by the plating resist. Finally, the plating resist and the copper foil are removed. | 12-23-2010 |
20100327396 | PATTERN STRUCTURE AND METHOD OF FORMING THE SAME - A pattern structure for a semiconductor device includes a plurality of first patterns, each of the first patterns extending in a first direction in the shape of a line, neighboring first patterns being spaced apart from each other by a gap distance, the plurality of first patterns including a plurality of trenches in parallel with the line shapes, respective trenches being between neighboring first patterns, the plurality of trenches including long trenches and short trenches alternately arranged in a second direction substantially perpendicular to the first direction, and at least a second pattern, the second pattern being coplanar with the first pattern, end portions of the first patterns being connected to the second pattern. | 12-30-2010 |
20110012223 | SEMICONDUCTOR-ON-INSULATOR WITH BACK SIDE SUPPORT LAYER - Embodiments of the present invention provide for the provisioning of efficient support to semiconductor-on-insulator (SOI) structures. Embodiments of the present invention may additionally provide for SOI structures with improved heat dissipation performance while preserving the beneficial electrical device characteristics that accompany SOI architectures. In one embodiment, an integrated circuit is disclosed. The integrated circuit comprises a silicon-on-insulator die from a silicon-on-insulator wafer. The silicon on insulator die comprises an active layer, an insulator layer, a substrate, and a strengthening layer. The substrate consists of an excavated substrate region, and a support region, the support region is in contact with the insulator layer. The support region and the strengthening layer are configured to act in combination to provide a majority of a required stabilizing force to the silicon-on-insulator die when it is singulated from the silicon-on-insulator wafer. | 01-20-2011 |
20110012224 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - In a semiconductor device having element isolation made of a trench-type isolating oxide film | 01-20-2011 |
20110012225 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - In a semiconductor device having element isolation made of a trench-type isolating oxide film | 01-20-2011 |
20110018090 | SEMICONDUCTOR DEVICE - To suppress stress variation on a channel forming region, a semiconductor device includes an element isolating region on the semiconductor substrate principal surface, and an element forming region on the principal surface to be surrounded by the element isolating region. The principal surface has orthogonal first and second directions. A circumferential shape of the element forming region has a first side extending along the first direction. The element forming region has a first transistor region (TR | 01-27-2011 |
20110024870 | LAYOUT FOR SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE - The invention relates to a semiconductor device and its layout, which allows a larger number of capacitors within the same area to increase the cell density, which enables to get a larger number of semiconductor chips out of one wafer, and which retains a sufficient gap between bit lines to prevent SAC failure of the storage node, and to a method of fabricating the semiconductor device. In a layout for a semiconductor device including active regions, device isolation films for defining the active regions, bit lines and word lines, and a method of fabricating the semiconductor device of the invention, each active region comprises a first active region, a right active region located on the right side of the first active region, a left active region located on the left side of the first active region, an upper active region located on the upper side of the first active region and a lower active region located on the lower side of the first active region, wherein the first active region, the right active region, the left active region, the upper active region and the lower active region respectively include an inclined portion having a bit-line contact region; and first and second portions having a storage node contact region, the first end and the second end being respectively formed on the left and right ends of the inclined portion at a predetermined tilt angle with respect to the inclined portion, the active region having two word lines and one bit line intersecting one another. | 02-03-2011 |
20110031580 | METHOD FOR MANUFACTURING NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE, AND NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - An isolation oxide film whose upper surface is higher than a surface of a substrate is formed in the substrate. A silicon oxide film is formed on the substrate between the isolation oxide films. A self-aligned polysilicon film is formed on the silicon oxide film between the isolation oxide films. After forming a resist pattern covering the peripheral circuitry, the isolation oxide films in the memory cell are etched by a predetermined thickness. An ONO film is formed on the entire surface of the substrate, a second resist pattern covering the memory cell is formed. Then, the ONO film, the polysilicon film | 02-10-2011 |
20110037140 | INTEGRATED CIRCUIT SYSTEM WITH SEALRING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture an integrated circuit system includes: forming an insulation region in a base layer; filling an insulator in the insulation region around a perimeter of a main chip region; forming a contact directly on and within planar extents of the insulator; and forming an upper layer over the contact to protect the main chip region. | 02-17-2011 |
20110037141 | Semiconductor Device and Method of Fabricating the Same - A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region. | 02-17-2011 |
20110042777 | Deep trench isolation structure - A deep trench isolation structure including a deep trench disposed within a substrate to surround an active area on the substrate and a dielectric material filled within the deep trench. The deep trench comprises at least a corner in an arc shape layout or in a polygonal line shape layout. Accordingly, the deep trench isolation structure can be obtained in a better stress condition and with less process time for trench filling. | 02-24-2011 |
20110042778 | SEMICONDUCTOR DEVICE HAVING LOCALIZED INSULATED BLOCK IN BULK SUBSTRATE AND RELATED METHOD - One or more trenches can be formed around a first portion of a semiconductor substrate, and an insulating layer can be formed under the first portion of the semiconductor substrate. The one or more trenches and the insulating layer electrically isolate the first portion of the substrate from a second portion of the substrate. The insulating layer can be formed by forming a buried layer in the substrate, such as a silicon germanium layer in a silicon substrate. One or more first trenches through the substrate to the buried layer can be formed, and open spaces can be formed in the buried layer (such as by using an etch selective to silicon germanium over silicon). The one or more first trenches and the open spaces can optionally be filled with insulative material(s). One or more second trenches can be formed and filled to isolate the first portion of the substrate. | 02-24-2011 |
20110042779 | FUSE LINK STRUCTURES USING FILM STRESS FOR PROGRAMMING AND METHODS OF MANUFACTURE - A method of forming a programmable fuse structure includes forming at least one shallow trench isolation (STI) in a substrate, fanning an e-fuse over the at least one STI and depositing an interlevel dielectric (ILD) layer over the e-fuse. Additionally, the method includes removing at least a portion of the at least one STI under the e-fuse to provide an air gap below a portion of the e-fuse and removing at least a portion of the ILD layer over the e-fuse to provide the air gap above the portion of the e-fuse. | 02-24-2011 |
20110042780 | METHODS OF MANUFACTURING SEMICONDUCTOR STRUCTURES AND SEMICONDUCTOR STRUCTURES OBTAINED BY SUCH METHODS - In preferred embodiments, this invention provides a semiconductor structure that has a semi-conducting support, an insulating layer arranged on a portion of the support and a semi-conducting superficial layer arranged on the insulating layer. Electronic devices can be formed in the superficial layer and also in the exposed portion of the semi-conducting bulk region of the substrate not covered by the insulating layer. The invention also provides methods of fabricating such semiconductor structures which, starting from a substrate that includes a semi-conducting superficial layer arranged on a continuous insulating layer both of which being arranged on a semi-conducting support, by transforming at least one selected region of a substrate so as to form an exposed semi-conducting bulk region of the substrate. | 02-24-2011 |
20110049668 | DEEP TRENCH ISOLATION STRUCTURES BETWEEN HIGH VOLTAGE SEMICONDUCTOR DEVICES AND FABRICATION METHODS THEREOF - Deep trench isolation structures between high voltage semiconductor devices and fabrication methods thereof are presented. The high voltage semiconductor device includes a semiconductor substrate, pluralities of intersecting deep trench isolation structures defining several high voltage semiconductor device regions, and an island at the center of the intersection between the two deep trench isolation structures, wherein the two intersecting deep trench isolation structures h | 03-03-2011 |
20110062546 | STRUCTURE AND METHOD TO MINIMIZE REGROWTH AND WORK FUNCTION SHIFT IN HIGH-K GATE STACKS - The present invention provides a semiconductor structure comprising high-k material portions that are self-aligned with respect to the active areas in the semiconductor substrate and a method of fabricating the same. The high-k material is protected from oxidation during the fabrication of the semiconductor structure and regrowth of the high-k material and shifting of the high-k material work function is prevented. | 03-17-2011 |
20110068431 | SEMICONDUCTOR STRUCTURES AND METHODS FOR FORMING ISOLATION BETWEEN FIN STRUCTURES OF FINFET DEVICES - Semiconductor structures and methods for forming isolation between fin structures formed from a bulk silicon wafer are provided. A bulk silicon wafer is provided having one or more fin structures formed therefrom. Forming of the fin structures defines isolation trenches between the one or more fin structures. Each of the fin structures has vertical sidewalls. An oxide layer is deposited in the isolation trenches and on the vertical sidewalls using HPDCVD in about a 4:1 ratio or greater. The oxide layer is isotropically etched to remove the oxide layer from the vertical sidewalls and a portion of the oxide layer from the bottom of the isolation trenches. A substantially uniformly thick isolating oxide layer is formed on the bottom of the isolation trench to isolate the one or more fin structures and substantially reduce fin height variability. | 03-24-2011 |
20110073985 | Method of Generating Uniformly Aligned Well and Isolation Regions in a Substrate and Resulting Structure - A solution for alleviating variable parasitic bipolar leakages in scaled semiconductor technologies is described herein. Placement variation is eliminated for edges of implants under shallow trench isolation (STI) areas by creating a barrier to shield areas from implantation more precisely than with only a standard photolithographic mask. An annealing process expands the implanted regions such their boundaries align within a predetermined distance from the edge of a trench. The distances are proportionate for each trench and each adjacent isolation region. | 03-31-2011 |
20110084355 | Isolation Structure For Semiconductor Device - A semiconductor device is provided. The semiconductor device includes a substrate, an isolation feature disposed on the substrate, and an active area disposed adjacent the isolation feature. The isolation feature may be a shallow trench isolation feature. The STI feature has a first width at the top of the feature and a second width at the bottom of the feature. The first width is less than the second width. Methods of fabricating a semiconductor device is also provided. A method includes forming shallow trench isolation features and then growing an epitaxial layer adjacent the STI features to form an active region. | 04-14-2011 |
20110084356 | LOCAL BURIED LAYER FORMING METHOD AND SEMICONDUCTOR DEVICE HAVING SUCH A LAYER - The present invention discloses a method of forming a local buried layer ( | 04-14-2011 |
20110089524 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same capable of reducing variations in the thickness of a semiconductor device are provided. The amount of oxygen implanted ions is less than the amount of implanted oxygen ions in the conventional epitaxial SIMOX wafers. Oxygen is ion-implanted into the surface layer of a silicon wafer from the surface of the wafer. Then, by heat treating the wafer, a thinning stop layer, which is an imperfect buried oxide film, is formed along the entire plane of the wafer. As a result, variation of the thickness of the semiconductor device formed in an active layer can be reduced, since the, the reliability of the accuracy of the end point of silicon wafer thinning is higher than that of a thinning using the conventional deep trench structure as an end point detector. | 04-21-2011 |
20110089525 | Manufacturing method for semiconductor device and semiconductor device - A trench is formed on a semiconductor substrate with a first insulation film patterned on the semiconductor substrate as a mask; a second insulation film is embedded in the trench and flattened; an upper portion of the first insulation film is selectively removed, and a part of a side face of the second insulation film is exposed; a part of the second insulation film is isotropically removed; a lower portion of the remaining first insulation film is selectively removed; and then a part of the remaining second insulation film is further isotropically removed so that an upper face of the second insulation film is at a predetermined height from a surface of the semiconductor substrate, a taper having a minimum taper angle of 90° or more is formed on the side face of the second insulation film, and a STI is formed. | 04-21-2011 |
20110095393 | CREATING EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) HAVING SUBSTANTIALLY UNIFORM THICKNESS - An extremely thin semiconductor-on-insulator (ETSOI) wafer is created having a substantially uniform thickness by measuring a semiconductor layer thickness at a plurality of selected points on a wafer; determining a removal thickness to be removed at each of the plurality of selected points such that removal of the removal thickness results in a substantially uniform within-wafer semiconductor layer thickness; implanting a species into the wafer at each of the plurality of selected points with at least one of a dose level and an energy level based on the removal thickness for the respective point; and polishing the semiconductor layer to thin the semiconductor layer. | 04-28-2011 |
20110101488 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor device includes: providing a substrate; forming a plurality of trenches by etching the substrate; forming a first isolation layer by filling the plurality of the trenches with a first insulation layer; recessing the first insulation layer filling a first group of the plurality of the trenches to a predetermined depth; forming a liner layer over the first group of the trenches with the first insulation layer recessed to the predetermined depth; and forming a second isolation layer by filling the first group of the trenches, where the liner layer is formed, with a second insulation layer. | 05-05-2011 |
20110101489 | SiCOH DIELECTRIC MATERIAL WITH IMPROVED TOUGHNESS AND IMPROVED Si-C BONDING, SEMICONDUCTOR DEVICE CONTAINING THE SAME, AND METHOD TO MAKE THE SAME - A low-k dielectric material with increased cohesive strength for use in electronic structures including interconnect and sensing structures is provided that includes atoms of Si, C, O, and H in which a fraction of the C atoms are bonded as Si—CH | 05-05-2011 |
20110101490 | CONTOURED INSULATOR LAYER OF SILICON-ON-INSULATOR WAFERS AND PROCESS OF MANUFACTURE - A silicon-on-insulator wafer. The SOI wafer comprises a top silicon layer, a silicon substrate, and an oxide insulator layer disposed across the wafer and between the silicon substrate and the top silicon layer. The oxide insulator layer has at least one of a contoured top surface and a contoured bottom surface. Also provided are processes for manufacturing such a SOI wafer. | 05-05-2011 |
20110108943 | HYBRID DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH ENHANCED MOBILITY CHANNELS - A semiconductor wafer structure for integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate; an electrically conductive back gate layer formed on the lower insulating layer; an upper insulating layer formed on the back gate layer; and a hybrid semiconductor-on-insulator layer formed on the upper insulating layer, the hybrid semiconductor-on-insulator layer comprising a first portion having a first crystal orientation and a second portion having a second crystal orientation. | 05-12-2011 |
20110115044 | DIFFUSION SIDEWALL FOR A SEMICONDUCTOR STRUCTURE - A method of forming diffusion sidewalls in a semiconductor structure and a semiconductor structure having diffusion sidewalls includes etching a trench into a semiconductor substrate to form first and second active regions, lining each trench with an oxide liner along exposed sidewalls of an active silicon region (RX) of the first and second active regions, removing the oxide liner formed along the exposed sidewalls of the RX region of one of the first and second active regions, forming diffusion sidewalls by epitaxially growing in-situ doped material within the exposed sidewalls of the RX region of the one of the first and second active regions, and forming an isolation region within the trench between the first and second active regions to electrically isolate the first and second active regions from each other. | 05-19-2011 |
20110115045 | SUBSTRATE FOR MANUFACTURING SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A substrate with which a semiconductor device with excellent electric characteristics and high reliability can be manufactured is provided. An aspect of the invention is a method for manufacturing a substrate for manufacturing a semiconductor device: a first silicon oxide film, a silicon nitride film, and a second silicon oxide film are stacked in this order over a surface of a semiconductor substrate by a thermal CVD method, and then a weakened layer is formed at a given depth of the semiconductor substrate; the semiconductor substrate and a substrate having an insulating surface are arranged to face each other, and the second silicon oxide film provided for the semiconductor substrate and a supporting substrate are bonded to each other; and the semiconductor substrate is separated at the weakened layer by heat treatment, whereby a semiconductor film separated from the semiconductor substrate is left over the substrate having the insulating surface. | 05-19-2011 |
20110115046 | METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE, AND SEMICONDUCTOR DEVICE - Methods for manufacturing a semiconductor substrate and a semiconductor device by which a high-performance semiconductor element can be formed are provided. A single crystal semiconductor substrate including an embrittlement layer and a base substrate are bonded to each other with an insulating layer interposed therebetween, and the single crystal semiconductor substrate is separated along the embrittlement layer by heat treatment to fix a single crystal semiconductor layer over the base substrate. Next, a plurality of regions of a monitor substrate are irradiated with laser light under conditions of different energy densities, and carbon concentration distribution and hydrogen concentration distribution in a depth direction of each region of the single crystal semiconductor layer which has been irradiated with the laser light is measured. Optimal irradiation intensity of laser light is irradiation intensity with which a local maximum of the carbon concentration and a shoulder peak of the hydrogen concentration are observed. A single crystal semiconductor layer is irradiated with optimal laser light at energy density detected by using the monitor substrate, whereby a semiconductor substrate is manufactured. | 05-19-2011 |
20110127632 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor memory device includes a substrate, a patterned dielectric layer on the substrate, a patterned conductive layer on the patterned dielectric layer, and a plurality of isolation structures to provide electrical isolation for the patterned conductive layer. Each of the isolation structures includes a base in the substrate, a first bank extending from the base to the patterned conductive layer, and a second bank extending from the base to the patterned conductive layer, the first bank and the second bank being separated from each other over the substrate. | 06-02-2011 |
20110127633 | Slotted Configuration for Optimized Placement of Micro-Components using Adhesive Bonding - An arrangement for improving adhesive attachment of micro-components in an assembly utilizes a plurality of parallel-disposed slots formed in the top surface of the substrate used to support the micro-components. The slots are used to control the flow and “shape” of an adhesive “dot” so as to quickly and accurately attach a micro-component to the surface of a substrate. The slots are formed (preferably, etched) in the surface of the substrate in a manner that lends itself to reproducible accuracy from one substrate to another. Other slots (“channels”) may be formed in conjunction with the bonding slots so that extraneous adhesive material will flow into these channels and not spread into unwanted areas. | 06-02-2011 |
20110133306 | SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - Provided are a semiconductor device and a method of forming the same. According to the method, a first buried oxide layer is locally formed in a semiconductor substrate and a core semiconductor pattern of a line form, a pair of anchor-semiconductor patterns and a support-semiconductor pattern are formed by patterning a semiconductor layer on the first buried oxide layer to expose the first buried oxide layer. The pair of anchor-semiconductor patterns contact both ends of the core semiconductor pattern, respectively, and the support-semiconductor pattern contacts one sidewall of the core semiconductor pattern, the first buried oxide layer below the core semiconductor pattern is removed. At this time, a portion of the first buried oxide layer below each of the anchor-semiconductor patterns and a portion of the first buried oxide layer below the support-semiconductor pattern remain. A second buried oxide layer is formed to fill a region where the first buried oxide layer below the core semiconductor pattern. | 06-09-2011 |
20110140228 | Method of Filling Large Deep Trench with High Quality Oxide for Semiconductor Devices - A method is disclosed for creating a semiconductor device structure with an oxide-filled large deep trench (OFLDT) portion having trench size TCS and trench depth TCD. A bulk semiconductor layer (BSL) is provided with a thickness BSLT>TCD. A large trench top area (LTTA) is mapped out atop BSL with its geometry equal to OFLDT. The LTTA is partitioned into interspersed, complementary interim areas ITA-A and ITA-B. Numerous interim vertical trenches of depth TCD are created into the top BSL surface by removing bulk semiconductor materials corresponding to ITA-B. The remaining bulk semiconductor materials corresponding to ITA-A are converted into oxide. If any residual space is still left between the so-converted ITA-A, the residual space is filled up with oxide deposition. Importantly, the geometry of all ITA-A and ITA-B should be configured simple and small enough to facilitate fast and efficient processes of oxide conversion and oxide filling. | 06-16-2011 |
20110140229 | TECHNIQUES FOR FORMING SHALLOW TRENCH ISOLATION - Techniques are disclosed for shallow trench isolation (STI). The techniques can be used to form STI structures on any number of semiconductor materials, including germanium (Ge), silicon germanium (SiGe), and III-V material systems. In general, an interfacial passivation layer is used as a liner between the semiconductor surface (such as diffusion) and isolation materials within the STI. The interfacial layer provides a passivation layer on trench surfaces to restrict free bonding electrons of the substrate material. In addition, this passivation layer is oxidized, thereby effectively forming a bi-layer (passivation and oxidation sub-layers) to form an electrically defect free interface. The interfacial bi-layer structure can be implemented, for example, with materials that will covalently bond with free bonding electrons of the substrate materials, and that will oxidize to provide transition to oxide material. | 06-16-2011 |
20110140230 | MANUFACTURE OF THIN SILICON-ON-INSULATOR (SOI) STRUCTURES - The present invention relates to a method of forming a SOI structure having a thin silicon layer by forming a first etch stop layer on a donor substrate, forming a second etch stop layer on the first etch stop layer, wherein the material of the second etch stop layer differs from the material of the first etch stop layer, forming a thin silicon layer on the second etch stop layer, preferably by epitaxy, and bonding the intermediate structure to a target substrate, followed by detaching the donor substrate by splitting initiated in the first etch stop layer at a weakened region and removing the remaining material of the etch stop layers to produce a final ETSOI structure. The invention also relates to the ETSOI structure produces by the described method. | 06-16-2011 |
20110147881 | HYBRID SUBSTRATE WITH IMPROVED ISOLATION AND SIMPLIFIED METHOD FOR PRODUCING A HYBRID SUBSTRATE - A hybrid substrate comprises first and second active areas made from semiconductor materials laterally offset from one another and separated by an isolation area. The main surfaces of the isolation area and of the first active area form a plane. The hybrid substrate is obtained from a source substrate successively comprising layers made from a first and second semiconductor materials separated by an isolation layer. A single etching mask is used to pattern the isolation area, first active area and second active area. The main surface of the first active area is released thereby forming voids in the source substrate. The etching mask is eliminated above the first active area. A first isolation material is deposited, planarized and etched until the main surface of the first active area is released. | 06-23-2011 |
20110147882 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes an interlayer dielectric with a single-layer structure having a plurality of pores. The porosity of the interlayer dielectric per unit volume varies in a thickness direction. | 06-23-2011 |
20110156200 | SEMICONDUCTOR DEVICE - A semiconductor memory device includes a semiconductor substrate provided with active areas and an element-isolating insulating film isolating the active areas from each other, the active areas each extending in a first direction; an interlayer insulating film formed on a surface of the semiconductor substrate; and a contact member provided in the interlayer insulating film, and including a first portion and a second portion, the first portion electrically connected to a wire above the semiconductor substrate, the second portion having a shape that spreads out of the first portion as viewed from above and connected to the first portion. A maximum width of the second portion measured in the first direction is larger than a width of the first portion measured in the first direction, and the second portion is in contact with the interlayer insulating film that surrounds the first portion. | 06-30-2011 |
20110163410 | METHOD FOR PRODUCING HYBRID COMPONENTS - A method for producing a hybrid substrate, including a support substrate, a continuous buried insulator layer and, on this continuous layer, a hybrid layer including alternating zones of a first material and at least one second material, wherein these two materials are different by their nature and/or their crystallographic characteristics. The method forms a hybrid layer, including alternating zones of first and second materials, on a homogeneous substrate, assembles this hybrid layer, the continuous insulator layer and the support substrate, and eliminates a part at least of the homogeneous substrate, before or after the assembling. | 07-07-2011 |
20110163411 | MULTI-LAYER MEMORY DEVICES - A nonvolatile memory device includes a semiconductor substrate having a first well region of a first conductivity type, and at least one semiconductor layer formed on the semiconductor substrate. A first cell array is formed on the semiconductor substrate, and a second cell array formed on the semiconductor layer. The semiconductor layer includes a second well region of the first conductivity type having a doping concentration greater than a doping concentration of the first well region of the first conductivity type. As the doping concentration of the second well region is increased, a resistance difference may be reduced between the first and second well regions. | 07-07-2011 |
20110169125 | METHOD FOR FORMING TRENCHES IN A SEMICONDUCTOR COMPONENT - A method is described for creating at least one recess in a semiconductor component, in particular a micromechanical or electrical semiconductor component, having the following steps: applying at least one mask to the semiconductor component, forming at least one lattice having at least one or more lattice openings in the mask over the recess to be formed, the lattice opening or lattice openings being formed as a function of the etching rate and/or the dimensioning of the recess to be formed; forming the recess below the lattice. | 07-14-2011 |
20110175190 | DEEP WELL STRUCTURES WITH SINGLE DEPTH SHALLOW TRENCH ISOLATION REGIONS - A semiconductor device structure includes a first type region and a second type region defined in a substrate, the first type region and second type region separated by one or more inter-well shallow trench isolation (STI) structures. At least one of the first type region and the second type region has one or more intra-well STI structures formed therein for isolating semiconductor devices formed within a same polarity well. The inter-well STI structures are formed at a substantially same depth with respect to the intra-well STI structures. A main well region is formed such that a bottom of the main well region is disposed above a bottom of the inter-well and intra-well STI features. One or more deep well regions couple the main well regions otherwise isolated by the intra-well STI structures, wherein the deep well regions are spaced away from the inter-well STI structures. | 07-21-2011 |
20110175191 | ISOLATION TRENCHES FOR SEMICONDUCTOR LAYERS - A method is for the formation of at least one isolation trench filled with thermal oxide in a semiconductor layer and a semiconductor device include at least one isolation trench filled with thermal oxide. The method allows obtaining in an easy way, isolation trenches exhibiting excellent functional morphological properties. The method is based on the idea of exploiting the properties of the thermal oxidation mechanism of a semiconductor material in order to obtain at least an isolation trench filled with thermal oxide. | 07-21-2011 |
20110180896 | METHOD OF PRODUCING BONDED WAFER STRUCTURE WITH BURIED OXIDE/NITRIDE LAYERS - A method of forming a bonded wafer structure includes providing a first semiconductor wafer substrate having a first silicon oxide layer at the top surface of the first semiconductor wafer substrate; providing a second semiconductor wafer substrate; forming a second silicon oxide layer on the second semiconductor wafer substrate; forming a silicon nitride layer on the second silicon oxide layer; and bringing the first silicon oxide layer of the first semiconductor wafer substrate into physical contact with the silicon nitride layer of the second semiconductor wafer substrate to form a bonded interface between the first silicon oxide layer and the silicon nitride layer. Alternatively, a third silicon oxide layer may be formed on the silicon nitride layer before bonding. A bonded interface is then formed between the first and third silicon oxide layers. A bonded wafer structure formed by such a method is also provided. | 07-28-2011 |
20110186957 | SEMICONDUCTOR ELEMENT COMPRISING A LOW VARIATION SUBSTRATE DIODE - A substrate diode of an SOI device may be formed on the basis of contact regions in an early manufacturing stage, i.e., prior to patterning gate electrode structures of transistors, thereby imparting superior stability to the sensitive diode regions, such as the PN junction. In some illustrative embodiments, only one additional deposition step may be required compared to conventional strategies, thereby providing a very efficient overall process flow. | 08-04-2011 |
20110186958 | SOI SUBSTRATE AND MANUFACTURING METHOD THEREOF - A bond substrate is irradiated with ions, so that an embrittlement layer is formed, then, the bond substrate is bonded to a base substrate. Next, a part of a region of the bonded bond substrate is heated at a temperature higher than a temperature of the other part of the region of the bond substrate, or alternatively, a first heat treatment is performed on the bonded bond substrate as a whole at a first temperature; and a second heat treatment is performed on a part of a region of the bonded bond substrate at a second temperature higher than the first temperature, so that separation of the bond substrate proceeds from the part of the region of the bond substrate to the other part of the region of the bond substrate in the embrittlement layer. Accordingly, a semiconductor layer is formed over the base substrate. | 08-04-2011 |
20110193189 | SEMICONDUCTOR SUBSTRATE, METHOD OF FABRICATING THE SAME, METHOD OF FABRICATING SEMICONDUCTOR DEVICE, AND METHOD OF FABRICATING IMAGE SENSOR - In an example embodiment, an image sensor includes a semiconductor layer and isolation regions disposed in the semiconductor layer. The isolation regions define active regions of the semiconductor layer. The image sensor further includes photoelectric converters disposed in the semiconductor layer and at least one wiring layer disposed over a top surface of the semiconductor layer. The image sensor also includes color filters disposed below a bottom surface of the semiconductor layer and lenses disposed below the color filters. Each lens is arranged to concentrate incoming light into an area spanned by a corresponding photoelectric converter. | 08-11-2011 |
20110193190 | SEMICONDUCTOR MATERIAL MANUFACTURE - Electronic apparatus, systems, and methods include a semiconductor layer bonded to a bulk region of a wafer or a substrate, in which the semiconductor layer can be bonded to the bulk region using electromagnetic radiation. Additional apparatus, systems, and methods are disclosed. | 08-11-2011 |
20110198721 | METHOD FOR THINNING A WAFER - A method for thinning a wafer is provided. In one embodiment, a wafer is provided having a plurality of semiconductor chips, the wafer having a first side and a second side opposite the first side, wherein each of the chips includes a set of through silicon vias (TSVs), each of the TSVs substantially sealed by a liner layer and a barrier layer. A wafer carrier is provided for attaching to the second side of the wafer. The first side of the wafer is thinned and thereafer recessed to partially expose portions of the liner layers, barrier layers and the TSVs protruding from the wafer. An isolation layer is deposited over the first side of the wafer and the top portions of the liner layers, barrier layers and the TSVs. Thereafter, an insulation layer is deposited over the isolation layer. The insulation layer is then planarized to expose top portions of the TSVs. A dielectric layer is deposited over the planarized first side of the wafer. One or more electrical contacts are formed in the dielectric layer for electrical connection to the exposed one or more TSVs. | 08-18-2011 |
20110204471 | SEMICONDUCTOR WAFERS WITH REDUCED ROLL-OFF AND BONDED AND UNBONDED SOI STRUCTURES PRODUCED FROM SAME - The disclosure relates to preparation of silicon on insulator structures with reduced unbonded regions and to methods for producing such wafers by minimizing the roll-off amount (ROA) of the handle and donor wafers. Methods for polishing wafers are also provided. | 08-25-2011 |
20110215436 | SEMICONDUCTOR DEVICES INCLUDING A DIODE STRUCTURE OVER A CONDUCTIVE STRAP AND METHODS OF FORMING SUCH SEMICONDUCTOR DEVICES - Semiconductor devices including at least one diode over a conductive strap. The semiconductor device may include at least one conductive strap over an insulator material, at least one diode comprising a single crystalline silicon material over a conductive material, and a memory cell on the at least one diode. The at least one diode may be formed from a single crystalline silicon material. Methods of forming such semiconductor devices are also disclosed. | 09-08-2011 |
20110215437 | METHOD OF PATTERNING SEMICONDUCTOR STRUCTURE AND STRUCTURE THEREOF - Method of patterning a semiconductor structure is disclosed. The method involves crystallographic etching techniques to enhance a patterned monocrystalline layer as a hard mask. In one embodiment, the method includes bonding a monocrystalline silicon layer to a non-crystalline protective layer; patterning the monocrystalline layer to form a hard mask; enhancing the pattern of the hard mask; stripping the hard mask after conventional etching of protective layer; and forming a gate oxide thereon. The enhanced patterning of the hard mask is performed with crystallographic etching to replace optical effects of rounding and dimension narrowing at the ends of a defined region with straight edges and sharp corners. A resulting structure from the use of the enhanced patterned hard mask includes a layer of composite materials on the substrate of the semiconductor structure. The layer of composite materials includes different materials in discrete blocks defined by straight edges within the layer. | 09-08-2011 |
20110221030 | CHARGE BREAKDOWN AVOIDANCE FOR MIM ELEMENTS IN SOI BASE TECHNOLOGY AND METHOD - A semiconductor device including at least one capacitor formed in wiring levels on a silicon-on-insulator (SOI) substrate, wherein the at least one capacitor is coupled to an active layer of the SOI substrate. A method of fabricating a semiconductor structure includes forming an SOI substrate, forming a BOX layer over the SOI substrate, and forming at least one capacitor in wiring levels on the BOX layer, wherein the at least one capacitor is coupled to an active layer of the SOI substrate. | 09-15-2011 |
20110227190 | ELECTRONIC DEVICE PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME - The invention provides an electronic device package structure and method of fabrication thereof. The electronic device package structure includes a chip having an active surface and a bottom surface. A dielectric layer is disposed on the active surface of the chip. At least one trench is formed through the dielectric layer. A first protection layer covers the dielectric layer and sidewalls of the trench. A second protection layer covers the first protection layer, filling the trench. | 09-22-2011 |
20110233718 | Heterogeneous Technology Integration - A heterogeneous integrated circuit having at least one tier made of multiple technologies and a method of making the heterogeneous integrated circuit. The heterogeneous integrated circuit includes a package substrate, a first die of a first technology, and a second die of a second technology, where the two dies are located in the same tier. One die can surround the other die. The heterogeneous integrated circuit can also include a wire-bond and/or horizontal micro-bump coupling the two dies. The heterogeneous integrated circuit can also include a wire bond or vertical micro-bump coupling one of the dies to the package substrate. The vertical micro-bump coupling can include a through-via. The two technologies can be any of various technologies including CMOS, glass, sapphire and quartz. One die can also be adjacent to the other die on the same tier and the two dies coupled using a horizontal micro-bump. | 09-29-2011 |
20110233719 | TEST METHOD ON THE SUPPORT SUBSTRATE OF A SUBSTRATE OF THE "SEMICONDUCTOR ON INSULATOR" TYPE - The invention relates to a test method comprising an electrical connection contact on the support of a substrate of the semiconductor-on-insulator type. | 09-29-2011 |
20110233720 | TREATMENT FOR BONDING INTERFACE STABILIZATION - A method and/or system are provided for producing a structure comprising a thin layer of semiconductor material on a substrate. The method includes creating an area of embrittlement in the thickness of a donor substrate, bonding the donor substrate with a support substrate and detaching the donor substrate at the level of the area of embrittlement to transfer a thin layer of the donor substrate onto the support substrate. The method also includes thermal treatment of this resulting structure to stabilize the bonding interface between the thin layer and the substrate support. The invention also relates to the structures obtained by such a process. | 09-29-2011 |
20110241157 | METHOD FOR MANUFACTURING A SEMICONDUCTOR SUBSTRATE - The invention relates to a method for manufacturing a semiconductor substrate, in particular a semiconductor-on-insulator substrate by providing a donor substrate and a handle substrate, forming a pattern of one or more doped regions typically inside the handle substrate, and then attaching such as by molecular bonding the donor and the handle substrate to obtain a donor-handle compound. | 10-06-2011 |
20110248376 | Semiconductor Devices Having a Support Structure for an Active Layer Pattern and Methods of Forming the Same - Semiconductor devices include a semiconductor substrate with a stack structure protruding from the semiconductor substrate and surrounded by an isolation structure. The stack structure includes an active layer pattern and a gap-filling insulation layer between the semiconductor substrate and the active layer pattern. A gate electrode extends from the isolation structure around the stack structure. The gate electrode is configured to provide a support structure for the active layer pattern. The gate electrode may be a gate electrode of a silicon on insulator (SOI) device formed on the semiconductor wafer and the semiconductor device may further include a bulk silicon device formed on the semiconductor substrate in a region of the semiconductor substrate not including the gap-filing insulation layer. | 10-13-2011 |
20110248377 | SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor substrate having an SOI layer is provided. Between an SOI layer and a glass substrate, a bonding layer is provided which is formed of one layer or a plurality of layers of phosphosilicate glass, borosilicate glass, and/or borophosphosilicate glass, using organosilane as one material by a thermal CVD method at a temperature of 500° C. to 800° C. | 10-13-2011 |
20110260282 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHODS - Methods of making fins and semiconductor structures containing fins are provided. The methods involve forming a multi-layer structure over fins and isolation materials and performing a multi-stage etching process to remove upper portions of the multi-layer structure and upper portions of isolation materials. Upper portions of the fins are exposed by removing the upper portions of the isolation materials via the multi-stage etching process. A stage of the multi-stage etching process removes an upper layer of the multi-layer structure and an upper portion of the isolation materials, and the stage can be terminated about at the same time when the upper surface of the underlying layer of the multi-layer structure is exposed. | 10-27-2011 |
20110260283 | DIELECTRIC COMPOSITION FOR THIN-FILM TRANSISTORS - An electronic device, such as a thin-film transistor, includes a substrate and a dielectric layer formed from a dielectric composition. The dielectric composition includes a dielectric material, a crosslinking agent, and an infrared absorbing agent. In particular embodiments, the dielectric material comprises a lower-k dielectric material and a higher-k dielectric polymer. When deposited, the lower-k dielectric material and the higher-k dielectric material form separate phases. The infrared absorbing agent allows the dielectric composition to attain a temperature that is significantly greater than the temperature attained by the substrate during curing. This difference in temperature allows the dielectric layer to be cured at relatively high temperatures and/or shorter time periods, permitting the selection of lower-cost substrate materials that would otherwise be deformed by the curing of the dielectric layer. | 10-27-2011 |
20110260284 | Method for Producing a Semiconductor Component, and Semiconductor Component - In the insulation layer ( | 10-27-2011 |
20110260285 | SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - To provide a semiconductor substrate including a crystalline semiconductor layer which is suitable for practical use, even if a material different from that of the semiconductor layer is used for a supporting substrate, and a semiconductor device using the semiconductor substrate. The semiconductor substrate includes a bonding layer which forms a bonding plane, a barrier layer formed of an insulating material containing nitrogen, a relief layer which is formed of an insulating material that includes nitrogen at less than 20 at. % and hydrogen at 1 at. % to 20 at. %, and an insulating layer containing a halogen, between a supporting substrate and a single-crystal semiconductor layer. The semiconductor device includes the above-described structure at least partially, and a gate insulating layer formed by a microwave plasma CVD method using SiH | 10-27-2011 |
20110266647 | Methods of Forming Isolated Active Areas, Trenches, and Conductive Lines in Semiconductor Structures and Semiconductor Structures Including the Same - Methods of pitch doubling of asymmetric features and semiconductor structures including the same are disclosed. In one embodiment, a single photolithography mask may be used to pitch double three features, for example, of a DRAM array. In one embodiment, two wordlines and a grounded gate over field may be pitch doubled. Semiconductor structures including such features are also disclosed. | 11-03-2011 |
20110266648 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried in the trenches is formed to form device isolation regions having protruding portions at sidewalls, wherein the device isolation regions decrease a portion of a width of active regions. | 11-03-2011 |
20110291225 | Semiconducture Structure and Method of Forming the Semiconductor Structure that Provides Two Individual Resistors or a Capacitor - A semiconductor structure is formed in the metal interconnect structure of an integrated circuit in a method that provides either two individual resistors that are vertically isolated from each other, or a metal-insulator-metal (MIM) capacitor. As a result, both semiconductor resistors and MIM capacitors can be formed in the same process flow. | 12-01-2011 |
20110291226 | Compound Semiconductor Device and Method for Fabricating the Same - A compound semiconductor device is provided, including a gallium arsenide (GaAs) substrate having a first protrusion portion and a second protrusion portion, wherein the first protrusion portion is formed over a first portion of the GaAs substrate and the second protrusion is formed over a second portion of the GaAs substrate. A first element is disposed over the first protrusion portion, and a second element is disposed over the second protrusion portion. | 12-01-2011 |
20110291227 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING - A method for manufacturing a semiconductor device is disclosed. The method includes forming a shallow trench isolation (STI) region extending in a first direction on a semiconductor substrate, forming a mask layer extending in a second direction that intersects with the first direction on the semiconductor substrate and forming a trench on the semiconductor substrate by using the STI region and the mask layer as masks. In addition, the method includes forming a charge storage layer so as to cover the trench and forming a conductive layer on side surfaces of the trench and the mask layer. Word lines are formed from the conductive layer on side surfaces of the trench that oppose in the first direction by etching. The word lines are separated from each other and extend in the second direction. | 12-01-2011 |
20110298083 | SOI WAFER, METHOD FOR PRODUCING SAME, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An SOI wafer including: a supporting substrate | 12-08-2011 |
20110304006 | METHOD OF ALIGNMENT MARK PROTECTION AND SEMICONDUCTOR DEVICE FORMED THEREBY - A method of protecting alignment marks from damage in a planarization process includes providing a substrate including a surface, forming trenches in the substrate from the surface, forming a first dielectric layer on the substrate, forming a second dielectric layer on the first dielectric layer, forming a patterned second dielectric layer by removing second dielectric over the trenches, resulting in openings defined by the trenches and the patterned second dielectric layer, forming a third dielectric layer on the patterned second dielectric layer, the third dielectric layer filling the openings, and planarizing the third dielectric layer by using the patterned second dielectric layer as a stop layer, resulting in residual third dielectric in the openings that includes a first portion in the substrate and a second portion above the surface of the substrate. | 12-15-2011 |
20110304007 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR SUBSTRATE - A method for manufacturing a semiconductor device includes forming at least one stripe-shaped protection film over a multilayer film in a scribe region of a semiconductor substrate having a plurality of semiconductor element regions formed therein, the protection film having a thickness larger in a center portion thereof than at an end surface thereof and being made of a member which transmits a laser beam, and removing the multilayer film in the scribe region by irradiating the protection film with a laser beam. | 12-15-2011 |
20110304008 | WAFER LEVEL PROCESSING METHOD AND STRUCTURE TO MANUFACTURE SEMICONDUCTOR CHIP - A semiconductor chip includes a silicon substrate, a transistor in or on a bottom side surface of the substrate, a metallization structure under a bottom side surface of the substrate, a dielectric layer under the substrate and between a first and second metal layers of the metallization structure, a passivation layer under the metallization structure and the dielectric layer, where an opening in the passivation layer may be under a contact point of the metallization structure, a polymer layer under the passivation layer, a metal post under the passivation layer and in the polymer layer, where the polymer layer may not cover a bottom surface of the metal post, a metal bump connected with the bottom surface of the metal post, a micro-lense over the top side surface of the substrate, and a glass substrate over the micro-lense and over the top side surface of the substrate. | 12-15-2011 |
20110309467 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Disclosed is a semiconductor device including a substrate for bonding ( | 12-22-2011 |
20110316116 | PHOTOSENSITIVE RESIN COMPOSITION, ADHESIVE FILM AND LIGHT-RECEIVING DEVICE - An object of the present invention is to provide a photosensitive resin composition which leaves a small amount of resin residues after patterning by light-exposure and development and can reduce condensation between the semiconductor wafer and the transparent substrate under a high temperature and high humidity environment, an adhesive film made of the photosensitive resin composition and a light-receiving device including the adhesive film. The photosensitive resin composition of the present invention contains an alkali soluble resin (A), a photopolymerization initiator (B) and a compound (C) having a phenolic hydroxyl group and a carboxyl group. | 12-29-2011 |
20120001293 | SEMICONDUCTOR ON GLASS SUBSTRATE WITH STIFFENING LAYER AND PROCESS OF MAKING THE SAME - A semiconductor-on-glass substrate having a relatively stiff (e.g. relatively high Young's modulus of 125 or higher) stiffening layer or layers placed between the silicon film and the glass in order to eliminate the canyons and pin holes that otherwise form in the surface of the transferred silicon film during the ion implantation thin film transfer process. The new stiffening layer may be formed of a material, such as silicon nitride, that also serves as an efficient barrier against penetration of sodium and other harmful impurities from the glass substrate into the silicon film. | 01-05-2012 |
20120007208 | Semiconductor Devices and Methods of Manufacturing the Same - Semiconductor devices and methods of manufacturing the same are provided. The semiconductor devices may include first and second active patterns. The second active patterns may protrude from the first active patterns. The semiconductor devices may also include a device isolation pattern between each of the first active patterns. The semiconductor devices may further include a sidewall mask on the first active patterns and the second active patterns. The semiconductor devices may additionally include a buried conductive pattern on the device isolation pattern. | 01-12-2012 |
20120007209 | SEMICONDUCTOR DEVICE STRUCTURES INCLUDING DAMASCENE TRENCHES WITH CONDUCTIVE STRUCTURES AND RELATED METHOD - A method and apparatus for providing a conductive structure adjacent to a damascene conductive structure in a semiconductor device structure. The semiconductor device structure includes an insulation layer with at least one damascene conductive structure formed therein, wherein the at least one damascene conductive structure includes an insulative, protective layer disposed thereon. The insulative material of the protective layer is able to resist removal by at least some suitable etchants for the insulative material of the insulation layer adjacent to the at least one damascene conductive structure. A self-aligned opening is formed by removing a portion of an insulation layer adjacent the at least one damascene conductive structure. The self-aligned opening is then filled with a conductive material to thereby provide another conductive structure adjacent to the at least one damascene conductive structure. | 01-12-2012 |
20120007210 | METHOD OF FORMING SHALLOW TRENCH ISOLATION STRUCTURE - A semiconductor structure is disclosed. The semiconductor structure includes: a substrate with at least a trench therein, wherein the trench is filled with an insulation layer; a first polysilicon layer disposed on the insulation layer and covering at least two opposite borders of a top surface of the insulation layer; a second polysilicon layer disposed above the first polysilicon layer and the substrate; and a dielectric layer disposed between the first and second polysilicon layers, wherein the first and second polysilicon layers are respectively shaped as first and second strips. | 01-12-2012 |
20120012970 | CAPACITOR DEVICE USING AN ISOLATED WELL AND METHOD THEREFOR - A semiconductor device includes an isolated p-type well, wherein the isolated p-type well is a first electrode of a capacitor device; a capacitor dielectric on the isolated p-type well; a p-type polysilicon electrode over the capacitor dielectric, wherein the p-type polysilicon electrode is a second electrode of the capacitor device; a first p-type contact region in the isolated p-type well, laterally extending from a first sidewall of the p-type polysilicon electrode; a second p-type contact region in the isolated p-type well, laterally extending from a second sidewall of the p-type polysilicon electrode, opposite the first sidewall of the p-type polysilicon electrode, wherein a portion of the isolated p-type well between the first and second p-type contact regions is under the p-type polysilicon electrode and the capacitor dielectric; and an n-type isolation region surrounding the isolated p-type well. This device may be conveniently coupled to a fringe capacitor. | 01-19-2012 |
20120012971 | Method of Fabricating Isolated Capacitors and Structure Thereof - A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors. | 01-19-2012 |
20120012972 | SINGLE-CRYSTAL SILICON SUBSTRATE, SOI SUBSTRATE, SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device of the present invention is arranged in such a manner that a MOS non-single-crystal silicon thin-film transistor including a non-single-crystal silicon thin film made of polycrystalline silicon, a MOS single-crystal silicon thin-film transistor including a single-crystal silicon thin film, and a metal wiring are provided on an insulating substrate. With this arrangement, (i) a semiconductor device in which a non-single-crystal silicon thin film and a single-crystal silicon thin-film device are formed and high-performance systems are integrated, (ii) a method of manufacturing the semiconductor device, and (iii) a single-crystal silicon substrate for forming the single-crystal silicon thin-film device of the semiconductor device are obtained. | 01-19-2012 |
20120032295 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SUCH A DEVICE - A semiconductor device and method for producing such a device is disclosed. One embodiment provides a semiconductor functional wafer having a first and second main surface. Component production processes are performed for producing a component functional region at the first main surface, wherein the component production processes produce an end state that is stable up to at least a first temperature. A carrier substrate is fitted to the first main surface. Access openings are produced to the first main surface. At least one further component production process is performed for producing patterned component functional regions at the first main surface of the functional wafer in the access openings. The end state produced in this process is stable up to a second temperature, which is less than the first temperature. | 02-09-2012 |
20120038021 | OVERLAY MARK ENHANCEMENT FEATURE - Methods and apparatuses for alignment are disclosed. An exemplary method includes providing a substrate having a device region and an alignment region; forming a first material layer over the substrate; forming a device feature and a dummy feature in the first material layer, wherein the device feature is formed in the device region and the dummy feature is formed in the alignment region; forming a second material layer over the first material layer; and forming an alignment feature in the second material layer, the alignment feature being disposed over the dummy feature in the alignment region. The device feature has a first dimension and the dummy feature has a second dimension, the second dimension being less than a resolution of an alignment mark detector | 02-16-2012 |
20120038022 | INSULATING SUBSTRATE FOR SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - Disclosed is a glass substrate ( | 02-16-2012 |
20120038023 | LOW LOSS SUBSTRATE FOR INTEGRATED PASSIVE DEVICES - Electronic elements having an active device region and integrated passive device (IPD) region on a common substrate preferably include a composite dielectric region in the IPD region underlying the IPD to reduce electro-magnetic (E-M) coupling to the substrate. Mechanical stress created by plain dielectric regions and its deleterious affect on performance, manufacturing yield and occupied area may be avoided by providing electrically isolated inclusions in the composite dielectric region of a material having a thermal expansion coefficient (TEC) less than that of the dielectric material in the composite dielectric region. For silicon substrates, non-single crystal silicon is suitable for the inclusions and silicon oxide for the dielectric material. The inclusions preferably have a blade-like shape separated by and enclosed within the dielectric material. | 02-16-2012 |
20120043639 | FABRICATING METHOD AND STRUCTURE OF SUBMOUNT - A fabricating method and structure of a submount are provided. The submount includes a semiconductor substrate, a first electrode, a second electrode and a first insulating adhesive member. The fabricating method of the submount includes the following steps. A semiconductor substrate is provided. An isolating groove is formed on a first surface of the semiconductor substrate, thereby defining a first region and a second region. A first electrode is formed on the first surface in the first region and a second electrode is formed on the first surface in the second region. A first insulating adhesive member is filled in the isolating groove. The semiconductor substrate is thinned from the second surface so as to expose the first insulating adhesive member from the second surface, thereby insulating the first region of the semiconductor substrate from the second region of the semiconductor substrate. | 02-23-2012 |
20120043640 | MATERIAL HAVING A LOW DIELECTRIC KONSTANT AND METHOD OF MAKING THE SAME - There is disclosed a method for producing a highly cross-linked polypropylene material by plasma polymerisation of a carbon containing gas, not specifically propylene, exhibiting low relative permittivity, high thermal stability and enhanced mechanical properties, said method and material being suitable for application not limited to interlayer dielectric deposition in microchip fabrication. | 02-23-2012 |
20120043641 | Epitaxy Silicon on Insulator (ESOI) - Methods and structures for semiconductor devices with STI regions in SOI substrates is provided. A semiconductor structure comprises an SOI epitaxy island formed over a substrate. The structure further comprises an STI structure surrounding the SOI island. The STI structure comprises a second epitaxial layer on the substrate, and a second dielectric layer on the second epitaxial layer. A semiconductor fabrication method comprises forming a dielectric layer over a substrate and surrounding a device fabrication region in the substrate with an isolation trench extending through the dielectric layer. The method also includes filling the isolation trench with a first epitaxial layer and forming a second epitaxial layer over the device fabrication region and over the first epitaxial layer. Then a portion of the first epitaxial layer is replaced with an isolation dielectric, and then a device such as a transistor is formed second epitaxial layer within the device fabrication region. | 02-23-2012 |
20120074517 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING SAME - One or more embodiments relate to a method for forming a semiconductor structure, including: forming a semiconductor layer; and forming a dielectric layer over a back side of said semiconductor layer. In one or more embodiments, the dielectric layer may be a silicone rubber layer. | 03-29-2012 |
20120074518 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - The invention relates to a semiconductor device, wherein a storage node contact hole is made large to solve any problem caused during etching a storage node contact hole with a small CD, a landing plug is formed to lower plug resistance. A semiconductor device according to the invention comprises: first and second active regions formed in a substrate, the first and second active being adjacent to each other, each of the first and second active regions including a bit-line contact region and a storage node contact region and a device isolation structure; a word line provided within a trench formed in the substrate; first and second storage node contact plugs assigned to the first and second active regions, respectively, the first and second storage node contact plugs being separated from each other by a bit line groove; and a bit line formed within the bit-line groove. | 03-29-2012 |
20120086100 | CMOS STRUCTURE AND METHOD OF MANUFACTURE - CMOS structures with a replacement substrate and methods of manufacture are disclosed herein. The method includes forming a device on a temporary substrate. The method further includes removing the temporary substrate. The method further includes bonding a permanent electrically insulative substrate to the device with a bonding structure. | 04-12-2012 |
20120098084 | SEMICONDUCTOR COMPONENT WITH ISOLATION TRENCH INTERSECTIONS - A semiconductor component with straight insulation trenches formed in a semiconductor material providing semiconductor areas laterally insulated from each other. Each insulation trench has a uniform width along its longitudinal direction represented by a central line. The semiconductor component has an intersecting area into which at least three of the straight insulation trenches lead. A center of the intersecting area is defined as a point of intersection of the continuations of the center lines. A central semiconductor area disposed in the intersecting area is connected with one of the semiconductor areas and contains the center of the intersecting area. | 04-26-2012 |
20120098085 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device, and method of manufacturing the device, having a p type diffusion layer; a V-groove including a bottom surface parallel to the rear surface and exposing the p type diffusion layer and a tapered side surface rising from the bottom surface; a p type semiconductor layer on the rear surface surrounded by the tapered side surface of the V-groove; and a p type isolation layer formed on the side surface and electrically connecting the p type diffusion layer on the front surface and the p type semiconductor layer on the rear surface. The V-groove has a chamfered configuration around the intersection between a corner part of the side surface and the bottom surface of the V-groove. An object is to prevent performance degradation due to stress concentration at the corner part of a recessed part caused by thermal history in soldering. | 04-26-2012 |
20120098086 | SOI SUBSTRATE AND METHOD FOR MANUFACTURING SOI SUBSTRATE - An SOI substrate and a manufacturing method of the SOI substrate, by which enlargement of the substrate is possible and its productivity can be increased, are provided. A step (A) of cutting a first single crystal silicon substrate to form a second single crystal silicon substrate which has a chip size; a step (B) of forming an insulating layer on one surface of the second single crystal silicon substrate, and forming an embrittlement layer in the second single crystal substrate; and a step (C) of bonding a substrate having an insulating surface and the second single crystal silicon substrate with the insulating layer therebetween, and conducting heat treatment to separate the second single crystal silicon substrate along the embrittlement layer, and forming a single crystal silicon thin film on the substrate having an insulating surface, are conducted. | 04-26-2012 |
20120104538 | DAMASCENE METHOD OF FORMING A SEMICONDUCTOR STRUCTURE AND A SEMICONDUCTOR STRUCTURE WITH MULTIPLE FIN-SHAPED CHANNEL REGIONS HAVING DIFFERENT WIDTHS - Disclosed is a damascene method for forming a semiconductor structure and the resulting semiconductor structure having multiple fin-shaped channel regions with different widths. In the method, fin-shaped channel regions are etched using differently configured isolating caps as masks to define the different widths. For example, a wide width isolating cap can comprise a dielectric body positioned laterally between dielectric spacers and can be used as a mask to define a relatively wide width channel region; a medium width isolating cap can comprise a dielectric body alone and can be used as a mask to define a medium width channel region and/or a narrow width isolating cap can comprise a dielectric spacer alone and can be used as a mask to define a relatively narrow width channel region. These multiple fin-shaped channel regions with different widths can be incorporated into either multiple multi-gate field effect transistors (MUGFETs) or a single MUGFET. | 05-03-2012 |
20120104539 | TRENCHES WITH REDUCED SILICON LOSS - An isolation trench in a substrate of a semiconductor device includes a first shallow portion with a dielectric sidewall and a second deeper portion without a dielectric sidewall. The isolation trench is formed by forming a first shallow portion of the trench, forming dielectric sidewalls on the first shallow portion, and then etching the substrate below the first shallow portion to form the second deeper portion. Shallow isolation trenches may be formed simultaneously with the etching of the second deeper portion. | 05-03-2012 |
20120104540 | TRENCH WITH REDUCED SILICON LOSS - An isolation trench in a substrate of a semiconductor device includes a first shallow portion, a transition region, and a second deeper portion. The isolation trench contains a dielectric filler. The isolation trench is formed by first forming a first shallow portion of the isolation trench, forming polysilicon sidewalls on the first shallow portion, and then etching the second deeper portion. | 05-03-2012 |
20120112309 | LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH SUBSEQUENT SELF ALIGNED SHALLOW TRENCH ISOLATION - A semiconductor substrate structure for manufacturing integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate, the lower insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; an electrically conductive layer formed on the lower insulating layer; an insulator with etch stop characteristics formed on the electrically conductive layer; an upper insulating layer formed on the etch stop layer; and a semiconductor layer formed on the upper insulating layer. A scheme of subsequently building a dual-depth shallow trench isolation with the deeper STI in the back gate layer self-aligned to the shallower STI in the active region in such a semiconductor substrate is also disclosed. | 05-10-2012 |
20120112310 | DIFFUSION SIDEWALL FOR A SEMICONDUCTOR STRUCTURE - A method of forming diffusion sidewalls in a semiconductor structure and a semiconductor structure having diffusion sidewalls includes etching a trench into a semiconductor substrate to form first and second active regions, lining each trench with an oxide liner along exposed sidewalls of an active silicon region (RX) of the first and second active regions, removing the oxide liner formed along the exposed sidewalls of the RX region of one of the first and second active regions, forming diffusion sidewalls by epitaxially growing in-situ doped material within the exposed sidewalls of the RX region of the one of the first and second active regions, and forming an isolation region within the trench between the first and second active regions to electrically isolate the first and second active regions from each other. | 05-10-2012 |
20120119321 | TOPOGRAPHY BASED PATTERNING - A mask having features formed by self-organizing material, such as diblock copolymers, is formed on a partially fabricated integrated circuit. A copolymer template, or seed layer, is formed on the surface of the partially fabricated integrated circuit. To form the seed layer, diblock copolymers, composed of two immiscible blocks, are deposited in the space between copolymer alignment guides. The copolymers self-organize, with the guides guiding the self-organization and with each block aggregating with other blocks of the same type, thereby forming the seed layer. Supplemental diblock copolymers are deposited over the seed layer. The copolymers in the seed layer guide self-organization of the supplemental copolymers, thereby vertically extending the pattern formed by the copolymers in the seed layer. Block species are subsequently selectively removed to form a pattern of voids defined by the remaining block species, which form a mask that can be used to pattern an underlying substrate. | 05-17-2012 |
20120119322 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A plurality of light-shielding films etc. are formed on a surface of a first insulating film. Then, a dummy pattern is formed on a surface of a second insulating film between adjoining ones of the light-shielding films etc., so that a height of the dummy pattern is equal to that of the second insulating film on the light-shielding films etc., as measured from the surface of the first insulating film. Thereafter, a third insulating film covering the dummy pattern and having a flat surface is formed over the surface of the second insulating film. Subsequently, a base layer is bonded to a support substrate so that the flat surface of the third insulating film faces the support substrate. A semiconductor device is manufactured in this manner. | 05-17-2012 |
20120126359 | Structure to Reduce Etching Residue - A structure for reducing partially etched materials is described. The structure includes a layout of an intersection area between two trenches. First, a large intersection area having a trapezoidal corner may be replaced with an orthogonal intersection between two trenches. The layout reduces the intersection area as well as the possibility of having partially etched materials left at the intersection area. The structure also includes an alternative way to fill the intersection area with either an un-etched small trapezoidal area or multiple un-etched square areas, so that the opening area at the intersection point is reduced and the possibility of having partially etched materials is reduced too. | 05-24-2012 |
20120126360 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME AND DESIGNING THE SAME - There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP | 05-24-2012 |
20120126361 | EPITAXIAL WAFER AND PRODUCTION METHOD THEREOF - A small amount of oxygen is ion-implanted in a wafer surface layer, and then heat treatment is performed so as to form an incomplete implanted oxide film in the surface layer. Thereby, wafer cost is reduced; a pit is prevented from forming in a surface of an epitaxial film; and a slip is prevented from forming in an external peripheral portion of a wafer. | 05-24-2012 |
20120133017 | SEMICONDUCTOR STRUCTURES INCLUDING POLYMER MATERIAL PERMEATED WITH METAL OXIDE - Methods of forming metal oxide structures and methods of forming metal oxide patterns on a substrate using a block copolymer system formulated for self-assembly. A block copolymer at least within a trench in the substrate and including at least one soluble block and at least one insoluble block may be annealed to form a self-assembled pattern including a plurality of repeating units of the at least one soluble block laterally aligned with the trench and positioned within a matrix of the at least one insoluble block. The self-assembled pattern may be exposed to a metal oxide precursor that impregnates the at least one soluble block. The metal oxide precursor may be oxidized to form a metal oxide. The self-assembled pattern may be removed to form a pattern of metal oxide lines on the substrate surface. Semiconductor device structures are also described. | 05-31-2012 |
20120139080 | METHOD OF FORMING SUBSTRATE CONTACT FOR SEMICONDUCTOR ON INSULATOR (SOI) SUBSTRATE - A semiconductor structure is provided that includes a material stack including an epitaxially grown semiconductor layer on a base semiconductor layer, a dielectric layer on the epitaxially grown semiconductor layer, and an upper semiconductor layer present on the dielectric layer. A capacitor is present extending from the upper semiconductor layer through the dielectric layer into contact with the epitaxially grown semiconductor layer. The capacitor includes a node dielectric present on the sidewalls of the trench and an upper electrode filling at least a portion of the trench. A substrate contact is present in a contact trench extending from the upper semiconductor layer through the dielectric layer and the epitaxially semiconductor layer to a doped region of the base semiconductor layer. A substrate contact is also provided that contacts the base semiconductor layer through the sidewall of a trench. Methods for forming the above-described structures are also provided. | 06-07-2012 |
20120146175 | INSULATING REGION FOR A SEMICONDUCTOR SUBSTRATE - An insulating region for a semiconductor wafer and a method of forming same. The insulating region can include a tri-layer structure of silicon oxide, boron nitride and silicon oxide. The insulating region may be used to insulate a semiconductor device layer from an underlying bulk semiconductor substrate. The insulating region can be formed by coating the sides of a very thin cavity with silicon oxide, and filling the remainder of the cavity between the silicon oxide regions with boron nitride. | 06-14-2012 |
20120146176 | SEMICONDUCTOR DEVICE - A semiconductor device receiving as input a radio frequency signal having a frequency of 500 MHz or more and a power of 20 dBm or more is provided. The semiconductor device includes: a silicon substrate; a silicon oxide film formed on the silicon substrate; a radio frequency interconnect provided on the silicon oxide film and passing the radio frequency signal; a fixed potential interconnect provided on the silicon oxide film and placed at a fixed potential; and an acceptor-doped layer. The acceptor-doped layer is formed in a region of the silicon substrate. The region is in contact with the silicon oxide film. The acceptor-doped layer is doped with acceptors. | 06-14-2012 |
20120153426 | VOID-FREE WAFER BONDING USING CHANNELS - A method of bonding first and second microelectronic elements includes pressing together a first substrate containing active circuit elements therein with a second substrate, with a flowable dielectric material between confronting surfaces of the respective substrates, each of the first and second substrates having a coefficient of thermal expansion less than 10 parts per million/° C., at least one of the confronting surfaces having a plurality of channels extending from an edge of such surface, such that the dielectric material between planes defined by the confronting surfaces is at least substantially free of voids and has a thickness over one micron, and at least some of the dielectric material flows into at least some of the channels. | 06-21-2012 |
20120153427 | INTEGRATED CIRCUIT AND METHOD OF FABRICATING SAME - A method includes providing a substrate with at least one semiconducting layer. The method also includes forming a plurality of isolation barriers within the at least one semiconducting layer, thereby forming a plurality of device islands. The method further includes inserting a plurality of electronic devices into a portion of the at least one semiconducting layer such that each electronic device is substantially isolated from each other electronic device by the device islands. | 06-21-2012 |
20120153428 | ELECTRONIC DEVICES, CIRCUITS AND THEIR MANUFACTURE - A method of manufacturing an electronic device, comprising a layer of semiconductive material and at least one insulative feature arranged to interrupt the layer of semiconductive material, comprises: providing a layer of semiconductive material, and a layer of compressible material supporting the layer of semiconductive material; and forming the or each insulative feature by a method comprising displacing a respective selected portion of the layer of semiconductive material towards the compressible material so as to compress compressible material under the or each displaced portion and separate at least partly the or each displaced portion from undisplaced semiconductive material. | 06-21-2012 |
20120153429 | 3D INTEGRATED CIRCUIT DEVICE FABRICATION WITH PRECISELY CONTROLLABLE SUBSTRATE REMOVAL - A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P− layer, and the P− layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P− layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P− layer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure. | 06-21-2012 |
20120161275 | METHODS FOR FORMING A BONDED SEMICONDUCTOR SUBSTRATE INCLUDING A COOLING MECHANISM - Bottom sides of two semiconductor substrates are brought together with at least one bonding material layer therebetween and bonded to form a bonded substrate. A cavity with two openings and a contiguous path therebetween is provided within the at least one bonding layer. At least one through substrate via and other metal interconnect structures are formed within the bonded substrate. The cavity is employed as a cooling channel through which a cooling fluid flows to cool the bonded semiconductor substrate during the operation of the semiconductor devices in the bonded substrate. Alternatively, a conductive cooling fin with two end portions and a contiguous path therebetween is formed within the at least one bonding layer. The two end portions of the conductive cooling fin are connected to heat sinks to cool the bonded semiconductor substrate during the operation of the semiconductor devices in the bonded substrate. | 06-28-2012 |
20120168895 | MODIFYING GROWTH RATE OF A DEVICE LAYER - A device includes a substrate with a device region on which a transistor is formed. The device region includes active edge regions and an active center region which have different oxidation growth rates. A growth rate modifier (GRM) comprising dopants which modifies oxidation growth rate is employed to produce a gate oxide layer which has a uniform thickness. The GRM may enhance or retard the oxidation growth, depending on the type of dopants used. Fluorine dopants enhance oxidation growth rate while nitrogen dopants retard oxidation growth rate. | 07-05-2012 |
20120168896 | DOUBLE SIDE WAFER PROCESS, METHOD AND DEVICE - A method of manufacturing double-sided semiconductor die by performing a first plurality of processes to a first side of a wafer and performing a second plurality of processes to a second side of the wafer, thereby forming at least a first semiconductor device on the first side of the wafer and at least a second semiconductor device on the second side of the wafer. The wafer may be cut to form a plurality of die having at least one semiconductor device on each side. | 07-05-2012 |
20120168897 | METHODS OF FORMING SEMICONDUCTOR TRENCH AND FORMING DUAL TRENCHES, AND STRUCTURE FOR ISOLATING DEVICES - Methods of forming a semiconductor trench and forming dual trenches and a structure for isolating devices are provided. The structure for isolating devices is disposed in a substrate having a periphery area and an array area. The structure for isolating devices includes a first isolation structure and a second isolation structure. The first isolation structure has a profile with at least three steps and is disposed in the substrate in the periphery area. The second isolation structure has a profile with at least two steps and is disposed in the substrate in the array area. | 07-05-2012 |
20120168898 | METHODS OF FORMING SINGLE CRYSTAL SILICON STRUCTURES AND SEMICONDUCTOR DEVICE STRUCTURES INCLUDING SINGLE CRYSTAL SILICON STRUCTURES - A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon substrate is exposed to an anisotropic etchant that undercuts the single crystal silicon. By controlling the length of the etch, single crystal silicon islands or smooth vertical walls in the single crystal silicon may be created. | 07-05-2012 |
20120175726 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device comprises a circuit portion, wells, and dummy wells. A circuit portion is formed on an upper surface of a semiconductor substrate of a first conductivity type. The wells are of a second conductivity type different from the first conductivity type. Each of wells is formed in the semiconductor substrate on an upper surface side, constitutes the circuit portion, and functions as an element. The dummy wells are of the second conductivity type. Each of the dummy wells is formed in the semiconductor substrate on the upper surface side, does not constitute the circuit portion, and does not function as an element. | 07-12-2012 |
20120181654 | Multi-Layer Single Crystal 3D Stackable Memory - Technology is described herein for manufacturing a three-dimensional 3D stacked memory structure having multiple layers of single crystal silicon or other semiconductor. The multiple layers of single crystal semiconductor are suitable for implementing multiple levels of high performance memory cells. | 07-19-2012 |
20120181655 | SOI Semiconductor Device Comprising a Substrate Diode and a Film Diode Formed by Using a Common Well Implantation Mask - When forming sophisticated SOI devices, a substrate diode and a film diode are formed by using one and the same implantation mask for determining the well dopant concentration in the corresponding well regions. Consequently, during the further processing, the well dopant concentration of any transistor elements may be achieved independently from the well regions of the diode in the semiconductor layer. | 07-19-2012 |
20120187522 | STRUCTURE AND METHOD FOR REDUCTION OF VT-W EFFECT IN HIGH-K METAL GATE DEVICES - A substrate is provided. An STI trench is formed in the substrate. A fill material is formed in the STI trench and then planarized. The substrate is exposed to an oxidizing ambient, growing a liner at a bottom and sidewalls of the STI trench. The liner reduces the Vt-W effect in high-k metal gate devices. | 07-26-2012 |
20120187523 | METHOD AND STRUCTURE FOR SHALLOW TRENCH ISOLATION TO MITIGATE ACTIVE SHORTS - A shallow trench isolation region is provided in which void formation is substantially or totally eliminated therefrom. The shallow trench isolation mitigates active shorts between two active regions of a semiconductor substrate. The shallow trench isolation region includes a bilayer liner which is present on sidewalls and a bottom wall of a trench that is formed in a semiconductor substrate. The bilayer liner of the present disclosure includes, from bottom to top, a shallow trench isolation liner, e.g., a semiconductor oxide and/or nitride, and a high k liner, e.g., a dielectric material having a dielectric constant that is greater than silicon oxide. | 07-26-2012 |
20120187524 | DOPED OXIDE FOR SHALLOW TRENCH ISOLATION (STI) - The embodiments described provide methods and structures for doping oxide in the STIs with carbon to make etch rate in the narrow and wide structures equal and also to make corners of wide STIs strong. Such carbon doping can be performed by ion beam (ion implant) or by plasma doping. The hard mask layer can be used to protect the silicon underneath from doping. By using the doping mechanism, the even surface topography of silicon and STI enables patterning of gate structures and ILD | 07-26-2012 |
20120193751 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING - Methods of making fins and semiconductor structures containing fins are provided. The methods involve forming a multi-layer structure over a semiconductor substrate. The multi-layer structure comprises a first layer over the semiconductor substrate, a second layer over the first layer, and a third layer over the second layer. The method also comprises removing upper portions of the semiconductor substrate and portions of the multi-layer structure to form fins of the semiconductor substrate and portions of the multi-layer structure. Further, the method comprises selectively oxidizing the first layer while oxidization of the second layer and the third layer is less than the oxidization of the first layer. The oxidation can be performed before gap fill recess or after gap fill recess. | 08-02-2012 |
20120193752 | Novel 3D Integration Method Using SOI Substrates and Structures Produced Thereby - A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer. | 08-02-2012 |
20120193753 | METHODS FOR REDUCING THE METAL CONTENT IN THE DEVICE LAYER OF SOI STRUCTURES AND SOI STRUCTURES PRODUCED BY SUCH METHODS - Methods for producing silicon on insulator structures with a reduced metal content in the device layer thereof are disclosed. Silicon on insulator structures with a reduced metal content are also disclosed. | 08-02-2012 |
20120193754 | MEMS DEVICE WITH INTEGRAL PACKAGING - A MEMS device and method of making same is disclosed. In one embodiment, a micro-switch includes a base assembly comprising a movable structure bearing a contact pad. The base assembly is wafer-scale bonded to a lid assembly comprising an activator and a signal path. The movable structure moves within a sealed cavity formed during the bonding process. The signal path includes an input line and an output line separated by a gap, which prevents signals from propagating through the micro-switch when the switch is deactivated. In operation, a signal is launched into the signal path. When the micro-switch is activated, a force is established by the actuator, which pulls a portion of the movable structure upwards towards the gap in the signal path, until the contact pad bridges the gap between the input line and output line, allowing the signal to propagate through the micro-switch. | 08-02-2012 |
20120199938 | Semiconductor Memory Device and Method of Manufacturing the same - A semiconductor memory device includes a semiconductor substrate defining active regions partitioned by an isolation region, conductive lines spaced apart from each other and crossing the active regions over the semiconductor substrate, a thin film pattern formed on a top portion of the conductive lines having opening portions exposing part of the conductive lines in a width wider than a width of the conductive lines, an insulating layer filling the opening portions and formed over the thin film pattern, and an air gap formed between the conductive lines below the insulating layer and the thin film pattern. | 08-09-2012 |
20120199939 | LOCALIZED BIASING FOR SILICON ON INSULATOR STRUCTURES - A silicon-on-insulator device has a localized biasing structure formed in the insulator layer of the SOI. The localized biasing structure includes a patterned conductor that provides a biasing signal to distinct regions of the silicon layer of the SOI. The conductor is recessed into the insulator layer to provide a substantially planar interface with the silicon layer. The conductor is connected to a bias voltage source. In an embodiment, a plurality of conductor is provided that respectively connected to a plurality of voltage sources. Thus, different regions of the silicon layer are biased by different bias signals. | 08-09-2012 |
20120199940 | SILICON CARBIDE AND RELATED WIDE-BANDGAP TRANSISTORS ON SEMI INSULATING EPITAXY - A method of making a semi-insulating epitaxial layer includes implanting a substrate or a first epitaxial layer formed on the substrate with boron ions to form a boron implanted region on a surface of the substrate or on a surface of the first epitaxial layer, and growing a second epitaxial layer on the boron implanted region of the substrate or on the boron implanted region of the first epitaxial layer to form a semi-insulating epitaxial layer. | 08-09-2012 |
20120205774 | ISOLATION STRUCTURE PROFILE FOR GAP FILLING - An trench isolation structure and method for manufacturing the trench isolation structure are disclosed. An exemplary trench isolation structure includes a first portion and a second portion. The first portion extends from a surface of a semiconductor substrate to a first depth in the semiconductor substrate, and has a width that tapers from a first width at the surface of the semiconductor substrate to a second width at the first depth, the first width being greater than the second width. The second portion extends from the first depth to a second depth in the semiconductor substrate, and has substantially the second width from the first depth to the second depth. | 08-16-2012 |
20120205775 | METHOD FOR MANUFACTURING AN ELECTRONIC DEVICE - The invention relates to a method for manufacturing a semiconductor device. Accordingly, the trench processing sequence is changed and stress absorbing layers are applied. A shallow trench structure is etched. A deep trench structure is etched. A liner oxide is applied in the deep and shallow trench structure. An amorphous polysilicon liner is deposited on top of the liner oxide. A nitride liner is applied on top of the amorphous polysilicon liner, and the deep and shallow trenches are filled with oxide. | 08-16-2012 |
20120211861 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a plurality of element-separating insulators, and contacts. The plurality of element-separating insulators are formed in an upper layer portion of the semiconductor substrate. The plurality of element-separating insulators partition the upper layer portion into a plurality of active areas extending in a first direction. The contacts are connected to the active areas. A recess is made in a part in the first direction of an upper surface of each of the active areas. The recess is made across the entire active area in a second direction orthogonal to the first direction. Positions in the first direction of two of the contacts connected respectively to mutually-adjacent active areas are different from each other. One of the contacts is in contact with a side surface of the recess and not in contact with a bottom surface of the recess. | 08-23-2012 |
20120211862 | SOI SUBSTRATE AND METHOD FOR MANUFACTURING SOI SUBSTRATE - The method for manufacturing an SOI substrate includes the following steps: forming an insulating film on a semiconductor substrate; exposing the semiconductor substrate to accelerated ions so that an embrittlement region is formed in the semiconductor substrate; bonding the semiconductor substrate to a base substrate with the insulating film interposed therebetween; separating the semiconductor substrate along the embrittlement region so that a semiconductor film is provided over the base substrate with the insulating film interposed therebetween; and forming a mask over the semiconductor film to etch part of the semiconductor film and part of the insulating film so that the periphery of the semiconductor film is on the inner side than the periphery of the insulating film. | 08-23-2012 |
20120211863 | METHOD OF ELIMINATING MICRO-TRENCHES DURING SPACER ETCH - A semiconductor structure includes a semiconductor substrate with a substrate region and a trench extending into the surface region of the semiconductor substrate. The trench includes sidewalls, a bottom and a depth. The semiconductor structure further includes a trench liner overlying the bottom and the sidewalls of the trench. The semiconductor structure also includes a shallow trench isolation structure filling at least the depth of the trench. The shallow trench isolation structure is formed from alternating layers of silicon nitride and high-density plasma oxide. | 08-23-2012 |
20120217610 | Bonded Semiconductor Structure With Pyramid-Shaped Alignment Openings and Projections - A bonded semiconductor structure is formed in a method that first forms a female semiconductor structure with pyramid-shaped openings and a male semiconductor structure with pyramid-shaped projections, and then inserts the projections into the openings to align the male semiconductor structure to the female semiconductor structure for bonding. | 08-30-2012 |
20120223406 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a semiconductor substrate, an insulating film, a heat conductive member, and an element. A cavity and a connecting hole are formed in the semiconductor substrate. The connecting hole spatially connects the cavity to an upper face of the semiconductor substrate. The insulating film is provided on inner faces of the cavity and the connecting hole. The heat conductive member is embedded in the cavity and the connecting hole. Heat conductivity of the heat conductive member is higher than heat conductivity of the insulating film. And, the element is formed in a region immediately above the cavity in the semiconductor substrate. | 09-06-2012 |
20120223407 | Superior Integrity of High-K Metal Gate Stacks by Capping STI Regions - When forming high-k metal gate electrode structures in an early manufacturing stage, integrity of an encapsulation and, thus, integrity of sensitive gate materials may be improved by reducing the surface topography of the isolation regions. To this end, a dielectric cap layer of superior etch resistivity is provided in combination with the conventional silicon dioxide material. | 09-06-2012 |
20120223408 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor device includes: providing a substrate; forming a plurality of trenches by etching the substrate; forming a first isolation layer by filling the plurality of the trenches with a first insulation layer; recessing the first insulation layer filling a first group of the plurality of the trenches to a predetermined depth; forming a liner layer over the first group of the trenches with the first insulation layer recessed to the predetermined depth; and forming a second isolation layer by filling the first group of the trenches, where the liner layer is formed, with a second insulation layer. | 09-06-2012 |
20120223409 | Integrated circuit structures, semiconductor structures, and semiconductor die - Methods for fabricating integrated circuit devices on an acceptor substrate devoid of circuitry are disclosed. Integrated circuit devices are formed by sequentially disposing one or more levels of semiconductor material on an acceptor substrate, and fabricating circuitry on each level of semiconductor material before disposition of a next-higher level. After encapsulation of the circuitry, the acceptor substrate is removed and semiconductor dice are singulated. Integrated circuit devices formed by the methods are also disclosed. | 09-06-2012 |
20120241901 | PACKAGE INTERCONNECTS - A method for forming a device is disclosed. A support substrate having first and second major surfaces is provided. An interconnect is formed through the first and second major surfaces in the support substrate. The interconnect has first and second portions. The first portion extends from one of the first or second major surfaces and the second portion extends from the other of the first and second major surfaces. The interconnect includes a partial via plug having a conductive material in a first portion of the interconnect. The via plug has a bottom at about an interface of the first and second portions. The second portion of the interconnect is heavily doped with dopants of a first polarity type. | 09-27-2012 |
20120241902 | SELF-ALIGNED DUAL DEPTH ISOLATION AND METHOD OF FABRICATION - FDSOI devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a device includes the following steps. A wafer is provided having a substrate, a BOX and a SOI layer. A hardmask layer is deposited over the SOI layer. A photoresist layer is deposited over the hardmask layer and patterned into groups of segments. A tilted implant is performed to damage all but those portions of the hardmask layer covered or shadowed by the segments. Portions of the hardmask layer damaged by the implant are removed. A first etch is performed through the hardmask layer to form a deep trench in the SOI layer, the BOX and at least a portion of the substrate. The hardmask layer is patterned using the patterned photoresist layer. A second etch is performed through the hardmask layer to form shallow trenches in the SOI layer. | 09-27-2012 |
20120256289 | Forming High Aspect Ratio Isolation Structures - An isolation structure, such as a trench isolation structure, may be formed by forming an aperture in a semiconductor substrate and then filling the aperture with boron. In some embodiments, the aperture filling may use atomic layer deposition. In some cases, the boron may be amorphous boron. The aperture may be a high aspect ratio aperture, such as a trench, in some embodiments. | 10-11-2012 |
20120256290 | MICROSTRUCTURE DEVICE COMPRISING A FACE TO FACE ELECTROMAGNETIC NEAR FIELD COUPLING BETWEEN STACKED DEVICE PORTIONS AND METHOD OF FORMING THE DEVICE - A galvanic-isolated coupling of circuit portions is accomplished on the basis of a stacked chip configuration. The semiconductor chips thus can be fabricated on the basis of any appropriate process technology, thereby incorporating one or more coupling elements, such as primary or secondary coils of a micro transformer, wherein the final characteristics of the micro transformer are adjusted during the wafer bond process. | 10-11-2012 |
20120256291 | SEMICONDUCTOR DEVICE - The cell size is reduced and device reliability is improved for a semiconductor device including plural transistors making up a multi-channel output circuit. In a multi-channel circuit configuration, a group of transistors having a common function of plural channels are surrounded by a common trench for insulated isolation from another group of transistors having another function. The collectors of mutually adjacent transistors on the high side are commonly connected to a VH power supply, whereas the emitters of mutually adjacent transistors on the low side are commonly connected to a GND power supply. | 10-11-2012 |
20120261787 | PASSIVE DEVICES FABRICATED ON GLASS SUBSTRATES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES - Passive devices fabricated on glass substrates, methods of manufacture and design structures are provided. The method includes forming an opaque or semi-opaque layer on at least a first side of a glass substrate. The method further includes forming one or more passive devices on the opaque or semi-opaque layer on a second side of the glass substrate. | 10-18-2012 |
20120261788 | SELF-ALIGNED AIRGAP INTERCONNECT STRUCTURES AND METHODS OF FABRICATION - Devices and methods for forming a self-aligned airgap interconnect structure includes etching a conductive layer to a substrate to form conductive structures with patterned gaps and filling the gaps with a sacrificial material. The sacrificial material is planarized to expose a top surface of the conductive layer. A permeable cap layer is deposited over the conductive structure and the sacrificial material. Self-aligned airgaps are formed by removing the sacrificial material through the permeable layer. | 10-18-2012 |
20120261789 | Wafer with Spacer Including Horizontal Member - In one embodiment, a method of forming an insulating spacer includes providing a base layer, providing an intermediate layer above an upper surface of the base layer, etching a first trench in the intermediate layer, depositing a first insulating material portion within the first trench, depositing a second insulating material portion above an upper surface of the intermediate layer, forming an upper layer above an upper surface of the second insulating material portion, etching a second trench in the upper layer, and depositing a third insulating material portion within the second trench and on the upper surface of the second insulating material portion. | 10-18-2012 |
20120261790 | SUBSTRATE STRUCTURE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a substrate structure, a semiconductor device, and a manufacturing method thereof. The substrate structure comprises: a semiconductor substrate; and a first isolation region, wherein the first isolation region comprises: a first trench extending through the semiconductor substrate; and a first dielectric layer filling the first trench. Due to the isolation region extending through the substrate, it is possible to make device structures on both surfaces of the substrate, so as to increase the utilization of the substrate and the integration degree of the devices. | 10-18-2012 |
20120261791 | Wide and Deep Oxide Trench in A Semiconductor Substrate with Interspersed Vertical Oxide Ribs - A semiconductor device structure with an oxide-filled large deep trench (OFLDT) portion having trench size TCS and trench depth TCD is disclosed. A bulk semiconductor layer (BSL) is provided with a thickness BSLT>TCD. A large trench top area (LTTA) is mapped out atop BSL with its geometry equal to OFLDT. The LTTA is partitioned into interspersed, complementary interim areas ITA-A and ITA-B. Numerous interim vertical trenches of depth TCD are created into the top BSL surface by removing bulk semiconductor materials corresponding to ITA-B. The remaining bulk semiconductor materials corresponding to ITA-A are converted into oxide. If any residual space is still left between the so-converted ITA-A, the residual space is filled up with oxide deposition. Importantly, the geometry of all ITA-A and ITA-B should be configured simple and small enough to facilitate fast and efficient processes of oxide conversion and oxide filling. | 10-18-2012 |
20120292734 | SEMICONDUCTOR DEVICES HAVING ENCAPSULATED ISOLATION REGIONS AND RELATED FABRICATION METHODS - Apparatus and related fabrication methods are provided for semiconductor device structures having encapsulated isolation regions. An exemplary method for fabricating a semiconductor device structure involves the steps of forming an isolation region of a first dielectric material in the semiconductor substrate adjacent to a first region of the semiconductor material, forming a first layer of a second dielectric material overlying the isolation region and the first region, and removing the second dielectric material overlying the first region leaving portions of the second dielectric material overlying the isolation region intact. The isolation region is recessed relative to the first region, and the second dielectric material is more resistant to an etchant than the first dielectric material. | 11-22-2012 |
20120292735 | CORNER TRANSISTOR SUPPRESSION - The threshold voltage of parasitic transistors formed at corners of shallow trench isolation regions is increased and mobility decreased by employing a high-K dielectric material. Embodiments include STI regions comprising a liner of a high-K dielectric material extending proximate trench corners. Embodiments also include STI regions having a recess formed in the trench, wherein the recess contains a high-K dielectric material, in the form of a layer or spacer, extending proximate trench corners. | 11-22-2012 |
20120292736 | BARRIER STRUCTURE - A starting substrate in the form of a semiconductor wafer ( | 11-22-2012 |
20120292737 | DIODE FOR ADJUSTING PIN RESISTANCE OF A SEMICONDUCTOR DEVICE - A diode comprises a P-type well formed in a semiconductor substrate, at least one N-type impurity doping area formed in the P-type well, an isolation area formed to surround the N-type impurity doping area, a P-type impurity doping area formed to surround the isolation area, first contacts formed in the N-type impurity doping area in a single row or a plurality of rows, and second contacts formed in the P-type impurity doping area in a single row or a plurality of rows, wherein pin resistance can be adjusted through changing any one of a distance between the N-type impurity doping area and the P-type impurity doping area, a contact pitch between the first contacts, and a contact pitch between the second contacts. | 11-22-2012 |
20120299146 | VERTICAL ESD PROTECTION DEVICE - A method for forming a vertical electrostatic discharge (ESD) protection device includes depositing a multi-layer n-type epitaxial layer on a substrate having p-type surface including first epitaxial depositing to form a first n-type epitaxial layer on the p-type surface, and second epitaxial depositing to form a second n-type epitaxial layer formed on the first n-type epitaxial layer. The first type epitaxial layer has a peak doping level which is at least double that of the second n-type epitaxial layer. A p+ layer is formed on the second n-type epitaxial layer. An etch step etches through the p+ layer and multi-layer n-type epitaxial layer to reach the substrate to form a trench. The trench is filled with a filler material to form a trench isolation region. A metal contact is formed on the p+ layer for providing contact to the p+ layer. | 11-29-2012 |
20120299147 | TRANSFER METHOD, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - After depressed portions ( | 11-29-2012 |
20120306046 | Power Semiconductor Device with High Blocking Voltage Capacity - A power semiconductor device includes an active device region disposed in a semiconductor substrate, an edge termination region disposed in the semiconductor substrate between the active device region and a lateral edge of the semiconductor substrate and a trench disposed in the edge termination region which extends from a first surface of the semiconductor substrate toward a second opposing surface of the semiconductor substrate. The trench has an inner sidewall, an outer sidewall and a bottom. The inner sidewall is spaced further from the lateral edge of the semiconductor substrate than the outer sidewall, and an upper portion of the outer sidewall is doped opposite as the inner sidewall and bottom of the trench to increase the blocking voltage capacity. Other structures can be provided which yield a high blocking voltage capacity such as a second trench or a region of chalcogen dopant atoms disposed in the edge termination region. | 12-06-2012 |
20120306047 | CHIP-ON-FILM STRUCTURE FOR LIQUID CRYSTAL PANEL - The present invention provides a chip on film (COF) structure for a liquid crystal panel, which is disposed on an edge of a glass substrate of an array substrate of a liquid crystal panel. The COF structure comprises a plastic substrate, a metal layer, an adhesive layer, a driver chip and an insulating protection layer. The COF structures further comprises at least one groove, and the groove is disposed on the plastic substrate over the output terminals of the metal layer. The at least one groove of the present invention can prevent from deformation and damage of the glass substrate when the COF structure is assembled with the glass substrate of the array substrate, and it can reduce the brightness difference of the glass substrate in the thermally pressed regions. | 12-06-2012 |
20120313214 | POLYSILICON STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A polysilicon structure and method of forming the polysilicon structure are disclosed, where the method includes a two-step deposition and planarization process. The disclosed process reduces the likelihood of defects such as voids, particularly where polysilicon is deposited in a trench having a high aspect ratio. A first polysilicon structure is deposited that includes a trench liner portion and a first upper portion. The trench liner portion only partially fills the trench, while the first upper portion extends over the adjacent field isolation structures. Next, at least a portion of the first upper portion of the first polysilicon structure is removed. A second polysilicon structure is then deposited that includes a trench plug portion and a second upper portion. The trench is filled by the plug portion, while the second upper portion extends over the adjacent field isolation structures. The second upper portion is then removed. | 12-13-2012 |
20120313215 | COMPACT THERMALLY CONTROLLED THIN FILM RESISTORS UTILIZING SUBSTRATE CONTACTS AND METHODS OF MANUFACTURE - A method of forming a semiconductor structure includes forming a resistor on an insulator layer over a substrate, and forming at least one dielectric layer over the resistor. The method also includes forming a substrate contact through the at least one dielectric layer, through the resistor, through the insulator layer, and into the substrate. The substrate contact comprises a high thermal conductivity material. | 12-13-2012 |
20120319230 | ETCHING NARROW, TALL DIELECTRIC ISOLATION STRUCTURES FROM A DIELECTRIC LAYER - Methods of forming isolation structures are disclosed. A method of forming isolation structures for an image sensor array of one aspect may include forming a dielectric layer over a semiconductor substrate. Narrow, tall dielectric isolation structures may be formed from the dielectric layer. The narrow, tall dielectric isolation structures may have a width that is no more than 0.3 micrometers and a height that is at least 1.5 micrometers. A semiconductor material may be epitaxially grown around the narrow, tall dielectric isolation structures. Other methods and apparatus are also disclosed. | 12-20-2012 |
20120319231 | Microelectronic Device Including Shallow Trench Isolation Structures Having Rounded Bottom Surfaces - Methods for rounding the bottom corners of a shallow trench isolation structure are described herein. Embodiments of the present invention provide a method comprising forming a first masking layer on a sidewall of an opening in a substrate, removing, to a first depth, a first portion of the substrate at a bottom surface of the opening having the first masking layer therein, forming a second masking layer on the first masking layer in the opening, and removing, to a second depth, a second portion of the substrate at the bottom surface of the opening having the first and second masking layers therein. Other embodiments also are described. | 12-20-2012 |
20120326265 | METHOD OF FORMING MEMORY CELL ACCESS DEVICE - A memory device includes an access device including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor region having a second conductivity type opposite the first conductivity type. Both the first and the second doped semiconductor regions are formed in a single-crystalline semiconductor body, and define a p-n junction between them. The first and second doped semiconductor regions are implemented in isolated parallel ridges formed in the single-crystal semiconductor body. Each ridge is crenellated, and the crenellations define semiconductor islands; the first doped semiconductor region occupies a lower portion of the islands and an upper part of the ridge, and the second doped semiconductor region occupies an upper portion of the islands, so that the p-n junctions are defined within the islands. | 12-27-2012 |
20120326266 | HIGH-VOLTAGE SEMICONDUCTOR DEVICE - A high-voltage semiconductor device is disclosed. The HV semiconductor device includes: a substrate; a well of first conductive type disposed in the substrate; a first doping region of second conductive type disposed in the p-well; a first isolation structure disposed in the well of first conductive type and surrounding the first doping region of second conductive type; and a first drift ring of second conductive type disposed between the first doping region of second conductive type and the first isolation structure. | 12-27-2012 |
20120326267 | COMPOSITE ISOLATION LAYER STRUCTURES FOR SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - An isolation structure includes an oxide region in a lower portion of a trench on a substrate, an oxide layer conforming to a sidewall of the trench in an upper portion of the trench above the oxide region and a nitride region in the upper portion of the trench on the oxide region and the oxide layer. The substrate may include silicon, the oxide region may include silicon oxide and the nitride region may include silicon nitride. The oxide region may have a thickness of more than half of a height from a bottom of the trench to a top of the trench. | 12-27-2012 |
20120326268 | SILICON EPITAXIAL WAFER, METHOD FOR MANUFACTURING THE SAME, BONDED SOI WAFER AND METHOD FOR MANUFACTURING THE SAME - A silicon epitaxial wafer having a silicon epitaxial layer grown by vapor phase epitaxy on a main surface of a silicon single crystal substrate, wherein the main surface of the silicon single crystal substrate is tilted with respect to a [100] axis at an angle θ in a [011] direction or a [0-1-1] direction from a (100) plane and at an angle Φ in a [01-1] direction or a [0-11] direction from the (100) plane, the angle θ and the angle Φ are less than ten minutes, and a dopant concentration of the silicon epitaxial layer is equal to or more than 1×10 | 12-27-2012 |
20130001737 | SEMICONDUCTOR DEVICES STRUCTURES INCLUDING AN ISOLATION STRUCTURE - A shallow isolation trench structure and methods of forming the same wherein the method of formation comprises a layered structure of a buffer film layer over a dielectric layer that is atop a semiconductor substrate. The buffer film layer comprises a material that is oxidation resistant and can be etched selectively to oxide films. The layered structure is patterned with a resist material and etched to form a shallow trench. A thin oxide layer is formed in the trench and the buffer film layer is selectively etched to move the buffer film layer back from the corners of the trench. An isolation material is then used to fill the shallow trench and the buffer film layer is stripped to form an isolation structure. When the structure is etched by subsequent processing step(s), a capped shallow trench isolation structure that covers the shallow trench corners is created. | 01-03-2013 |
20130009276 | METHODS OF FILLING ISOLATION TRENCHES FOR SEMICONDUCTOR DEVICES AND RESULTING STRUCTURES - The invention relates to a method and resulting structure that can substantially minimize and/or eliminate void formation during an isolation trench isolation fill process for typical trench shaped and goal-post shaped isolation regions. First, a thin thermal oxidation layer is grown on the sidewall of each trench and then a layer of polysilicon is deposited above the oxidation layer and oxidized. In one embodiment, a repeating series of polysilicon deposition and polysilicon oxidation steps are performed until each trench has been completely filled. In another embodiment, within a goal-post shaped trench having a wider upper portion and a narrower lower portion, the remainder of the upper wider trench portion is filled using a conventional high density plasma technique. | 01-10-2013 |
20130015552 | Electrical Isolation Of High Defect Density Regions In A Semiconductor DeviceAANM Kizilyalli; Isik C.AACI San FranciscoAAST CAAACO USAAGP Kizilyalli; Isik C. San Francisco CA USAANM Bour; David P.AACI CupertinoAAST CAAACO USAAGP Bour; David P. Cupertino CA USAANM Brown; Richard J.AACI Los GatosAAST CAAACO USAAGP Brown; Richard J. Los Gatos CA USAANM Edwards; Andrew P.AACI San JoseAAST CAAACO USAAGP Edwards; Andrew P. San Jose CA USAANM Nie; HuiAACI CupertinoAAST CAAACO USAAGP Nie; Hui Cupertino CA USAANM Romano; Linda T.AACI SunnyvaleAAST CAAACO USAAGP Romano; Linda T. Sunnyvale CA US - Embodiments of the invention include a III-nitride semiconductor layer including a first portion having a first defect density and a second portion having a second defect density. The first defect density is greater than the second defect density. An insulating material is disposed over the first portion. The insulating material is not formed on or is removed from the second portion. | 01-17-2013 |
20130020673 | PROTECTION DIODE AND SEMICONDUCTOR DEVICE HAVING THE SAME - A protection diode includes a semiconductor substrate having a first region, a second region surrounding the first region, and a third region surrounding the second region; a first insulation layer disposed between the second region and the third region; a first conductive type semiconductor portion disposed in the third region; a second conductive type semiconductor portion disposed in the second region; and a capacity reduction layer disposed in the first region. | 01-24-2013 |
20130037905 | HYBRID SUBSTRATELESS DEVICE WITH ENHANCED TUNING EFFICIENCY - In a hybrid integrated module, a semiconductor die is mechanically coupled face-to-face to an integrated device in which the substrate has been removed. For example, the integrated circuit may include an optical device fabricated on a silicon-on-insulator (SOI) wafer in which the backside silicon handler has been completely removed, thereby facilitating improved device performance and highly efficient thermal tuning of the operating wavelength of the optical device. Moreover, the semiconductor die may be a VLSI chip that provides power, and serves as a mechanical handler and/or an electrical driver. The thermal tuning efficiency of the substrateless optical device may be enhanced by over 100× relative to an optical device with an intact substrate, and by 5× relative to an optical device in which the substrate has only been removed in proximity to the optical device. | 02-14-2013 |
20130037906 | Semiconductor Device and a Method for Forming a Semiconductor Device - A semiconductor device having a semiconductor die is provided. The semiconductor die includes a main horizontal surface, an outer edge, an active area, and a peripheral area. The peripheral area includes a dielectric structure surrounding the active area and extending from the main horizontal surface into the semiconductor die. The dielectric structure includes, in a horizontal cross-section, at least one substantially L-shaped portion that is inclined against the outer edge. Further, a method for forming a semiconductor device is provided. | 02-14-2013 |
20130037907 | OPTOELECTRONIC INTEGRATED CIRCUIT SUBSTRATE AND METHOD OF FABRICATING THE SAME - An optoelectronic integrated circuit substrate may include a first region and a second region. The first region and the second region each include at least two buried insulation layers having different thicknesses. The at least two buried insulation layers of the first region are formed at a greater depth and have a greater thickness as compared to the at least two buried insulation layers of the second region. A micro-electromechanical systems (MEMS) structure may be formed in a third region that does not include a buried insulation layer. | 02-14-2013 |
20130043554 | METHOD AND STRUCTURE FOR VERTICAL INTEGRATION OF SEMICONDUCTOR DEVICES - A vertically integrated semiconductor device includes multiple continuous single crystal silicon layers vertically separated from one another by a dielectric layer or layers. Semiconductor devices are disposed on an underlying single crystal silicon substrate and the continuous single crystal silicon layers. The individual devices are interconnected to one another using tungsten or doped polysilicon leads that extend through openings formed in the continuous single crystal silicon layers. The method for forming the structure includes forming a dielectric material over the single crystal silicon layer or substrate and forming an opening extending down to the surface of the single crystal silicon material to act as a seed layer. An epitaxial silicon growth process begins at the seed location and laterally overgrows the openings. Growth fronts from the various seed locations meet to form a continuous single crystal silicon layer which is then polished. | 02-21-2013 |
20130056845 | METHOD FOR FORMING AN ISOLATION TRENCH - A method forms at least one isolation trench in a substrate having an upper surface. The method includes at least: forming, across the substrate thickness, at least one first cavity opened towards the upper surface; totally filling this first cavity with a dielectric material of a first type; forming a second cavity in an upper portion of the first cavity thus filled, said second cavity being opened towards the upper surface and having a substantially concave profile; totally filling this second cavity with a dielectric material of a second type; and leveling the free surface of the trench substantially down to the upper surface level. | 03-07-2013 |
20130062725 | SYSTEM AND METHOD OF GALVANIC ISOLATION IN DIGITAL SIGNAL TRANSFER INTEGRATED CIRCUITS UTILIZING CONDUCTIVITY MODULATION OF SEMICONDUCTOR SUBSTRATE - A galvanic isolation system provides galvanic isolation in digital transfer integrated circuits by using conductivity modulation of the semiconductor substrate. Modulation of the conductivity of the substrate affects eddy current losses of a (differential) RF inductor that is isolated from the substrate by a sufficient amount of dielectric material, which provides a basis for signal transfer from the modulated substrate to the inductor across the isolation barrier. | 03-14-2013 |
20130062726 | SEMICONDUCTOR FUSE WITH ENHANCED POST-PROGRAMMING RESISTANCE - Post programming resistance of a semiconductor fuse is enhanced by using an implantation to form an amorphous silicon layer and to break up an underlying high-κ/metal gate. Embodiments include forming a shallow trench isolation (STI) region in a silicon substrate, forming a high-κ dielectric layer on the STI region, forming a metal gate on the high-κ dielectric layer, forming a polysilicon layer over the metal gate, performing an implantation to convert the polysilicon layer into an amorphous silicon layer, wherein the implantation breaks up the metal gate, and forming a silicide on the amorphous silicon layer. By breaking up the metal gate, electrical connection of the fuse contacts through the metal gate is eliminated. | 03-14-2013 |
20130062727 | CRACK STOP STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in a form of a grid to form a crack stop structure. | 03-14-2013 |
20130069195 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - According to one embodiment, a fabrication method for a semiconductor device includes: injecting an ion into a first substrate; joining the first substrate and a second substrate; irradiating a microwave to agglomerate the ion in a planar state in a desired position in the first substrate and form an agglomeration region spreading in a planar state; separating the second substrate provided with a part of the first substrate from the rest of the first substrate by exfoliating the joined first substrate from the second substrate in the agglomeration region; and grinding a part of the second substrate on a back surface opposite to an exfoliated surface in the second substrate provided with a part of the first substrate. | 03-21-2013 |
20130075857 | ISOLATION STRUCTURE, SEMICONDUCTOR DEVICE HAVING THE SAME, AND METHOD FOR FABRICATING THE ISOLATION STRUCTURE - An isolation structure of a semiconductor, a semiconductor device having the same, and a method for fabricating the isolation structure are provided. An isolation structure of a semiconductor device may include a trench formed in a substrate, an oxide layer formed on a bottom surface and an inner sidewall of the trench, a filler formed on the oxide layer to fill a part of inside of the trench, and a fourth oxide layer filling an upper portion of the filler of the trench to a height above an upper surface of the trench, an undercut structure being formed on a boundary area between the inner sidewall and the oxide layer. | 03-28-2013 |
20130087882 | LATERAL ETCH STOP FOR NEMS RELEASE ETCH FOR HIGH DENSITY NEMS/CMOS MONOLITHIC INTEGRATION - Structure and method for fabricating a barrier layer that separates an electromechanical device and a CMOS device on a substrate. An example structure includes a protective layer encapsulating the electromechanical device, where the barrier layer may withstand an etch process capable of removing the protective layer, but not the barrier layer. The substrate may be silicon-on-insulator or a multilayer wafer substrate. The electromechanical device may be a microelectromechanical system (MEMS) or a nanoelectromechanical system (NEMS). | 04-11-2013 |
20130093039 | HIGH-K DIELECTRIC AND SILICON NITRIDE BOX REGION - Aspects of the invention provide for preventing undercuts during wafer etch processing and enhancing back-gate to channel electrical coupling. In one embodiment, aspects of the invention include a semiconductor structure, including: a high-k buried oxide (BOX) layer atop a bulk silicon wafer, the high-k BOX layer including: at least one silicon nitride layer; and a high-k dielectric layer; and a silicon-on-insulator (SOI) layer positioned atop the high-k BOX layer. | 04-18-2013 |
20130093040 | SHALLOW TRENCH ISOLATION STRUCTURE HAVING A NITRIDE PLUG - A semiconductor structure and method for forming a shallow trench isolation (STI) structure having one or more oxide layers and a nitride plug. Specifically, the structure and method involves forming one or more trenches in a substrate. The STI structure is formed having one or more oxide layers and a nitride plug, wherein the STI structure is formed on and adjacent to at least one of the one or more trenches. One or more gates are formed on the substrate and spaced at a distance from each other. A dielectric layer is formed on and adjacent to the substrate, the STI structure, and the one or more gates. | 04-18-2013 |
20130093041 | Semiconductor Device and Method for Manufacturing the Same - The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention may comprise: a substrate; a device region located on the substrate; and at least one stress introduction region separated from the device region by an isolation structure, with stress introduced into at least a portion of the at least one stress introduction region, wherein the stress introduced into the at least a portion of the at least one stress introduction region is produced by utilizing laser to illuminate an amorphized portion comprised in the at least one stress introduction region to recrystallize the amorphized portion. The semiconductor device according to an embodiment of the invention produces stress in a simpler manner and thereby improves the performance of the device. | 04-18-2013 |
20130093042 | TSV Formation Processes Using TSV-Last Approach - A device includes a semiconductor substrate having a front surface and a back surface opposite the front surface. An insulation region extends from the front surface into the semiconductor substrate. An inter-layer dielectric (ILD) is over the insulation region. A landing pad extends from a top surface of the ILD into the insulation region. A through-substrate via (TSV) extends from the back surface of the semiconductor substrate to the landing pad. | 04-18-2013 |
20130099349 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a semiconductor substrate having a first surface and a second surface, and having a LSI on the first surface of the semiconductor substrate, a first insulating layer with an opening, the first insulating layer provided on the first surface of the semiconductor substrate, a conductive layer on the opening, the conductive layer being connected to the LSI, and a via extending from a second surface of the semiconductor substrate to the conductive layer through the opening, the via having a size larger than a size of the opening in a range from the second surface to a first interface between the semiconductor substrate and the first insulating layer, and having a size equal to the size of the opening in the opening. | 04-25-2013 |
20130113068 | LOW-K DIELECTRIC PROTECTION SPACER FOR PATTERNING THROUGH SUBSTRATE VIAS THROUGH A LOW-K WIRING LAYER - A low-K value dielectric protection spacer for patterning through substrate vias (TSVs) through a low-K value wiring layer. A method for forming a low-K value dielectric protection spacer includes etching a via opening through a low-K value dielectric interconnect layer. A protective layer is deposited in the via opening and on the low-K value dielectric interconnect layer. At least a portion of the protective layer is etched from the bottom of the via opening and from a horizontal surface of the low-K value dielectric interconnect layer. The etching leaving a protective sidewall spacer on a sidewall of the via opening. A through substrate via is etched through the bottom of the via opening and through the semiconductor substrate. The through substrate via is filled with a conductive material. | 05-09-2013 |
20130119506 | FORMATION OF STI TRENCHES FOR LIMITING PN-JUNCTION LEAKAGE - Methods and structure are provided to facilitate isolation of respective ground plane regions in an SOTB semiconductor device. In one aspect a shallow STI trench can be combined with Si:C or Si:C/SiGe layers to confine n-type and p-type regions. In a further aspect, Ge can be implanted at the bottom of a shallow STI trench and subsequently oxidized to form SiGe oxide thereby extending the effective isolation provided by the shallow STI trench. In an aspect, a shallow STI trench can be extended to expose an underlying layer of SiGe, wherein the SiGe is subsequently oxidized to extending the effective isolation provide by the shallow STI trench. Such aspects enable a shallow STI trench to be seamlessly filled while having an extended region of isolation. | 05-16-2013 |
20130119507 | SEMICONDUCTOR DEVICE USING GROUP III-V MATERIAL AND METHOD OF MANUFACTURING THE SAME - Semiconductor devices using a group III-V material, and methods of manufacturing the same, include a substrate having a groove, a group III-V material layer filling in the groove and having a height the same as a height of the substrate, a first semiconductor device on the group III-V material layer, and a second semiconductor device on the substrate near the groove. The group III-V material layer is spaced apart from inner side surfaces of the groove. | 05-16-2013 |
20130134545 | SELF-LIMITING OXYGEN SEAL FOR HIGH-K DIELECTRIC, RELATED METHOD AND DESIGN STRUCTURE - A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate including: a high-K dielectric region; a blocking region disposed against at least one surface of the high-K dielectric region and adapted to form an oxidized layer in response to exposure to oxygen; and an oxygen rich region disposed against the blocking region such that the blocking region is interposed between the oxygen rich region and the high-K dielectric region. | 05-30-2013 |
20130134546 | HIGH DENSITY MULTI-ELECTRODE ARRAY - A method includes forming one or more trenches in a substrate; lining the one or more trenches with a dielectric liner; filling the one or more trenches with a conductive electrode to form one or more trench electrodes; forming a transistor layer on the substrate; connecting each of the one or more trench electrodes to at least one access transistor in the transistor layer; and thinning the substrate to expose at least a portion of each of the trench electrodes. | 05-30-2013 |
20130134547 | METHOD FOR FABRICATING A LOCALLY PASSIVATED GERMANIUM-ON-INSULATOR SUBSTRATE - The invention relates to a method for fabricating a locally passivated germanium-on-insulator substrate wherein, in order to achieve good electron mobility, nitridized regions are provided at localised positions. Nitridizing is achieved using a plasma treatment. The resulting substrates also form part of the invention. | 05-30-2013 |
20130140669 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A first MISFET which is a semiconductor element is formed on an SOI substrate. The SOI substrate includes a supporting substrate which is a base, BOX layer which is an insulating layer formed on a main surface (surface) of the supporting substrate, that is, a buried oxide film; and an SOI layer which is a semiconductor layer formed on the BOX layer. The first MISFET as a semiconductor element is formed to the SOI layer. In an isolation region, an isolation groove is formed penetrating though the SOI layer and the BOX layer so that a bottom surface of the groove is positioned in the middle of a thickness of the supporting substrate. An isolation film is buried in the isolation groove being formed. Then, an oxidation resistant film is interposed between the BOX layer and the isolation film. | 06-06-2013 |
20130140670 | STRUCTURE AND METHOD FOR REDUCTION OF VT-W EFFECT IN HIGH-K METAL GATE DEVICES - A substrate is provided. An STI trench is formed in the substrate. A fill material is formed in the STI trench and then planarized. The substrate is exposed to an oxidizing ambient, growing a liner at a bottom and sidewalls of the STI trench. The liner reduces the Vt-W effect in high-k metal gate devices. | 06-06-2013 |
20130154049 | Integrated Circuits on Ceramic Wafers Using Layer Transfer Technology - Novel integrated circuits (ICs) on ceramic wafers and methods of fabricating ICs on ceramic wafers are disclosed. In one embodiment, an active layer comprising IC circuit components is coupled to a selected wafer comprising a ceramic. A surface of the ceramic is processed to enable direct bonding between the selected wafer and the active layer. Another embodiment comprises an active layer comprising IC circuit components and a selected wafer comprising a ceramic and an intermediate layer. A surface of the intermediate layer is processed to enable direct bonding. In some embodiments the intermediate layer comprises a material selected from the following: silicon carbide, silicon dioxide, silicon nitride and diamond. Methods of fabrication are described, wherein layer transfer technology is employed to form active layers and to couple the active layers to the selected wafers. | 06-20-2013 |
20130154050 | Integrated Circuit and IC Manufacturing Method - Disclosed is an integrated circuit die comprising an active substrate including a plurality of components laterally separated from each other by respective isolation structures, at least some of the isolation structures carrying a further component, wherein the respective portions of the active substrate underneath the isolation structures carrying said further components are electrically insulated from said components. A method of manufacturing such an IC die is also disclosed. | 06-20-2013 |
20130161782 | Heterogeneous Chip Integration with Low Loss Interconnection through Adaptive Patterning - Integrating a semiconductor component with a substrate through a low loss interconnection formed through adaptive patterning includes forming a cavity in the substrate, placing the semiconductor component therein, filling a gap between the semiconductor component and substrate with a fill of same or similar dielectric constant as that of the substrate and adaptively patterning a low loss interconnection on the fill and extending between the contacts of the semiconductor component and the electrical traces on the substrate. The contacts and leads are located and adjoined using an adaptive patterning technique that places and forms a low loss radio frequency transmission line that compensates for any misalignment between the semiconductor component contacts and the substrate leads. | 06-27-2013 |
20130168801 | METHOD OF FORMING ISOLATION AREA AND STRUCTURE THEREOF - The instant disclosure relates to a method of forming an isolation area. The method includes the steps of: providing a substrate having a first type of ion dopants, where the substrate has a plurality of trenches formed on the cell areas and the isolation area between the cell areas of the substrate, with the side walls of the trenches having an oxidation layer formed thereon and the trenches are filled with a metallic structure; removing the metallic structure from the trenches of the isolation area; implanting a second type of ions into the substrate under the trenches of the isolation area; and filling all the trenches with an insulating structure, where the trenches of the isolation area are filled up fully by the insulating structure to form a non-metallic isolation area. | 07-04-2013 |
20130168802 | SOI STRUCTURES WITH REDUCED METAL CONTENT - Methods for producing silicon on insulator structures with a reduced metal content in the device layer thereof are disclosed. Silicon on insulator structures with a reduced metal content are also disclosed. | 07-04-2013 |
20130175659 | FinFETs with Vertical Fins and Methods for Forming the Same - In a method for forming a device, a (110) silicon substrate is etched to form first trenches in the (110) silicon substrate, wherein remaining portions of the (110) silicon substrate between the first trenches form silicon strips. The sidewalls of the silicon strips have (111) surface orientations. The first trenches are filled with a dielectric material to from Shallow Trench Isolation (STI) regions. The silicon strips are removed to form second trenches between the STI regions. An epitaxy is performed to grow semiconductor strips in the second trenches. Top portions of the STI regions are recessed, and the top portions of the semiconductor strips between removed top portions of the STI regions form semiconductor fins. | 07-11-2013 |
20130175660 | Dummy Gate Structure for Semiconductor Devices - A structure and method for fabricating a spacer structure for semiconductor devices, such as a multi-gate structure, is provided. The dummy gate structure is formed by depositing a dielectric layer, forming a mask over the dielectric layer, and patterning the dielectric layer. The mask is formed to have a tapered edge. In an embodiment, the tapered edge is formed in a post-patterning process, such as a baking process. In another embodiment, a relatively thick mask layer is utilized such that during patterning a tapered results. The profile of the tapered mask is transferred to the dielectric layer, thereby providing a tapered edge on the dielectric layer. | 07-11-2013 |
20130175661 | Integrated Circuit Having Back Gating, Improved Isolation And Reduced Well Resistance And Method To Fabricate Same - A structure includes a silicon substrate; at least two wells in the silicon substrate; and a deep trench isolation (DTI) separating the two wells. The DTI has a top portion and a bottom portion having a width that is larger than a width of the top portion. The structure further includes at least two semiconductor devices disposed over one of the wells, where the at least two semiconductor devices are separated by a shallow trench isolation (STI). In the structure sidewalls of the top portion of the DTI and sidewalls of the STI are comprised of doped, re-crystallized silicon. The doped, re-crystallized silicon can be formed by an angled ion implant that uses, for example, one of Xe, In, BF | 07-11-2013 |
20130175662 | SEMICONDUCTOR MATERIAL MANUFACTURE - Electronic apparatus, systems, and methods include a semiconductor layer bonded to a bulk region of a wafer or a substrate, in which the semiconductor layer can be bonded to the bulk region using electromagnetic radiation. Additional apparatus, systems, and methods are disclosed. | 07-11-2013 |
20130181321 | SOI Structure and Method for Utilizing Trenches for Signal Isolation and Linearity - Disclosed is a structure for improved electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and an associated method for the structure's fabrication. The structure comprises a first portion of a trench extending through the top semiconductor layer and through a base oxide layer below the top semiconductor layer. A handle wafer is situated below the base oxide layer and a second portion of the trench, having sloped sidewalls, extends into the handle wafer. The sloped sidewalls are amorphized by an implant, for example, Xenon or Argon, to reduce carrier mobility in the handle wafer and improve electrical signal isolation between the adjacent devices situated in the top semiconductor layer. | 07-18-2013 |
20130187253 | HIGH DENSITY MULTI-ELECTRODE ARRAY - A high density micro-electrode array includes a transistor layer including a plurality of access transistors and a substrate in operable communication with the transistor layer including, wherein at least a portion of the substrate includes a plurality of trenches. The system includes a plurality of electrodes at least partially located in the plurality of trenches, wherein each of the plurality of electrodes is connected to at least one of the plurality of access transistors and wherein each of the electrodes is separated by a distance less than approximately one microns. | 07-25-2013 |
20130193548 | SEMICONDUCTOR DEVICES HAVING A TRENCH ISOLATION LAYER AND METHODS OF FABRICATING THE SAME - Semiconductor devices including a trench isolation layer are provided. The semiconductor device includes a substrate having a trench therein, a liner insulation layer that covers a bottom surface and sidewalls of the trench and includes micro trenches located at bottom inner corners of the liner insulation layer, a first isolating insulation layer filling the micro trenches and a lower region of the trench that are surrounded by the liner insulation layer, and a second isolating insulation layer filling the trench on the first isolating insulation layer. The liner insulation layer on sidewalls of an upper region of the trench having a thickness that gradually increases toward a bottom surface of the trench, and the liner insulation layer on sidewalls of the lower region of the trench having a thickness that is uniform. Related methods are also provided. | 08-01-2013 |
20130200482 | SHALLOW TRENCH ISOLATION FOR DEVICE INCLUDING DEEP TRENCH CAPACITORS - A method for formation of a shallow trench isolation (STI) in an active region of a device comprising trench capacitive elements, the trench capacitive elements comprising a metal plate and a high-k dielectric includes etching a STI trench in the active region of the device, wherein the STI trench is directly adjacent to at least one of the metal plate or high-k dielectric of the trench capacitive elements; and forming an oxide liner in the STI trench, wherein the oxide liner is formed selectively to the metal plate or high-k dielectric, wherein forming the oxide liner is performed at a temperature of about 600° C. or less. | 08-08-2013 |
20130200483 | FIN STRUCTURE AND METHOD OF FORMING THE SAME - A method of forming a fin structure is provided. The method includes forming a hard mask material layer on a substrate, and then patterning the hard mask material layer to form a first hard mask layer. Thereafter, a portion of the substrate is removed to form two trenches, wherein a remaining substrate forms a fin between the trenches. Afterwards, an insulating layer is formed in each trench, wherein the insulating layers expose an upper portion of the fin. Further, the upper portion of the fin is trimmed, so that the trimmed upper portion is narrower than a lower portion of the fin, and a fin structure having an inverse T shape is formed. | 08-08-2013 |
20130200484 | PROCESS FOR MANUFACTURING A WAFER BY ANNEALING OF BURIED CHANNELS - A process for manufacturing an SOI wafer, including the steps of: forming, in a wafer of semiconductor material, cavities delimiting structures of semiconductor material; thinning out the structures through a thermal process; and completely oxidizing the structures. | 08-08-2013 |
20130200485 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device, the method comprising, forming an opening in an insulating layer, which is formed on a semiconductor substrate, using a photoresist pattern formed on the insulating layer as a mask, forming a first element isolation portion in the semiconductor substrate by implanting an ion into the semiconductor substrate using the photoresist pattern as a mask, forming a second element isolation portion, in the semiconductor substrate, whose outer edge is outside an outer edge of the opening, by implanting an ion into the semiconductor substrate through the opening, and forming a third element isolation portion, which is inside the outer edge of the second element isolation portion, by embedding an insulating member in the opening and removing the insulating layer. | 08-08-2013 |
20130214381 | METHODS OF FORMING ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES - Disclosed herein are various methods of forming isolation structures, such as trench isolation structures, for semiconductor devices. In one example, the method includes forming a trench in a semiconducting substrate, forming a lower isolation structure in the trench, wherein the lower isolation structure has an upper surface that is below an upper surface of the substrate, and forming an upper isolation structure above the lower isolation structure, wherein a portion of the upper isolation structure is positioned within the trench. | 08-22-2013 |
20130214382 | METHOD OF FORMING SUBSTRATE CONTACT FOR SEMICONDUCTOR ON INSULATOR (SOI) SUBSTRATE - A semiconductor structure is provided that includes a material stack including an epitaxially grown semiconductor layer on a base semiconductor layer, a dielectric layer on the epitaxially grown semiconductor layer, and an upper semiconductor layer present on the dielectric layer. A capacitor is present extending from the upper semiconductor layer through the dielectric layer into contact with the epitaxially grown semiconductor layer. The capacitor includes a node dielectric present on the sidewalls of the trench and an upper electrode filling at least a portion of the trench. A substrate contact is present in a contact trench extending from the upper semiconductor layer through the dielectric layer and the epitaxially semiconductor layer to a doped region of the base semiconductor layer. A substrate contact is also provided that contacts the base semiconductor layer through the sidewall of a trench. Methods for forming the above-described structures are also provided. | 08-22-2013 |
20130214383 | METHOD FOR FORMING ISOLATION STRUCTURE - [Problem] To provide a method for forming an isolation structure having a low shrinkage percentage and a low tensile stress. | 08-22-2013 |
20130221478 | METHODS OF FORMING ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES BY EMPLOYING A SPIN-ON GLASS MATERIAL OR A FLOWABLE OXIDE MATERIAL - Disclosed herein are various methods of forming isolation structures, such as trench isolation structures, for semiconductor devices using a spin-on glass material or a flowable oxide material. In one example, the method includes forming a trench in a semiconducting substrate, forming a lower isolation structure comprised of an insulating material in at least the trench, wherein the lower isolation structure has an upper surface that is below an upper surface of the substrate, and forming an upper isolation structure above the lower isolation structure, wherein a portion of the upper isolation structure is positioned within the trench. | 08-29-2013 |
20130221479 | CMOS STRUCTURE AND METHOD OF MANUFACTURE - CMOS structures with a replacement substrate and methods of manufacture are disclosed herein. The method includes forming a device on a temporary substrate. The method further includes removing the temporary substrate. The method further includes bonding a permanent electrically insulative substrate to the device with a bonding structure. | 08-29-2013 |
20130221480 | Semiconductor Devices and Methods of Manufacture Thereof - Methods of fabricating semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a method of fabricating a semiconductor device includes providing a workpiece having a plurality of trenches formed therein, forming a liner over the workpiece, and forming a layer of photosensitive material over the liner. The layer of photosensitive material is removed from over the workpiece except from over at least a portion of each of the plurality of trenches. The layer of photosensitive material is partially removed from over the workpiece, leaving a portion of the layer of photosensitive material remaining within a lower portion of the plurality of trenches over the liner. | 08-29-2013 |
20130221481 | SEMICONDUCTOR SUBSTRATE, METHOD OF MANUFACTURING SEMICONDUCTOR SUBSTRATE, THIN FILM TRANSISTOR, SEMICONDUCTOR CIRCUIT, LIQUID CRYSTAL DISPLAY APPARATUS, ELECTROLUMINESCENCE APPARATUS, WIRELESS COMMUNICATION APPARATUS, AND LIGHT EMITTING APPARATUS - A semiconductor substrate ( | 08-29-2013 |
20130228893 | TRENCH ISOLATION STRUCTURE AND METHOD FOR FORMING THE SAME - A trench isolation structure and a method of forming the same are provided. The trench isolation structure includes: a semiconductor substrate, and trenches formed on the surface of the semiconductor substrate and filled with a dielectric layer, wherein the material of the dielectric layer is a crystalline material. By using the present invention, the size of the divot can be reduced, and device performances can be improved. | 09-05-2013 |
20130234280 | SHALLOW TRENCH ISOLATION IN DYNAMIC RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF - A manufacturing method of STI in DRAM includes the following steps. Step 1 is providing a substrate and step 2 is forming at least one trench in the substrate. Step 3 is doping at least one of side portions and bottom portions of the trench with a dopant. Step 4 is forming an oxidation inside the trench and step 5 is providing a planarization step to remove the oxidation. The stress of the corners of STI is reduced so as to modify the defect of the substrate and improve the DRAM variability in retention time. | 09-12-2013 |
20130234281 | Wafer with Spacer including Horizontal Member - A method of forming an insulating spacer is disclosed that includes providing a base layer, providing an intermediate layer above an upper surface of the base layer, etching a first trench in the intermediate layer, depositing a first insulating material portion within the first trench, depositing a second insulating material portion above an upper surface of the intermediate layer, forming an upper layer above an upper surface of the second insulating material portion, etching a second trench in the upper layer, and depositing a third insulating material portion within the second trench and on the upper surface of the second insulating material portion. A wafer is also disclosed. | 09-12-2013 |
20130241026 | NOVEL SEMICONDUCTOR DEVICE AND STRUCTURE - A device including a first layer of first transistors interconnected by at least one first interconnection layer, wherein the first interconnection layer includes copper or aluminum, a second layer including second transistors, the second layer overlaying the first interconnection layer, wherein the second layer is less than 2 micron thick, wherein the second layer has a coefficient of thermal expansion; and a connection path connecting at least one of the second transistors to the first interconnection layer, wherein the connection path includes at least one through-layer via, and wherein the through-layer via includes material whose co-efficient of thermal expansion is within 50 percent of the second layer coefficient of thermal expansion. | 09-19-2013 |
20130241027 | SEMICONDUCTOR DEVICE HAVING ISOLATION REGION - A semiconductor device can include an isolation region that defines a plurality of active regions. The plurality of active regions can include an upper surface having a short axis in a first direction and a long axis in a second direction. The plurality of active regions can be repeatedly disposed along the first direction and along the second direction, and can be spaced apart from each other. The isolation region can include a first insulating layer being in contact with side walls of a short axis pair of active regions which can be the closest active regions in the first direction among the plurality of active regions, and continuously extending along a first shortest distance between the short axis pair of active regions. | 09-19-2013 |
20130241028 | SILICON-ON-INSULATOR SUBSTRATE AND FABRICATION METHOD - An SOI substrate and a method for forming the SOI substrate are provided. An SOI substrate can be formed by forming a silicon-germanium layer on a first baseplate. A top silicon layer can be formed on the silicon-germanium layer. A first insulating layer can be formed on the top silicon layer. An ion implanted layer can be formed in one of the silicon-germanium layer and the first baseplate. A second baseplate can be bonded to the first insulating layer. A first annealing process can be performed to anneal and split the one of the silicon-germanium layer and the first baseplate at the ion implanted layer. The silicon-germanium layer can be removed from the top silicon layer to expose the top silicon layer and to form the SOI substrate comprising the first insulating layer formed between the top silicon layer and the second baseplate. | 09-19-2013 |
20130241029 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME AND DESIGNING THE SAME - There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP | 09-19-2013 |
20130249047 | THROUGH SILICON VIA STRUCTURE AND METHOD FOR FABRICATING THE SAME - A through silicon via structure is provided, including a substrate, an isolation layer, a conductive layer and a dielectric layer. The substrate has a through-hole therein. The isolation layer is disposed on two sidewalls of the through-hole. The conductive layer is disposed in the through-hole and covers the isolation layer, and the conductive layer includes a first portion and a second portion, wherein the first portion fills a portion of the through-hole, and the second portion is located on the sidewalls in the other portion of the through-hole, such that the conductive layer has a concave part. The dielectric layer is disposed in the concave part and fills the concave part. | 09-26-2013 |
20130249048 | SEMICONDUCTOR DEVICE WITH ISOLATION LAYER, ELECTRONIC DEVICE HAVING THE SAME, AND METHOD FOR FABRICATING THE SAME - A semiconductor device with an isolation layer buried in a trench includes an interface layer formed on the surface of the trench, a buffer layer formed in the interface layer at a bottom corner of the trench, a liner layer formed over the interface layer, and a gap-fill layer gap-filling the trench over the liner layer. The trench includes a micro-trench formed at the bottom corner thereof, and the buffer layer fills the micro-trench. | 09-26-2013 |
20130249049 | CYCLIC CARBOSILANE DIELECTRIC FILMS - Embodiments of the invention provide dielectric films and low-k dielectric films and methods for making dielectric and low-k dielectric films. Dielectric films are made from carbosilane-containing precursors. In embodiments of the invention, dielectric film precursors comprise attached porogen molecules. In further embodiments, dielectric films have nanometer-dimensioned pores. | 09-26-2013 |
20130256828 | SEMICONDUCTOR DEVICES HAVING INCREASED CONTACT AREAS BETWEEN CONTACTS AND ACTIVE REGIONS AND METHODS OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a substrate including first and second junction regions, a word line buried in the substrate, a bit line provided over the word line to cross the word line, a first contact provided between the substrate and the bit line and electrically connected to the first junction region, and a second contact provided between the bit lines and electrically connected to the second junction region. An overlapping area of a lower portion of the second contact may be greater than an overlapping area of an upper portion of the second contact with respect to the second junction region. | 10-03-2013 |
20130256829 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An AlGaN/GaN HEMT includes a compound semiconductor stack structure; an element isolation structure which demarcates an element region on the compound semiconductor stack structure; a first insulating film which is formed on the element region and is not formed on the element isolation structure; a second insulating film which is formed on at least the element isolation structure and is higher in hydrogen content than the first insulating film; and a gate electrode which is formed on the element region of the compound semiconductor stack structure via the second insulating film. | 10-03-2013 |
20130277795 | FARBRICATION OF A LOCALIZED THICK BOX WITH PLANAR OXIDE/SOI INTERFACE ON BULK SILICON SUBSTRATE FOR SILICON PHOTONICS INTEGRATION - Line trenches are formed in a stack of a bulk semiconductor substrate and an oxygen-impermeable layer such that the depth of the trenches in the bulk semiconductor substrate is greater than the lateral spacing between a pair of adjacently located line trenches. Oxygen-impermeable spacers are formed on sidewalls of the line trenches. An isotropic etch, either alone or in combination with oxidation, removes a semiconductor material from below the oxygen-impermeable spacers to expand the lateral extent of expanded-bottom portions of the line trenches, and to reduce the lateral spacing between adjacent expanded-bottom portions. The semiconductor material around the bottom portions is oxidized to form a semiconductor oxide portion that underlies multiple oxygen-impermeable spacers. Semiconductor-on-insulator (SOI) portions are formed above the semiconductor oxide portion and within the bulk semiconductor substrate. | 10-24-2013 |
20130285193 | METAL-INSULATOR-METAL (MIM) CAPACITOR WITH DEEP TRENCH (DT) STRUCTURE AND METHOD IN A SILICON-ON-INSULATOR (SOI) - A structure forming a metal-insulator-metal (MIM) trench capacitor is disclosed. The structure comprises a multi-layer substrate having a metal layer and at least one dielectric layer. A trench is etched into the substrate, passing through the metal layer. The trench is lined with a metal material that is in contact with the metal layer, which comprises a first node of a capacitor. A dielectric material lines the metal material in the trench. The trench is filled with a conductor. The dielectric material that lines the metal material separates the conductor from the metal layer and the metal material lining the trench. The conductor comprises a second node of the capacitor. | 10-31-2013 |
20130285194 | OPTICAL PROXIMITY CORRECTION FOR ACTIVE REGION DESIGN LAYOUT - The present disclosure provides an integrated circuit design method. In an example, a method includes receiving an integrated circuit design layout that includes an active region feature, a contact feature, and an isolation feature, wherein a portion of the active region feature is disposed between the contact feature and the isolation feature; determining whether a thickness of the portion of the active region feature disposed between the contact feature and the isolation feature is less than a threshold value; and modifying the integrated circuit design layout if the thickness is less than the threshold value, wherein the modifying includes adding a supplementary active region feature adjacent to the portion of the active region feature disposed between the contact feature and the isolation feature. | 10-31-2013 |
20130285195 | VERTICALLY INTEGRATED SEMICONDUCTOR DEVICES - A vertically integrated semiconductor device includes multiple continuous single crystal silicon layers vertically separated from one another by a dielectric layer or layers. Semiconductor devices are disposed on an underlying single crystal silicon substrate and the continuous single crystal silicon layers. The individual devices are interconnected to one another using tungsten or doped polysilicon leads that extend through openings formed in the continuous single crystal silicon layers. The method for forming the structure includes forming a dielectric material over the single crystal silicon layer or substrate and forming an opening extending down to the surface of the single crystal silicon material to act as a seed layer. An epitaxial silicon growth process begins at the seed location and laterally overgrows the openings. Growth fronts from the various seed locations meet to form a continuous single crystal silicon layer which is then polished. | 10-31-2013 |
20130292791 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - In order to prevent formation of voids in STI film, after a second buried insulating layer is filled and planarized, a high density cap is formed embedded in the center region of the second buried insulating layer of the STI trench. The high density cap shields and protects the weaker center region of the second buried insulating layer of the STI trench from the subsequent processing steps and prevents formation of voids in the second buried insulating layer. | 11-07-2013 |
20130292792 | SEMICONDUCTOR DEVICE WITH BURIED BIT LINES AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes active regions separated by a trench, a separation layer dividing the trench, and buried bit lines buried in the trench with the separation layer interposed between the buried bit lines. | 11-07-2013 |
20130299938 | ISOLATED ZENER DIODE, AN INTEGRATED CIRCUIT INCORPORATING MULTIPLE INSTANCES OF THE ZENER DIODE, A METHOD OF FORMING THE ZENER DIODE AND A DESIGN STRUCTURE FOR THE ZENER DIODE - Disclosed is a Zener diode having a scalable reverse-bias breakdown voltage (V | 11-14-2013 |
20130320483 | SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATES WITH ULTRA-THIN SOI LAYERS AND BURIED OXIDES - Semiconductor-on-insulator (SOI) substrates including a buried oxide (BOX) layer having a thickness of less than 300 Å are provided. The (SOI) substrates having the thin BOX layer are provided using a method including a step in which oxygen ions are implanted at high substrate temperatures (greater than 600° C.), and at a low implant energy (less than 40 keV). An anneal step in an oxidizing atmosphere follows the implant step and is performed at a temperature less than 1250° C. The anneal step in oxygen containing atmosphere converts the region containing implanted oxygen atoms formed by the implant step into a BOX having a thickness of less than 300 Å. In some instances, the top semiconductor layer of the SOI substrate has a thickness of less than 300 Å. | 12-05-2013 |
20130320484 | SEMICONDUCTOR DEVICE FORMATION - An apparatus of and method for making a semiconductor structure having a shallow trench isolation (STI) trench with a substantially v-shaped profile, that is the distance between top portions is greater than the distance between bottom portions of shallow trench isolation (STI) structure sidewalls adjacent to the trench, provides for substantially seamless and substantially void-free gate structures. The semiconductor structures are formed by implanting an implantation species into the sidewalls, which allows for the top portions of the sidewalls to be etched away at a greater rate than that of the bottom portions, resulting in the substantially v-shaped profile. And the substantially v-shaped profile allows for subsequent device layers to more easily and smoothly fill in the v-shaped trenches, due to a wider opening toward the tops of the trenches. | 12-05-2013 |
20130328157 | SPACER ISOLATION IN DEEP TRENCH - A method of forming improved spacer isolation in deep trench including recessing a node dielectric, a first conductive layer, and a second conductive layer each deposited within a deep trench formed in a silicon-on-insulator (SOI) substrate, to a level below a buried oxide layer of the SOI substrate, and creating an opening having a bottom surface in the deep trench. Further including depositing a spacer along a sidewall of the deep trench and the bottom surface of the opening, and removing the spacer from the bottom surface of the opening. Performing at least one of an ion implantation and an ion bombardment in one direction at an angle into an upper portion of the spacer. Removing the upper portion of the spacer from the sidewall of the deep trench. Depositing a third conductive layer within the opening. | 12-12-2013 |
20130328158 | SEMICONDUCTOR SEAL RING DESIGN FOR NOISE ISOLATION - A semiconductor structure includes a substrate layer and a conductive layer connected with the substrate layer. An active circuit is connected with the conductive layer. A seal ring is connected with the conductive layer and separated from the active circuit by an assembly isolation region. An electrical isolation region is positioned in the conductive layer and adjacent to the assembly isolation region, where the electrical isolation region extends to the substrate layer. | 12-12-2013 |
20130328159 | IMPLEMENTING ISOLATED SILICON REGIONS IN SILICON-ON-INSULATOR (SOI) WAFERS USING BONDED-WAFER TECHNIQUE - Methods and structures are provided for implementing independently voltage controlled isolated silicon regions under a buried oxide layer for biasing field effect transistors above the buried oxide layer on Silicon-on-Insulator (SOI) wafers. Using a bonded-wafer technique, a first bulk substrate wafer is bonded with a second wafer providing a buried oxide (BOX) layer under a transistor silicon layer creating an SOI wafer. An independently voltage controlled isolated silicon region is created in the created SOI wafer beneath the BOX layer. The transistor silicon layer is polished to a desired thickness, and normal processing is continued with transistors and desired circuits placed over the isolated silicon region. A contact is formed through the transistor silicon layer and BOX layer to the isolated silicon region for connecting the independently voltage controlled isolated silicon region to a voltage. | 12-12-2013 |
20130328160 | SEMICONDUCTOR DEVICE - Semiconductor device comprises a memory cell region, a peripheral region, and first wiring. The memory cell region includes a first isolation region, and a first active region provided so as to be divided off by the first isolation region. The peripheral region includes a second isolation region, and a second active region divided off by the first and second isolation regions and protruding from the upper surface of an insulating film located in the first and second isolation regions. The first wiring is buried in portions of a semiconductor substrate within the memory cell region and the peripheral region, so as to extend over the first and second active regions in a first direction. The first-direction width of the second active region is constant. | 12-12-2013 |
20130334650 | SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF - A semiconductor structure is located in a recess of a substrate. The semiconductor structure includes a liner, a silicon rich layer and a filling material. The liner is located on the surface of the recess. The silicon rich layer is located on the liner. The filling material is located on the silicon rich layer and fills the recess. Furthermore, a semiconductor process forming said semiconductor structure is also provided. | 12-19-2013 |
20130334651 | DUAL SHALLOW TRENCH ISOLATION LINER FOR PREVENTING ELECTRICAL SHORTS - A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate. | 12-19-2013 |
20130334652 | NITRIDE SHALLOW TRENCH ISOLATION (STI) STRUCTURES - A shallow trench isolation (STI) structure includes a top surface formed completely of silicon nitride. The top surface of the STI structure is coplanar with a top substrate surface or extends above the top substrate surface. The STI structures include further dielectric materials beneath the silicon nitride and an oxide liner and any portions that extend above the substrate surface are formed of silicon nitride. | 12-19-2013 |
20130334653 | Semiconductor Device with an Edge Termination Structure - A semiconductor device having a semiconductor die and an edge termination structure is provided. The semiconductor die includes an outer edge and an active area defining a main horizontal surface and being spaced apart from the outer edge. The edge termination structure includes at least one vertical trench having an insulated side wall forming, in a horizontal cross-section, an acute angle with the outer edge. The acute angle is lower than about 20°. | 12-19-2013 |
20130341754 | SHALLOW TRENCH ISOLATION STRUCTURES - Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate. | 12-26-2013 |
20130341755 | SOI SUBSTRATE, METHOD FOR MANUFACTURING SOI SUBSTRATE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An insulating portion has a first region, a second region, and a third region in the stated order from the silicon portion side, the nitrogen concentration of the first region is lower than the nitrogen concentration of the second region and the oxygen concentration of the first region, the nitrogen concentration of the third region is lower than the nitrogen concentration of the second region and the oxygen concentration of the third region, and the thickness of the first region is larger than the thickness of the third region. | 12-26-2013 |
20130341756 | SEMICONDUCTOR ON GLASS SUBSTRATE WITH STIFFENING LAYER AND PROCESS OF MAKING THE SAME - A semiconductor-on-glass substrate having a relatively stiff (e.g. relatively high Young's modulus of 125 or higher) stiffening layer or layers placed between the silicon film and the glass in order to eliminate the canyons and pin holes that otherwise form in the surface of the transferred silicon film during the ion implantation thin film transfer process. The new stiffening layer may be formed of a material, such as silicon nitride, that also serves as an efficient barrier against penetration of sodium and other harmful impurities from the glass substrate into the silicon film. | 12-26-2013 |
20140001596 | Sinker with a Reduced Width | 01-02-2014 |
20140015092 | SEALED SHALLOW TRENCH ISOLATION REGION - A method for formation of a sealed shallow trench isolation (STI) region for a semiconductor device includes forming a STI region in a substrate, the STI region comprising a STI fill; forming a sealing recess in the STI fill of the STI region; and forming a sealing layer in the sealing recess over the STI fill. | 01-16-2014 |
20140015093 | CHARGE BREAKDOWN AVOIDANCE FOR MIM ELEMENTS IN SOI BASE TECHNOLOGY AND METHOD - A semiconductor device including at least one capacitor formed in wiring levels on a silicon-on-insulator (SOI) substrate, wherein the at least one capacitor is coupled to an active layer of the SOI substrate. A method of fabricating a semiconductor structure includes forming an SOI substrate, forming a BOX layer over the SOI substrate, and forming at least one capacitor in wiring levels on the BOX layer, wherein the at least one capacitor is coupled to an active layer of the SOI substrate. | 01-16-2014 |
20140027878 | SELF-ALIGNED TRENCH OVER FIN - A stack of a first hard mask portion and a second hard mask portion is formed over a semiconductor material layer by anisotropically etching a stack, from bottom to top, of a first hard mask layer and a second hard mask layer. The first hard mask portion is laterally recessed by an isotropic etch. A dielectric material layer is conformally deposited and planarized. The dielectric material layer is etched employing an anisotropic etch that is selective to the first hard mask portion to form a dielectric material portion that laterally surrounds the first hard mask portion. After removal of the second and first hard mask portions, the semiconductor material layer is etched employing the dielectric material portion as an etch mask. Optionally, portions of the semiconductor material layer underneath the first and second hard mask portions can be undercut at a periphery. | 01-30-2014 |
20140035093 | Integrated Circuit Interposer and Method of Manufacturing the Same - Systems and methods are provided for an interposer for coupling two or more integrated circuit dies to a circuit package. A first integrated circuit portion is disposed on a first location of a single semiconductor substrate. A second integrated circuit portion is disposed on a second location of the single semiconductor substrate, where the second integrated circuit portion is electrically isolated from the first integrated circuit portion along a first axis. The first and second integrated circuit portions are configured to provide an electrical coupling to two or more corresponding top die integrated circuits across a second axis that is perpendicular to the first axis. | 02-06-2014 |
20140035094 | SEMICONDUCTOR STRUCTURE - One or more embodiments relate to a semiconductor structure, comprising: a silicon rubber layer; and a semiconductor layer overlying the silicon rubber layer. | 02-06-2014 |
20140042586 | SILICON SUBSTRATE AND METHOD OF FABRICATING THE SAME - There are provided a silicon substrate and a method of fabricating the same, the silicon substrate including: first and second silicon substrates having corresponding bonding surfaces; a silicon oxide film formed between the first and second silicon substrates and having at least one trench communicating with the outside; and a hermetic portion formed on an end portion of the trench according to oxidation of the silicon oxide film. | 02-13-2014 |
20140061850 | SEMICONDUCTOR DEVICE WITH BURIED BITLINE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming active regions which are separated by a plurality of first trenches, forming supports which fill the first trenches; etching the active regions and defining second trenches which are shallower than the first trenches, forming spacers on sidewalls of the second trenches, etching bottoms of the second trenches and defining third trenches, forming punch-through preventing patterns which fill lower portions of the third trenches, etching sidewalls which are not protected by the punch-through preventing patterns and the spacers, and forming recessed sidewalls which face each other, and forming buried bit lines in the recessed sidewalls. | 03-06-2014 |
20140070360 | FinFETs with Vertical Fins and Methods for Forming the Same - In a method for forming a device, a ( | 03-13-2014 |
20140077332 | Band Engineered Semiconductor Device and Method for Manufacturing Thereof - The disclosure is related to a band engineered semiconductor device comprising a substrate, a protruding structure that is formed in a recess in the substrate and is extending above the recess having a buried portion and an extended portion, and wherein at least the extended portion comprises a semiconductor material having an inverted ‘V’ band gap profile with a band gap value increasing gradually from a first value at lateral edges of the structure to a second value, higher than the first value, in a center of the structure. The disclosure is also related to the method of manufacturing of such band engineered semiconductor device. | 03-20-2014 |
20140084411 | SEMICONDUCTOR-ON-INSULATOR (SOI) DEEP TRENCH CAPACITOR - Aspects of the present invention relate to a semiconductor-on-insulator (SOI) deep trench capacitor. One embodiment includes a method of forming a deep trench capacitor structure. The method includes: providing a SOI structure including a first and second trench opening in a semiconductor layer of the SOI structure, forming a doped semiconductor layer covering the semiconductor layer, forming a first dielectric layer covering the doped semiconductor layer, forming a node metal layer over the first dielectric layer, forming a second dielectric layer covering the node metal layer, filling a remaining portion of each trench opening with a metal layer to form an inner node in each of the trench openings, the metal layer including a plate coupling each of the inner nodes, and forming a node connection structure to conductively connect the node metal layer in the first trench opening with the node metal layer in the second trench opening. | 03-27-2014 |
20140084412 | SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE STRUCTURES - A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure. | 03-27-2014 |
20140091425 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In a semiconductor integrated circuit device including fuse elements for performing laser trimming processing, a dummy fuse formed of a first polycrystalline Si film is formed between the fuse elements formed of a second polycrystalline Si film, and a nitride film is formed on the dummy fuse. In this manner, the step difference of an interlayer film caused by the presence and absence of the fuse element formed of the polycrystalline Si film is eliminated, to thereby prevent SOG films having moisture-absorption characteristics on an inner surface of a fuse opening region and on an internal element side from connecting to each other. | 04-03-2014 |
20140103483 | SEMICONDUCTOR DEVICE - A semiconductor device comprises a semiconductor substrate; an element-forming region that includes semiconductor elements formed on the semiconductor substrate; a buried electrode plug formed so as to penetrate through the semiconductor substrate; and a trench-type electrode that is buried in a trench within the semiconductor substrate positioned between the element-forming region and the buried electrode plug. | 04-17-2014 |
20140110817 | SUB-LITHOGRAPHIC SEMICONDUCTOR STRUCTURES WITH NON-CONSTANT PITCH - Fin structures and methods of manufacturing fin structures using a dual-material sidewall image transfer mask to enable patterning of sub-lithographic features is disclosed. The method of forming a plurality of fins includes forming a first set of fins having a first pitch. The method further includes forming an adjacent fin to the first set of fins. The adjacent fin and a nearest fin of the first set of fins have a second pitch larger than the first pitch. The first set of fins and the adjacent fin are sub-lithographic features formed using a sidewall image transfer process. | 04-24-2014 |
20140117490 | SEMICONDUCTOR DEVICE INCLUDING ESD PROTECTION DEVICE - A semiconductor device includes a semiconductor-on-insulator (SOI) substrate having a bulk substrate layer, an active semiconductor layer and a buried insulator layer disposed between the bulk substrate layer and the active semiconductor layer. A trench is formed through the SOI substrate to expose the bulk substrate layer. A doped well is formed in an upper region of the bulk substrate layer adjacent trench. The semiconductor device further includes a first doped region different from the doped well that is formed in the trench. | 05-01-2014 |
20140117491 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD - Various embodiments provide semiconductor structures and fabrication methods. In an exemplary method, a semiconductor substrate can contain a shallow trench isolation (STI) structure that includes a fuse region. A protective layer can be provided on the high-K dielectric layer, which is provided on the semiconductor substrate. A portion of each of the protective layer and the high-K dielectric layer can be removed from the fuse region to expose the STI structure. A fuse layer can be formed on the exposed surface of the STI structure. A portion of the fuse layer, the remaining portion of the protective layer, and a remaining portion of the high-K dielectric layer outside of the fuse region can be removed from the semiconductor substrate to form a fuse structure. | 05-01-2014 |
20140131831 | INTEGRATED CIRUIT INCLUDING AN FIN-BASED DIODE AND METHODS OF ITS FABRICATION - A method is provided for forming an integrated circuit having a diode. The method includes forming at least one fin in a shallow trench isolation (STI) oxide layer disposed above a substrate layer. The at least one fin extends from a bottom end adjacent the substrate layer to a top end. The method further includes adding a cathode implant in a first region of the at least one fin and the substrate layer and adding an anode implant in a second region of the at least one fin and the substrate layer such that a junction is formed in the substrate layer below the at least one fin. The method also includes etching away a portion of the STI oxide layer to expose the top end of the at least one fin. | 05-15-2014 |
20140131832 | METHOD FOR MANUFACTURING SEMICONDUCTOR LAYOUT PATTERN, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes providing a substrate having a mask layer formed thereon, providing a first photomask having a first layout pattern and a second photomask having a second layout pattern, the first layout pattern including a plurality of active area portions and at least a neck portion connecting two adjacent active area portions, transferring the first layout pattern from the first photomask to the mask layer to form a plurality of active area patterns and at least a neck pattern connecting two adjacent active area patterns in the mask layer, and transferring the second layout pattern from the second photomask to the mask layer to remove the neck pattern to form a patterned mask. The patterned mask includes the active area patterns. A slot is at least formed between the two adjacent active area patterns. | 05-15-2014 |
20140145295 | DOUBLE DENSITY SEMICONDUCTOR FINS AND METHOD OF FABRICATION - Methods and structures having increased fin density are disclosed. Structures with two sets of fins are provided. A lower set of fins is interleaved with an upper set of fins in a staggered manner, such that the lower set of fins and upper set of fins are horizontally and vertically non-overlapping. | 05-29-2014 |
20140145296 | Semiconductor Device with an Edge Termination Structure Having a Closed Vertical Trench - A semiconductor device includes a semiconductor die having an outer edge and an active area defining a main horizontal surface and being spaced apart from the outer edge. The semiconductor device further includes an edge termination structure having a closed vertical trench surrounding the active area. The edge termination structure further includes at least one vertical trench arranged, in a horizontal cross-section, between the closed vertical trench and the active area. The at least one vertical trench includes an insulated side wall forming an acute angle with the outer edge. | 05-29-2014 |
20140151843 | SEMICONDUCTOR DEVICE STRUCTURES INCLUDING METAL OXIDE STRUCTURES, AND RELATED METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES - Methods of forming metal oxide structures and methods of forming metal oxide patterns on a substrate using a block copolymer system formulated for self-assembly. A block copolymer at least within a trench in the substrate and including at least one soluble block and at least one insoluble block may be annealed to form a self-assembled pattern including a plurality of repeating units of the at least one soluble block laterally aligned with the trench and positioned within a matrix of the at least one insoluble block. The self-assembled pattern may be exposed to a metal oxide precursor that impregnates the at least one soluble block. The metal oxide precursor may be oxidized to form a metal oxide. The self-assembled pattern may be removed to form a pattern of metal oxide lines on the substrate surface. Semiconductor device structures are also described. | 06-05-2014 |
20140167208 | CHEMICAL MECHANICAL PLANARIZATION PROCESS AND STRUCTURES - A semiconductor device includes a substrate having a first and second region, a first structure and a second structure. The first structure is formed over the substrate in the first region. The first structure has a first height. The second structure is formed over the substrate in the second region. The second structure has a second height different from the first height. | 06-19-2014 |
20140167209 | Method of Manufacturing a Semiconductor Device and a Semiconductor Workpiece - A semiconductor device is manufactured in a semiconductor substrate comprising a first main surface, the semiconductor substrate including chip areas. The method of manufacturing the semiconductor substrate comprises forming components of the semiconductor device in the first main surface in the chip areas, removing substrate material from a second main surface of the semiconductor substrate, the second main surface being opposite to the first main surface, forming a separation trench into a first main surface of the semiconductor substrate, the separation trench being disposed between adjacent chip areas. The method further comprises forming at least one sacrificial material in the separation trench, and removing the at least one sacrificial material from the trench. | 06-19-2014 |
20140167210 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD - Various embodiments provide a semiconductor structure and fabrication method. An exemplary semiconductor structure can include a semiconductor substrate having an isolation trench formed in the semiconductor substrate. A first barrier layer can be disposed on a bottom surface and a sidewall of the isolation trench. A light absorption layer can be disposed at least on a surface portion of the first barrier layer over the bottom surface of the isolation trench. A second barrier layer can fill the isolation trench to form an isolation structure in the semiconductor substrate. The isolation structure can have a top surface flushed with or over a top surface of the semiconductor substrate. | 06-19-2014 |
20140167211 | METHOD FOR AMNUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a silicon nitride film having an opening portion on a semiconductor substrate, forming a silicon oxide film on the silicon nitride film and on a side face of the opening portion, performing an etching treatment to the silicon oxide film so that a sidewall is formed on the side face of the opening portion, forming a trench on the semiconductor substrate with use of the sidewall and the silicon nitride film as a mask, and forming an insulating layer in the trench. The step of forming the silicon oxide film includes oxidizing the silicon nitride film with a plasma oxidation method or a radical oxidation method. | 06-19-2014 |
20140175596 | SEMICONDUCTOR SUBSTRATE FOR PHOTONIC AND ELECTRONIC STRUCTURES AND METHOD OF MANUFACTURE - A method of forming a substrate with isolation areas suitable for integration of electronic and photonic devices is provided. A common reticle and photolithographic technique is used to fabricate a mask defining openings for etching first and second trench isolation areas in a substrate, with the openings for the second trench isolation areas being wider than the openings for the first trench isolation areas. The first and second trench isolation areas are etched in the substrate through the mask. The second trench isolation areas are further etched to the deeper than the first trench isolation areas. The trench isolation areas are filled with oxide material. Electrical devices can be formed on the substrate and electrically isolated by the first trench isolation areas and photonic devices can be formed over the second trench isolation areas and be optically isolated from the substrate. | 06-26-2014 |
20140175597 | TRENCH WITH REDUCED SILICON LOSS - An isolation trench in a substrate of a semiconductor device includes a first shallow portion, a transition region, and a second deeper portion. The isolation trench contains a dielectric filler. The isolation trench is formed by first forming a first shallow portion of the isolation trench, forming polysilicon sidewalls on the first shallow portion, and then etching the second deeper portion. | 06-26-2014 |
20140191358 | Two-Portion Shallow-Trench Isolation - A shallow trench isolation (STI) and method of forming the same is provided. The STI structure comprises an upper insulating portion and a lower insulating portion, wherein the lower insulating portion includes a first insulator and an insulating layer surrounding the first insulator, the upper insulating portion includes a second insulator and a buffer layer surrounding the second insulator. A part of the buffer layer interfaces between the first insulator and the second insulator, and the outer sidewall of the buffer layer and the sidewall of the first insulator are leveled. | 07-10-2014 |
20140197516 | INTEGRATION OF 3D STACKED IC DEVICE WITH PERIPHERAL CIRCUITS - An integrated circuit device includes a substrate including a first region and a second region. A pit is formed in the first region. A stack of active layers alternating with insulating layers is deposited in the pit. The stack includes a particular insulating layer. The particular insulating layer has a first thickness, where a sum of the first thickness, thickness of active layers, and thicknesses of other insulating layers is essentially equal to a depth of the pit. The first thickness is different than the thicknesses of the other insulating layers by an amount within a range of process variations for the depth of the pit, for the thicknesses of the active layers, and for the thicknesses of other insulating layers. The device includes a planarized surface over the first and second regions, where an uppermost one of the active layers has a top surface below the planarized surface. | 07-17-2014 |
20140210038 | SOI RF DEVICE AND METHOD FOR FORMING THE SAME - A SOI RF device and a method for forming the same are provided. A trench exposed a part of the high resistivity silicon base is formed in the SOI substrate; a non-doped polysilicon layer is disposed on the high resistivity silicon base which is exposed by the trench; and at least a part of the non-doped polysilicon layer is covered by an above metal layer. With effects of the metal layer which is applied with a RF signal or a superposed signal, and fixed charges in the BOX layer, an inversion layer may be formed at a surface of the non-doped polysilicon layer. Since carriers may easily recombine at the grain boundaries of polysilicon, eddy current generated on a surface of the high resistivity silicon base is reduced, loss of the RF signal is reduced, and linearity of the RF signal device is improved. | 07-31-2014 |
20140217544 | METHODS OF FORMING A TRANSISTOR DEVICE ON A BULK SUBSTRATE AND THE RESULTING DEVICE - One illustrative method disclosed herein includes forming a trench within an isolated region of a bulk semiconductor substrate, forming a region of an insulating material in the trench and forming a semiconductor material within the trench and above the upper surface of the region of insulating material. A substrate disclosed herein includes an isolated substrate region in a bulk semiconductor substrate, a region of an insulating material that is positioned within a trench defined in the isolated substrate region and a semiconductor material positioned within the trench and above the upper surface of the region of insulating material. | 08-07-2014 |
20140246751 | Integrated Circuit Using Deep Trench Through Silicon (DTS) - An embodiment radio frequency area of an integrated circuit includes a substrate having a first resistance, the substrate including an implant region, a buried oxide layer disposed over the substrate, an interface layer between the substrate and the buried oxide layer, the interface layer having a second resistance lower than the first resistance, a silicon layer disposed over the buried oxide layer, and an interlevel dielectric disposed in a deep trench, the deep trench extending through the silicon layer, the buried oxide layer, and the interface layer over the implant region. In an embodiment, the deep trench extends through a polysilicon layer disposed over the silicon layer. | 09-04-2014 |
20140246752 | SEGMENTED GUARD RING STRUCTURES WITH ELECTRICALLY INSULATED GAP STRUCTURES AND DESIGN STRUCTURES THEREOF - Disclosed are guard ring structures with an electrically insulated gap in a substrate to reduce or eliminate device coupling of integrated circuit chips, methods of manufacture and design structures. The method includes forming a guard ring structure comprising a plurality of metal layers within dielectric layers. The method further includes forming diffusion regions to electrically insulate a gap in a substrate formed by segmented portions of the guard ring structure. | 09-04-2014 |
20140252533 | INSULATING STRUCTURE, A METHOD OF FORMING AN INSULATING STRUCTURE, AND A CHIP SCALE ISOLATOR INCLUDING SUCH AN INSULATING STRUCTURE - A method of forming an insulating structure, comprising forming an insulating region comprising at least one electrical or electronic component or part thereof embedded within the insulating region, and forming a surface structure in a surface of the insulating region. | 09-11-2014 |
20140252534 | METHOD OF MAKING DEEP TRENCH, AND DEVICES FORMED BY THE METHOD - A method for forming a semiconductor device includes providing a semiconductor-on-insulator (SOI) structure, and forming at least one hard mask (HM) layer over the SOI structure. The SOI structure includes an insulator layer and a semiconductor layer over the insulator layer. The method further comprises forming a trench inside the at least one HM layer and the semiconductor layer, and depositing a spacer layer in the trench. The spacer layer comprises a bottom surface portion over the bottom surface of the trench, and a side wall portion along the side wall of the trench. The method further comprises etching the bottom surface portion of the spacer layer while the side wall portion of the spacer layer remains, and etching the insulator layer to extend the trench into the insulator layer. | 09-11-2014 |
20140252535 | Integrated Passive Device Having Improved Linearity and Isolation - Disclosed is a structure for improved electrical signal isolation in a semiconductor substrate between integrated passive devices (IPDs) and an associated method for the structure's fabrication. The structure includes an amorphized region in the semiconductor substrate, a dielectric layer formed over the amorphized region, and IPDs formed over the dielectric layer. The amorphized region is not recrystallized and may be formed by utilizing an inert implant that does not charge-dope the amorphized region, while forming a plurality of charge carrier traps at an interface between the amorphized region and the dielectric layer to prevent a parasitic conduction layer from forming at the interface. The inert implant may include one of Argon, Xenon and Germanium. In many implementations, the structure does not include an active device. | 09-11-2014 |
20140264719 | Varied STI Liners for Isolation Structures in Image Sensing Devices - An integrated circuit device incorporating a plurality of isolation trench structures configured for disparate applications and a method of forming the integrated circuit are disclosed. In an exemplary embodiment, a substrate having a first region and a second region is received. A first isolation trench is formed in the first region, and a second isolation trench is formed in the second region. A first liner layer is formed in the first isolation trench, and a second liner layer is formed in the second isolation trench. The second liner layer has a physical characteristic that is different from a corresponding physical characteristic of the first liner layer. An implantation procedure is performed on the second isolation trench and the second liner layer formed therein. The physical characteristic of the second liner layer may be selected to enhance an implantation depth or an implantation uniformity compared to the first liner layer. | 09-18-2014 |
20140264720 | Method and Structure for Nitrogen-Doped Shallow-Trench Isolation Dielectric - An isolation feature with a nitrogen-doped fill dielectric and a method of forming the isolation feature are disclosed. In an exemplary embodiment, the method of forming the isolation feature comprises receiving a substrate having a top surface. A recess is etched in the substrate, the recess extending from the top surface into the substrate. A dielectric is deposited within the recess such that the depositing of the dielectric includes introducing nitrogen during a chemical vapor deposition process. Accordingly, the deposited dielectric includes a nitrogen-doped dielectric. The deposited dielectric may include a nitrogen-doped silicon oxide. In some embodiments, the depositing of the dielectric disposes the nitrogen-doped dielectric in contact with a surface of the recess. In further embodiments, a liner material is deposited within the recess prior to the depositing of the dielectric within the recess. | 09-18-2014 |
20140264721 | ISOLATION STRUCTURE IN A SEMICONDUCTOR DEVICE PROCESSES AND STRUCTURES - Substantially planar or even layers in semiconductor trenches allow for even distribution of subsequent layers in semiconductor processing and reduce divots in semiconductor device layers. A semiconductor device may include an isolation structure formed in a trench. The isolation structure may have a cover oxide layer and a base oxide layer holding the cover oxide layer. The top surface of the isolation structure is substantially planar. An oxidation process may substantially eliminate nitrogen from a top portion of the isolation structure, resulting in a balanced etch rate in the top portion and a substantially even isolation structure top surface. | 09-18-2014 |
20140264722 | SEMICONDUCTOR DEVICE - A semiconductor chip includes a first circuit and a second circuit having different reference potentials. A first potential which is a reference potential of the first circuit is applied to the semiconductor chip through any of plural lead terminals, and a second potential which is a reference potential of the second circuit is applied to the semiconductor chip through any of plural lead terminals. A substrate of the semiconductor chip has a structure in which a buried insulating layer and a semiconductor layer of a first conductivity type are laminated on a semiconductor substrate such as a SOI substrate. A fixed potential is applied to the semiconductor substrate through a die pad and a lead terminal for a substrate potential. The fixed potential is applied to the semiconductor chip through a different route from the reference potential of the first circuit and the reference potential of the second circuit. | 09-18-2014 |
20140284759 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An aspect of the present embodiment, there is provided a method of manufacturing a semiconductor device, the method includes providing trenches in an end terminal area of a substrate, the end terminal area surrounding an element area of the a substrate, the trenches surrounding the element area, filling a fluent material mixed with carbonate, oxide and solvent in the each of the trenches, burning the fluent material in the trench to embed an insulator in the trench, and providing an element unit in the element area. | 09-25-2014 |
20140291799 | SEMICONDUCTOR DEVICE INCLUDING STI STRUCTURE AND FABRICATION METHOD - Semiconductor devices including STI structures and their fabrication methods are provided. A mask layer is provided on a semiconductor substrate and patterned to form an opening in the mask layer to expose a surface portion of the semiconductor substrate. A trench is then formed in the semiconductor substrate by etching along the opening. A first dielectric layer is formed in the trench and has a top surface lower than a top surface of the semiconductor substrate to provide an uncovered sidewall surface of the trench in the semiconductor substrate. An epitaxial layer is formed on the uncovered sidewall surface of the trench in the semiconductor substrate. The epitaxial layer includes a spacing to expose a surface portion of the first dielectric layer. A second dielectric layer is formed on the exposed surface portion of the first dielectric layer to fill the spacing formed in the epitaxial layer. | 10-02-2014 |
20140306317 | FINFET FIN HEIGHT CONTROL - Fin height control techniques for FINFET fabrication are disclosed. The technique includes a method for controlling the height of plurality of fin structures to achieve uniform height thereof relative to a top surface of isolation material located between fin structures on a semiconductor substrate. The isolation material located between fin structures may be selectively removed after treatment to increase its mechanical strength such as by, for example, annealing and curing. A sacrificial material may be deposited over the isolation material between the fin structures in a substantially uniform thickness. The top portion of the fin structures may be selectively removed to achieve a uniform planar surface over the fin structures and sacrificial material. The sacrificial material may then be selectively removed to achieve a uniform fin height relative to the isolation material. | 10-16-2014 |
20140306318 | TRENCH FORMATION METHOD AND A SEMICONDUCTOR STRUCTURE THEREOF - In one embodiment, a method of making a trench for a semiconductor device can include: (i) providing a semiconductor substrate; (ii) forming a patterned hard mask layer with an opening on the semiconductor substrate, where a thickness of the patterned hard mask layer is from about 100 nm to about 400 nm; and (iii) using the patterned hard mask layer as a mask, and etching the semiconductor substrate to form the trench in the semiconductor substrate. | 10-16-2014 |
20140312455 | PATTERNS OF A SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device including a plurality of active patterns, a plurality of first isolation layer patterns and a plurality of second isolation layer patterns may be provided. In particular, the active patterns may be arranged both in a first direction and in a second direction, and may protrude from a substrate and have a length in the first direction. The first isolation layer patterns may fill a first space, the first space provided between the active patterns and arranged in the first direction, and support two opposing sidewalls of neighboring active patterns. The second isolation layer patterns may fill a second space between the active patterns and the first isolation layer patterns. Accordingly, the active patterns of the semiconductor device may not collapse or incline because the first isolation layer patterns support the active patterns. | 10-23-2014 |
20140332920 | SHALLOW TRENCH ISOLATION - A shallow trench isolation (STI) and method of forming the same is provided. The STI structure includes an upper insulating portion and a lower insulating portion, where the lower insulating portion includes a first insulator and an insulating layer surrounding the first insulator, the upper insulating portion includes a second insulator and a buffer layer surrounding the second insulator. Apart of the buffer layer interfaces between the first insulator and the second insulator, and the outer sidewall of the buffer layer and the sidewall of the first insulator are leveled. | 11-13-2014 |
20140332921 | SEMICONDUCTOR DEVICES HAVING A TRENCH ISOLATION LAYER AND METHODS OF FABRICATING THE SAME - Semiconductor devices including a trench isolation layer are provided. The semiconductor device includes a substrate having a trench therein, a liner insulation layer that covers a bottom surface and sidewalls of the trench and includes micro trenches located at bottom inner corners of the liner insulation layer, a first isolating insulation layer filling the micro trenches and a lower region of the trench that are surrounded by the liner insulation layer, and a second isolating insulation layer filling the trench on the first isolating insulation layer. The liner insulation layer on sidewalls of an upper region of the trench having a thickness that gradually increases toward a bottom surface of the trench, and the liner insulation layer on sidewalls of the lower region of the trench having a thickness that is uniform. Related methods are also provided. | 11-13-2014 |
20140353795 | INTEGRATED CIRCUITS INCLUDING FINFET DEVICES WITH SHALLOW TRENCH ISOLATION THAT INCLUDES A THERMAL OXIDE LAYER AND METHODS FOR MAKING THE SAME - Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes etching an enhanced high-aspect-ratio process (eHARP) oxide fill that is disposed in an STI trench between two adjacent fins to form a recessed eHARP oxide fill. The two adjacent fins extend from a bulk semiconductor substrate. A silicon layer is formed overlying the recessed eHARP oxide fill. The silicon layer is converted to a thermal oxide layer to further fill the STI trench with oxide material. | 12-04-2014 |
20140361399 | STRIPE STRUCTURES AND FABRICATION METHOD THEREOF - A method is provided for fabricating stripe structures. The method includes providing a substrate; and forming a to-be-etched layer on the substrate. The method also includes forming a hard mask pattern having a first stripe on the to-be-etched layer; and forming a photoresist pattern having a stripe opening on the to-be-etched layer and the hard mask pattern having the first stripe. Further, the method includes forming a polymer layer on a top surface and side surfaces of the photoresist pattern to reduce a width of the stripe opening; forming hard mask patterns having a second stripe by etching the hard mask pattern having the first stripe using the photoresist pattern having the polymer layer as an etching mask; and forming the stripe structures by etching the to-be-etching layer using the hard mask pattern having the second stripe as an etching mask until the substrate is exposed. | 12-11-2014 |
20150008556 | ISOLATION TRENCH THROUGH BACKSIDE OF SUBSTRATE - Among other things, one or more semiconductor arrangements comprising isolation trenches, and techniques for forming such isolation trenches are provided. A substrate comprises a front side surface and a backside surface. One or more devices are formed over the front side surface. A wet etch is performed to form a tapered portion of an isolation trench. A dry etch is performed to form a non-tapered portion of the isolation trench. Because both the wet etch and the dry etch are performed, etching time is reduced compared to merely using the dry etch due to the wet etch having a relatively faster etch rate than the dry etch. In an embodiment, the isolation trench provides isolation for a current leakage path associated with a device or other material formed over the front side surface. In an embodiment, metal is formed within the isolation trench for backside metallization. | 01-08-2015 |
20150008557 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a buried insulating film formed on the substrate, an SOI layer formed on the buried insulating film, an insulating film formed to extend from a top surface of the SOI layer to the buried insulating film and to divide the SOI layer into a first SOI layer and a second SOI layer isolated from the first SOI layer, an element formed in the first SOI layer, and an electrode having at one end thereof a pad located directly above the second SOI layer, the other end of the electrode being connected to the first SOI layer. A cavity region is formed between the buried insulating film and the substrate directly below the first SOI layer. The portion of the buried insulating film directly below the second SOI layer is at least partially in direct contact with the substrate. | 01-08-2015 |
20150014807 | METHOD OF FORMING A SHALLOW TRENCH ISOLATION STRUCTURE - Embodiments of the disclosure include a shallow trench isolation (STI) structure and a method of forming the same. A trench is formed in a substrate. A silicon oxide and a silicon liner layer are formed on sidewalls and a bottom surface of the trench. A flowable silicon oxide material fills in the trench, is cured, and then is partially removed. Another silicon oxide is deposited in the trench to fill the trench. The STI structure in a fabricated device includes a bottom portion having silicon oxide and a top portion having additionally a silicon oxide liner and a silicon liner on the sidewalls. | 01-15-2015 |
20150014808 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A fabrication method for a semiconductor structure at least includes the following steps. First, a pattern mask with a predetermined layout pattern is formed on a substrate. The layout pattern is then transferred to the underneath substrate so as to form at least a fin-shaped structure in the substrate. Subsequently, a shallow trench isolation structure is formed around the fin-shaped structure. Afterwards, a steam oxidation process is carried out to oxidize the fin-shaped structure protruding from the shallow trench isolation and to form an oxide layer on its surface. Finally, the oxide layer is removed completely. | 01-15-2015 |
20150014809 | FIN DIODE STRUCTURE - A fin diode structure and method of manufacturing the same is provided in present invention, which the structure includes a substrate, a doped well formed in the substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well, and a doped region of first conductivity type formed globally in the substrate between the fins of first conductivity type, the fins of second conductivity type, the shallow trench isolation and the doped well and connecting with the fins of first doped type and the fins of second doped type. | 01-15-2015 |
20150021734 | SEMICONDUCTOR DEVICE, A MICRO-ELECTRO-MECHANICAL RESONATOR AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device includes a silicon substrate layer with a decoupling region. The decoupling region of the silicon substrate layer comprises an array of lamellas laterally spaced apart from each other by cavities. Each lamella of the array of lamellas comprises at least 20% silicon dioxide. | 01-22-2015 |
20150035113 | Epitaxial Structures and Methods of Forming the Same - An embodiment is a method. A first III-V compound semiconductor is epitaxially grown in a trench on a substrate, and the epitaxial growth is performed in a chamber. The first III-V compound semiconductor has a first surface comprising a facet. After the epitaxial growth, the first surface of the first III-V compound semiconductor is etched to form an altered surface of the first III-V compound semiconductor. Etching the first surface is performed in the chamber in situ. A second III-V compound semiconductor is epitaxially grown on the altered surface of the first III-V compound semiconductor. The epitaxial growth of the first III-V compound semiconductor may be performed in a MOCVD chamber, and the etch may use an HCl gas. Structures resulting from methods are also disclosed. | 02-05-2015 |
20150041947 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE, AND DISPLAY DEVICE - An objective of the present invention is to increase production efficiency of high-performance flexible semiconductor devices. A semiconductor device manufacturing method includes: a step of forming an insulating substrate ( | 02-12-2015 |
20150041948 | SEMICONDUCTOR DEVICE INCLUDING STI STRUCTURE AND METHOD FOR FORMING THE SAME - Semiconductor devices and fabrication methods are disclosed. A mask layer having an opening is formed on a semiconductor substrate. The semiconductor substrate is etched along the opening of the mask layer to form a trench therein. The mask layer is laterally etched from the opening of the mask layer along a top surface of the semiconductor substrate to expose a surface portion of the semiconductor substrate on each side of the opening. A liner oxide layer is formed by a thermal oxidation process on interior surface of the trench and on the exposed surface portion of the semiconductor substrate. The thermal oxidation process is controlled such that an upper corner between the top surface of the semiconductor substrate and the trench is rounded after the liner oxide layer is formed. An insulation layer is formed on the liner oxide layer and fills the trench. | 02-12-2015 |
20150048475 | Semiconductor Structures With Shallow Trench Isolations - A method is disclosed that includes the operations outlined below. An insulating material is disposed within a plurality of trenches on a semiconductor substrate and over the semiconductor substrate. The first layer is formed over the insulating material. The first layer and the insulating material are removed. | 02-19-2015 |
20150048476 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE - Semiconductor devices with reduced substrate defects and methods of manufacture are disclosed. The method includes forming a dielectric material on a substrate. The method further includes forming a shallow trench structure and deep trench structure within the dielectric material. The method further includes forming a material within the shallow trench structure and deep trench structure. The method further includes forming active areas of the material separated by shallow trench isolation structures. The shallow trench isolation structures are formed by: removing the material from within the deep trench structure and portions of the shallow trench structure to form trenches; and depositing an insulator material within the trenches. | 02-19-2015 |
20150054120 | Multiple-Threshold Voltage Devices and Method of Forming Same - A method comprises growing a channel layer over a substrate, wherein the channel layer comprises a first channel region and a second channel region, and wherein the first channel region and the second channel region are separated by a first isolation region, depositing a hard mask layer over the channel layer, patterning the hard mask layer, applying a first delta doping process to the first channel region to form a first delta doping layer over the first channel region, applying a second delta doping process to the second channel region to form a second delta doping layer over the second channel region, wherein the second delta doping layer is of a different doping density from the first delta doping layer and applying a diffusion process to the first delta doping layer and the second delta doping layer. | 02-26-2015 |
20150054121 | FINFET FORMED OVER DIELECTRIC - A method for semiconductor fabrication includes patterning one or more mandrels over a semiconductor substrate, the one or more mandrels having dielectric material formed therebetween. A semiconductor layer is formed over exposed portions of the one or more mandrels. A thermal oxidation is performed to diffuse elements from the semiconductor layer into an upper portion of the one or more mandrels and concurrently oxidize a lower portion of the one or more mandrels to form the one or more mandrels on the dielectric material. | 02-26-2015 |
20150061069 | INTEGRATING A CAPACITOR IN AN INTEGRATED CIRCUIT - In one aspect, an integrated circuit (IC) includes an isolation trench dividing the IC into a first section and a second section, an active electronic device disposed in the first section of the IC and a capacitor disposed in the second section of the IC and electrically isolated from the active electronic device. | 03-05-2015 |
20150061070 | SEMICONDUCTOR DEVICE - A first isolation trench insulates and separates a low-voltage region, a high-voltage region, and a connection region of the semiconductor layer from each other. A low-potential signal processing circuit is in the low-voltage region, and operates at a lower potential. A high-potential signal processing circuit is in the high-voltage region, and operates at a higher potential. A capacitor is on the connection region and transmits the second alternating current signal from the low-potential signal processing circuit to the high-potential signal processing circuit. The capacitor includes a low-potential electrode connected to the low-potential signal processing circuit, and a high-potential electrode connected to the high-potential signal processing circuit. First wiring layers of the low-potential electrode and second wiring layers of the high-potential electrode are capacitively coupled. Side wall surfaces of the first wiring layers and those of the second wiring layers are opposed to each other. | 03-05-2015 |
20150069569 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes: a first semiconductor region extending in a first direction; second semiconductor regions extending in a second direction crossing the first direction from the first semiconductor region and arranged in the first direction; and a first element isolation region provided between the second semiconductor regions. A width of the first semiconductor region in the second direction is wider than a width of the second semiconductor region in the first direction. | 03-12-2015 |
20150076653 | OVERLAY PERFORMANCE FOR A FIN FIELD EFFECT TRANSISTOR DEVICE - Approaches for improving overlay performance for an integrated circuit (IC) device are provided. Specifically, the IC device (e.g., a fin field effect transistor (FinFET)) is provided with an oxide layer and a pad layer formed over a substrate, wherein the oxide layer comprises an alignment and overlay mark, an oxide deposited in a set of openings formed through the pad layer and into the substrate, a mandrel layer deposited over the oxide material and the pad layer, and a set of fins patterned in the IC device without etching the alignment and overlay mark. With this approach, the alignment and overlay mark is provided with the fin cut (FC) layer and, therefore, avoids finification. | 03-19-2015 |
20150076654 | ENLARGED FIN TIP PROFILE FOR FINS OF A FIELD EFFECT TRANSISTOR (FINFET) DEVICE - Approaches for providing enlarged fin tips for a set of fins of a fin field effect transistor device (FinFET) are disclosed. Specifically, approaches are provided for patterning a hardmask formed over a substrate; forming a set of fin tips from the substrate using a first etch; and forming a set of fins from the substrate using a second etch, wherein each of the set of fin tips has a width greater than a most narrow section of each of the set of fins. Each of the fin tips has a tapered profile that enlarges towards a top end thereof to compensate for erosion losses during processing. | 03-19-2015 |
20150084155 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method for fabricating a semiconductor device includes defining a curved active region by forming a plurality of trenches over a semiconductor substrate, forming an insulating layer to fill the plurality of trenches, and forming a pair of gate lines crossing the curved active region, so that it is possible to prevent leaning of an active region by forming a curved active region. | 03-26-2015 |
20150091127 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to an example embodiment, a semiconductor device includes a substrate having a cell array region and a peripheral circuit region. The substrate includes first active regions defined by a first trench isolation region in the cell array region, a second active region defined by a second trench isolation region in the peripheral circuit region, and at least one deep trench isolation region. The first active regions may be aligned to extend longitudinally in a first direction in the cell array region. The at least one deep trench isolation region is recessed in the substrate to a level lower than those of other points of a bottom surface of the second trench isolation region in the peripheral circuit region. The at least one deep trench isolation region includes at least one point that is spaced apart in the first direction from a corresponding one of the first active regions. | 04-02-2015 |
20150091128 | FORMING THREE DIMENSIONAL ISOLATION STRUCTURES - A three dimensional shallow trench isolation structure including sets of parallel trenches extending in two perpendicular directions may be formed by depositing a conformal deposition in a first set of parallel trenches, oxidizing the second set of trenches to enable selective deposition in said second set of trenches and then conformally depositing in said second set of trenches. In some embodiments, only one wet anneal, one etch back, and one high density plasma chemical vapor deposition step may be used to fill both sets of trenches. | 04-02-2015 |
20150097263 | METHOD AND APPARATUS FOR HIGH YIELD CONTACT INTEGRATION SCHEME - A methodology for forming contact areas by a multiple patterning process that provides increased yield and lower risk of contact-to-contact short at points of tight tip-to-tip spacing and the resulting device are disclosed. Embodiments include forming one or more trench patterning layers on a planarized surface of a wafer, forming one or more trenches in the one or more trench patterning layers, forming a block mask at one or more points along the one or more trenches, extending the one or more trenches down to a substrate level of the wafer, and removing the block mask from the one or more points. | 04-09-2015 |
20150097264 | DIODE STRING IMPLEMENTATION FOR ELECTROSTATIC DISCHARGE PROTECTION - A diode string having a plurality of diodes for ESD protection of a CMOS IC device comprises a first diode and a last diode in the diode string, wherein the first diode and the last diode are both formed on a bottom layer in a silicon substrate, and remaining diodes in the diode string. The remaining diodes are formed on a top layer placed on top of the bottom layer. The diode string further comprises a plurality of conductive lines that connect the first diode and the last diode on the bottom layer sequentially with the remaining diodes on the top layer to form a three dimensional ( | 04-09-2015 |
20150102453 | Fabricating Shallow-Trench Isolation Semiconductor Devices To Reduce Or Eliminate Oxygen Diffusion - A method is disclosed for forming a semiconductor device. A first opening is formed for an STI on a semiconductor substrate and a first process is performed to deposit first oxide into the first opening. A second opening is formed to remove a portion of the first oxide from the first opening and second process(es) is/are performed to deposit second oxide into the second opening and over a remaining portion of the first oxide. A portion of the semiconductor device is formed over a portion of a surface of the second oxide. A semiconductor device includes an STI including a first oxide formed in a lower portion of a trench of the STI and a second oxide formed in an upper portion of the trench and above the first oxide. The semiconductor device includes a portion of the semiconductor device formed over a portion of the second oxide. | 04-16-2015 |
20150102454 | FORMING FINS OF DIFFERENT MATERIALS ON THE SAME SUBSTRATE - A semiconductor substrate may be formed by providing an providing a semiconductor-on-insulator (SOI) substrate including a base semiconductor layer, a buried insulator layer above the base semiconductor layer, and a SOI layer comprising a first semiconductor material above the buried insulator layer; forming an isolation region in the SOI layer isolating a first portion of the SOI layer from a second portion of the SOI layer; removing the second portion of the SOI layer to expose a portion of the buried insulator layer; forming a hole in the exposed portion of the buried insulator layer to expose a portion of the base semiconductor layer; and forming a semiconductor layer made of a second semiconductor material on the exposed portion of the base semiconductor layer, so that the replacement semiconductor layer covers the exposed region of the buried insulator layer. | 04-16-2015 |
20150108601 | SEMICONDUCTOR DEVICE INCLUDING A WALL OXIDE FILM AND METHOD FOR FORMING THE SAME - A semiconductor device includes an oxide film structure having different thicknesses depending on where the oxide film structure is formed. In the semiconductor device, a wall oxide film is formed to have different thicknesses depending on locations of sidewalls of an active region. The semiconductor device includes an active region, a first wall oxide film disposed over a first sidewall of the active region that extends along a first direction of the active region, the first wall oxide film having a first thickness, and a second wall oxide film disposed over a second sidewall of the active region that extends along a second direction of the active region, a second wall oxide film having a second thickness that is different from the first thickness. | 04-23-2015 |
20150115395 | OXIDE DEFINITION (OD) GRADIENT REDUCED SEMICONDUCTOR DEVICE AND METHOD OF MAKING - A method of reducing an oxide definition (OD) density gradient in an integrated circuit (IC) semiconductor device having a placed layout and a set of design rule checking (DRC) rules associated with the placed layout. The method includes computing OD density in insertion regions from OD density information corresponding to the placed layout to identify an OD density gradient. The method further includes selecting and adding dummy cells to at least one insertion region to reduce the OD density gradient. | 04-30-2015 |
20150115396 | Insulation Structure Formed in a Semiconductor Substrate and Method for Forming an Insulation Structure - A method for forming an insulation structure in a semiconductor body includes forming a trench extending from a first surface into a semiconductor body, the trench having a first width in a horizontal direction of the semiconductor body, and forming a void spaced apart from the first surface in a vertical direction of the semiconductor body, the void having a second width in a horizontal direction that is greater than the first width, wherein the trench and the void are arranged adjacent to each other in a vertical direction. | 04-30-2015 |
20150123239 | SHALLOW TRENCH ISOLATION AND FORMATION THEREOF - One or more methods of forming shallow trench isolation (STI) and resulting semiconductor arraignments are provided. A method of forming STI includes forming a nitride liner in a first opening and second opening and recessing the nitride liner in the first opening and second opening while forming an oxide structure in the first opening and second opening, thus forming a first STI region in the first opening and a second STI region in the second opening. A semiconductor arraignment includes a first STI region in an active area and a second STI region in an isolation area, where a first recessed nitride layer height in the first STI region is different than a second recessed nitride layer height in the second STI region. | 05-07-2015 |
20150123240 | Semiconductor Device and Method of Forming Shallow P-N Junction with Sealed Trench Termination - A semiconductor device has a substrate including a semiconductor material of a first conductivity type. A first layer including a semiconductor material of a second conductivity type is formed in the substrate with a boundary between the first layer and the semiconductor material of the first conductivity type as a p-n junction. A vertical trench is formed through the first layer by anisotropic etch and extends at least to the boundary. The vertical trench has a rounded or polygonal shape with a depth less than 40 micrometers. An insulating material is deposited in the vertical trench. An insulating layer is formed over a sidewall of the vertical trench. The shallow vertical trench filled with insulating material increases breakdown voltage and reduces manufacturing time and complexity. The semiconductor device can be a discrete diode, transistor, rectifier, transient voltage suppressor, silicon controlled rectifier, and triode. | 05-07-2015 |
20150123241 | SEMICONDUCTOR DEVICE - An integrated heat sink array is introduced in SOI power devices having multiple unit cells, which can be used to reduce the temperature rise in obtaining more uniform temperature peaks for all the unit cells across the device area, so that the hot spot which is prone to breakdown can be avoided, thus the safe operating area of the device can be improved. Also the array sacrifice less area of the device, therefore results in low Rdson. | 05-07-2015 |
20150130015 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND ANTENNA SWITCH MODULE - Disclosed is a semiconductor device having a radio frequency switch. Also disclosed are an antenna switch module and a method of manufacturing the semiconductor device. The semiconductor device includes a metal wiring insulating film bonded to a silicon substrate. In the semiconductor device, a crystal defect layer extends into the silicon substrate from a surface of the silicon substrate. Crystal defects are throughout the crystal defect layer. The semiconductor device and an integrated circuit are in the antenna switch module. The integrated circuit in the antenna switch module is mounted with the radio-frequency switch device and the silicon substrate. The method of manufacturing the semiconductor device includes a step of forming crystal defects throughout a silicon substrate. Radiation or a diffusion is used to form the crystal defects. After the step of forming the crystal defects, the method includes a step of implanting ions into a surface of the silicon substrate to form a crystal defect layer. | 05-14-2015 |
20150137308 | SELF-ALIGNED DUAL-HEIGHT ISOLATION FOR BULK FINFET - A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region. | 05-21-2015 |
20150137309 | Methods of Fabricating Isolation Regions of Semiconductor Devices and Structures Thereof - Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and at least one trench formed in the workpiece. The at least one trench includes sidewalls, a bottom surface, a lower portion, and an upper portion. A first liner is disposed over the sidewalls and the bottom surface of the at least one trench. A second liner is disposed over the first liner in the lower portion of the at least one trench. A first insulating material is disposed over the second liner in the lower portion of the at least one trench. A second insulating material is disposed over the first insulating material in the upper portion of the at least one trench. The first liner, the second liner, the first insulating material, and the second insulating material comprise an isolation region of the semiconductor device. | 05-21-2015 |
20150145099 | Formation Of Semiconductor Device With Resistors - A semiconductor device includes a semiconductor substrate, trench isolations, a sacrificial layer, a first resist protect oxide (RPO) layer, a second RPO layer and a silicide layer. The semiconductor substrate has first portions and second portions which are alternately disposed, and each of the second portions includes a first resist region with a first resistance, a second resist region with a second resistance and a silicide region. The second resistance is greater than the first resistance. The trench isolations are in the first portions. The sacrificial layer is on the first resist region. The first RPO layer is on the sacrificial layer. The first RPO layer together with the sacrificial layer have a first thickness. The second RPO layer is on the second resist region, in which the second RPO layer has a second thickness smaller than the first thickness. The silicide layer is on the silicide region. | 05-28-2015 |
20150294897 | STRUCTURES AND METHODS FOR FORMING FIN STRUCTURES - Structures and methods are provided for forming fin structures. A first fin structure is formed on a substrate. A shallow-trench-isolation structure is formed surrounding the first fin structure. At least part of the first fin structure is removed to form a cavity. A first material is formed on one or more side walls of the cavity. A second material is formed to fill the cavity, the second material being different from the first material. At least part of the STI structure is removed to form a second fin structure including the first material and the second material. At least part of the first material that surrounds the second material is removed to fabricate semiconductor devices. | 10-15-2015 |
20150294898 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - To provide a semiconductor device having improved performance. The semiconductor device has a first insulating film formed on the main surface of a semiconductor substrate and a second insulating film formed on the first insulating film. The semiconductor device further has a first opening portion penetrating through the second insulating film and reaching the first insulating film, a second opening portion penetrating through the first insulating film and reaching the semiconductor substrate, and a trench portion formed in the semiconductor substrate. A first opening width of the first opening portion and a second opening width of the second opening portion are greater than a trench width of the trench portion. The trench portion is closed by a third insulating film while leaving a space in the trench portion. | 10-15-2015 |
20150294902 | ISOLATED SEMICONDUCTOR LAYER IN BULK WAFER BY LOCALIZED SILICON EPITAXIAL SEED FORMATION - An integrated circuit may be formed by forming a buried isolation layer in an isolation recess in a single-crystal silicon-based substrate. Exposed lateral surfaces of the substrate at the buried isolation layer are covered with a dielectric sidewall. A seed trench is formed through the buried isolation layer to expose the substrate. A single-crystal silicon-based seed layer is formed through the seed trench, extending above the top surface of the buried isolation layer. A silicon-based non-crystalline layer is formed contacting the seed layer. A cap layer is formed over the non-crystalline layer. A radiant-induced recrystallization process converts the non-crystalline layer to a single-crystal layer aligned with the seed layer. The cap layer is removed and the single-crystal layer is planarized, leaving an isolated semiconductor layer over the buried isolation layer. | 10-15-2015 |
20150294972 | SEMICONDUCTOR DEVICE - The instant disclosure relates to a semiconductor device includes a semiconductor substrate, a plurality of buried bit lines, a plurality of insulating structures, and a plurality of self-aligned spacers. The semiconductor substrate has a plurality of active areas defined thereon. The buried bit lines are disposed in the semiconductor substrate, wherein two of the buried bit lines are positioned in each of the active areas. The insulating structures are disposed on the semiconductor substrate, wherein each of the insulating structures is positioned on and opposite to the two of the buried bit lines. The self-aligned spacers are disposed on the sidewalls of the insulating structures respectively to partially expose the surface of the semiconductor substrate. | 10-15-2015 |
20150294983 | ISOLATED SEMICONDUCTOR LAYER OVER BURIED ISOLATION LAYER - An integrated circuit may be formed by forming an isolation recess in a single-crystal silicon-based substrate. Sidewall insulators are formed on sidewalls of the isolation recess. Thermal oxide is formed at a bottom surface of the isolation recess to provide a buried isolation layer, which does not extend up the sidewall insulators. A single-crystal silicon-based semiconductor layer is formed over the buried isolation layer and planarized to be substantially coplanar with the substrate adjacent to the isolation recess, thus forming an isolated semiconductor layer over the buried isolation layer. The isolated semiconductor layer is laterally separated from the substrate. | 10-15-2015 |
20150295018 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device including a substrate having an isolation structure therein is disclosed. A capacitor is disposed on the isolation structure and includes a polysilicon electrode, an insulating layer disposed on the polysilicon electrode, and a metal electrode disposed on the insulating layer. A method for forming the semiconductor device is also disclosed. | 10-15-2015 |
20150303097 | COMPOSITE SUBSTRATE MANUFACTURING METHOD, AND COMPOSITE SUBSTRATE - Disclosed is a composite substrate manufacturing method whereby, after bonding a semiconductor substrate ( | 10-22-2015 |
20150303246 | SYSTEMS AND METHODS FOR FABRICATING A POLYCRYSTALINE SEMICONDUCTOR RESISTOR ON A SEMICONDUCTOR SUBSTRATE - In accordance with embodiments of the present disclosure, an integrated circuit may include at least one region of shallow-trench isolation field oxide, at least one region of dummy diffusion, and a polycrystalline semiconductor resistor. The at least one region of shallow-trench isolation field oxide may be formed on a semiconductor substrate. The at least one region of dummy diffusion may be formed adjacent to the at least one region of shallow-trench isolation field oxide on the semiconductor substrate. The polycrystalline semiconductor resistor may comprise at least one resistor arm formed with a polycrystalline semiconductor material, wherein the at least one resistor arm is formed over each of the at least one region of shallow-trench isolation field oxide and the at least one region of dummy diffusion. | 10-22-2015 |
20150303252 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate in which a multi-depth trench is formed, the multi-depth trench including a shallow trench and a deep trench arranged below the shallow trench, a first dielectric material formed in partial area of the multi-depth trench, the first dielectric material including a slope in the shallow trench that extends upward from a corner where a bottom plane of the shallow trench and a sidewall of the deep trench meets, the slope being inclined with respect to the bottom plane of the shallow trench, and a second dielectric material formed in areas of the multi-depth trench in which the first dielectric material is absent. | 10-22-2015 |
20150303253 | ISOLATION STRUCTURE, SEMICONDUCTOR DEVICE HAVING THE SAME, AND METHOD FOR FABRICATING THE ISOLATION STRUCTURE - An isolation structure of a semiconductor, a semiconductor device having the same, and a method for fabricating the isolation structure are provided. An isolation structure of a semiconductor device may include a trench formed in a substrate, an oxide layer formed on a bottom surface and an inner sidewall of the trench, a filler formed on the oxide layer to fill a part of inside of the trench, and a fourth oxide layer filling an upper portion of the filler of the trench to a height above an upper surface of the trench, an undercut structure being formed on a boundary area between the inner sidewall and the oxide layer. | 10-22-2015 |
20150303265 | SEMICONDUCTOR DEVICE WITH TRENCH ISOLATION - A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes an epitaxial layer and a dielectric material. The epitaxial layer is in a trench of the semiconductor and is peripherally enclosed thereby, in which the epitaxial layer is formed by performing etch and epitaxy processes. The etch and epitaxy process includes etching out a portion of a sidewall of the trench and a portion of a bottom surface of the trench and forming the epitaxial layer conformal to the remaining portion of the sidewall and the remaining portion of the bottom surface. The dielectric material is peripherally enclosed by the epitaxial layer. | 10-22-2015 |
20150318215 | METHODS FOR REMOVING SELECTED FINS THAT ARE FORMED FOR FINFET SEMICONDUCTOR DEVICES - One illustrative method disclosed herein includes, among other things, forming a plurality of trenches in a semiconductor substrate to thereby define a plurality of fins in the substrate, forming a layer of insulating material in the trenches, performing an etching process sequence to remove at least a portion of one of the plurality of fins and thereby define a fin cavity, wherein the etching process sequence includes performing a first anisotropic etching process and, after performing the first anisotropic etching process, performing a second isotropic etching process. In this embodiment, the method concludes with the step of forming additional insulating material in the fin cavity. | 11-05-2015 |
20150318341 | Semiconductor Device and Method for Forming Same - A system and method for forming a resistor system is provided. An embodiment comprises a resistor formed in a U-shape. The resistor may comprise multiple layers of conductive materials, with a dielectric layer filling the remainder of the U-shape. The resistor may be integrated with a dual metal gate manufacturing process or may be integrated with multiple types of resistors. | 11-05-2015 |
20150325645 | METHOD PROVIDING AN EPITAXIAL GROWTH HAVING A REDUCTION IN DEFECTS AND RESULTING STRUCTURE - Disclosed are methods and resulting structures which provide an opening for epitaxial growth, the opening having an associated projection for reducing the size of the contact area on a substrate at which growth begins. During growth, the epitaxial material grows vertically from the contact area and laterally over the projection. The projection provides a stress relaxation region for the lateral growth to reduce dislocation and stacking faults at the side edges of the grown epitaxial material. | 11-12-2015 |
20150333016 | SEMICONDUCTOR DEVICES AND METHODS OF MAKING THE SAME - In one embodiment, methods for making semiconductor devices are disclosed. | 11-19-2015 |
20150333121 | SHALLOW TRENCH ISOLATION INTEGRATION METHODS AND DEVICES FORMED THEREBY - Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion. | 11-19-2015 |
20150340267 | Deep Trench Isolation Structure and Method for Improved Product Yield - A semiconductor structure having a deep trench isolation structure for improved product yield is disclosed. The semiconductor structure includes a deep trench having a filler material therein. The deep trench is adjacent to field oxide regions in a semiconductor substrate. A high density plasma (HDP) oxide layer, substantially free of thermal oxide, is situated over the filler material in the deep trench. The HDP oxide layer has a substantially co-planar top surface with at least one of the field oxide regions. According to the present disclosure, formation of nodules in the deep trench is prevented. | 11-26-2015 |
20150340273 | SILICON WAVEGUIDE ON BULK SILICON SUBSTRATE AND METHODS OF FORMING - Various methods include: forming an optical waveguide in a bulk silicon layer, the optical waveguide including a set of shallow trench isolation (STI) regions overlying a silicon substrate region; ion implanting the silicon substrate to amorphize a portion of the silicon substrate; forming a set of trenches through the STI regions and into the underlying silicon substrate region; undercut etching the silicon substrate region under the STI regions through the set of trenches to form a set of cavities, wherein the at least partially amorphized portion of the silicon substrate etches at a rate less than an etch rate of the silicon substrate; and sealing the set of cavities. | 11-26-2015 |
20150340279 | METHOD FOR MANUFACTURING SOI WAFER AND SOI WAFER - The present invention provides a method for manufacturing SOI wafer, wherein, after plasma treatment has been performed on at least one surface of a bonding interface of the bond wafer and a bonding interface of the base wafer, bonding is performed through the oxide film, and the bond wafer is delaminated at the ion implanted layer by the delamination heat treatment comprising a first heat treatment at 250° C. or less for 2 hours or more and a second heat treatment at 400° C. to 450° C. for 30 minutes or more. Thereby, the method of manufacturing the SOI wafer that is small in SOI layer film thickness range, is small in surface roughness of the SOI layer surface, is smooth in shape of a terrace part and has no defects such as voids, blisters and so forth in the SOI layer can be provided. | 11-26-2015 |
20150348824 | SEMICONDUCTOR WAFER AND METHOD FOR PROCESSING A SEMICONDUCTOR WAFER - According to various embodiments, a semiconductor wafer may include: a semiconductor body including an integrated circuit structure; and at least one tetrahedral amorphous carbon layer formed at least one of over or in the integrated circuit structure, the at least one tetrahedral amorphous carbon layer may include a substance amount fraction of sp | 12-03-2015 |
20150348870 | SEMICONDUCTOR STRUCTURES WITH ISOLATED OHMIC TRENCHES AND STAND-ALONE ISOLATION TRENCHES AND RELATED METHOD - A method of forming a semiconductor structure in a semiconductor-on-insulator (SOI) substrate and semiconductor structure so formed are provided. The SOI substrate includes a semiconductor layer; a bulk semiconductor region underlying the semiconductor layer; and an insulation layer between the two. The method includes substantially simultaneously forming a first opening and a second opening extending from the semiconductor layer to the conductive region; introducing an insulating material to the side walls of the first opening; at least partially filling the first opening with a semiconductor material to provide an ohmic contact trench; and at least partially filling the second opening with an insulating material to form a device isolation trench. Insulating regions, for example, shallow trench isolation (STI) regions, may be formed about the device isolation trench and the ohmic contact trench. Semiconductor structures are also provided. The benefits of combining the features of SOI and STI structures are provided. | 12-03-2015 |
20150349046 | WELL RESISTORS AND POLYSILICON RESISTORS - An integrated circuit containing a well resistor has STI field oxide and resistor dummy active areas in the well resistor. STI trenches are etched and filled with trench fill dielectric material. The trench fill dielectric material is removed from over the active areas by a CMP process, leaving STI field oxide in the STI trenches. Subsequently, dopants are implanted into a substrate in the well resistor area to form the well resistor. An integrated circuit containing a polysilicon resistor has STI field oxide and resistor dummy active areas in an area for the polysilicon resistor. A layer of polysilicon is formed and planarized by a CMP process. A polysilicon etch mask is formed over the CMP-planarized polysilicon layer to define the polysilicon resistor. A polysilicon etch process removes polysilicon in areas exposed by the polysilicon etch mask, leaving the polysilicon resistor. | 12-03-2015 |
20150357408 | SEMICONDUCTOR DEVICE WITH ISOLATING LAYER ON SIDE AND BOTTOM SURFACES - A method for manufacturing a semiconductor device comprises includes providing a substrate with a surface, forming an isolating layer on part of the surface, and forming a first semiconductor portion and spaced therefrom a second semiconductor portion on the surface of the substrate. The isolating layer is interposed between a side surface of the first semiconductor portion and a side surface of the second semiconductor portion which face each other. The method further includes forming a first side isolation layer on the side surface of the first semiconductor portion. | 12-10-2015 |
20150364360 | METHOD OF FORMING SHALLOW TRENCH ISOLATION AND SEMICONDUCTOR DEVICE - According to an exemplary embodiment, a semiconductor device is provided. The semiconductor device includes: a substrate; a first vertical structure protruding from the substrate; a second vertical structure protruding from the substrate; an STI between the first vertical structure and the second vertical structure; wherein a first horizontal width between the first vertical structure and the STI is substantially the same as a second horizontal width between the second vertical structure and the STI. | 12-17-2015 |
20150364361 | SHALLOW TRENCH ISOLATION REGIONS MADE FROM CRYSTALLINE OXIDES - A method of manufacturing a semiconductor device that involves etching a trench in a semiconductor substrate, epitaxially growing a crystalline structure in the trench and forming semiconductor structures on either side of the crystalline structure. Crystalline oxides may include rare earth oxides, aluminum oxides or Perovskites. | 12-17-2015 |
20150371685 | Methods of Forming Semiconductor Devices to Include Single Body Interconnection Patterns Using Fine Patterning Techniques, and Semiconductor Device So Formed - A method of forming fine patterns for a semiconductor device includes providing a substrate with a first region and a second region, forming a conductive layer on the substrate, the conductive layer including a plate portion covering the first region and first protruding portions extending from the plate portion in a first direction and covering a portion of the second region, forming first mask patterns on the conductive layer, the first mask patterns extending in the first direction and being spaced apart from each other in a second direction crossing the first direction, forming a second mask pattern on the second region to cover the first protruding portions, and patterning the conductive layer using the first and second mask patterns as an etch mask to form conductive patterns. In plan view, each of the first protruding portions is overlapped with a corresponding one of the first mask patterns. | 12-24-2015 |
20150371946 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - In the present invention, in a twin plug-forming step, a conductive material is removed so as to form a groove for separating a diffusion layer ( | 12-24-2015 |
20150371961 | SEMICONDUCTOR DEVICE - A semiconductor device capable of, regardless of frequency, suppressing propagation of unnecessary signals to a semiconductor element or a semiconductor circuit through a semiconductor substrate, and of suppressing deterioration of signal quality of the semiconductor device caused by parasitic capacitive coupling. The semiconductor device is provided with a semiconductor substrate ( | 12-24-2015 |
20150372084 | RAISED FIN STRUCTURES AND METHODS OF FABRICATION - A method of fabricating raised fin structures is provided, the fabricating including: providing a substrate and at least one dielectric layer over the substrate; forming a trench in the at least one dielectric layer, the trench having a lower portion, a lateral portion, and an upper portion, the upper portion being at least partially laterally offset from the lower portion and being joined to the lower portion by the lateral portion; and, growing a material in the trench to form the raised fin structure, wherein the trench is formed to ensure that any growth defect in the lower portion of the trench terminates either in the lower portion or the lateral portion of the trench and does not extend into the upper portion of the trench. | 12-24-2015 |
20150380257 | METHOD OF FORMING FINFET HAVING FINS OF DIFFERENT HEIGHT - A device is fabricated on a silicon-on-insulator (SOI) wafer formed of a substrate, a bottom oxide layer on the substrate and an active silicon layer on the bottom oxide layer, where the active silicon layer has a surface opposite the bottom oxide layer. A first mask is formed over the surface at a first portion of the wafer, leaving a second portion of the wafer unmasked. The wafer is etched at the unmasked second portion of the wafer to form a depression in the active silicon layer. A thermal oxide layer is formed to substantially fill the depression, the first mask is removed, and fins are formed at the first and second portions of the wafer. | 12-31-2015 |
20150380316 | UNIFORM EXPOSED RAISED STRUCTURES FOR NON-PLANAR SEMICONDUCTOR DEVICES - The use of two different materials for shallow trench isolation and deep structural trenches with a dielectric material therein (e.g., flowable oxide and a HARP oxide, respectively) causes non-uniform heights of exposed portions of raised semiconductor structures for non-planar semiconductor devices, due to the different etch rates of the materials. Non-uniform openings adjacent the exposed portions of the raised structures from recessing the isolation and dielectric materials are filled with additional dielectric material to create a uniform top layer of one material (the dielectric material), which can then be uniformly recessed to expose uniform portions of the raised structures. | 12-31-2015 |
20160005814 | Dummy Gate Structure for Semiconductor Devices - A structure and method for fabricating a spacer structure for semiconductor devices, such as a multi-gate structure, is provided. The dummy gate structure is formed by depositing a dielectric layer, forming a mask over the dielectric layer, and patterning the dielectric layer. The mask is formed to have a tapered edge. In an embodiment, the tapered edge is formed in a post-patterning process, such as a baking process. In another embodiment, a relatively thick mask layer is utilized such that during patterning a tapered results. The profile of the tapered mask is transferred to the dielectric layer, thereby providing a tapered edge on the dielectric layer. | 01-07-2016 |
20160005815 | Semiconductor Constructions - Some embodiments include semiconductor constructions having semiconductor material patterned into two mesas spaced from one another by at least one dummy projection. The dummy projection has a width along a cross-section of X and the mesas have widths along the cross-section of at least 3X. Some embodiments include semiconductor constructions having a memory array region and a peripheral region adjacent the memory array region. Semiconductor material within the peripheral region is patterned into two relatively wide mesas spaced from one another by at least one relatively narrow projection. The relatively narrow projection has a width along a cross-section of X and the relatively wide mesas have widths along the cross-section of at least 3X. | 01-07-2016 |
20160020139 | GAP-FILLING DIELECTRIC LAYER METHOD FOR MANUFACTURING THE SAME AND APPLICATIONS THEREOF - A gap-filling dielectric layer, method for fabricating the same and applications thereof are disclosed. A silicon-containing dielectric layer is firstly deposited on a substrate. The silicon-containing dielectric layer is then subjected to a curing process, an in-situ wetting treatment and an annealing process in sequence, whereby a gap-filling dielectric layer with a nitrogen atom density less than 1×10 | 01-21-2016 |
20160027683 | Shallow Trench Isolation Structures in Semiconductor Device and Method for Manufacturing the Same - Shallow trench isolation structures in a semiconductor device and a method for manufacturing the same. The method include steps hereinafter. A substrate is provided with a pad oxide layer and a first patterned photoresist layer thereon. A first trench is formed in the substrate corresponding to the first patterned photoresist layer. A first dielectric layer is deposited in the first trench and on the substrate. A second patterned photoresist layer is provided to form an opening in the first dielectric layer and a second trench in the substrate corresponding to the second patterned photoresist layer. A second dielectric layer is deposited covering the first trench and the second trench in the substrate and the first dielectric layer on the substrate. The second dielectric layer is removing by chemical-mechanical polishing until the first dielectric layer is exposed. The first dielectric layer on the substrate selectively is removed. | 01-28-2016 |
20160035713 | SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR DEVICE - A semiconductor device includes a voltage generation circuit configured to generate a specific voltage; a first terminal configured to output the specific voltage; a second terminal configured to receive a temperature sensitive voltage; an analog/digital conversion circuit configured to convert the specific voltage and the temperature sensitive voltage to digital values; a storage unit configured to store the specific voltage and the temperature sensitive voltage; and a third terminal configured to transmit the specific voltage and the temperature sensitive voltage to an external semiconductor device. | 02-04-2016 |
20160035827 | Fin Structure of Semiconductor Device - A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a first wall extending along a first plane, the fin including a doped region defining a first furrow on a first side of the first plane. A dielectric is disposed within the first furrow, such that the dielectric is in contact with the first furrow between a first end of the dielectric and a second end of the dielectric. The first end is separated a first distance from the first plane. The dielectric disposed within the furrow increases the isolation of a channel portion of adjacent fins, and thus decreases current leakage of a FinFET, as compared to a FinFET including fins that do not include a dielectric disposed within a furrow. | 02-04-2016 |
20160035833 | TRAP RICH LAYER FOR SEMICONDUCTOR DEVICES - An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer. | 02-04-2016 |
20160042989 | PROCESS FOR MANUFACTURING A COMPOSITE STRUCTURE - The disclosure relates to a process for manufacturing a composite structure, the process comprising the following steps: a) providing a donor substrate and a carrier substrate; b) forming a dielectric layer; c) forming a covering layer; d) forming a weakened zone in the donor substrate; e) joining the carrier substrate and the donor substrate via a contact surface having an outline; f) fracturing the donor substrate via the weakened zone, steps b) and e) being executed so that the outline is inscribed in the outline, and step c) being executed so that the covering layer covers the peripheral surface of the dielectric layer. | 02-11-2016 |
20160043081 | METHOD OF FORMING SEMICONDUCTOR FINS - Embodiments of the present invention provide methods of removing fin portions from a finFET. At a starting point, a high-K dielectric layer is disposed on a substrate. A fin hardmask and lithography stack is deposited on the high-k dielectric. A fin hardmask is exposed, and a first portion of the fin hardmark is removed. The lithography stack is removed. A second portion of the fin hardmask is removed. Fins are formed. A gap fill dielectric is deposited and recessed. | 02-11-2016 |
20160043172 | SEMICONDUCTOR DEVICE INCLUDING A WALL OXIDE FILM AND METHOD FOR FORMING THE SAME - A semiconductor device includes an oxide film structure having different thicknesses depending on where the oxide film structure is formed. In the semiconductor device, a wall oxide film is formed to have different thicknesses depending on locations of sidewalls of an active region. The semiconductor device includes an active region, a first wall oxide film disposed over a first sidewall of the active region that extends along a first direction of the active region, the first wall oxide film having a first thickness, and a second wall oxide film disposed over a second sidewall of the active region that extends along a second direction of the active region, a second wall oxide film having a second thickness that is different from the first thickness. | 02-11-2016 |
20160049367 | INTEGRATED CIRCUIT STRUCTURE INCLUDING FUSE AND METHOD THEREOF - An integrated circuit structure includes a fuse. The integrated circuit structure further includes a first dielectric layer and a patterned dummy. The fuse is disposed on a substrate. The first dielectric layer covers the fuse. The patterned dummy is disposed on the first dielectric layer and the patterned dummy has a first recess exposing a part of the first dielectric layer directly above the fuse. A method of forming the integrated circuit structure including a fuse is also provided. | 02-18-2016 |
20160056180 | HETEROGENEOUS SEMICONDUCTOR MATERIAL INTEGRATION TECHNIQUES - Techniques are disclosed for heteroepitaxial growth of a layer of lattice-mismatched semiconductor material on an initial substrate, and transfer of a defect-free portion of that layer to a handle wafer or other suitable substrate for integration. In accordance with some embodiments, transfer may result in the presence of island-like oxide structures on the handle wafer/substrate, each having a defect-free island of the lattice-mismatched semiconductor material embedded within its upper surface. Each defect-free semiconductor island may have one or more crystalline faceted edges and, with its accompanying oxide structure, may provide a planar surface for integration. In some cases, a layer of a second, different semiconductor material may be heteroepitaxially grown over the handle wafer/substrate to fill areas around the transferred islands. In some other cases, the handle wafer/substrate itself may be homoepitaxially grown to fill areas around the transferred islands. | 02-25-2016 |
20160056227 | WELL RESISTORS AND POLYSILICON RESISTORS - An integrated circuit containing a well resistor has STI field oxide and resistor dummy active areas in the well resistor. STI trenches are etched and filled with trench fill dielectric material. The trench fill dielectric material is removed from over the active areas by a CMP process, leaving STI field oxide in the STI trenches. Subsequently, dopants are implanted into a substrate in the well resistor area to form the well resistor. An integrated circuit containing a polysilicon resistor has STI field oxide and resistor dummy active areas in an area for the polysilicon resistor. A layer of polysilicon is formed and planarized by a CMP process. A polysilicon etch mask is formed over the CMP-planarized polysilicon layer to define the polysilicon resistor. A polysilicon etch process removes polysilicon in areas exposed by the polysilicon etch mask, leaving the polysilicon resistor. | 02-25-2016 |
20160064354 | METHOD FOR ELECTRONIC CIRCUIT ASSEMBLY ON A PAPER SUBSTRATE - A methodology for a thin, flexible substrate having integrated passive circuit elements, and the resulting device are disclosed. Embodiments may include integrating one or more passive circuit components on a first or second surface of a substrate, and interconnecting one or more integrated circuit (IC) dies on a second surface of the interposer to the one or more passive circuit components with one or more metal-filled vias between the first and second surfaces, the first and second surfaces being opposite surfaces of the substrate. | 03-03-2016 |
20160064479 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate, a first dielectric layer, a first conductive layer, and an isolation structure. The substrate has a trench. The first dielectric layer is disposed on the substrate between two neighboring trenches. The first conductive layer is disposed on the first dielectric layer. The isolation structure, including a step zone and a recessed zone, is disposed in the trench, wherein an upper surface of the step zone is higher than an upper surface of the first dielectric layer. | 03-03-2016 |
20160064481 | BORON RICH NITRIDE CAP FOR TOTAL IONIZING DOSE MITIGATION IN SOI DEVICES - A semiconductor-on-insulator (SOI) structure that includes a cap layer composed of a boron-rich compound or doped boron nitride located between a top semiconductor layer and a buried insulator layer is provided. The cap layer forms a conductive path between the top semiconductor layer and the buried insulator layer in the SOI structure to dissipate total ionizing dose (TID) accumulated charges, thus advantageously mitigating TID effects in fully depleted SOI transistors. | 03-03-2016 |
20160064573 | SEMICONDUCTOR DEVICE INCLUDING ZENER DIODE AND METHOD OF MANUFACTURING THEREOF - An embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes an insulator formed on a top surface of a semiconductor substrate. The semiconductor device also includes a semiconductor layer containing a first region of a first conductivity type and formed on the insulator layer. The first region is a P+ region or an N+ region and has a volume of over 50-80% of that of the semiconductor layer. The semiconductor device further includes a second region of a second conductivity type in direct contact with the first region and forming a P-N junction with the first region. The second region has a doping concentration heavier than that of the first region. In addition, the semiconductor device includes a first metallization region in electrical contact with the first region and a second metallization region in electrical contact with the second region. | 03-03-2016 |
20160071759 | Method of Forming a Semiconductor Substrate With Buried Cavities and Dielectric Support Structures - A method of forming a semiconductor device includes forming a plurality of trenches extending into a semiconductor substrate from a first surface of the semiconductor substrate. Each of the trenches includes a narrower part in open communication with a wider part that is spaced apart from the first surface by the narrower part. The narrower part of adjacent trenches is laterally separated by a first region of the semiconductor substrate. The wider part of adjacent trenches is laterally separated by a second region of the semiconductor substrate that is narrower than the first region. The method further includes introducing an oxidizing agent into the wider part of the trenches through the narrower part of the trenches to oxidize the second region of the semiconductor substrate between adjacent trenches to form dielectric support structures that support the first region of the semiconductor. | 03-10-2016 |
20160071760 | HIGH RESISTIVITY SILICON-ON-INSULATOR WAFER MANUFACTURING METHOD FOR REDUCING SUBSTRATE LOSS - A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm; a Group IVA nitride layer in contact with the semiconductor handle substrate, the Group IVA nitride layer selected from the group consisting of carbon nitride, silicon carbon nitride, and a combination thereof; a dielectric layer in contact with the Group IVA nitride layer; and a semiconductor device layer in contact with the dielectric layer. | 03-10-2016 |
20160071761 | METHOD FOR PRODUCING HYBRID SUBSTRATE, AND HYBRID SUBSTRATE - A hybrid substrate has an SOI structure having a good silicon active layer, without defects such as partial separation of the silicon active layer is obtained without trimming the outer periphery of the substrate. An SOI substrate is obtained by sequentially laminating a first silicon oxide film and a silicon active layer in this order on a silicon substrate. A terrace portion that does not have the silicon active layer is formed in the outer peripheral portion of the silicon substrate surface. A second silicon oxide film is formed on the silicon active layer surface of the SOI substrate The bonding surfaces of the SOI substrate and a supporting substrate that has a thermal expansion coefficient different from that of the SOI substrate is subjected to an activation treatment. The SOI substrate and the supporting substrate are bonded with the second silicon oxide film being interposed therebetween. | 03-10-2016 |
20160079339 | INDUCTOR HEAT DISSIPATION IN AN INTEGRATED CIRCUIT - The present invention relates generally to semiconductor structures and methods of manufacturing and, more particularly, to improving heat dissipation of devices, such as active devices like inductors, by filling portions of the semiconductor structure with thermally conductive and electrical isolating material that may serve as a heat sink to a base substrate. In an embodiment, an inductor may be formed above a cavity region in which the thermally conductive and electrical isolating material has been formed. Heat may then be dissipated from the inductor to the cavity, and eventually to the base substrate, through trenches filled with the thermally conductive and electrical isolating material. | 03-17-2016 |
20160079340 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to one embodiment includes a semiconductor substrate, an insulating member provided in a first region on the semiconductor substrate, an insulating film provided in a second region not provided with the insulating member on the semiconductor substrate, a conductive member provided on the insulating member and on the insulating film, and a first and a second vias connected to the conductive member. An upper surface of the insulating film is lower than an upper surface of the insulating member. An upper part of the conductive member is provided in both the first region and the second region, and a lower part is provided in the second region and not provided in the first region. The conductive member has at least one portion located on the first region between the first via and the second via. | 03-17-2016 |
20160093591 | MICROELECTROMECHANICAL SYSTEM (MEMS) BOND RELEASE STRUCTURE AND METHOD OF WAFER TRANSFER FOR THREE-DIMENSIONAL INTEGRATED CIRCUIT (3D IC) INTEGRATION - A microelectromechanical system (MEMS) bond release structure is provided for manufacturing of three-dimensional integrated circuit (3D IC) devices with two or more tiers. The MEMS bond release structure includes a MEMS sacrificial release layer which may have a pillar or post structure, or alternatively, a continuous sacrificial layer for bonding and release. | 03-31-2016 |
20160111448 | FIN-SHAPED STRUCTURE AND METHOD THEREOF - A method of forming a fin-shaped structure includes the following steps. A substrate having at least a fin structure thereon is provided. A liner is formed on sidewalls of the fin structure. An oxide layer is formed between the fin structure and the substrate. The fin structure is removed until a bottom layer of the fin structure is reserved, to form a recess between the liner. A buffer epitaxial layer and an epitaxial layer are sequentially formed in the recess. A top part of the liner is removed until sidewalls of the epitaxial layer are exposed. Moreover, a fin-shaped structure formed by said method is also provided. | 04-21-2016 |
20160118248 | CRYSTAL FORMATION ON NON-LATTICE MATCHED SUBSTRATES - A semiconductor structure can be created by forming an insulator layer over a surface of a substrate. An intermediate layer can be formed on top of the insulator layer, wherein openings in the intermediate layer may expose regions of the insulator. Openings may be formed in the exposed regions of the insulator layer to create exposed areas of the substrate. A first element of a multi-element semiconductor can be deposited onto the exposed regions of the insulator layer, into the openings in the exposed regions of the insulator layer, and onto the exposed areas of the substrate. A capping layer can be formed over the first element of the multi-element semiconductor. The first element can be melted. A liquid solution can be created by dissolving a second element of the multi-element semiconductor into first element. A multi-element semiconductor, seeded off the substrate, can be formed from the liquid solution. | 04-28-2016 |
20160118293 | METHOD FOR PHOTOLITHOGRAPHY-FREE SELF-ALIGNED REVERSE ACTIVE ETCH - A layer of partially planarized organosilicate (DUO) is spin-coated onto a layer of high density plasma (HDP) oxide on a silicon wafer after the shallow trench isolation (STI) is filled with the HDP oxide. Then the DUO layer is etched using a specialized process specifically tuned to etch the DUO and high density plasma (HDP) oxide at a certain selectivity. The higher areas of the wafer topography (active Si areas) have thinner DUO and as the etch process proceeds it starts to etch through the HDP oxide in these areas (active Si areas). The etch process is stopped after a certain depth is reached and before touching down on the silicon nitride oxidation layer. The DUO is removed and a standard chemical-mechanical polish (CMP) is performed on the silicon wafer. After the CMP step the silicon nitride is removed, exposing the silicon substrate between the field oxides. | 04-28-2016 |
20160126086 | NON-PLANAR SEMICONDUCTOR DEVICE WITH ASPECT RATIO TRAPPING - As disclosed herein, a semiconductor device with aspect ratio trapping is provided, including a bulk substrate, a plurality of isolation pillars formed on the bulk substrate, wherein one or more gaps are formed between the isolation pillars, an oxide layer formed by epitaxy on the bulk substrate, between the isolation pillars, wherein the oxide layer partially fills the gaps between the isolation pillars, one or more fins formed over the oxide layer between the isolation pillars, such that the one or more fins fill the gaps between the isolation pillars, wherein the oxide layer electrically isolates the one or more fins from the bulk substrate. The oxide layer has an aspect ratio that is selected to substantially eliminate defects at the interface between the oxide layer and the fins. The semiconductor device may also include a semiconductor layer between the bulk substrate and oxide layer. | 05-05-2016 |
20160133698 | SEMICONDUCTOR STRUCTURE AND PREPARATION METHOD THEREOF - A semiconductor structure includes a substrate, a semiconductor device in the substrate, and an isolating structure in the substrate and adjacent to the semiconductor device. The isolating structure has a roughness surface at a sidewall of the isolating structure, and the roughness surface includes carbon atoms thereon. | 05-12-2016 |
20160133721 | SELECTIVELY FORMING A PROTECTIVE CONDUCTIVE CAP ON A METAL GATE ELECTRODE - A replacement gate structure that includes a conductive metal gate electrode is formed in a gate cavity, wherein the gate cavity is formed in a dielectric material formed above an active region of a semiconductor device. An upper surface of the conductive metal gate electrode and an upper surface of the dielectric material are planarized during a common planarization process, and a protective conductive cap is selectively formed on and in direct physical contact with the planarized upper surface of the conductive metal gate electrode. A contact structure is formed in a dielectric insulating layer formed above the replacement gate structure, the contact structure directly contacting the protective conductive cap. | 05-12-2016 |
20160163687 | OXIDE DEFINITION (OD) GRADIENT REDUCED SEMICONDUCTOR DEVICE - An integrated circuit (IC) semiconductor device has a high oxide definition (OD) density region, a low OD density region adjacent to the high OD density region, and dummy cells in the high OD density region and the low OD density region to smooth a density gradient between the high OD density region and the low OD density region. | 06-09-2016 |
20160181105 | SILICON-GERMANIUM (SiGe) FIN FORMATION | 06-23-2016 |
20160181146 | SHALLOW TRENCH ISOLATIONS AND METHOD OF MANUFACTURING THE SAME | 06-23-2016 |
20160190240 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a semiconductor substrate, a first active area, a second active area, a first trench, at least one raised portion, and a first dielectric. The first active area is in the semiconductor substrate. The second active area is in the semiconductor substrate. The first trench is in the semiconductor substrate and separates the first active area and the second active area from each other. The raised portion is raised from the semiconductor substrate and is disposed in the first trench. The first dielectric is in the first trench and covers the raised portion. | 06-30-2016 |
20160196972 | FABRICATION OF III-V-ON-INSULATOR PLATFORMS FOR SEMICONDUCTOR DEVICES | 07-07-2016 |
20160197095 | SEMICONDUCTOR DEVICE | 07-07-2016 |
20160204048 | INTEGRATED CIRCUIT HEAT DISSIPATION USING NANOSTRUCTURES | 07-14-2016 |
20160204197 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF | 07-14-2016 |
20160254179 | METHOD FOR FABRICATING SHALLOW TRENCH ISOLATION AND SEMICONDUCTOR STRUCTURE USING THE SAME | 09-01-2016 |
20160379885 | STRUCTURES AND METHODS FOR RELIABLE PACKAGES - A device and method of forming the device that includes cavities formed in a substrate of a substrate device, the substrate device also including conductive vias formed in the substrate. Chip devices, wafers, and other substrate devices can be mounted to the substrate device. Encapsulation layers and materials may be formed over the substrate device in order to fill the cavities. | 12-29-2016 |
20160379943 | METHOD AND APPARATUS FOR HIGH PERFORMANCE PASSIVE-ACTIVE CIRCUIT INTEGRATION - An electronic device comprises an active radio frequency (RF) circuit element, and a passive RF circuit element integrated into the same silicon-on-insulation (SOI) substrate, and a dielectric carrier substrate bonded to the SOI substrate. | 12-29-2016 |
20160380001 | SELECTIVE OXIDATION FOR MAKING RELAXED SILICON GERMANIUM ON INSULATOR STRUCTURES - Methods and devices are provided to fabricate semiconductor devices with, e.g., SiGe-on-insulator structures. For example, a method for fabricating a semiconductor device includes forming a crystalline buffer layer on a substrate, forming an epitaxial semiconductor layer on the crystalline buffer layer, patterning the epitaxial semiconductor layer to form a patterned epitaxial semiconductor layer, and oxidizing a surface region of the crystalline buffer layer selective to the patterned epitaxial semiconductor layer to convert the surface region of the crystalline buffer layer to an insulating layer. The insulating layer insulates the patterned epitaxial semiconductor layer from the crystalline buffer layer. In one example structure, the substrate is a silicon substrate, the crystalline buffer layer is formed of germanium, the epitaxial semiconductor layer is formed of silicon-germanium, and the insulating layer is formed of amorphous germanium-oxide. | 12-29-2016 |
20180025935 | SEMICONDUCTOR STRUCTURE HAVING AN ISOLATION LAYER FOR REDUCING PARASITIC EFFECT | 01-25-2018 |
20190148355 | Intelligent Diode Structures | 05-16-2019 |