Entries |
Document | Title | Date |
20080203518 | METHOD FOR POSITIONING SUB-RESOLUTION ASSIST FEATURES - The present application is directed to a method of selectively positioning sub-resolution assist features (SRAF) in a photomask pattern for an interconnect. The method comprises determining if a first interconnect pattern option will result in improved circuit performance compared with a second interconnect pattern option, where the first option is designed to be formed with SRAF and the second option is designed to be formed without SRAF. If it is determined that the first option will result in improved circuit performance, the first pattern option is selected as a target pattern and one or more SRAF patterns are positioned to facilitate patterning of the first pattern option. If it is not determined that the first option will result in improved performance, the second pattern option is selected as a target pattern. | 08-28-2008 |
20080217726 | INTEGRATED CIRCUIT SYSTEM EMPLOYING DIPOLE MULTIPLE EXPOSURE - An integrated circuit system that includes: providing a first mask including a first feature; exposing the first mask to a radiation source to form an image of the first feature on a photoresist material that is larger than a structure to be formed, the photoresist material being formed over a substrate that includes the integrated circuit system; providing a second mask including a second feature; aligning the second mask over the image of the first mask to form an overlap region; and exposing the second mask to the radiation source to form an image of the second feature on the photoresist material that is larger than the structure to be formed. | 09-11-2008 |
20080217727 | Radio frequency isolation for SOI transistors - According to an exemplary embodiment, a structure includes at least one SOI (semiconductor-on-insulator) transistor situated over a buried oxide layer, where the buried oxide layer overlies a bulk substrate. The structure further includes an electrically charged field control ring situated over the buried oxide layer and surrounding the at least one SOI transistor. A width of the electrically charged field control ring is greater than a thickness of the buried oxide layer. The electrically charged field control ring reduces a conductivity of a surface portion of the bulk substrate underlying the field control ring, thereby minimizing RF coupling of the at least one SOI transistor through the bulk substrate. The structure further includes an isolation region situated between the electrically charged field control ring and the at least one SOI transistor. A method to achieve and implement the disclosed structure is also provided. | 09-11-2008 |
20080224251 | Optimal Rasterization for Maskless Lithography - A lithographic system is provided in which an extent of overlap between pattern sections is adjusted in order to match a size of a pattern section to a size of a repeating portion of the pattern to be formed. | 09-18-2008 |
20080224252 | Semiconductor device having an element isolating insulating film - In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent formation of facets. Subsequently, unwanted portions of the epitaxial layer are removed by means of CMP to complete an STI element isolating structure. | 09-18-2008 |
20080237776 | DRAM layout with vertical FETs and method of formation - DRAM cell arrays having a cell area of less than about 4 F | 10-02-2008 |
20080251877 | METHODS FOR FABRICATING COMPLEX MICRO AND NANOSCALE STRUCTURES AND ELECTRONIC DEVICES AND COMPONENTS MADE BY THE SAME - This invention provides processing steps, methods and materials strategies for making patterns of structures for electronic, optical and optoelectronic devices. Processing methods of the present invention are capable of making micro- and nano-scale electronic structures, such as T-gates, gamma gates, and shifted T-gates, having a selected non-uniform cross-sectional geometry. The present invention provides lithographic processing strategies for sub-pixel patterning in a single layer of photoresist useful for making and integrating device components comprising dielectric, conducting, metal or semiconductor structures having non-uniform cross-sectional geometries. Processing methods of the present invention are complementary to conventional microfabrication and nanofabrication platforms, and can be effectively integrated into existing photolithographic, etching and thin film deposition patterning strategies, systems and infrastructure. | 10-16-2008 |
20080265360 | Semiconductor Layer Structure And Method Of Making The Same - A semiconductor layer structure includes a donor substrate and a detach region carried by the donor substrate. A device structure is carried by the donor substrate and positioned proximate to the detach region. The device structure includes a stack of crystalline semiconductor layers. The stack of crystalline semiconductor layers includes a pn junction. | 10-30-2008 |
20080283957 | Method of Fabricating Semiconductor Device Having Self-Aligned Contact Plug and Related Device - Methods of fabricating a semiconductor device having a self-aligned contact plug are provided. Methods include forming a lower insulating layer on a semiconductor substrate, forming a plurality of interconnection patterns parallel to each other on the lower insulating layer; forming an upper insulating layer that is configured to fill between the interconnection patterns, and forming a plurality of first mask patterns crossing the plurality of interconnection patterns, ones of the plurality of first mask patterns parallel to each other on the semiconductor substrate having the upper insulating layer. Methods may include forming a second mask pattern that is self-aligned to the plurality of first mask patterns and that is between ones of the plurality of first mask patterns, etching the upper insulating layer and the lower insulating layer using the first and second mask patterns and the plurality of interconnection patterns as etch masks to form a plurality of contact holes exposing the semiconductor substrate, and forming a plurality of contact plugs in respective ones of the plurality of contact holes. Semiconductor devices are also provided. | 11-20-2008 |
20080315345 | Technique for Stable Processing of Thin/Fragile Substrates - A semiconductor on insulator (SOI) wafer includes a semiconductor substrate having first and second main surfaces opposite to each other. A dielectric layer is disposed on at least a portion of the first main surface of the semiconductor substrate. A device layer has a first main surface and a second main surface. The second main surface of the device layer is disposed on a surface of the dielectric layer opposite to the semiconductor substrate. A plurality of intended die areas are defined on the first main surface of the device layer. The plurality of intended die areas are separated from one another. A plurality of die access trenches are formed in the semiconductor substrate from the second main surface. Each of the plurality of die access trenches are disposed generally beneath at least a respective one of the plurality of intended die areas. | 12-25-2008 |
20090001499 | THICK ACTIVE LAYER FOR MEMS DEVICE USING WAFER DISSOLVE PROCESS - Methods for producing MEMS (microelectromechanical systems) devices with a thick active layer and devices produced by the method. An example method includes heavily doping a first surface of a first silicon wafer with P-type impurities, and heavily doping a first surface of a second silicon wafer with N-type impurities. The heavily doped first surfaces are then bonded together, and a second side of the first wafer opposing the first side of the first wafer is thinned to a desired thickness, which may be greater than about 30 micrometers. The second side is then patterned and etched, and the etched surface is then heavily doped with P-type impurities. A cover is then bonded to the second side of the first wafer, and the second wafer is thinned. | 01-01-2009 |
20090001500 | Method and structure for implanting bonded substrates for electrical conductivity - A partially completed multi-layered substrate, e.g., silicon on silicon. The substrate has a thickness of material from a first substrate. The thickness of material comprises a first face region. The substrate has a second substrate having a second face region. Preferably, the first face region of the thickness of material is joined to the second face region of the second substrate. The substrate has an interface region formed between the first face region of the thickness of material and the second face region of the second substrate. A plurality of particles are implanted within a portion of the thickness of the material and a portion of the interface region to electrically couple a portion of the thickness of material to a portion of the second substrate. | 01-01-2009 |
20090032898 | Methods for Defining Dynamic Array Section with Manufacturing Assurance Halo and Apparatus Implementing the Same - A method is disclosed for defining a dynamic array section to be manufactured on a semiconductor chip. The method includes defining a peripheral boundary of the dynamic array section. The method also includes defining a manufacturing assurance halo outside the boundary of the dynamic array section. The method further includes controlling chip layout features within the manufacturing assurance halo to ensure that manufacturing of conductive features inside the boundary of the dynamic array section is not adversely affected by chip layout features within the manufacturing assurance halo. | 02-05-2009 |
20090032899 | Integrated circuit design based on scan design technology - An integrated circuit is provided with a scan chain including a scan flip-flop and a dummy block. The dummy block has a clock terminal receiving a clock signal, a scan input terminal connected to a scan data line within the scan chain, and a scan output terminal connected to another scan data line within the scan chain. The dummy block is configured to output data on the scan output terminal in response to input data fed to the scan input terminal, not responsively to the clock signal. | 02-05-2009 |
20090057809 | STRESS TRANSFER IN AN INTERLAYER DIELECTRIC BY PROVIDING A STRESSED DIELECTRIC LAYER ABOVE A STRESS-NEUTRAL DIELECTRIC MATERIAL IN A SEMICONDUCTOR DEVICE - By forming a stressed dielectric layer on different transistors and subsequently relaxing a portion thereof, the overall process efficiency in an approach for creating strain in channel regions of transistors by stressed overlayers may be enhanced while nevertheless transistor performance gain may be obtained for each type of transistor, since a highly stressed material positioned above the previously relaxed portion may also efficiently affect the underlying transistor. | 03-05-2009 |
20090065889 | Semiconductor integrated circuit device and method for designing the same - A semiconductor integrated circuit device has a basic cell structure which allows avoidance of wiring congestion of signal lines or the like. The semiconductor integrated circuit device comprises a plurality of basic cells having predetermined functions, respectively, which are configured by connecting semiconductor elements via wirings. Each of the basic cells has a polygonal shape when viewed from the top. Moreover, a power source line is provided in an inner portion of the basic cell. | 03-12-2009 |
20090079023 | METHOD OF FABRICATING AN INTEGRATED CIRCUIT WITH STRESS ENHANCEMENT - A method of fabricating an integrated circuit including arranging a plurality of cells to form a desired floor plan of the integrated circuit, wherein each cell comprises at least one transistor, forming a plurality of circuit constituents from the plurality of cells of the floor plan, wherein each circuit constituent comprises at least one cell and belongs to one of a plurality circuit constituent types, and applying mechanical stress to channel regions of the at least one transistor of each cell based on the circuit constituent type of the circuit constituent to which the cell belongs. | 03-26-2009 |
20090085147 | MULTI-DIRECTIONAL TRENCHING OF A DIE IN MANUFACTURING SUPERJUNCTION DEVICES - A method of manufacturing a superjunction device includes providing a semiconductor wafer having at least one die. At least one first trench having a first orientation is formed in the at least one die. At least one second trench having a second orientation that is different from the first orientation is formed in the at least one die. | 04-02-2009 |
20090085148 | MULTI-DIRECTIONAL TRENCHING OF A PLURALITY OF DIES IN MANUFACTURING SUPERJUNCTION DEVICES - A method of manufacturing a superjunction device includes providing a semiconductor wafer having a plurality of dies. A first plurality of trenches having a first orientation are formed in a first die. A second plurality of trenches having a second orientation are formed in a second die. The second orientation is different from the first orientation. | 04-02-2009 |
20090085149 | SEMICONDUCTOR DEVICE AND METHOD OF PROCESSING THE SAME - Provided is a semiconductor wafer. In the semiconductor wafer, formation and etching of an n type epitaxial layer and formation and etching of a p type epitaxial layer are alternately performed for at least three times, so that all semiconductor layers are formed of epitaxial layers on a semiconductor substrate. Thereby, the respective semiconductor layers can be formed to have reduced widths. Thus, if a required breakdown voltage is the same, dopant concentrations of the respective semiconductor layers can be increased and a resistance value of the wafer can be reduced. In addition, a space portion remaining in the end is buried with an insulating layer, so that a defect can be avoided in a junction surface of the epitaxial layers. | 04-02-2009 |
20090134488 | Immersion Liquid, Exposure Apparatus, and Exposure Process - An immersion liquid is provided comprising an ion-forming component, e.g. an acid or a base, that has a relatively high vapor pressure. Also provided are lithography processes and lithography systems using the immersion liquid. | 05-28-2009 |
20090140371 | Semiconductor integrated device and manufacturing method for the same - A first exemplary aspect of an exemplary embodiment of the present invention is a semiconductor integrated device comprising a semiconductor substrate, a first impurity layer of a first conductivity type formed in the semiconductor substrate, a second impurity layer of a second conductivity type formed on the first impurity layer, a first well of the first conductivity type formed on the second impurity layer and supplied with potential from the first impurity layer via an impurity region of the first conductivity type selectively formed in a part of the second impurity layer, and a second well of the second conductivity type formed on the second impurity layer and supplied with potential from the second impurity layer, wherein the impurity concentrations of the first impurity layer and the impurity region are higher than that of the first well, and the impurity concentration of the second impurity layer is higher than that of the second well. | 06-04-2009 |
20090194840 | Method of Double Patterning, Method of Processing a Plurality of Semiconductor Wafers and Semiconductor Device - A method of double patterning is disclosed. The method includes forming a first photosensitive layer; exposing the first photosensitive layer using a first reticle; developing the first photosensitive layer thereby forming a first image pattern including first elements; forming a second photosensitive layer; exposing the second photosensitive layer using the first reticle; and developing the second photosensitive layer thereby forming a second image pattern. | 08-06-2009 |
20090218653 | Exposure apparatus, method for cleaning member thereof, maintenance method for exposure apparatus, maintenance device, and method for producing device - A lithography apparatus includes a part having a photocatalytic coating. The lithography apparatus can be an extreme ultraviolet lithography apparatus or an immersion lithography apparatus. | 09-03-2009 |
20090230501 | Three dimensional structure memory - A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques. | 09-17-2009 |
20090243028 | CAPACITIVE ISOLATION CIRCUITRY WITH IMPROVED COMMON MODE DETECTOR - An integrated circuit having voltage isolation capabilities comprising a first galvanically isolated area of the integrated circuit containing a first group of functional circuitry for processing a data stream. The first group of functional circuitry located in a substrate of the integrated circuit. Capacitive isolation circuitry located in conductive layers of the integrated circuit provides a high voltage isolation link between the first group of functional circuitry and a second group of functional circuitry connected to the integrated circuit through the capacitive isolation circuitry. The capacitive isolation circuitry includes a differential transmitter for transmitting data in a differential signal to the second group of functional circuitry via the capacitive isolation circuitry. A differential receiver receives data within the differential signal from the second group of functional circuitry via the capacitive isolation circuitry. A detector circuit within the differential receiver detects the received data. The detector circuit monitors the differential signal and generates a first logical output when a voltage generated responsive to the differential signal exceeds a programmable voltage threshold level and generates a second logical output when the voltage generated responsive to the differential signal falls below the programmable voltage threshold level. | 10-01-2009 |
20090256232 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - The semiconductor device includes: memory cells each having a first multilayer electrode including a first lower electrode made of a first conductive film and a first upper electrode made of a second conductive film formed one on the other with a first interface film therebetween; and a diode having a diode electrode made of the second conductive film and a second interface film as a silicon oxide film formed at the interface between the diode electrode and a substrate. The first interface film has a thickness with which electrical connection between the lower electrode and the upper electrode is maintained, and the second interface film has a thickness with which epitaxial growth between the substrate and the diode electrode is inhibited. | 10-15-2009 |
20090267175 | DOUBLE PATTERNING TECHNIQUES AND STRUCTURES - Double patterning techniques and structures are generally described. In one example, a method includes depositing a first photoresist to a semiconductor substrate, forming a first integrated circuit (IC) pattern in the first photoresist, the first IC pattern comprising one or more trench structures, protecting the first IC pattern in the first photoresist from actions that form a second IC pattern in a second photoresist, depositing the second photoresist to the first IC pattern, and forming the second IC pattern in the second photoresist, the second IC pattern comprising one or more structures that are sufficiently close to the one or more trench structures of the first IC pattern to cause scumming of the second photoresist in the one or more trench structures of the first IC pattern. | 10-29-2009 |
20090278222 | INTEGRATED CIRCUIT WITH UNIFORM POLYSILICON PERIMETER DENSITY, METHOD AND DESIGN STRUCTURE - Disclosed are embodiments of forming an integrated circuit with a desired decoupling capacitance and with the uniform and targeted across-chip polysilicon perimeter density. The method includes laying out functional blocks to form the circuit according to the design and also laying out one or more decoupling capacitor blocks to achieve the desired decoupling capacitance. Then, local polysilicon perimeter densities of the blocks are determined and, as necessary, the decoupling capacitor blocks are reconfigured in order to adjust for differences in the local polysilicon perimeter densities. This reconfiguring is performed in a manner that essentially maintains the desired decoupling capacitance. Due to the across-chip polysilicon perimeter density uniformity, functional devices in different regions of the chip will exhibit limited performance parameter variations (e.g., limited threshold voltage variations). Also disclosed herein are embodiments of an integrated circuit structure formed according to the method embodiments and a design structure for the integrated circuit. | 11-12-2009 |
20090321870 | SHUTTLE WAFER AND METHOD OF FABRICATING THE SAME - A method of fabricating a shuttle wafer is provided. First, a wafer including a number of shots is provided. Each of the shots includes a number of dies. A material layer is then formed on the wafer. After that, a shuttle mask having a number of IC designs is provided. A first IC design corresponds to a first die of each of the shots. A portion of the IC designs on the shuttle mask is covered for exposing the first IC design. Thereafter, the first IC designs of the shuttle mask are transferred onto the material layer, so as to form at least an effective IC pattern on the first die of each of the shots and to form an ineffective IC pattern on each of the other dies of each of the shots. | 12-31-2009 |
20100006972 | WAFER SCALE MEMBRANE FOR THREE-DIMENSIONAL INTEGRATED CIRCUIT DEVICE FABRICATION - An fabrication of three-dimensional integrated devices and three-dimensional integrated devices fabricated therefrom are described. A device side of a donor wafer is coated with a polymer film and exposure of a substrate side to an oxidizing plasma creates a continuous SiO | 01-14-2010 |
20100032792 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method for manufacturing a semiconductor device includes forming an N-well and a P-well formed in a semiconductor substrate. An isolation layer may be formed in the semiconductor substrate. At least one dummy active pattern may be formed in a boundary area between the N-well and the P-well. A salicide blocking layer may be over the upper surface of the at least one dummy active pattern. A non-salicide region may be formed over the upper surface of the at least one dummy active pattern by carrying out a salicide process over the semiconductor substrate provided with the salicide blocking layer. | 02-11-2010 |
20100038742 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - This invention is directed to offer a technology that makes it possible to form desired bump electrodes easily when the bump electrodes are to be formed at locations lowered by a step. There is formed an isolation layer | 02-18-2010 |
20100038743 | INFORMATION STORAGE SYSTEM WHICH INCLUDES A BONDED SEMICONDUCTOR STRUCTURE - An information storage system includes a bonded semiconductor structure having a memory circuit region carried by an interconnect region. The memory circuit region includes a memory control device region having a vertically oriented memory control device. The memory circuit region includes a memory device region in communication with the memory control device region. The memory device region includes a memory device whose operation is controlled by the vertically oriented memory control device. | 02-18-2010 |
20100078756 | SEMICONDUCTOR DEVICE WITH SEMICONDUCTOR BODY AND METHOD FOR THE PRODUCTION OF A SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor body with a front-sided surface. An active cell region with a semiconductor device structure and an edge region surrounding the active cell region are arranged in the semiconductor body. The front-sided surface of the semiconductor body includes a passivation layer over the edge region and over the active cell region. The passivation layer includes a semiconducting insulation layer of a semiconducting material, the bandgap of which is greater than the bandgap of the material of the semiconductor body. | 04-01-2010 |
20100084732 | Semiconductor Device and Method of Manufacturing the Same - Disclosed herein is a method of manufacturing a semiconductor device that is adapted to improve the production yield. The method generally includes etching a semiconductor substrate to form a trench, filling the trench with a conductive material, separating the filled conductive material to form a plurality of gate patterns and a bit line contact region, and etching the substrate to define an isolation region. | 04-08-2010 |
20100102413 | LITHOGRAPHIC APPARATUS, DEVICE MANUFACTURING METHOD AND POSITION CONTROL METHOD - A lithographic apparatus includes a support configured to support a patterning device, the patterning device configured to pattern a beam of radiation to form a patterned beam of radiation; a positioning device configured to move the support in a first direction; a measurement device configured to measure a relative position of the patterning device with respect to the support and to generate a measuring signal, the measurement device including a reference unit constructed and arranged to be coupled to the patterning device at a fixed relative position, and a position sensor configured to measure the position of the reference unit with respect to the support, wherein the positioning device is constructed and arranged to correct a position of the support based on the measuring signal. | 04-29-2010 |
20100117187 | METHOD FOR FORMING GATE IN FABRICATING SEMICONDUCTOR DEVICE - In fabricating a semiconductor device, by forming gate electrode lines to meet a design rule with additional simple processes such as a masking process, an etching process and the like for securing an isolation space between the gate electrode lines according to the design rule, the method of embodiments can overcome a problem in the related gate forming process so that a chip size is increased and high mask quality is required since the process has to proceed in consideration of additional design guide rules B | 05-13-2010 |
20100164051 | SEMICONDUCTOR DEVICE HAVING SADDLE FIN-SHAPED CHANNEL AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate with an isolation layer formed in the semiconductor substrate to delimit active regions. Recess patterns for gates are defined in the active regions and the isolation layer. Gate patterns are formed in and over the recess patterns for gates, and a gate spacer is formed to cover the gate patterns. The recess patterns for gates have a first depth in the active regions and a second depth, which is greater than the first depth, in the isolation layer. Gaps are created between the gate patterns and upper parts of the recess patterns for gates that are defined in the isolation layer. The gate spacer fills the gaps and protects the gate spacer so as to prevent bridging. | 07-01-2010 |
20100176479 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device including depositing a hardmask layer on a layer of the semiconductor device, selectively etching a pattern of continuous lines in the hardmask layer, depositing an antireflective coating over remaining portions of the hardmask layer, depositing a photoresist layer on the antireflective coating, patterning the photoresist layer with a plurality of isolation trenches via a lithography process, each of the isolation trenches extending perpendicular to and crossing portions of at least one of the continuous lines of the underlying hardmask layer, and with each isolation trench having an initial width. The method further includes reducing the width of each of the isolation trenches from the initial width to desired width via a shrinking process, etching the antireflective coating underlying the isolation trenches to expose intersecting portions of the underlying continuous lines, and etching the exposed intersecting portions of the underlying continuous lines of the hardmask layer to form a pattern of line segments having line ends separated by the desired width. | 07-15-2010 |
20100258900 | ON-CHIP EMBEDDED THERMAL ANTENNA FOR CHIP COOLING - An apparatus comprises a first layer within a semiconductor chip having active structures electrically connected to other active structures and having electrically isolated first inactive structures. A second layer within the semiconductor chip is physically connected to the first layer. The second layer comprises an insulator and has second inactive structures. The first inactive structures are physically aligned with the second inactive structures. | 10-14-2010 |
20100258901 | SEMICONDUCTOR DEVICE, INK CARTRIDGE, AND ELECTRONIC DEVICE - A semiconductor device includes: a semiconductor substrate including an active element formation face on which an active element is formed; detection electrodes detecting a remaining amount of ink by being wet in the ink; an antenna transmitting and receiving information; a storage circuit storing information relating to the ink; and a control circuit controlling the detection electrodes, the antenna, and the storage circuit. | 10-14-2010 |
20100289111 | System and Method for Designing Cell Rows - A system and method for designing integrated circuits is disclosed. An embodiment comprises placing a standard cell with a first cell height into a cell row with a different height. The standard cell may have a height smaller than the cell row or else may have a height that is larger than the cell row. Vertical fillers and horizontal fillers are utilized to extend and connect the standard cell to adjacent cells without having to redesign the entire cell row. | 11-18-2010 |
20100289112 | METHOD AND APPARATUS OF CORE TIMING PREDICTION OF CORE LOGIC IN THE CHIP-LEVEL IMPLEMENTATION PROCESS THROUGH AN OVER-CORE WINDOW ON A CHIP-LEVEL ROUTING LAYER - A method and/or an apparatus of core timing prediction is disclosed. In one embodiment, a method may include generating a core timing model of a core logic that is accurately transferable to any chip-level integration process. The method may reduce performance degradation and/or performance variation of the core logic caused by a number of interactions between core logic components and chip-level components in the chip-level integration process. In addition, the core timing model of the core logic may be generated by filling un-wired tracks with metal in any of an outermost layer of the core logic after a core logic routing and constructing a layer at least an area of and adjacent to any of the outermost layer of the core logic with grounded metal that is orthogonal to those of the metal used in the outermost layer of the core logic. | 11-18-2010 |
20100320558 | CIRCUIT LAYOUT STRUCTURE AND METHOD TO SCALE DOWN IC LAYOUT - A circuit layout structure includes a substrate including a first region and a second region, and a set of conductive lines including a first conductive line and a second conductive line which respectively pass through the first region and the second region, wherein a variable spacing lies between the first conductive line and the second conductive line and the first conductive line and the second conductive line selectively have a first region line width and a second region line width so that the first region line width and the second region line width are substantially different. | 12-23-2010 |
20110024869 | DESIGN METHOD, DESIGN PROGRAM AND DESIGN SUPPORT DEVICE FOR SEMICONDUCTOR INTEGRATED CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT - A design method for a semiconductor integrated circuit, includes : a first calculating step; a second calculating step; and a setting step. The first step is a step of calculating a consumption current amount of a layout target circuit based on circuit information. The second calculating step is a step of calculating a suppliable current amount per unit area in a region where a power can be supplied from a power wiring line. The setting step is a step of setting a cell size of the layout target circuit based on the consumption current amount so that a consumption current amount per unit area of the layout target circuit is smaller than the suppliable current amount per unit area. | 02-03-2011 |
20110089522 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor wafer has a main surface. A main chip region is formed on the main surface. A sub-chip region is smaller in area than the main chip region, and positioned on an edge side of the semiconductor wafer relative to the main chip region. The sub-chip region is identical to the main chip region in design pattern. Accordingly, a semiconductor device in which occurrence of a pattern failure at the edge of the wafer can be prevented when chips are arranged in the surface of the semiconductor wafer and a method of manufacturing the same can be obtained. | 04-21-2011 |
20110089523 | SYSTEMS AND PROCESSES FOR FORMING THREE-DIMENSIONAL CIRCUITS - Provided are systems and processes for forming a three-dimensional circuit on a substrate. A radiation source produces a beam that is directed at a substrate having an isolating layer interposed between circuit layers. The circuit layers communicate with reach other via a seed region exhibiting a crystalline surface. At least one circuit layer has an initial microstructure that exhibits electronic properties unsuitable for forming circuit features therein. After being controllably heat treated, the initial microstructure of the circuit layer having unsuitable properties is transformed into one that exhibits electronic properties suitable for forming circuit feature therein. Also provided are three-dimensional circuit structures optionally formed by the inventive systems and/or processes. | 04-21-2011 |
20110133303 | MIM/MIS structure with praseodymium titanate or praseodymium oxide as insulator material - A semiconductor component including a first integrated circuit in a substrate which is adapted to produce electrical signals with a high-frequency signal component, wherein the substrate is such that the high-frequency signal component can propagate on a substrate surface and/or in the substrate interior, a second integrated circuit in the same substrate which is such that its function can be compromised by high-frequency signals, and a countersignal circuit in the same substrate which is adapted to deliver an electrical countersignal which at least at a selected location of the substrate surface and/or the substrate interior attenuates or eliminates the high-frequency electrical signal component emanating from the first integrated circuit, wherein the countersignal circuit includes a receiver which is adapted to produce an electrical signal dependent on the instantaneous field strength of the high-frequency signal component, and a shielding transistor provided in the substrate and having a control electrode and a first field electrode and a second field electrode, whose control electrode is connected on the input side to the receiver and whose first and second field electrodes are acted upon with a predeterminable first and second electrical potential. | 06-09-2011 |
20110133304 | Structure and Method for Placement, Sizing and Shaping of Dummy Structures - A chip includes a number a plurality of functional areas of a layer and a number of dummy structures within the layer. The dummy structures are spaced from the functional areas. Each dummy structure has a size that is a function of the size and density of the functional areas. | 06-09-2011 |
20110204470 | METHOD, SYSTEM, AND APPARATUS FOR ADJUSTING LOCAL AND GLOBAL PATTERN DENSITY OF AN INTEGRATED CIRCUIT DESIGN - An integrated circuit (IC) design method providing a circuit design layout having a plurality of functional blocks disposed a distance away from each other; identifying a local pattern density to an approximate dummy region, on the circuit design layout, within a predefined distance to one of the functional blocks; performing a local dummy insertion to the approximate dummy region according to the local pattern density; repeating the identifying and performing to at least some other of the functional blocks; and implementing a global dummy insertion to a non-local dummy region according to a global pattern density. | 08-25-2011 |
20110221029 | BALANCED ADAPTIVE BODY BIAS CONTROL - Systems and methods of balanced adaptive body bias control. In accordance with a first embodiment of the present invention, a method of balanced adaptive body bias control comprises determining a desirable dynamic condition for circuitry of an integrated circuit. A first dynamic indicator corresponding to the desirable dynamic condition is accessed. Second and third dynamic indicators of the integrated circuit are accessed. A first body biasing voltage is adjusted by an increment so as to change the first dynamic indicator in the direction of the desirable dynamic condition. A second body biasing voltage is adjusted based on a relationship between the second dynamic indicator and the third dynamic indicator. | 09-15-2011 |
20110227188 | INTEGRATED CIRCUITS INCLUDING DUMMY STRUCTURES AND METHODS OF FORMING THE SAME - An integrated circuit includes a core area. The core area has at least one edge region and a plurality of transistors disposed in the edge region. A plurality of dummy structures are disposed outside the core area and adjacent to the at least one edge region. Each channel of the transistors in a channel width direction faces at least one of the dummy structures. | 09-22-2011 |
20110227189 | Dishing-Free Gap-Filling with Multiple CMPs - A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed. | 09-22-2011 |
20110254119 | Semiconductor Device and Method of Manufacturing the Same - A method of manufacturing semiconductor devices includes forming a tunnel insulating layer, a conductive layer for a floating gate, and a hard mask layer on a semiconductor substrate, forming a first trench in the semiconductor substrate by partially etching the hard mask layer, the conductive layer for the floating gate, the tunnel insulating layer, and the semiconductor substrate, forming a first ion implantation region having a first impurity concentration into the semiconductor substrate of inner walls of the first trench by performing a first ion implantation process, forming a second trench extending from the first trench by etching the semiconductor substrate of a bottom of the first trench, and forming a second ion implantation region having a second impurity concentration lower than the first impurity concentration into the semiconductor substrate of inner walls of the second trench by performing a second ion implantation process, wherein a depth of the first trench is shallower than that of a junction region. | 10-20-2011 |
20110272775 | 3D INTEGRATED CIRCUIT SYSTEM AND METHOD - A semiconductor fabrication system and method are presented. A three dimensional multilayer integrated circuit fabrication method can include forming a first device layer and forming a second device layer on top of the first device layer with minimal detrimental heat transfer to the first layer by utilizing a controlled laser layer formation annealing process. A controlled laser crystallization process can be utilized and the controlled laser can include creating an amorphous layer; defining a crystallization area in the amorphous layer, where in the crystallization area is defined to promote single crystal growth (i.e. prevent multi-crystalline growth); and applying laser to the crystallization area, wherein the laser is applied in a manner that prevents undesired heat transfer to another layer. | 11-10-2011 |
20110291224 | EFFICIENT PITCH MULTIPLICATION PROCESS - Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. The mask is formed by patterning a photoresist layer which simultaneously defines mask elements corresponding to features in the array, interface and periphery areas of the integrated circuit. The pattern is transferred to an amorphous carbon layer. Sidewall spacers are formed on the sidewalls of the patterned amorphous carbon layer. A layer of protective material is deposited and then patterned to expose mask elements in the array region and in selected parts of the interface or periphery areas. Amorphous carbon in the array region or other exposed parts is removed, thereby leaving a pattern including free-standing, pitch multiplied spacers in the array region. The protective material is removed, leaving a pattern of pitch multiplied spacers in the array region and non-pitch multiplied mask elements in the interface and periphery areas. The pattern is transferred to a hard mask layer, through which an underlying substrate is etched. | 12-01-2011 |
20110298082 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF DRIVING THE SAME - A transistor causes fluctuation in the threshold and mobility due to the factor such as fluctuation of the gate length, the gate width, and the gate insulating film thickness generated by the difference of the manufacturing steps and the substrate to be used. As a result, there is caused fluctuation in the current value supplied to the pixel due to the influence of the characteristic fluctuation of the transistor, resulting in generating streaks in the display image. A light emitting device is provided which reduces influence of characteristics of transistors in a current source circuit constituting a signal line driving circuit until the transistor characteristics do not affect the device and which can display a clear image with no irregularities. A signal line driving circuit of the present invention can prevent streaks in a displayed image and uneven luminance. Also, the present invention makes it possible to form elements of a pixel portion and driving circuit portion from polysilicon on the same substrate integrally. In this way, a display device with reduced size and current consumption is provided as well as electronic equipment using the display device. | 12-08-2011 |
20110316114 | SIMPLIFIED PITCH DOUBLING PROCESS FLOW - A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material. | 12-29-2011 |
20120018838 | METHOD FOR MODULAR ARRANGEMENT OF A SILICON BASED ARRAY AND MODULAR SILICON BASED ARRAY - A silicon based module, including: a substrate; a first chip assembly fixed to the substrate, the first chip assembly including a first silicon chip and a first driver die having electrical circuitry; and a second chip assembly fixed to the substrate, the second chip assembly including a second silicon chip and a second driver die having electrical circuitry. Portions of the first and second chip assemblies are aligned in a longitudinal direction for the substrate; and portions of the first and second silicon chips are aligned in a width direction orthogonal to the longitudinal direction. Method for forming a silicon based module. | 01-26-2012 |
20120025344 | TRACEABLE INTEGRATED CIRCUITS AND PRODUCTION METHOD THEREOF - An embodiment of a method for producing traceable integrated circuits includes forming on a wafer of semiconductor material functional regions for implementing specific functionalities of corresponding integrated circuits, forming at least one seal ring around each functional region of the corresponding integrated circuit, and forming on each integrated circuit at least one marker indicative of information of the integrated circuit. Forming on each integrated circuit at least one marker may include forming the at least one marker on at least a portion of the respective seal ring that is visible. | 02-02-2012 |
20120032293 | EDGE DEVICES LAYOUT FOR IMPROVED PERFORMANCE - A word line driver includes an active area having a length that extends in a first direction over a semiconductor substrate. A plurality of fingers formed over an upper surface of the active area. Each of the plurality of fingers has a length that extends in a second direction and forms a MOS transistor with a portion of the active area. A first dummy structure is disposed between an outer one of the plurality of fingers and an edge of the semiconductor substrate. The first dummy structure includes a portion that is at least partially disposed over a portion of the active area. | 02-09-2012 |
20120032294 | METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE - A semiconductor device comprising: a first single crystal silicon layer comprising first transistors, first alignment mark, and at least one metal layer overlying said first single crystal silicon layer, wherein said at least one metal layer comprises copper or aluminum more than other materials; a second layer overlying said at least one metal layer, said second layer comprising second transistors, second alignment mark, and a through via through said second layer, wherein said through via is a part of a connection path between said first transistors and said second transistors, wherein alignment of said through via is based on said first alignment mark and said second alignment mark and effected by a distance between said first alignment mark and said second alignment mark. | 02-09-2012 |
20120038019 | MEMS Device and Fabrication Method - A method and structure for uncovering captive devices in a bonded wafer assembly comprising a top wafer and a bottom wafer. One embodiment method includes forming a plurality of cuts in the top wafer and removing a segment of the top wafer defined by the plurality of cuts. The bottom wafer remains unsingulated after the removal of the segment. | 02-16-2012 |
20120119320 | DIODE FOR ADJUSTING PIN RESISTANCE OF A SEMICONDUCTOR DEVICE - A diode comprises a P-type well formed in a semiconductor substrate, at least one N-type impurity doping area formed in the P-type well, an isolation area formed to surround the N-type impurity doping area, a P-type impurity doping area formed to surround the isolation area, first contacts formed in the N-type impurity doping area in a single row or a plurality of rows, and second contacts formed in the P-type impurity doping area in a single row or a plurality of rows, wherein pin resistance can be adjusted through changing any one of a distance between the N-type impurity doping area and the P-type impurity doping area, a contact pitch between the first contacts, and a contact pitch between the second contacts. | 05-17-2012 |
20120126358 | TONE INVERSION WITH PARTIAL UNDERLAYER ETCH - A method for tone inversion for integrated circuit fabrication includes providing a substrate with an underlayer on top of the substrate; creating a first pattern, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; covering the first pattern with a layer of image reverse material (IRM); and etching the second pattern into the substrate. A structure for tone inversion for integrated circuit fabrication includes a substrate; a partially etched underlayer comprising a first pattern located over the substrate, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; and an image reversal material (IRM) layer located over the partially etched underlayer. | 05-24-2012 |
20120153424 | HARDMASK COMPOSITION, METHOD OF FORMING A PATTERN USING THE SAME, AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING THE PATTERN - A hard mask composition, a method of forming a pattern, and a semiconductor integrated circuit device, the hard mask composition including a solvent; and a compound, the compound including a structural unit represented by the following Chemical Formula 1: | 06-21-2012 |
20120153425 | PROCESS FOR FABRICATING INTEGRATED-CIRCUIT CHIPS - Integrated-circuit chips are fabricated according to a process wherein weak portions are formed in a substrate wafer surrounding a plurality of locations. An integrated-circuit chip is defined at each location by destroying the weak portions so as to singulate integrated-circuit chips. | 06-21-2012 |
20120168894 | HARD MASK COMPOSITION, METHOD OF FORMING A PATTERN, AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING THE PATTERN - A hard mask composition, a method of forming a pattern, and a semiconductor integrated circuit device, the hard mask composition including a solvent; and an aromatic ring-containing compound, the aromatic ring-containing compound including at least one of a moiety represented by the following Chemical Formula 1 and a moiety represented by the following Chemical Formula 2: | 07-05-2012 |
20120175725 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor storage device according to an embodiment includes a memory cell array provided on a semiconductor substrate and comprising a plurality of memory cells configured to store data therein, and a peripheral circuit part provided on the semiconductor substrate and configured to control the memory cell array. An element isolation part is provided between active areas where the memory cells and the peripheral circuit part are formed. A sidewall film is provided on a side surface of the active area in the peripheral circuit part. | 07-12-2012 |
20120211860 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor storage device according to an embodiment comprises active areas on a semiconductor substrate. An element isolation is arranged between the active areas and filled by an insulating film. A plurality of memory cells configured to store data are formed on the active areas. Air gaps are arranged between upper-end edge parts of the active areas where the memory cells are formed and an insulating film in the element isolation. | 08-23-2012 |
20120261786 | SEMICONDUCTOR DEVICE, INK CARTRIDGE, AND ELECTRONIC DEVICE - A semiconductor device includes: a semiconductor substrate including an active element formation face on which an active element is formed; detection electrodes detecting a remaining amount of ink by being wet in the ink; an antenna transmitting and receiving information; a storage circuit storing information relating to the ink; and a control circuit controlling the detection electrodes, the antenna, and the storage circuit. | 10-18-2012 |
20120267751 | INTERPOSER HAVING MOLDED LOW CTE DIELECTRIC - A method for making an interconnection component is disclosed, including forming a plurality of metal posts extending away from a reference surface. Each post is formed having a pair of opposed end surface and an edge surface extending therebetween. A dielectric layer is formed contacting the edge surfaces and filling spaces between adjacent ones of the posts. The dielectric layer has first and second opposed surfaces adjacent the first and second end surfaces. The dielectric layer has a coefficient of thermal expansion of less than 8 ppm/° C. The interconnection component is completed such that it has no interconnects between the first and second end surfaces of the posts that extend in a lateral direction. First and second pluralities of wettable contacts are adjacent the first and second opposed surfaces. The wettable contacts are usable to bond the interconnection component to a microelectronic element or a circuit panel. | 10-25-2012 |
20120280354 | METHODS FOR FABRICATING HIGH-DENSITY INTEGRATED CIRCUIT DEVICES - An integrated circuit device having a plurality of lines is described in which the widths of the lines, and the spacing between adjacent lines, vary within a small range which is independent of variations due to photolithographic processes, or other patterning processes, involved in manufacturing the device. A sequential sidewall spacer formation process is described for forming an etch mask for the lines, which results in first and second sets of sidewall spacers arranged in an alternating fashion. As a result of this sequential sidewall spacer process, the variation in the widths of the lines across the plurality of lines, and the spacing between adjacent lines, depends on the variations in the dimensions of the sidewall spacers. These variations are independent of, and can be controlled over a distribution much less than, the variation in the size of the intermediate mask element caused by the patterning process. | 11-08-2012 |
20120299145 | APPARATUS FOR THREE-DIMENSIONAL INTEGRATED CIRCUIT DEVICE FABRICATION INCLUDING WAFER SCALE MEMBRANE - Apparatus configured for the fabrication of three-dimensional integrated devices and three-dimensional integrated devices fabricated therefrom are described. A device side of a donor wafer is coated with a polymer film and exposure of a substrate side to an oxidizing plasma creates a continuous SiO | 11-29-2012 |
20120306045 | Active Tiling Placement for Improved Latch-Up Immunity - A semiconductor device includes CMP dummy tiles ( | 12-06-2012 |
20120313213 | POLYGON SHAPED POWER AMPLIFIER CHIPS - A semiconductor structure having: a wafer; and a plurality of chips disposed on the wafer, each one of the chips having a linear array of a plurality of transistors, the linear array being at an oblique angle with respect to grid lines in the wafer separating the chips. Each one of the transistors has a plurality of parallel control electrodes extending longitudinally along an axis perpendicular to the axis along which the plurality of transistors is distributed. A matching circuit is disposed on the integrated circuit chip between a corner of the integrated circuit chip and the plurality of transistors. | 12-13-2012 |
20120326263 | SEMICONDUCTOR DIODE - A semiconductor diode includes a semiconductor substrate having a lightly doped region with a first conductivity type therein. A first heavily doped region with a second conductivity type opposite to the first conductivity type is in the lightly doped region. A second heavily doped region with the first conductivity type is in the lightly doped region and is in direct contact with the first heavily doped region. A first metal silicide layer is on the semiconductor substrate and is in direct contact with the first heavily doped region. A second metal silicide layer is on the semiconductor substrate and is in direct contact with the second heavily doped region. The second metal silicide layer is spaced apart from the first metal silicide layer. | 12-27-2012 |
20120326264 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device of the present invention includes the steps of forming a single crystal semiconductor device, attaching the single crystal semiconductor device on a substrate, forming a TFT on a glass substrate, and electrically connecting the single crystal semiconductor device and the TFT. In the step of forming a single crystal semiconductor device, an alignment mark is provided at the single crystal semiconductor device. In the step of attaching a single crystal semiconductor device, the single crystal semiconductor device is positioned and attached on the glass substrate based on the machining accuracy of an attachment device. In the step of forming a TFT, the TFT is positioned and provided on the glass substrate based on the alignment mark provided at the single crystal semiconductor device. | 12-27-2012 |
20130001735 | THERMALLY CONDUCTIVE SUBSTRATE FOR GALVANIC ISOLATION - A galvanic isolation integrated circuit system includes a semiconductor substrate; a layer of thermally conductive material, e.g., CVD nano- or poly-diamond thin film or boron nitride CVD thin film, formed over the semiconductor substrate; a first integrated circuit structure formed over the layer of thermally conductive material; a second integrated circuit structure formed over the layer of thermally conductive material, the second integrated circuit structure being spaced apart from the first integrated circuit structure; and a galvanic isolation structure formed over the layer of thermally conductive material between the first and second integrated circuit structures and connected to the first integrated circuit structure and the second integrated circuit structure. | 01-03-2013 |
20130001736 | HIGH-VOLTAGE INTEGRATED CIRCUIT DEVICE - A high-voltage integrated circuit device has formed therein a high-voltage junction terminating region that is configured by a breakdown voltage region formed of an n-well region, a ground potential region formed of a p-region, a first contact region and a second contact region. An opposition section of the high-voltage junction terminating region, whose distance to an intermediate-potential region formed of a p-drain region is shorter than those of other sections, is provided with a resistance higher than those of the other sections. Accordingly, a cathode resistance of a parasitic diode formed of the p-region and the n-well region increases, locally reducing the amount of electron holes injected at the time of the input of a negative-voltage surge. As a result, an erroneous operation or destruction of a logic part of a high-side circuit can be prevented when the negative-voltage surge is applied to an H-VDD terminal or a Vs terminal. | 01-03-2013 |
20130009274 | MEMORY HAVING THREE-DIMENSIONAL STRUCTURE AND MANUFACTURING METHOD THEREOF - Provided are a memory having a 3-dimensional structure and a method of fabricating the same, by which high integration density can be obtained. A contact region connected to a word line is formed to extend from a cell region in a first direction. A plurality of step difference layers constituting the contact region are formed to have step differences in a second direction different from the first direction. Also, provided is a method of fabricating a nonvolatile memory by which step differences are formed in a direction substantially perpendicular to a direction in which active regions are aligned. An insulating layer and etching layers are sequentially formed. By performing a selective etching process and pattern transfer, step differences are formed in a direction perpendicular to a direction in which multilayered active layers are disposed. Furthermore, the etching layers are removed using a wet etching process, and an oxide-nitride-oxide (ONO) layer and conductive layers are provided on the multilayered active layers having exposed side surfaces to form cell transistors. Thus, a memory having a high integration density is fabricated. | 01-10-2013 |
20130009275 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND TERMINAL STRUCTURE OF STANDARD CELL - A semiconductor integrated circuit device includes a first standard cell and a second standard cell adjacent to the first standard cell in a first direction. An interconnect is provided to extend in the first direction to electrically connect input and output terminal portions, which extend in a second direction orthogonal to the first direction. The output terminal portion extends in a first sub-direction of the second direction from a region connected to the interconnect, but not in a second sub-direction opposite to the first sub-direction. The input terminal portion extends in a second sub-direction of the second direction from a region connected to the interconnect, but not in the first sub-direction. | 01-10-2013 |
20130015551 | METHOD FOR FABRICATING MEMORY DEVICE WITH BURIED DIGIT LINES AND BURIED WORD LINESAANM Wang; Kuo-ChenAACI Chiayi CityAACO TWAAGP Wang; Kuo-Chen Chiayi City TW - A method for fabricating a memory array includes providing a semiconductor substrate having thereon a plurality of line-shaped active areas and intermittent line-shaped trench isolation regions between the plurality of line-shaped active areas, which extend along a first direction; forming buried word lines extending along a second direction in the semiconductor substrate, the buried word lines intersecting with the line-shaped active areas and the intermittent line-shaped trench isolation regions, wherein the second direction is not perpendicular to the first direction; forming buried digit lines extending along a third direction in the semiconductor substrate, wherein the third direction is substantially perpendicular to the second direction; and forming storage nodes at storage node sites between the buried digit lines. | 01-17-2013 |
20130043553 | DUMMY FILL TO REDUCE SHALLOW TRENCH ISOLATION (STI) STRESS VARIATION ON TRANSISTOR PERFORMANCE - An integrated circuit includes an active layer including an active pattern diffusion region. The integrated circuit further includes at least one guard band conforming to a shape of the active layer, the at least one guard band comprising a dummy diffusion layer, wherein the guard bans is spaced from the active layer at a first constant spacing in an X-axis direction and a second constant spacing in a Y-axis direction, which is perpendicular to the X-axis direction. The integrated circuit further includes a plurality of dummy diffusion patterns outside the at least one guard band. | 02-21-2013 |
20130062724 | Power Module and Power Converter Containing Power Module - A power module includes a semiconductor chip, a first coupling conductor with one main surface coupled to one main surface of the semiconductor chip, a second coupling conductor with one main surface coupled to the other main surface of the semiconductor chip, a coupling terminal supplied with electrical power from the direct current power source, and resin material to seal the semiconductor chip, and in which the resin member has a protruding section that protrudes from the space where the first and second coupling conductors are formed opposite each other, and the coupling terminal is clamped on the protruding section, and at least one of the first or second coupling conductors is coupled to a coupling terminal by way of a metallic material that melts at a specified temperature. | 03-14-2013 |
20130087880 | MEMS DEVICE AND METHOD OF MANUFACTURE - A MEMS logic device comprising agate which pivots on a torsion hinge, two conductive channels on the gate, one on each side of the torsion hinge, source and drain landing pads under the channels, and two body bias elements under the gate, one on each side of the torsion hinge, so that applying a threshold bias between one body bias element and the gate will pivot the gate so that one channel connects the respective source and drain landing pad, and vice versa. An integrated circuit with MEMS logic devices on the dielectric layer, with the source and drain landing pads connected to metal interconnects of the integrated circuit. A process of forming the MEM switch. | 04-11-2013 |
20130087881 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - An interconnect plug which connects a first circuit metal interconnect to a second circuit metal interconnect provided above the first circuit metal interconnect is disposed near a feeding plug which connects a first feeding metal interconnect to a second feeding metal interconnect provided above the first feeding metal interconnect. The feeding plug and the interconnect plug are displaced relative to each other in a direction in which the first feeding metal interconnect extends. | 04-11-2013 |
20130099348 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor memory device includes: a cell array including a plurality of first wirings, a plurality of second wirings that intersects the plurality of first wirings, and memory cells that are formed at intersections of the first wirings and the second wirings and are connected between the first and second wirings; a first contact plug that comes into contact with a side portion of the first wiring provided at a first position and extends to the first wiring provided at a second position higher than the first position in a laminated direction; and a second contact plug that comes into contact with a side portion of the second wiring provided at a third position between the first position and the second position and extends to the second wiring provided at a fourth position higher than the second position in the laminated direction. | 04-25-2013 |
20130105935 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR DESIGNING THE SAME | 05-02-2013 |
20130105936 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING IMPROVED INTERCONNECT ACCURACY NEAR CELL BOUNDARIES | 05-02-2013 |
20130105937 | SIMPLIFIED PITCH DOUBLING PROCESS FLOW | 05-02-2013 |
20130113067 | THERMAL WARP COMPENSATION IC PACKAGE - An apparatus and method for temperature induced warpage compensation in an integrated circuit package is disclosed. The apparatus consists of bonded layers of material having different thermal coefficients of expansion. The bonded layers are bonded to the top of the integrated circuit package. By appropriate choice of temperature coefficients the layers of material can compensate for either convex or concave warpage. In some embodiments, the layers of material have apertures therein allowing compensation for more complex warpages. As well, in some embodiments the top layer of material does not have a planar cross-section. A method is also disclosed for manufacturing an integrated circuit package assembly. The apparatus and method provide an alternative to methods of dealing with IC package warpage known in the art. | 05-09-2013 |
20130140667 | LOCALIZED CARRIER LIFETIME REDUCTION - A semiconductor structure includes a substrate, a first power device and a second power device in the substrate, at least one isolation feature between the first and second power device, and a trapping feature adjoining the at least one isolation feature in the substrate. | 06-06-2013 |
20130140668 | Forming Structures on Resistive Substrates - A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices. | 06-06-2013 |
20130147005 | ELECTROPLATING METHODS FOR FABRICATING INTEGRATED CIRCUIT DEVICES AND DEVICES FABRICATED THEREBY - Provided are methods of fabricating a semiconductor device and semiconductor devices fabricated thereby. In the methods, dummy recess regions may be formed between cell recess regions and a peripheral circuit region. Due to the presence of the dummy recess regions, it may be possible to reduce a concentration gradient of a suppressor contained in a plating solution near the dummy pattern region, to make the concentration of the suppressor more uniform in the cell pattern region, and to supply an electric current more effectively to the cell pattern region. As a result, a plating layer can be more uniformly formed in the cell pattern region, without void formation therein. | 06-13-2013 |
20130147006 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor memory includes a memory cell array area provided with first and second memory cells and having a first active area and a first element isolation area constituting a line & space structure, and having a floating gate electrode and a control gate electrode in the first active area, a word line contact area adjacent to the memory cell array area and having a second active area, first and second word lines with a metal silicide structure, functioning respectively as the control gate electrodes of the first and second memory cells and arranged to straddle the memory cell array area and the word line contact area. A dummy gate electrode is arranged just below the first and second word lines in the second active area. | 06-13-2013 |
20130161781 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed, which can improve device characteristics by increasing a process margin between an active region and a storage node contact. The semiconductor device includes an active region, a device isolation film formed to have a lower height than the active region, and exposing an upper part of the active region, and a barrier pattern formed at a sidewall of the exposed active region of an upper part of the device isolation film. | 06-27-2013 |
20130168800 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device that includes first and second isolation patterns disposed on a substrate. Alternately stacked interlayer insulating patterns and a conductive patterns are disposed on a surface of the substrate between the first and second isolation patterns. A support pattern penetrates the conductive patterns and the interlayer insulating patterns and has a smaller width than the first and second isolation patterns. First and second vertical structures are disposed between the first isolation and the support pattern and penetrate the conductive patterns and the interlayer insulating patterns. A second vertical structure is disposed between the second isolation pattern and the support pattern and penetrates the conductive patterns and the interlayer insulating patterns. A distance between top and bottom surfaces of the support pattern is greater than a distance between a bottom surface of the support pattern and the surface of the substrate. | 07-04-2013 |
20130175658 | TONE INVERSION WITH PARTIAL UNDERLAYER ETCH FOR SEMICONDUCTOR DEVICE FORMATION - A structure for tone inversion for integrated circuit fabrication includes a substrate; a partially etched underlayer comprising a first pattern located over the substrate, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; and an image reversal material (IRM) layer located over the partially etched underlayer. | 07-11-2013 |
20130181320 | Manufacturing Techniques for Workpieces with Varying Topographies - Some embodiments relate to a method for processing a workpiece. In the method, an anti-reflective coating layer is provided over the workpiece. A first patterned photoresist layer, which has a first photoresist tone, is provided over the anti-reflective coating layer. A second patterned photoresist layer, which has a second photoresist tone opposite the first photoresist tone, is provided over the first patterned photoresist layer. An opening extends through the first and second patterned photoresist layers to allow a treatment to be applied to the workpiece through the opening. Other embodiments are also disclosed. | 07-18-2013 |
20130207225 | MEMORY CELL PROFILES - Examples of the present disclosure provide devices and methods for processing a memory cell. A method embodiment includes removing a key-hole shaped column from a material, to define a profile for the memory cell. The method also includes partially filling the key-hole shaped column with a first number of materials. The method further includes filling the remaining portion of the key-hole shaped column with a second number of materials. | 08-15-2013 |
20130214379 | PHOTOSENSITIVE RESIN COMPOSITION, PHOTOSENSITIVE RESIN COMPOSITION FILM, AND SEMICONDUCTOR DEVICE USING THE PHOTOSENSITIVE RESIN COMPOSITION OR PHOTOSENSITIVE RESIN COMPOSITION FILM - A photosensitive resin composition contains: (a) an alkali-soluble polyimide; (b) a compound which has two or more epoxy groups and/or oxetanyl groups in each molecule; and (c) a quinonediazide compound. Less than 10 parts by weight of an acrylic resin is contained per 100 parts by weight of the polyimide (a); and the content of the compound (b) is not less than 20 parts by weight per 100 parts by weight of the polyimide (a). | 08-22-2013 |
20130214380 | AREA AND POWER SAVING STANDARD CELL METHODOLOGY - A semiconductor integrated circuit including a circuit for adaptive power supply regulation and designed using a process that increases operating speed used for characterizing circuit operation at a slow corner. In some embodiments a slow corner voltage is set to a higher than expected level for timing analysis performed by automated design tools. | 08-22-2013 |
20130228892 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor device includes a semiconductor substrate, isolation regions disposed in the semiconductor substrate, and device regions disposed between the isolation regions in the semiconductor substrate. The device further includes a first line disposed on the device regions and the isolation regions, a line width of the first line on the isolation regions being larger than a line width of the first line on the device regions. | 09-05-2013 |
20130241025 | ELECTRONIC SYSTEM HAVING INCREASED COUPLING BY USING HORIZONTAL AND VERTICAL COMMUNICATION CHANNELS - An embodiment of an electronic system may be provided so as to have superior coupling by implementing a communication mechanism that provides at least for horizontal communication for example, on the basis of wired and/or wireless communication channels, in the system. Hence, by enhancing vertical and horizontal communication capabilities in the electronic system, a reduced overall size may be achieved, while nevertheless reducing complexity in PCBs coupled to the electronic system. In this manner, overall manufacturing costs and reliability of complex electronic systems may be enhanced. | 09-19-2013 |
20130249045 | SEMICONDUCTOR DEVICES WITH STRESS RELIEF LAYERS AND METHODS OF MANUFACTURING THE SAME - A semiconductor device having a via structure in a stress relief layer is provided. The semiconductor device may include an isolation layer on the circuit region, a stress relief layer on the via region, and a via structure in the stress relief layer and the substrate. The stress relief layer may have a thickness larger than that of the isolation layer and a stepped cross section. | 09-26-2013 |
20130256827 | EFFICIENT PITCH MULTIPLICATION PROCESS - Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. A photoresist layer is patterned to simultaneously define mask elements in the array, interface and periphery areas. The pattern is transferred to an amorphous carbon layer. Spacers are formed on the sidewalls of the patterned amorphous carbon layer. Protective material is deposited and patterned to expose mask elements in the array region and in parts of the interface or periphery areas. Exposed amorphous carbon is removed, leaving free-standing spacers in the array region. The protective material is removed, leaving a pattern of pitch multiplied spacers in the array region and non-pitch multiplied mask elements in the interface and periphery areas. The pattern is transferred to a hard mask layer, through which the substrate is etched. | 10-03-2013 |
20130264675 | APPARATUS FOR FORMING MEMORY LINES AND VIAS IN THREE DIMENSIONAL MEMORY ARRAYS USING DUAL DAMASCENE PROCESS AND IMPRINT LITHOGRAPHY - A memory layer in a three-dimensional memory array is provided. The memory layer includes a plurality of memory lines and vias formed by a damascene process using an imprint lithography template having a plurality of depths, wherein at least one depth corresponds to the memory lines and wherein at least one depth corresponds to the vias, and a plurality of memory cells operatively coupled to the memory lines. Numerous other aspects are disclosed. | 10-10-2013 |
20130270670 | SEMICONDUCTOR PACKAGE WITH THROUGH SILICON VIA INTERCONNECT - The invention provides a semiconductor package with a through silicon via (TSV) interconnect. An exemplary embodiment of the semiconductor package with a TSV interconnect includes a semiconductor substrate, having a front side and a back side. A contact array is disposed on the front side of the semiconductor substrate. An isolation structure is disposed in the semiconductor substrate, underlying the contact array. The TSV interconnect is formed through the semiconductor substrate, overlapping with the contact array and the isolation structure. | 10-17-2013 |
20130285190 | Layout of a MOS Array Edge with Density Gradient Smoothing - A multi-step density gradient smoothing layout style is disclosed in which a plurality of unit cells are arranged into an array with a feature density. One or more edges of the array is bordered by a first edge sub-array which has a feature density that is less than the feature density of the array. The first edge sub-array is bordered by second edge sub-array which has a feature density that is less than the feature density of the first edge sub-array, and is approaching that of the background circuitry. | 10-31-2013 |
20130285191 | POWER CONVERSION APPARATUS - The power conversion apparatus includes semiconductor modules and a circuit board on which a control circuit is formed. Each semiconductor module includes signal terminals electrically connected to the circuit board. The signal terminals of each semiconductor module are arranged in a line so as to form a terminal row along a first direction. The semiconductor modules are grouped into upper arm semiconductor modules and lower arm semiconductor modules each connected to a corresponding one of the upper arm semiconductor module. Upper arm terminal rows as the terminal rows of the upper arm semiconductor modules and lower arm terminal rows as the terminal rows of the lower arm semiconductor modules are arranged in a staggered manner along a second direction perpendicular to the first direction and to a third direction in which the signal terminals of the semiconductor modules project, the first, second and third directions being perpendicular to one another. | 10-31-2013 |
20130285192 | LOW NOISE MEMORY ARRAY - A circuit compatible with dynamic random access memories (DRAM) and static random access memories (SRAM) is disclosed. The circuit includes a substrate having a first conductivity type. A trench isolation region ( | 10-31-2013 |
20130313677 | STRUCTURE FOR PICKING UP A COLLECTOR AND MANUFACTURING METHOD THEREOF - A structure for picking up a collector region is disclosed. The structure includes a pair of polysilicon stacks formed in the isolation regions and extending below the collector region; and a pair of collector electrodes contacting on the polysilicon stacks, wherein the pair of polysilicon stacks includes: a first polysilicon layer located below the isolation regions, and a second polysilicon layer located on and in contact with the first polysilicon layer, the first polysilicon layer being doped with a dopant having a higher diffusivity or higher concentration than a dopant of the second polysilicon layer, wherein a depth of the polysilicon stacks is greater than a depth of the collector region; the depth of the collector region is greater than a depth of the second polysilicon layer; and the depth of the second polysilicon layer is greater than a depth of the isolation regions. | 11-28-2013 |
20130328155 | GENERATION OF ADDITIONAL SHAPES ON A PHOTOMASK FOR A MULTIPLE EXPOSURE PROCESS - The disclosed aspects relate to controlling density of photomasks. One or more unprintable auxiliary patterns can be placed near a mask feature as well as onto a location of a feature of the main pattern. If a density is measured and is not within an acceptable density range, one or more printable auxiliary patterns can be replaced with unprintable auxiliary patterns and/or one or more unprintable auxiliary patterns can be replaced with printable auxiliary patterns. The disclosed aspects can be utilized to create a photomask and/or a semiconductor device, such as a large scale integrated circuit device, that comprises the photomask. | 12-12-2013 |
20130328156 | DESIGN SUPPORT METHOD, RECORDING MEDIUM STORING DESIGN SUPPORT PROGRAM AND SEMICONDUCTOR DEVICE - A design support method includes: selecting, by a computer, a power feed point of an integrated semiconductor circuit on a first board model in which a power supply layer and a ground layer are stacked; determining a first placement position of a first protrusion portion from the first board model on a side of the first board model, the first protrusion portion being corresponding to the power feed point; determining a second placement position of a second protrusion portion from the first board model on the side of the first board model, the second protrusion portion provided so as to separate from the first placement position by a distance; and placing the first protrusion portion and the second protrusion portion on the first placement position and the second placement position, respectively. | 12-12-2013 |
20130341753 | Three-dimensional array structure for memory devices - A disclosed memory device includes a three-dimension array structure that includes memory layers and transistor structures disposed between the memory layers. Each memory layer is connected to a common electrode, and each transistor structure includes transistors that share common column structures and common base structures. The transistors also each include a connector structure that is spaced apart from a common column structure by a common base structure. | 12-26-2013 |
20140001595 | Layout Architecture for Performance Improvement | 01-02-2014 |
20140035091 | Electrostatic Discharge Protection Circuit Including a Distributed Diode String - An integrated circuit includes first and second terminals. The integrated circuit further includes a first plurality of diodes arranged in series between the first terminal and a power supply terminal and a second plurality of diodes arranged in series between the second terminal and the power supply terminal. The integrated circuit also includes a conductor configured to couple a first node within the first plurality of diodes to a second node within the second plurality of diodes. The first node is located between a first diode of the first plurality of diodes and a last diode of the first plurality of diodes, and the second node is located between a first diode of the second plurality of diodes and a last diode of the second plurality of diodes. | 02-06-2014 |
20140042585 | SYSTEM FOR DESIGNING A SEMICONDUCTOR DEVICE, DEVICE MADE, AND METHOD OF USING THE SYSTEM - This disclosure relates to a method of making a semiconductor device. The method includes comparing a schematic design of the semiconductor device to a layout design of the semiconductor device. The method further includes generating layout style information based on the layout design and generating array edge information based on the layout design and the schematic design. The method further includes selectively revising the layout design using smart dummy insertion using the layout style information and the array edge information. The method further includes performing a design rule check on the revised layout design using the layout style information and the array edge information. This disclosure also relates to a system for making a semiconductor device and a semiconductor device. | 02-13-2014 |
20140048904 | Semiconductor Device, Integrated Circuit and Manufacturing Method Thereof - One embodiment of a semiconductor device includes a semiconductor body with a first side and a second side opposite to the first side. The semiconductor device further includes a first contact trench extending into the semiconductor body at the first side. The first contact trench includes a first conductive material electrically coupled to the semiconductor body adjoining the first contact trench. The semiconductor further includes a second contact trench extending into the semiconductor body at the second side. The second contact trench includes a second conductive material electrically coupled to the semiconductor body adjoining the second contact trench. | 02-20-2014 |
20140061849 | THREE-DIMENSIONAL DEVICES HAVING REDUCED CONTACT LENGTH - Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with strings of memory cells formed on the alternating levels. One such apparatus includes a memory array formed substantially within a cavity of a substrate. Peripheral circuitry can be formed adjacent to a surface of the substrate and adjacent to the memory array. Additional apparatuses and methods are described. | 03-06-2014 |
20140070357 | SOI DEVICE WITH EMBEDDED LINER IN BOX LAYER TO LIMIT STI RECESS - A semiconductor substrate having an isolation region and method of forming the same. The method includes the steps of providing a substrate having a substrate layer, a buried oxide (BOX), a silicon on insulator (SOI) layer, a pad oxide layer, and a pad nitride layer, forming a shallow trench region, etching the pad oxide layer to form ears and etching the BOX layer to form undercuts, depositing a liner on the shallow trench region, depositing a soft mask over the surface of the shallow trench region, filling the shallow trench region, etching the soft mask so that it is recessed to the top of the BOX layer, etching the liner off certain regions, removing the soft mask, and filling and polishing the shallow trench region. The liner prevents shorting of the semiconductor device when the contacts are misaligned. | 03-13-2014 |
20140070358 | METHOD OF TAILORING SILICON TRENCH PROFILE FOR SUPER STEEP RETROGRADE WELL FIELD EFFECT TRANSISTOR - A methodology is disclosed enabling the formation of silicon trench profiles for devices, such as SSRW FETs, having a resultant profile that enables desirable epitaxial growth of semiconductor materials. Embodiments include forming a trench in a silicon wafer between STI regions, thermally treating the silicon surfaces of the trench, and forming Si:C in the trench. The process eliminates a need for an isotropic silicon etch to achieve a desirable flat surface. Further, the flat bottom surface provides a desirable surface for epitaxial growth of semiconductor materials, such as Si:C. | 03-13-2014 |
20140070359 | SEMICONDUCTOR MEMORY ARRAY STRUCTURE - A memory array includes a rhomboid-shaped AA region surrounded by a first and second STI structures. The first STI structure extends along a first direction on the longer sides of the rhomboid-shaped AA region and has a depth d1. The second STI structure extends along the second direction on the shorter sides of the rhomboid-shaped AA region and has two depths: d2 and d3, wherein d1 and d2 are shallower than d3. | 03-13-2014 |
20140077330 | THREE-DIMENSIONAL INTEGRATED CIRCUIT DEVICE USING A WAFER SCALE MEMBRANE - A donor wafer containing integrated semiconductor device. The donor wafer has a donor wafer membrane portion that has a device layer and a buried insulating layer. The donor wafer membrane portion has a number of integrated semiconductor devices where each integrated semiconductor device within the plurality of semiconductor devices corresponds to a die formed on the donor wafer. The donor wafer membrane portion has a diameter of at least 200 mm. The donor wafer has a crystalline substrate that is substantially removed from an area of the donor wafer membrane portion such that the device layer and the buried insulating layer of the donor wafer membrane in the area is configured to conform to a pattern specific topology on an acceptor surface. The donor wafer further has a support structure attached to regions of the donor wafer that are outside of the donor wafer membrane portion. | 03-20-2014 |
20140077331 | DIODE STRUCTURES USING FIN FIELD EFFECT TRANSISTOR PROCESSING AND METHOD OF FORMING THE SAME - A method of forming one or more diodes in a fin field-effect transistor (FinFET) device includes forming a hardmask layer having a fin pattern, said fin pattern including an isolated fin area, a fin array area, and a FinFET area. The method further includes etching a plurality of fins into a semiconductor substrate using the fin pattern, and depositing a dielectric material over the semiconductor substrate to fill spaces between the plurality of fins. The method further includes planarizing the semiconductor substrate to expose the hardmask layer. The method further includes implanting a p-type dopant into the fin array area and portions of the FinFET area, and implanting an n-type dopant into the isolated fin area, a portion of the of fin array area surrounding the p-well and portions of the FinFET area. The method further includes annealing the semiconductor substrate. | 03-20-2014 |
20140103482 | SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNELS AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern. | 04-17-2014 |
20140110816 | SEMICONDUCTOR DEVICES - Provided are semiconductor devices and methods of fabricating the same. In methods of forming the same, an etch stop pattern and a separate spacer can be formed on a sidewall of a bit line contact, wherein the etch stop pattern and the separate spacer each comprise material having an etch selectivity relative to an oxide. A storage node contact plug hole can be formed so that the etch stop pattern and the separate spacer form a portion of a sidewall of the storage node contact plug hole spaced apart from the bit line contact. The storage node contact plug hole can be cleaned to remove a natural oxide formed in the storage node contact plug hole. Related devices are also disclosed. | 04-24-2014 |
20140117488 | PATTERN DECOMPOSITION LITHOGRAPHY TECHNIQUES - Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may he arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes. | 05-01-2014 |
20140117489 | SUB-SECOND ANNEALING LITHOGRAPHY TECHNIQUES - Techniques are disclosed for sub-second annealing a lithographic feature to, for example, tailor or otherwise selectively alter its profile in one, two, or three dimensions. Alternatively, or in addition to, the techniques can be used, for example, to smooth or otherwise reduce photoresist line width/edge roughness and/or to reduce defect density. In some cases, the sub-second annealing process has a time-temperature profile that can effectively change the magnitude of resist shrinkage in one or more dimensions or otherwise modify the resist in a desired way (e.g., smooth the resist). The techniques may be implemented, for example, with any type of photoresist (e.g., organic, inorganic, hybrid, molecular photoresist materials) and can be used in forming, for instance, processor microarchitectures, memory circuitry, logic arrays, and numerous other digital/analog/hybrid integrated semiconductor devices. | 05-01-2014 |
20140131829 | ISOLATION STRUCTURES AND METHODS OF FORMING THE SAME - A method of forming of a semiconductor structure has isolation structures. A substrate having a first region and a second region is provided. The first region and the second region are implanted with neutral dopants to form a first etching stop feature and a second stop feature in the first region and the second region, respectively. The first etching stop feature has a depth D | 05-15-2014 |
20140131830 | SOLID STATE DEVICES HAVING FINE PITCH STRUCTURES - In various embodiments, a method for forming a memory array includes forming a plurality of rows and columns of hardmask material, etching holes in the one or more layers of insulating material using the combined masking properties of the rows of hardmask material and the columns of hardmask material, and forming memory cells in the holes. The corners of the holes can be rounded. | 05-15-2014 |
20140145293 | INTEGRATED CIRCUIT HAVING IMPROVED RADIATION IMMUNITY - An integrated circuit having improved radiation immunity is described. The integrated circuit comprises a substrate; a P-well formed on the substrate and having N-type transistors of a memory cell; and an N-well formed on the substrate and having P-type transistors of the memory cell; wherein the N-well has minimal dimensions for accommodating the P-type transistors. | 05-29-2014 |
20140145294 | WAFER SEPARATION - A method is provided for separation of a wafer into individual ICs. Channels are formed in the one or more metallization layers on a front-side of the wafer along respective lanes. The lanes are located between the ICs and extend between a front-side of the metallization layers and a backside of the substrate. A backside of the substrate is thinned, and laser pulses are applied via the backside of the substrate to change the crystalline structure of the silicon substrate along the lanes. The plurality of portions in the silicon substrate and the channels are configured to propagate cracks in the silicon substrate along the lanes during expansion of the IC wafer. The channels assist to mitigate propagation of cracks outside of the lanes in the metallization layers during expansion of the IC wafer. | 05-29-2014 |
20140167206 | SHALLOW TRENCH ISOLATION STRUCTURE AND METHOD OF MANUFACTURE - A semiconductor device includes a substrate and a first and second plurality of stack structures arranged over the substrate. The first and second plurality of stack structures are separated by a gap. The substrate includes a first trench between the structures of the first plurality of stack structures, a second trench between the structures of the second plurality of stack structures, and a third trench in the gap. A depth of the first trench is less than a depth of the third trench. | 06-19-2014 |
20140175594 | ACTIVE PAD PATTERNS FOR GATE ALIGNMENT MARKS - Methods for forming RX pads having gate alignment marks configured to enable noise reduction between layers while resulting in little or no non-uniformity of CMP processes for the IC, and the resulting devices, are disclosed. Embodiments include: providing, on a substrate, a RX pad having a SPM with a SPM horizontal and vertical positions at horizontal and vertical midpoints, respectively, of the first RX pad; providing a second RX pad abutting the first RX pad and a first STI pad abutting the second RX pad, each having a vertical midpoint at the SPM vertical position; forming a first gate alignment mark on the second RX pad and having vertical endpoints horizontally aligned with vertical endpoints of the second RX pad; and forming a second gate alignment mark on the first STI pad and having vertical endpoints horizontally aligned with vertical endpoints of the first STI pad. | 06-26-2014 |
20140175595 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a semiconductor device, including: a substrate; a plurality of first semiconductor elements and a second semiconductor element arranged on a mount area of the substrate; an external electrode to supply electricity to the first and second semiconductor elements; and a frame of reflective material formed at a periphery of the mount area. Extensions of the first external electrodes are formed at the inner side of the plurality of wirings, and the first external electrodes are formed along the periphery of the mount area at the outer side of at least one of the second external electrodes or the wiring connected to the second external electrodes, and electrodes of the plurality of first semiconductor elements are electrically connected to the pair of first external electrodes by a bonding wire that bridges across at least one of the pair of the second external electrodes or the wiring electrically connected to the pair of second external electrodes with intervening a part of the frame therebetween. | 06-26-2014 |
20140264715 | METHODS AND APPARATUS FOR CONGESTION-AWARE BUFFERING USING VOLTAGE ISOLATION PATHWAYS FOR INTEGRATED CIRCUIT DESIGNS WITH MULTI-POWER DOMAINS - A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred. | 09-18-2014 |
20140264716 | SEMICONDUCTOR WAFER, SEMICONDUCTOR PROCESS AND SEMICONDUCTOR PACKAGE - The present invention provides a semiconductor wafer, semiconductor package and semiconductor process. The semiconductor wafer includes a substrate, at least one metal segment and a plurality of dielectric layers. The semiconductor wafer is defined as a plurality of die areas and a plurality of trench areas, each of the die areas has an integrated circuit including a plurality of patterned metal layers disposed between the dielectric layers. The trench areas are disposed between the die areas, and the at least one metal segment is disposed in the trench area and insulated from the integrated circuit of the die area. | 09-18-2014 |
20140264717 | Method of Fabricating a FinFET Device - A method of forming a fin structure of a semiconductor device includes providing a substrate, creating a mandrel pattern over the substrate, depositing a first spacer layer over the mandrel pattern, and removing portions of the first spacer layer to form first spacer fins. The method also includes performing a first fin cut process to remove a subset of the first spacer fins, depositing a second spacer layer over the un-removed first spacer fins, and removing portions of the second spacer layer to form second spacer fins. The method further includes forming fin structures, and performing a second fin cut process to remove a subset of the fin structures. | 09-18-2014 |
20140264718 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The wiring comprises a plurality of second conductive layers extending upwardly from an upper surface of the first conductive layers comprising the stepped portion. The plurality of second conductive layers are formed such that upper ends thereof are aligned with a surface parallel to the substrate, and such that a diameter thereof decreases from the upper end thereof to a lower end thereof. The plurality of second conductive layers are formed such that the greater a length thereof in the perpendicular direction, the larger a diameter of the upper end thereof. | 09-18-2014 |
20140284758 | SELF-ALIGNED BIPOLAR JUNCTION TRANSISTORS - Device structures, fabrication methods, and design structures for a bipolar junction transistor. An intrinsic base is formed on the substrate, a terminal is formed on the intrinsic base, and an extrinsic base is formed that is arranged in juxtaposition with the intrinsic base on the substrate. The intrinsic base and terminal are respectively comprised of first and second semiconductor materials. | 09-25-2014 |
20140291798 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction. | 10-02-2014 |
20140299963 | INTERPOSER DEVICE - An interposer device The invention relates to an interposer device comprising a doped silicon substrate ( | 10-09-2014 |
20140312454 | Structure Designs and Methods for Integrated Circuit Alignment - Devices and methods for pattern alignment are disclosed. The device includes an assembly isolation region, a seal ring region around the assembly isolation region, and a scribe line region around the seal ring region, and a plurality of die alignment marks disposed within the seal ring region that are alternately disposed adjacent the scribe line region and the assembly isolation region. | 10-23-2014 |
20140319647 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING DIFFERENTIAL AMPLIFIER AND METHOD OF ARRANGING THE SAME - A semiconductor integrated circuit comprises: a transistor region having a center line; a first block arranged in one side of the center line of the transistor region, and comprising a plurality of first and second groups each having a plurality of first and second segment transistors constituting first and second transistors of a differential amplifier; and a second block arranged in the other side of the center line, and having an arrangement corresponding to the arrangement of the first and second groups of the first block. | 10-30-2014 |
20140327105 | ELECTROSTATIC DISCHARGE DIODE - A method includes thinning a back-side of a substrate to expose a portion of a first via that is formed in the substrate. The method also includes forming a first diode at the back-side of the substrate. The first diode is coupled to the first via. | 11-06-2014 |
20140339672 | WAFER DIE SEPARATION - A method of separating dice of a singulated wafer that is supported on a dicing tape sheet is disclosed. The method may include attaching the dicing tape sheet to a ring frame; relatively raising a portion of the dicing tape sheet supporting the wafer with respect to the ring frame; and attaching support tape to the ring frame and the dicing tape sheet. | 11-20-2014 |
20140339673 | WAFER PROCESSING - A method of separating dies of a singulated wafer is disclosed. The method may include supporting the singulated wafer on a supporting portion of a sheet of dicing tape that has a first ring attached to a first annular portion of the sheet that encompasses the supporting portion. The method may further include radially expanding the supporting portion by relative axial displacement of the supporting portion with respect to the first ring. The method may also include further expanding the supporting portion by radially outward displacement of a support surface that supports at least an annular portion of the sheet. The method may also include attaching a second ring to a second annular portion of the sheet. | 11-20-2014 |
20140374872 | Controlled Buckling Structures in Semiconductor Interconnects and Nanomembranes for Stretchable Electronics - In an aspect, the present invention provides stretchable, and optionally printable, components such as semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed, and related methods of making or tuning such stretchable components. Stretchable semiconductors and electronic circuits preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention are adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices. | 12-25-2014 |
20140374873 | METHODS AND APPARATUS FOR CONGESTION-AWARE BUFFERING USING VOLTAGE ISOLATION PATHWAYS FOR INTEGRATED CIRCUIT DESIGNS WITH MULTI-POWER DOMAINS - A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred. | 12-25-2014 |
20150028446 | WAFER DICING WITH WIDE KERF BY LASER SCRIBING AND PLASMA ETCHING HYBRID APPROACH - Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, approaches for wafer dicing with wide kerf by using a laser scribing and plasma etching hybrid approach are described. For example, a method of dicing a semiconductor wafer including a plurality of integrated circuits separated by dicing streets involves forming a mask above the semiconductor wafer, the mask having a layer covering and protecting the integrated circuits. The method also involves patterning the mask with a laser scribing process to provide a patterned mask having a pair of parallel gaps for each dicing street, exposing regions of the semiconductor wafer between the integrated circuits. Each gap of each pair of parallel gaps is separated by a distance. The method also involves etching the semiconductor wafer through the gaps in the patterned mask to singulate the integrated circuits. | 01-29-2015 |
20150061068 | NON-VOLATILE MEMORY DEVICE, METHOD FOR FABRICATING PATTERN ON WAFER AND METHOD FOR MANUFACTURING NON-VOLATILE MEMORY DEVICE USING SAME - According to an embodiment, a method for fabricating a pattern includes forming a mask covering a first layer, and a second layer selectively provided on the first layer, and forming a groove dividing the first layer and the second layer using the mask. The mask includes a first portion formed on a region of the first layer on a first side of the second layer, a second portion formed on a region of the first layer on a second side of the second layer opposite to the first side, first extending parts extending over the second layer from the first portion toward the second portion, and second extending parts extending over the second layer from the second portion toward the first portion. Each of the second extending parts is located between the first extending parts adjacent to each other. | 03-05-2015 |
20150069568 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes a semiconductor substrate and a memory array. The semiconductor substrate has a first face. The memory array region is provided on the first face and includes a plurality of semiconductor pillars. The semiconductor pillars extend in a first direction perpendicular to the first face. Each of the semiconductor pillars includes a plurality of memory cells connected in series. Each of the semiconductor pillars is disposed at the nodes of a honeycomb shape when viewed in the first direction. When the semiconductor pillars are projected onto a first plane along the first and second directions perpendicular to the first direction, a component in the second direction of an interval between the semiconductor pillars has first and second intervals repeated alternately. The second interval is an integer multiple of the first interval greater than or equal to 2. | 03-12-2015 |
20150115392 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a bit line disposed over a semiconductor substrate, a supporting film being perpendicular to the bit line, a first storage node contact disposed at a lower part of a region disposed between the bit line and the supporting film, and a second storage node contact having a line shape, disposed over the first storage node contact and the bit line, isolated by the supporting film, and patterned in a diagonal direction across the bit line. | 04-30-2015 |
20150115393 | METHODS OF STRESS BALANCING IN GALLIUM ARSENIDE WAFER PROCESSING - Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. To avoid warpage, the tensile stress of a conductive layer deposited onto a GaAs substrate can be offset by depositing a compensating layer having negative stress over the GaAs substrate. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices. | 04-30-2015 |
20150303263 | METHOD FOR LOW TEMPERATURE BONDING AND BONDED STRUCTURE - A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO | 10-22-2015 |
20150311142 | SEMICONDUCTOR SYSTEM, DEVICE AND STRUCTURE WITH HEAT REMOVAL - A 3D device including: a first layer including first transistors, the first layer overlaid by at least one interconnection layer; a second layer including second transistors, the second layer overlaying the interconnection layer; a plurality of electrical connections connecting the second transistors with the interconnection layer; and at least one thermally conductive and electrically non-conductive contact, where the at least one thermally conductive and electrically non-conductive contact thermally connects the second layer to a top or bottom surface of the 3D device. | 10-29-2015 |
20150318348 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a substrate, a dam element, a first isolation layer, a second isolation layer, and a conductive layer. The substrate has a conductive pad, a trench, a sidewall, a first surface, and a second surface opposite to the first surface. The conductive pad is located on the second surface. The trench has a first opening at the first surface, and has a second opening at the second surface. The dam element is located on the second surface and covers the second opening. The dam element has a concave portion that is at the second opening. The first isolation layer is located on a portion of the sidewall. The second isolation layer is located on the first surface and the sidewall that is not covered by the first isolation layer, such that an interface is formed between the first and second isolation layers. | 11-05-2015 |
20150325440 | Method for Forming a Semiconductor Device and Semiconductor Device - A method for forming a semiconductor device includes depositing an epitaxial layer on a semiconductor substrate, forming an oxygen diffusion region within the epitaxial layer by oxygen diffusion from the semiconductor substrate into a part of the epitaxial layer and tempering at least the oxygen diffusion region of the epitaxial layer at a temperature between 400° C. and 480° C. for more than 15 minutes. | 11-12-2015 |
20150325527 | RADIUSED ALIGNMENT POST FOR SUBSTRATE MATERIAL - A method includes growing a substrate material that includes an integrated circuit. The method includes forming an alignment post on the substrate material and forming a radiused top portion on the alignment post to enable alignment of a connector to the substrate material. | 11-12-2015 |
20150325532 | SEMICONDUCTOR INTEGRATED DEVICE INCLUDING FINFET DEVICE AND PROTECTING STRUCTURE - A semiconductor integrated device includes a substrate having an active region defined thereon, a plurality of active fins positioned in the active region, and a plurality of first protecting fins surrounding the active region. Each of the plurality of active fins extends along a first direction and includes a first length along the first direction. The plurality of first protecting fins extend along the first direction. One of the plurality of first protecting fins immediately adjacent to the active region has a second length along the first direction, and the second length is longer than the first length. | 11-12-2015 |
20150357279 | LAYOUT DESIGN FOR MANUFACTURING A MEMORY CELL - A layout design usable for manufacturing a memory cell includes a first and second active area layout pattern associated with forming a first and second active area, an isolation region outside the first and second active area, a first polysilicon layout pattern associated with forming a first polysilicon structure, a second polysilicon layout pattern associated with forming a second polysilicon structure, a first interconnection layout pattern associated with forming a first interconnection structure, and a second interconnection layout pattern associated with forming a second interconnection structure. The first active area does not overlap the second active area. The first polysilicon layout pattern overlaps the first active area layout pattern. The second polysilicon layout pattern overlaps the first active area layout pattern and the second active area layout pattern. The first interconnection layout pattern overlaps the second active area layout pattern. The second interconnection layout pattern overlaps the isolation region. | 12-10-2015 |
20150364461 | ESD PROTECTION DEVICE - An ESD protection device includes a zener diode, and a series circuit of diodes and a series circuit of diodes that are connected in parallel with the zener diode. At the connection point between the diodes, an Al electrode film is formed on the surface of a Si substrate, and at the connection point between diodes, an Al electrode film is formed on the surface of the Si substrate. The diodes are formed on the surface of the Si substrate, and the diodes are formed in the thickness direction of the Si substrate. The Si substrate has a longitudinal direction and a shorter direction orthogonal to the longitudinal direction in planar view, and the Al electrode films are formed respectively at both ends in the shorter direction of the Si substrate. Thus, provided is an ESD protection device which suppresses the ESL, and keeps the clamp voltage low. | 12-17-2015 |
20150371941 | SEMICONDUCTOR DEVICE - An ESD protection device includes a Si substrate and a rewiring layer. The rewiring layer includes Ti/Cu/Ti electrodes are electrically connected through contact holes to an ESD protection circuit with Al electrodes films, which is formed at the surface of the Si substrate. The Al electrode film is electrically connected to the Ti/Cu/Ti electrode, whereas the Al electrode film is electrically connected to the Ti/Cu/Ti electrode. A diode forming region is formed between Al electrode films, whereas a diode forming region is formed between Al electrode films. The Ti/Cu/Ti electrode has no overlap with the diode forming region, whereas the Ti/Cu/Ti electrode has no overlap with the diode forming region. Thus, a semiconductor device is provided which is able to reduce the generation of parasitic capacitance, and able to be applied up to a higher frequency band. | 12-24-2015 |
20150380239 | BLOCK CO-POLYMER PHOTORESIST - An integrated circuit is made by depositing a pinning layer on a substrate. A block copolymer photoresist is formed on the pinning layer. The block copolymer has two blocks A and B that do not self-assemble under at least some annealing conditions. The exposed block copolymer photoresist is processed to cleave at least some block copolymer bonds in the exposed selected regions. The exposed pinning layer is processed to create a chemical epitaxial pattern to direct the local self assembly of the block copolymer. | 12-31-2015 |
20150380481 | CONVERSION OF STRAIN-INDUCING BUFFER TO ELECTRICAL INSULATOR - Techniques are disclosed for converting a strain-inducing semiconductor buffer layer into an electrical insulator at one or more locations of the buffer layer, thereby allowing an above device layer to have a number of benefits, which in some embodiments include those that arise from being grown on a strain-inducing buffer and having a buried electrical insulator layer. For instance, having a buried electrical insulator layer (initially used as a strain-inducing buffer during fabrication of the above active device layer) between the Fin and substrate of a non-planar integrated transistor circuit may simultaneously enable a low-doped Fin with high mobility, desirable device electrostatics and elimination or otherwise reduction of substrate junction leakage. Also, the presence of such an electrical insulator under the source and drain regions may further significantly reduce junction leakage. In some embodiments, substantially the entire buffer layer is converted to an electrical insulator. | 12-31-2015 |
20160013204 | MEMORY CELL PROFILES | 01-14-2016 |
20160033880 | PHOTOMASK INCLUDING FOCUS METROLOGY MARK, SUBSTRATE TARGET INCLUDING FOCUS MONITOR PATTERN, METROLOGY METHOD FOR LITHOGRAPHY PROCESS, AND METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE - A photomask includes a focus metrology mark region that includes a plurality of focus monitor patterns. To measure a focal variation of a feature pattern formed on a substrate, a substrate target for lithography metrology including a focus metrology mark formed on the same level as the feature pattern is used. A lithography metrology apparatus includes a projection device including a polarizer; a detection device detecting the powers of ±n-order diffracted light beams from among output beams diffracted by the focus metrology mark of a to-be-measured substrate; and a determination device which determines, from a power deviation between the ±n-order diffracted light beams, defocus experienced by the feature pattern. | 02-04-2016 |
20160064294 | SEMICONDUCTOR MANUFACTURING FOR FORMING BOND PADS AND SEAL RINGS - An integrated circuit die includes a first bond pad having a bond contact area at a first depth into a plurality of build-up layers over a semiconductor substrate of the integrated circuit die, having sidewalls that surround the bond contact area, the sidewalls extending from the first depth to a top surface of the plurality of build-up layers, and having a top portion that extends over a portion of a top surface of the plurality of build-up layers. | 03-03-2016 |
20160071798 | Semiconductor Device - A semiconductor device including a multiplicity of large current power elements with each power element divided into a multiplicity of divisional elements and arranged such that the power elements belonging to different power elements are arranged in a repetitive sequential order. The IC chip of the semiconductor device is formed to have output wires extending from the respective divisional elements connected to corresponding output pads without crossing other output wires. Arranged on the IC chip are output bumps in association with the respective output pads. A rewiring layer is provided having output coupling wires for connecting together the bumps that belong to the same power element and connecting them further to an external output electrode. | 03-10-2016 |
20160071984 | DIODE WITH INSULATED ANODE REGIONS - A diode is integrated on a semiconductor chip having anode and cathode surfaces opposite to each other. The diode comprises a cathode region extending inwardly from the cathode surface, a drift region extending between the anode surface and the cathode region, and a plurality of anode regions extending from the anode surface in the drift region. The diode further comprises a cathode electrode coupled with the cathode region, and an anode electrode that contacts one or more contacted anode regions of said anode regions and is electrically insulated from one or more floating anode regions of the anode regions. The diode is configured so that charge carriers are injected from the floating anode regions into the drift region in response to applying of a control voltage exceeding a threshold voltage. | 03-10-2016 |
20160093507 | METHOD OF LOCALIZED ANNEALING OF SEMI-CONDUCTING ELEMENTS USING A REFLECTIVE AREA - A method of making crystal semi-conducting material-based elements, including providing a support having amorphous semi-conducting material-based semi-conducting elements, the support being further provided with one or more components and with a reflective protective area configured so as to reflect a light radiation in a given wavelength range, exposing the element(s) to a laser radiation emitting in the given wavelength range so as to recrystallize the elements, the reflective protective area being arranged on the support relative to the elements and to the components so as to reflect the laser radiation and protect the components from this radiation. | 03-31-2016 |
20160093693 | METHODS FOR FORMING VERTICAL SEMICONDUCTOR PILLARS - A method for forming a semiconductor device includes providing a semiconductor structure, which includes a semiconductor substrate and a first mask layer on the substrate. The first mask layer is used to form a plurality of first trenches that extends into the substrate and extends laterally in a first direction and do not intersect each other. The first trenches are then filled with a fill material. Next, a second mask layer is formed on the semiconductor structure filled with the fill material. The second mask layer is then used to form a second plurality of trenches in the semiconductor substrate that extend laterally in a second direction and do not intersect each other. Each of the second trenches intersects at least one of the first plurality of trenches. Next, the fill material is removed to form a plurality of vertical pillars defined by intersecting first trenches and second trenches. | 03-31-2016 |
20160181174 | INTEGRATED CIRCUIT COOLING APPARATUS | 06-23-2016 |
20180025973 | CHIP | 01-25-2018 |
20190148313 | INTEGRATED CIRCUIT DEVICE | 05-16-2019 |
20190148367 | 3D CIRCUIT WITH N AND P JUNCTIONLESS TRANSISTORS | 05-16-2019 |