| Entries |
| Document | Title | Date |
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| 20100299647 | METHOD AND APPARATUS FOR MANAGING THE CONFIGURATION AND FUNCTIONALITY OF A SEMICONDUCTOR DESIGN - A method of managing the configuration, design parameters, and functionality of an integrated circuit (IC) design using a hardware description language (HDL). Instructions can be added, subtracted, or generated by the designer interactively during the design process, and customized HDL descriptions of the IC design are generated through the use of scripts based on the user-edited instruction set and inputs. The customized HDL description can then be used as the basis for generating “makefiles” for purposes of simulation and/or logic level synthesis. The method further affords the ability to generate an HDL model of a complete device, such as a microprocessor or DSP. A computer program implementing the aforementioned method and a hardware system for running the computer program are also disclosed. | 11-25-2010 |
| 20100325597 | GENERALIZED CONSTRAINT COLLECTION MANAGEMENT METHOD - Techniques are provided to allow users of Electronic Design Automation (EDA) tools to define constraint template types for efficiently associating constraints with design objects to specify design intent. Processes for creating and validating the constraints are provided by user-defined plug-ins, thereby allowing users to annotate circuit designs with constraints for proprietary layout and fabrication processes without exposing the constraints to tool vendors or competitors. The constraints are re-created from the template types whenever the circuit design is loaded into the EDA tool, so that the constraints are based upon the latest version of the template type. The constraints are also re-created when validation fails. Constraint groups are reusable in different designs, technology nodes, and processes because they automatically expand to provide the specific constraints to achieve a goal. The specific constraints in a template type can be modified as technology changes, and the modification will automatically be applied to the design objects. | 12-23-2010 |
| 20110016444 | Collaborative Environment For Physical Verification Of Microdevice Designs - A collaborative environment for performing physical verification processes on integrated circuit designs. Multiple physical verification results may be stored in a “unified” results database/directory (e.g., unified at least from a user's perspective), where results from various verification processes, such as Design-Rule-Check (DRC) processes, Layout-Versus-Schematic comparison (LVS) processes, Design-For-Manufacturing (DFM) processes Optical Proximity Correction (OPC) processes, and Optical Rule Check (ORC) processes are accessible from the same style of user interface, which may be a graphical user interface. The basic abilities for design team-based interactions can be equally available to each process involved in the physical verification of an integrated circuit design. | 01-20-2011 |
| 20110016445 | Layout design system and layout design method - In a layout design of a semiconductor circuit, by selecting a frequently-used layout cell based on a layout design, a common location (coordinate) at which dummy metal is arranged is specified. A new layout cell in which dummy metal is arranged in advance at the specified arrangement location is generated. Dummy metal is arranged by replacing the frequently-used layout cell from which the new layout cell is generated by the new layout cell having dummy metal or by overlapping them. Thus, process such as wiring correction in which the amount of data depends on processing speed can be carried out by use of the inexpensive computer having low throughputs and the small amount of memory. | 01-20-2011 |
| 20110078645 | CIRCUIT DESIGN SYSTEM AND CIRCUIT DESIGN METHOD - A circuit design system | 03-31-2011 |
| 20110099530 | SPINE SELECTION MODE FOR LAYOUT EDITING - Methods, software, and systems implementing software provide for accepting a user's selection of a database object defining layout being displayed. The database objects can include objects defining paths and path segments. Automatic layout tools may be used in creating at least some of the objects. The user's selection begins a recursive process of automatically selecting additional database objects based on criteria designed to create an uninterrupted spine from database objects on a single interconnect layer, of the same width, and collectively arranged such that the spine has a first end and a second end, and can be traced from the first end to the second end without backtracking. | 04-28-2011 |
| 20110107284 | Semiconductor integrated circuit and method of designing semiconductor integrated circuit - A method of designing a semiconductor integrated circuit includes placing a functional block, determining a location of a power pad, and placing a power wiring structure connecting the power pad and the functional block. The placing the power wiring structure includes placing a plurality of first power wirings in a first wiring layer; placing a plurality of second power wirings in a second wiring layer that is an upper layer of the first wiring layer, the plurality of second power wirings overlapping the plurality of first power wirings at a plurality of intersections; placing vias connecting the plurality of first power wirings and the plurality of second power wirings at all of the plurality of intersections; analyzing a voltage drop with regard to the functional block; and if an amount of the voltage drop exceeds an acceptable amount, then removing a part of the vias on a current path to the functional block. | 05-05-2011 |
| 20110138346 | MEASURE OF ANALYSIS PERFORMED IN PROPERTY CHECKING - The amount of analysis performed in determining the validity of a property of a digital circuit is measured concurrent with performance of the analysis, and provided as an output when a true/false answer cannot be provided e.g. when stopped due to resource constraints. In some embodiments, a measure of value N indicates that a given property that is being checked will not be violated within a distance N from an initial state from which the analysis started. Therefore, in such embodiments, a measure of value N indicates that the analysis has implicitly or explicitly covered every possible excursion of length N from the initial state, and formally proved that no counter-example is possible within this length N. | 06-09-2011 |
| 20110197172 | Design verification apparatus and design verification program - A design verification apparatus includes a processor to produce and place constraint conditions on verification datasets provided to verify a first design specification of a target product. The processor produces those constraint conditions from a second design specification of the target product, based on links from units of processing which constitute a procedure defined for each verification item in the second design specification to units of processing in the first design specification. The processor outputs data identifying the resulting verification datasets having the constraint conditions, together with their corresponding verification items. | 08-11-2011 |
| 20110197173 | POLISHING ESTIMATION/EVALUATION DEVICE, OVERPOLISHING CONDITION CALCULATION DEVICE, AND COMPUTER-READABLE NON-TRANSITORY MEDIUM THEREOF - A polishing estimation/evaluation device includes a dividing unit, an overpolished area extracting unit, and a dummy modifying unit. The dividing unit divides a layout of an integrated circuit into a plurality of partial areas. The overpolished area extracting unit refers to an overpolishing condition indicating whether overpolishing occurs in a vicinity of a partial area based on a wiring density in the partial area and a wiring density in surrounding areas of the partial area, and extracts a partial area where the overpolishing occurs from the plurality of partial areas obtained by the division by the dividing unit. The dummy modifying unit modifies dummy wiring in the partial area where the overpolishing occurs extracted by the overpolished area extracting unit and/or dummy wiring in surrounding areas of the partial area to reduce the number of partial areas where the overpolishing occurs. | 08-11-2011 |
| 20110265053 | METHOD AND SOFTWARE FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT - In order to improve a failure detection rate in a layout automatic design process of a DFT circuit, signal lines of the DFT circuit are aggregated by an AND tree circuit | 10-27-2011 |
| 20110307852 | SYSTEMATIC BENCHMARKING SYSTEM AND METHOD FOR STANDARDIZED DATA CREATION, ANALYSIS AND COMPARISON OF SEMICONDUCTOR TECHNOLOGY NODE CHARACTERISTICS - One aspect provides a method of standardized data creation and analysis of semiconductor technology node characteristics. In one embodiment, the method includes: (1) designing representative benchmark circuits for a clock path, a data path and a flip-flop path, (2) establishing at least one standard sensitization and measurement rule for delay and power for the representative benchmark circuits and across corners in the technology nodes, (3) performing a simulation by sweeping through a range of values and at predetermined intervals across the corners, (4) extracting data from the simulation, (5) writing the data to a databank and (6) parsing and interpreting the data to produce at least one report. | 12-15-2011 |
| 20120042295 | AUTOMATED PLANNING IN PHYSICAL SYNTHESIS - A method, system, and computer usable program product for automated planning in physical synthesis are provided in the illustrative embodiments. A state of an integrated circuit design is identified where the state is a representation of a particular configuration of circuit components having a particular electrical characteristic. A first operation applicable to the first state is selected and applied to reach a second state of the design. A consequence of reaching the second state is analyzed. If the consequence indicates an improvement in the design, a solution is presented to achieve the improvement. The solution includes manipulations of design components using a set of operations to reach the second state from the first state. | 02-16-2012 |
| 20120060134 | Wiring Design Support Apparatus and Wiring Design Support Method - According to one embodiment, a wiring design support apparatus comprises a display, a drawing module, and a data creation module. The display is configured to display a three-dimensional object. The drawing module is configured to draw a line connecting two points on a surface of the three-dimensional object displayed by the display. The data creation module is configured to create first three-dimensional data indicating a wiring based on the line drawn by the drawing module. | 03-08-2012 |
| 20120060135 | Integrated Circuit Transformer Devices for On-Chip Millimeter-Wave Applications - Methods are provided for building integrated circuit transformer devices having compact and optimized architectures for use in MMW (millimeter-wave) applications. The integrated circuit transformer devices have universal and scalable architectures that can be used as templates or building blocks for constructing various types of on-chip devices for millimeter-wave applications. | 03-08-2012 |
| 20120102444 | ON-CHIP TUNABLE TRANSMISSION LINES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES - An on-chip tunable transmission line (t-line), methods of manufacture and design structures are provided. The structure includes a tunable transmission line (t-line) with fixed characteristic impedance comprising functionally-differentiated switches used for inductance and capacitance, respectively. | 04-26-2012 |
| 20120117526 | COMPUTER READABLE NON-TRANSITORY MEDIUM STORING DESIGN AIDING PROGRAM, DESIGN AIDING APPARATUS, AND DESIGN AIDING METHOD - A computer readable non-transitory medium storing a design aiding program causes a computer to execute a process of determining worst-case corner candidates for each of a plurality of condition sets. The design aiding program causes the computer to execute a process of mapping the worst-case corner candidates that are within an allowable range. The design aiding program causes a computer to execute a process of determining the worst-case corner candidates that minimize the number of the worst-case corner candidates mapped to the condition sets by handling the worst-case corner candidates thus mapped as a single worst-case corner candidate to be worst-case corners. | 05-10-2012 |
| 20120124535 | Optimal Chip Acceptance Criterion and its Applications - At least one target metric is identified for an integrated circuit chip design for which manufacturing chip testing is to be optimized. At least one surrogate metric is also identified for the integrated circuit chip design for which manufacturing chip testing is to be optimized. A relationship between the at least one target metric and the at least one surrogate metric is modeled using a general joint probability density function. A chip disposition criterion is determined based on the general joint probability density function. The chip disposition criterion determines, for a given physical chip putatively manufactured in accordance with the design, based on the at least one surrogate metric for the given physical chip, whether the given physical chip is to be accepted or discarded during the manufacturing chip testing. | 05-17-2012 |
| 20120131527 | TARGETED PRODUCTION CONTROL USING MULTIVARIATE ANALYSIS OF DESIGN MARGINALITIES - Targeted production control using multivariate analysis of design marginalities. A list of a plurality of metrology operations is accessed during production of an integrated circuit device. The list is generated from operations performed in the design of the integrated circuit device. At least one of the plurality of metrology operations is performed on the integrated circuit device. A manufacturing process of the integrated circuit device may be adjusted responsive to results of the performing. | 05-24-2012 |
| 20120159411 | DESIGN SUPPORT APPARATUS AND INFORMATION PROCESSING METHOD THEREOF - Layout information indicating a layout of circuits on a print circuit board is obtained. With reference to the layout information, a connection portion, which electrically connects a ground pattern of the print circuit board and an external ground of the print circuit board, is specified, and a pin, which is included in a connector laid out on the print circuit board and is connected to the ground pattern, is identified. Then, a discharge route between the pin and connection portion is determined. | 06-21-2012 |
| 20120159412 | TRANSISTOR-LEVEL LAYOUT SYNTHESIS - A layout tool partially replicates the layout of a base cell to determine the layout for a target cell. The base cell is information representing an arrangement of a set of transistors having an established layout. The target cell is information indicating the desired arrangement of another set of transistors. The layout tool identifies correspondences between subsets of the base cell transistors and subsets of the target cell transistors and replicates the layout of the identified base cell subsets to determine the layout for the identified target cell subsets. In addition, the layout tool can identify base cell subsets that closely match target cell subsets, but for which the layout cannot be exactly replicated because of obstructions in the target cell subsets. For such identified base cell subsets, the layout tool can determine a layout by adjusting the base cell subset layouts to avoid the obstructions. | 06-21-2012 |
| 20120167027 | ELECTRONIC DEVICE AND METHOD FOR CHECKING LAYOUT DISTANCE OF A PRINTED CIRCUIT BOARD - An electronic device and a method for checking layout distance of a printed circuit board (PCB) including presetting a checking condition to determine a reference layer. A high speed signal path is selected from a PCB design file, and a layer where the selected high speed signal path is located can be determined A reference layer of the determined layer is determined according to the checking condition, and a split line of the reference layer is determined. A shortest distance between each segment of the selected high speed signal path and the split line is calculated. If the shortest distance between a segment and the split line is less than the standard distance, layout of the segment is determined to be invalid. | 06-28-2012 |
| 20120198402 | SYSTEMS AND METHODS FOR MAPPING STATE ELEMENTS OF DIGITAL CIRCUITS FOR EQUIVALENCE VERIFICATION - Systems and methods for mapping state elements of digital circuits for equivalence verification are provided. One method for mapping state elements for equivalence verification between a first circuit and a second circuit includes (a) determining a first sequential depth from primary inputs and primary outputs of the first circuit and the second circuit to each state element thereof, wherein the first sequential depth is a minimum count of state elements along any path between two points of a circuit, (b) identifying and mapping first state elements of the first circuit and the second circuit having a unique first sequential depth, (c) determining a second sequential depth from the identified first state elements of the first circuit and the second circuit to the remaining state elements, (d) identifying second state elements of the first circuit and the second circuit having a unique second sequential depth, and (e) repeating (c) and (d) unless the process is no longer generating new unique mappings of state elements. | 08-02-2012 |
| 20120221988 | METHOD AND SYSTEM FOR POWER DELIVERY NETWORK ANALYSIS - The subject application relates to a method and system for power delivery network analysis. The present disclosure is directed towards a computer-implemented method for analyzing a power delivery network (PDN) associated with an electronic circuit design. Embodiments may include extracting, using at least one processor, an electromagnetic (EM) model for each of one or more discontinuity structures associated with the circuit design and generating a three dimensional adaptive mesh model that is based upon, at least in part, the extracted EM model. Numerous other features are also within the scope of the present disclosure. | 08-30-2012 |
| 20120278776 | SYSTEM AND METHODS FOR CONVERTING PLANAR DESIGN TO FINFET DESIGN - A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated. | 11-01-2012 |
| 20120278777 | SYSTEM AND METHODS FOR CONVERTING PLANAR DESIGN TO FINFET DESIGN - A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted. | 11-01-2012 |
| 20120304138 | CIRCUIT DESIGN CHECKING FOR THREE DIMENSIONAL CHIP TECHNOLOGY - A tool that allows three dimensional chip circuit designs to be checked subsequent to 3D design layer mirroring. The 3D chip design is converted to a corresponding 2D chip design by mirroring one or more design layers from the mirrored side of a 3D design and merging those design layers with unmirrored design layers from the unmirrored side of a 3D design. The converted circuit design can be processed by standard verification checks. The tool may also receive design layers corresponding to an integrated circuit that will pass through multiple semiconductor chips. Each design cell is examined to determine if it corresponds to a mirrored or unmirrored side of its respective semiconductor chip. If the respective design cell corresponds to the mirrored side, the design cell is mirrored. All mirrored cells are then merged with the unmirrored design cells in the correct order. The merged design is processed by standard verification checks. The tool also has the capability to create terminal metal abstracts for two adjoining chips. One of the abstracts is mirrored and then merged with the other for connectivity and alignment checking. | 11-29-2012 |
| 20120304139 | METHOD OF FAST ANALOG LAYOUT MIGRATION - A method of fast analog layout migration from an original layout is disclosed. Various placement constraints, including topology, matching and symmetry are extracted from the schematic or netlist as well as the original layout. In addition, relative placement patterns are extracted from the original layout for matching and symmetry constraints. A constraint hierarchy tree can be built according to the constraints, and relative placement patterns are attached accordingly. By using the constraint hierarchy tree, multiple new placement results are efficiently explored that preserve the relative placement patterns for matching and symmetry constraints. | 11-29-2012 |
| 20120331434 | COMPUTING DEVICE AND METHOD FOR CHECKING SIGNAL TRANSMISSION LINES - A computing device and a method reads design standards of signal transmission lines in a printed circuit board (PCB) layout file, and determines a minimum reference length of line segments of the signal transmission lines from the design standards. The device and method then selects a signal transmission line from a circuit board, and computes an actual length of each line segment of the selected signal transmission line. If each actual length is more than or equal to the minimum reference length, the device and method determines length design of the selected signal transmission line satisfies the design standards. Otherwise, if any actual length is less than the minimum reference length, the device and method determines the length design of the signal transmission line does not satisfy the design standards. | 12-27-2012 |
| 20130014067 | MACRO LAYOUT VERIFICATION APPARTUS - A macro layout verification apparatus for verifying a layout of a macro to be placed as a functional block on a semiconductor device. The apparatus includes: a unit, which assumes as a virtual wiring line, a wiring line that uses an unused intra-macro channel located adjacent to an intra-macro wiring line; a unit which calculates a parallel wiring length along which the virtual wiring line and the intra-macro wiring line run; and a unit which outputs information concerning the virtual wiring line when the parallel wiring length exceeds a reference value defined as a design rule. | 01-10-2013 |
| 20130019219 | SYSTEM AND METHOD FOR HIERARCHY RECONSTRUCTION FROM FLATTENED GRAPHIC DATABASE SYSTEM LAYOUTAANM Chen; Shu-YuAACI Hsinchu CityAACO TWAAGP Chen; Shu-Yu Hsinchu City TWAANM Lin; Yi-TangAACI Hsinchu CityAACO TWAAGP Lin; Yi-Tang Hsinchu City TWAANM Lei; Cheok-KeiAACI AndarAACO MOAAGP Lei; Cheok-Kei Andar MOAANM Chen; Hsiao-HuiAACI Hsinchu CityAACO TWAAGP Chen; Hsiao-Hui Hsinchu City TWAANM Chang; Yu-NingAACI Hsinchu CityAACO TWAAGP Chang; Yu-Ning Hsinchu City TWAANM Wann; HsingjenAACI CarmelAAST NYAACO USAAGP Wann; Hsingjen Carmel NY USAANM Chang; Chih-ShengAACI HsinchuAACO TWAAGP Chang; Chih-Sheng Hsinchu TWAANM Chen; Chien-WenAACI Hsinchu CityAACO TWAAGP Chen; Chien-Wen Hsinchu City TW - System and method for hierarchy reconstruction from a flattened layout are described. In one embodiment, a method for producing a reconstructed layout for an integrated circuit design from an original layout and a revised layout includes, for each pattern of the original layout, determining a pattern of the revised layout that corresponds to the pattern of the original layout; and assigning the corresponding pattern of the revised layout to a temporary instance, the temporary instance corresponding to an instance of the pattern of the original layout and citing to a temporary cell. The method further includes creating a temporary reconstructed layout from the temporary instances; and producing the reconstructed layout from the temporary reconstructed layout, wherein a hierarchy of the reconstructed layout is similar to a hierarchy of the original layout. | 01-17-2013 |
| 20130031521 | METHOD AND APPARATUS FOR PREEMPTIVE DESIGN VERIFICATION VIA PARTIAL PATTERN MATCHING - An approach is provided for preemptive design verification via partial pattern matching. Data corresponding to one or more problematic layout patterns associated with an integrated circuit manufacturing process is received. Data corresponding to a block of intellectual property including a layout design is received. At least a boundary of the layout design is scanned against the one or more problematic layout patterns. One or more partial matches of the one or more problematic layout patterns are identified at least at the boundary. Results are generated indicating the one or more partial matches. | 01-31-2013 |
| 20130055183 | 3D INTER-STRATUM CONNECTIVITY ROBUSTNESS - There is provided a method for verifying inter-stratum connectivity for two or more strata to be combined into a 3D chip stack. Each of the two or more strata has 3D elements including active 3D elements, mechanical 3D elements, and dummy 3D elements. The method includes performing a respective 2D layout versus schematic verification on each of the two or more strata with respect to at least the 3D elements to pre-ensure an absence of shorts between the 3D elements when the two or more strata are subsequently stacked into the 3D chip stack. The method further includes checking inter-stratum interconnectivity between each adjacent pair of strata in the 3D chip stack. | 02-28-2013 |
| 20130125074 | SYSTEM AND METHOD FOR DESIGNING DIGITAL CIRCUITRY WITH AN ACTIVITY SENSOR - A system for designing digital circuitry comprising: a digital circuit simulator based on a file containing a functional description of this digital circuit; means for estimating an output variable from the digital circuit when executing a test bench supplied to the simulator; event counters, the events being detected using control signals provided by the simulator when executing the test bench. Said system further comprises means for selecting a portion of the event counters by iteratively optimizing a model for calculating the output variable of the digital circuit using output data from the event counters and means for registering the selected portion of event counters and the optimized calculation model. | 05-16-2013 |
| 20130125075 | METHOD FOR RAPID ESTIMATION OF LAYOUT-DEPENDENT THRESHOLD VOLTAGE VARIATION IN A MOSFET ARRAY - An automated method for estimating layout-induced variations in threshold voltage in an integrated circuit layout. The method begins with the steps of selecting a diffusion area within the layout for analysis. Then, the system identifies Si/STI edges on the selected area as well as channel areas and their associated gate/Si edges. Next, the threshold voltage variations in each identified channel area are identified, which requires further steps of calculating threshold voltage variations due to effects in a longitudinal direction; calculating threshold voltage variations due to effects in a transverse direction; and combining the longitudinal and transverse variations to provide an overall variation. Finally, a total variation is determined by combining variations from individual channel variations. | 05-16-2013 |
| 20130139119 | PARTITIONING AND SCHEDULING UNIFORM OPERATOR LOGIC TREES FOR HARDWARE ACCELERATORS - A circuit design is compiled for hardware-accelerated functional verification by removing internal gates of a uniform operator tree (e.g., an assertion tree) while retaining node information, and partitioning the circuit to optimize connectivity without being constrained by the uniform operator tree. After partitioning, sub-trees are constructed for the partitions, and aggregated to form a master tree. The sub-trees can have leaf nodes at varying depths based on ranks of the leaf nodes, and the master tree can similarly provide inputs from the sub-trees at varying depths based on simulation depths for the sub-trees. The resynthesized master tree is structurally distinct from the original uniform operator tree but, since the inputs are commutative (e.g., OR gates), the functional equivalence of the model is preserved. | 05-30-2013 |
| 20130167097 | Asymmetric Segmented Channel Transistors - Structures, layouts and methods of forming integrated circuits are described. In various embodiments, the current invention includes an asymmetric segmented transistor. The asymmetric segmented transistor includes a source region and a drain region disposed within an active region, a floating source/drain region disposed within the active region, a first channel region disposed in the active region between the source region and the floating source/drain region, the first channel having a first length and a first width. A second channel region is disposed in the active region between the drain region and the floating source/drain region, the second channel having a second length and a second width. A first gate dielectric overlies the first channel region and a second gate dielectric overlies the second channel region. A gate line overlies the first gate dielectric and the second gate dielectric. | 06-27-2013 |
| 20130185687 | PARAMETERIZED CELL LAYOUT GENERATION GUIDED BY A DESIGN RULE CHECKER - A method for generating a layout for a cell of an integrated circuit (IC) guided by design rule checking (DRC) is disclosed. In the method, a model is defined, wherein the model comprises a plurality of parameters for generating a layout of the cell. Next an initial layout for the cell can be generated according to an initial set of values for the plurality of parameters. Then design rule checking (DRC) is performed for the initial layout based on a set of design rules. If any violations are found, the corresponding violation reports will be associated with the model. Therefore, a new set of values for the plurality of parameters can be generated by analyzing the violation reports collectively based on the model. With the new set of values for the plurality of parameters and above steps repeated, until no violation is found, a “DRC clean” layout can be generated. | 07-18-2013 |
| 20130198705 | CIRCUIT VERIFICATION USING COMPUTATIONAL ALGEBRAIC GEOMETRY - In one exemplary embodiment of the invention, a method includes: receiving a first description for a circuit whose operation over a plurality of inputs is to be verified; receiving a second description for expected behavior of the circuit, where the expected behavior in the second description is expressed as a set of algebraic systems of multivariable polynomials over at least one Galois field; applying at least one computational algebraic geometry technique to a combination of the first description and the second description to determine whether the circuit is verified, where verification of the circuit confirms that at least one output obtained based on the first description corresponds to at least one expected value based on the expected behavior expressed in the second description; and outputting an indication as to whether the circuit is verified. | 08-01-2013 |
| 20130198706 | FORMAT CONVERSION FROM VALUE CHANGE DUMP (VCD) TO UNIVERSAL VERIFICATION METHODOLOGY (UVM) - A system and method is disclosed for functional verification and/or simulation of dies in a multi-die 3D ICs. The system and method include converting an I/O trace, embodied as a Value Change Dump, to one or more Universal Verification Methodology objects. This conversion aids in identify and fixing issues contained in die. | 08-01-2013 |
| 20130198707 | "ELECTRON-BEAM LITHOGRAPHY METHOD WITH CORRECTION OF LINE ENDS BY INSERTION OF CONTRAST PATTERNS" - A method of electron-beam lithography is provided, notably for technologies of critical dimension of the order of 22 nm. In such methods applied notably to networks of lines, the methods of the prior art do not offer precise and efficient correction of the shortenings of line ends. The method provided solves this problem by carrying out the insertion of contrast intensification structures of types which are optimized for the structure of the lines to be corrected. The method allows the semi-automatic or automatic calculation of the dimensions and locations of said structures. Advantageously, these calculations may be modeled to produce a target design, derived from libraries of components. They may be supplemented with a joint optimization of the size of the etchings and of the radiated doses, as a function of the process energy latitude. | 08-01-2013 |
| 20130198708 | Placement and Area Adjustment for Hierarchical Groups in Printed Circuit Board Design - Aspects of the invention are directed towards placing components within a layout design for a PCB. More specifically, various implementations of the invention provide methods and apparatuses that can dynamically adjust the shape or placement of component groups during an HGP process. With some implementations of the invention, an HGP process for planning the layout of a PCB is provided. Furthermore, component groups, which conflict, geographically, with either another component group or some other object within the layout design are allowed to be placed during the planning process. Subsequently, the placement locations for one or both of the conflicting component groups are adjusted to resolve the conflict. In some implementations, the geometric boundary, or footprint, of one or both of the component groups is adjusted to resolve the conflict. | 08-01-2013 |
| 20130198709 | Verification Test Set and Test Bench Map Maintenance - Aspects of the invention provide for the maintenance of user modified portions of a map between a test bench and a test set generator during an iterative electronic design process. Various implementations of the invention provide for matching sections within a design for an electronic device with corresponding sections in a map between the elements in the design to elements in a graph representation of the design. The matched sections are then compared to determine if any discrepancies exists, such as, for example, if the design has been recently changed. If any discrepancies do exist, then it is determined whether the section of the map can be updated or must be replaced entirely to resolve the discrepancies. Various implementations of the invention provide that the process can be repeated during an iterative design flow such that as the design is modified during the iterative design flow, the map can be updated to reflect the changes. | 08-01-2013 |
| 20130212547 | METHOD OF EXTRACTING BLOCK BINDERS AND AN APPLICATION IN BLOCK PLACEMENT FOR AN INTEGRATED CIRCUIT - A method is directed to automatic extraction of block binders before block placement and application of block binders in block placement of an integrated circuit. Having block binders reduces the effective block count the block placement has to handle, and enables obtaining better placement result in shorter run time. The method includes an algorithm of processing the nodes of a hierarchical net-list to identify candidate nodes or create new candidate nodes to contain identified nodes. The method includes an algorithm of extracting a block binder out of blocks under each candidate node. The method includes an algorithm of automatic packing and generation of various configurations for a block binder to provide flexibility in block placement. The method also includes adapting any block placement algorithm to select to the best fit configuration of any block binder during the placement process. | 08-15-2013 |
| 20130227508 | COMPUTER SYSTEM AND METHOD FOR DETERMINING A TEMPERATURE RISE IN DIRECT CURRENT (DC) LINES CAUSED BY JOULE HEATING OF NEARBY ALTERNATING CURRENT (AC) LINES - A computer system performs a verification process that quickly and efficiently determines a temperature rise of DC conductor lines of an IC design caused by Joule heating in nearby AC conductor lines of the IC design, and whether the temperature rise is acceptable in terms of an electromigration performance of the IC design. | 08-29-2013 |
| 20130227509 | PROTOTYPE AND EMULATION SYSTEM FOR MULTIPLE CUSTOM PROTOTYPE BOARDS - A test system for testing prototype designs includes a host workstation, multiple interface devices, and multiple prototype boards. The prototype boards include programmable devices which implement one or more partitions of a user design and an associated verification modules. The verification modules probe signals of the partitions and transmit the probed signals to the interface devices. The verification modules can also transmit output signals generated by one or more partitions on the prototype boards to the host workstation via the interface devices, and transmit input signals, which are received from the host workstation via the interface devices, to one or more partitions on the prototype boards. | 08-29-2013 |
| 20130239077 | LVS Implementation for FinFET Design - A method includes converting an active region in a layout of an integrated circuit into a fin-based structure that has a fin. The active region belongs to an integrated circuit device, and has a planar layout structure. The method further includes extracting a Resistance-Capacitance (RC) loading of the integrated circuit device using the parameters of the fin-based structure. The steps of converting and extracting are performed by a computer. | 09-12-2013 |
| 20130275934 | SOLVING CONGESTION USING NET GROUPING - A method, system, and computer program product for solving a congestion problem in an integrated circuit (IC) design are provided in the illustrative embodiments. A congested g-edge is selected from a set of congested g-edges. A set of congesting nets is selected, wherein the set of congesting nets cause congestion in the selected congested g-edges by crossing the selected congested g-edge. A vacancy data structure corresponding to the selected congested g-edge is populated. A subset of the set of the congesting nets is selected. The subset of the set of the congesting nets is rerouted to a candidate g-edge identified in the vacancy data structure. | 10-17-2013 |
| 20130311962 | INSTRUCTION-BY-INSTRUCTION CHECKING ON ACCELERATION PLATFORMS - Method, apparatus and product for performing instruction-by-instruction checking on an acceleration platform. The method comprising: simulating by a hardware accelerator an execution of a testcase on a circuit design enhanced by a tracer module, wherein during the simulation the tracer module is configured to collect and record information regarding instruction which are completed by the circuit design and regarding register value modifications; and off-loading the recorded information from the hardware accelerator to a computerized apparatus, whereby based on the off-loaded recorded information, the computerized apparatus can perform an instruction-by-instruction checking that each recorded register modification is justified by an instruction which is was completed prior to the register modification. | 11-21-2013 |
| 20130326444 | RECORDING MEDIUM FOR GENERATION PROGRAM, GENERATION METHOD, AND GENERATION APPARATUS - In a generation method, the computer detects a contact between a pin data group of a first connection destination included in three-dimensional shape data and a pin data group of a first connection source included in three-dimensional shape data of a connector, and determines first contact information that indicates combinations of pin data items of the pin data group of the first connection destination and respective pin data items of the pin data group of the first connection source. Furthermore, the computer detects a contact between a pin data group of a second connection destination and a pin data group of a second connection source, and determines second contact information that indicates combinations of pin data items of the pin data group of the second connection destination and respective pin data items of the pin data group of the second connection source, and generates a connection relationship data group. | 12-05-2013 |
| 20130339915 | CAPACITANCE EXTRACTION FOR ADVANCED DEVICE TECHNOLOGIES - A method and apparatus to provide a capacitance to a design an integrated circuit is described. In one embodiment, the method receive a layout of the integrated circuit and applying canonical hierarchical models to the layout, wherein the canonical hierarchical models include a first type canonical model to capture a first capacitance of a device having a plurality of first conductors and a second type canonical model to capture a second capacitance between at least a portion of the device and one or more second conductors of the integrated circuit. The method further includes determining a capacitance for the layout based on the applying. | 12-19-2013 |
| 20140013291 | Device for and a Method of Designing a Sensor Arrangement for a Safe Automated System, An Automated System, a Program Element and a Computer-Readable Medium - A device for designing a sensor arrangement for an automated system, the device comprising a first input unit for receiving a specification of a plurality of sensor measurements to be carried out by the sensor arrangement, a second input unit for receiving a specification of a confidence region together with an associated confidence level for each of the specified sensor measurements, a third input unit for receiving a specification of a target confidence level for the automated system, and a configuration unit for configuring the plurality of sensor measurements and for configuring the combination of the sensor measurements in a manner to guarantee the target confidence level for the automated system. | 01-09-2014 |
| 20140068534 | Designing Photonic Switching Systems Utilizing Equalized Drivers - Designing a photonics switching system is provided. A photonic switch diode is designed to attain each performance metric in a plurality of performance metrics associated with a photonic switching system based on a weighted value corresponding to each of the plurality of performance metrics. A switch driver circuit is selected from a plurality of switch driver circuits for the photonic switching system. It is determined whether each performance metric associated with the photonic switching system meets or exceeds a threshold value corresponding to each of the plurality of performance metrics based on the photonic switch diode designed and the switch driver circuit selected. In response to determining that each performance metric associated with the photonic switching system meets or exceeds the threshold value corresponding to each of the performance metrics, the photonic switching system is designed using the photonic switch diode designed and the switch driver circuit selected. | 03-06-2014 |
| 20140068535 | SYSTEM AND METHOD FOR CONFIGURING A TRANSISTOR DEVICE USING RX TUCK - The present disclosure relates to methods and systems for designing and fabricating an integrated circuit. In particular, a method includes electronically searching a virtual layout of an integrated circuit to locate a dummy polysilicon structure positioned between adjacent terminals of first and second MOSFET devices that are connected to different nodes of the integrated circuit. The method includes changing a configuration of the dummy polysilicon structure of the virtual layout to extend an active silicon region adjacent to the dummy polysilicon structure and to form an electrical connection between the dummy polysilicon structure and one of a supply voltage node and a ground node of the integrated circuit. | 03-06-2014 |
| 20140123090 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR TESTING AN INTEGRATED CIRCUIT FROM A COMMAND LINE - A system, method, and computer program product are provided for testing a circuit representation. A command line input is received at a command line interface. The command line input is translated into one or more test conditions. Additionally, a test environment configured to simulate the circuit representation and verify the one or more test conditions is generated. | 05-01-2014 |
| 20140137059 | METHOD AND APPARATUS FOR PLASMA PROCESSING - Plasma processing focus ring design arrangements, including: acquiring a surface voltage and a sheath thickness above a surface of the object to be processed, and a surface voltage and a sheath thickness above a surface of the focus ring, by an equivalent circuit analysis; performing 2D plasma and 2D electric field analysis, based on the equivalent circuit analysis; and designing configuration of the focus ring and the processing stage, to achieve a plasma-sheath interface flattening condition by making a sum of a height from a height reference point to a surface of the object and a sheath thickness from the surface of the object to a plasma-sheath interface above the object, equal to a sum of a height from the height reference point to a surface of the focus ring and a sheath thickness from the surface of the focus ring to a plasma-sheath interface above the focus ring. | 05-15-2014 |
| 20140189625 | PERFORMANCE-DRIVEN AND GRADIENT-AWARE DUMMY INSERTION FOR GRADIENT-SENSITIVE ARRAY - The present disclosure relates to an arrangement and a method of performance-aware buffer zone placement for a high-density array of unit cells. A first feature density of the array is measured and maximum variation for a parameter within a unit cell is determined. A look-up table of silicon data is consulted to predict a buffer zone width and gradient value that achieves a variation that is less than the maximum variation for the unit cell. The look-up table contains a suite of silicon test cases of various array and buffer zone geometries, wherein variation of the parameter within a respective test structure is measured and cataloged for the various buffer zone geometries, and is also extrapolated from the suite of silicon test cases. A buffer zone is placed at the border of the array with a width that is less than or equal to the buffer zone width. | 07-03-2014 |
| 20140215420 | SYSTEM AND METHODS FOR CONVERTING PLANAR DESIGN TO FINFET DESIGN - A method and layout generating machine for generating a layout for a device having FinFETs from a first layout for a device having planar transistors are disclosed. A planar layout with a plurality of FinFET active areas is received and corresponding FinFET active areas are generated with active area widths. Mandrels are generated according to the active area widths and adjusted such that a beta ratio of a beta number for each FinFET active area to a beta number for each corresponding planar active area is within a predetermined beta ratio range. | 07-31-2014 |
| 20140258949 | METHOD OF DESIGNING ARRANGEMENT OF TSV IN STACKED SEMICONDUCTOR DEVICE AND DESIGNING SYSTEM FOR ARRANGEMENT OF TSV IN STACKED SEMICONDUCTOR DEVICE - A method of designing arrangement of through silicon vias (TSVs) in a stacked semiconductor device is provided The method includes: determining a plurality of TSV candidate grids representing positions, into which the TSVs are insertable, in each of a plurality of semiconductor dies stacked mutually and included in a stacked semiconductor device; creating a plurality of path graphs representing linkable signal paths for a plurality of signals transmitted through the stacked semiconductor device, respectively, based on the TSV candidate grids; determining initial TSV insertion positions corresponding to shortest signal paths for the signals based on the path graphs; and determining final TSV insertion positions by verifying the initial TSV insertion positions so that a plurality of signal networks corresponding to the shortest signal paths for the signals have routability. | 09-11-2014 |
| 20140282324 | PREDICTIVE 3-D VIRTUAL FABRICATION SYSTEM AND METHOD - A virtual fabrication environment for semiconductor device structures that includes the use of virtual metrology measurement data to optimize a virtual fabrication sequence is described. Further, calibration of the virtual fabrication environment is performed by comparing virtual metrology data generated from a virtual fabrication run with a subset of measurements performed in a physical fabrication environment. Additionally, virtual experiments conducted in the virtual fabrication environment of the present invention generate multiple device structure models using ranges of process and design parameter variations for an integrated process flow and design space of interest. | 09-18-2014 |
| 20140282325 | Methods for Layout Verification for Polysilicon Cell Edge Structures in FinFET Standard Cells using Filters - Methods for verifying the layout for standard cells using finFET standard cell structures with polysilicon on cell edges. Standard cells are defined using finFET transistors. Polysilicon dummy structures are formed on the edges of the active areas of the standard cells. Where two standard cells abut a single polysilicon dummy structure is formed. In a design flow, a pre-layout netlist schematic for the standard cells is formed that does not include devices corresponding to the polysilicon dummy structures. After an automated place and route process forms a device layout using the standard cells, a post layout netlist schematic is extracted including MOS devices corresponding to the polysilicon dummy structures. A layout versus schematic comparison is then performed, but during the comparison MOS devices corresponding to the polysilicon dummy structures are filtered from the post-layout netlist and are not compared. Additional methods are disclosed. | 09-18-2014 |
| 20140282326 | Methods for Layout Verification for Polysilicon Cell Edge Structures in FinFET Standard Cells - Methods for standard cells using finFET standard cell structures with polysilicon on OD edges. Standard cells are defined using finFET transistors and having gate structures forming a transistor at an intersection with a semiconductor fin. Polysilicon dummy structures are formed on the edges of the active areas or OD areas of the standard cells. In a design flow, a pre-layout netlist schematic for the standard cells includes a three terminal MOS device corresponding to the polysilicon dummy structure on the edges of the standard cell. After an automated place and route process forms a device layout using the standard cells, a post layout netlist is extracted. Where two standard cells abut one another, a single polysilicon dummy structure is formed on the common boundary. A layout versus schematic comparison is then performed comparing the pre-layout netlist and the post-layout netlist to verify the layout obtained. Additional methods are disclosed. | 09-18-2014 |
| 20140289687 | INFORMATION PROCESSING APPARATUS AND DESIGN VERIFICATION METHOD - A computation unit locates data of a first component in a first circuit, as well as data of a second component in the second circuit. The computation unit then obtains data of a first portion of the first circuit by tracing wiring lines from component to component in the first circuit, with the first component as the start point. Similarly the computation unit obtains data of a second portion of the second circuit by tracing wiring lines from component to component in the second circuit, with the second component as the start point. The computation unit outputs data indicating differences between the first portion and second portion, based on the obtained data of the first portion and the obtained data of the second portion. | 09-25-2014 |
| 20140304670 | RC Corner Solutions for Double Patterning Technology - A method includes selecting a process corner, determining model parameters for forming an integrated circuit, and generating a file using the model parameters for the process corner. The generating the file is performed using a computer. The file includes at least two of a first capacitance table, a second capacitance table, and a third capacitance table. The first capacitance table stores greatest parasitic capacitances between layout patterns of the integrated circuit when lithography masks including the layout patterns shift relative to each other. The second capacitance table stores smallest parasitic capacitances between the layout patterns when the lithography masks shift relative to each other. The third capacitance table stores nominal parasitic capacitances between the layout patterns when the lithography masks do not shift relative to each other. | 10-09-2014 |
| 20140310668 | VERIFICATION ASSISTANCE FOR DIGITAL CIRCUIT DESIGNS - To assist verification of a digital circuit design, a data processing system presents, within a graphical user interface of a display device, a presentation including a plurality of verification notifications arising from verification of a digital circuit design. The data processing system detects one or more user operations by which a user interacts with the plurality of verification notifications utilizing one or more user input devices and stores, in a memory, user operation information regarding the one or more user operations detected by the data processing system. The data processing system determines, based on said user operation information, a recommended subsequent user operation and presents, within the graphical user interface, an indication of the recommended subsequent user operation. | 10-16-2014 |
| 20140337812 | CIRCUIT VERIFICATION METHOD AND CIRCUIT VERIFICATION APPARATUS - A control section of a circuit verification apparatus acquires waveform data of output in a transient state of a verification target circuit by a circuit simulation and stores the waveform data in a storage section. When the control section detects input to a functional model of the verification target circuit during functional verification performed by the use of the functional model, the control section generates an output signal of the functional model by the use of the waveform data stored in the storage section. | 11-13-2014 |
| 20140351776 | DETECTING DEVICE AND METHOD FOR PCB LAYOUT - A detecting device includes an input device, a display, and a computer system. The computer system includes a setting module, a storing module, a detecting module, and a control module. The storing module stores a PCB layout file. The setting module receives detecting parameters inputted by the input device. The detecting module detects the PCB layout file according to the detecting parameters to obtain detecting data corresponding to the detecting parameters. The control module displays a “fail” message on the display if the detecting data does not match standard data. | 11-27-2014 |
| 20140351777 | PROTOTYPE AND EMULATION SYSTEM FOR MULTIPLE CUSTOM PROTOTYPE BOARDS - A system for emulating a circuit design is presented. The system includes a host workstation coupled by an emulation interface to a field programmable gate array (FPGA) configured to emulate and verify the circuit design when the host workstation is invoked to verify the circuit design. The emulation interface is configured to provide timing and control information for at least the verify. The system further includes computer readable storage medium including instructions, which when executed cause a computer to compile a portion of the circuit design and an associated verification module adapted to configure the FPGA. The compilation is in accordance with a description file. | 11-27-2014 |
| 20140372960 | MACHINE-LEARNING BASED DATAPATH EXTRACTION - A datapath extraction tool uses machine-learning models to selectively classify clusters of cells in an integrated circuit design as either datapath logic or non-datapath logic based on cluster features. A support vector machine and a neural network can be used to build compact and run-time efficient models. A cluster is classified as datapath if both the support vector machine and the neural network indicate that it is datapath-like. The cluster features may include automorphism generators for the cell clusters, or physical information based on the cell locations from a previous (e.g., global) placement, such as a ratio of a total cell area for a given cluster to a half-perimeter of a bounding box for the given cluster. | 12-18-2014 |
| 20150020040 | METHOD FOR AUTOMATIC DESIGN OF AN ELECTRONIC CIRCUIT, CORRESPONDING SYSTEM AND COMPUTER PROGRAM PRODUCT - A method for the automatic design of an electronic circuit includes operations for evaluation of the thermal effects in the electronic circuit. The method generates a layout of the electronic circuit. Abstract data at the substrate level associated to the layout of the electronic circuit is then generated. A grid of partitioning is generated with respect to a view regarding the aforesaid abstract into meshes and nodes. The grid is applied to the substrate. On the basis of the grid (TG), a list of nodes or netlist representing a thermal network that represents the thermal behavior of the substrate or of its portions or elements is extracted. The netlist is useful in simulation operations, in particular of a SPICE type, for making an evaluation of thermal effects in the electronic circuit. | 01-15-2015 |
| 20150058819 | Interposer Defect Coverage Metric and Method to Maximize the Same - Provided is a method of assigning a first set of probe pads to an interposer for maximizing a defect coverage for the interposer. The interposer includes a second set of nets and the defect coverage is based on a ratio between a tested net length and an overall net length. The method includes processing the second set such that every net interconnecting more than two micro-bumps is divided into a plurality of nets and every two of the more than two micro-bumps are interconnected by one of the plurality of nets. The method further includes calculating an untested length of each net in the second set; selecting a first net from the second set with the maximum untested length; selecting two probe pads from the first set based on a user-defined cost function; and connecting the two probe pads to the first net with two dummy nets. | 02-26-2015 |
| 20150067624 | SYSTEM AND METHOD FOR LEAKAGE ESTIMATION FOR STANDARD INTEGRATED CIRCUIT CELLS WITH SHARED POLYCRYSTALLINE SILICON-ON-OXIDE DEFINITION-EDGE (PODE) - A system and method of producing an integrated circuit using abutted cells having shared polycrystalline silicon on an oxide definition region edge (PODE) includes modeling inter-cell leakage current in a plurality of different cells. Each of the plurality of different cells is abutted with another cell and having the shared PODE. The method also comprises verifying a pre-determined acceptable power consumption of the integrated circuit based on the inter-cell leakage current. | 03-05-2015 |
| 20150067625 | MACHINE-LEARNING BASED DATAPATH EXTRACTION - A datapath extraction tool uses machine-learning models to selectively classify clusters of cells in an integrated circuit design as either datapath logic or non-datapath logic based on cluster features. A support vector machine and a neural network can be used to build compact and run-time efficient models. A cluster is classified as datapath if both the support vector machine and the neural network indicate that it is datapath-like. The cluster features may include automorphism generators for the cell clusters, or physical information based on the cell locations from a previous (e.g., global) placement, such as a ratio of a total cell area for a given cluster to a half-perimeter of a bounding box for the given cluster. | 03-05-2015 |
| 20150067626 | KNOWLEDGE-BASED ANALOG LAYOUT GENERATOR - A computer-implemented method for generating a layout of a design includes invoking the computer to receive a schematic representation of the design, generating a connection graph associated with the design, comparing the connection graph with a plurality of connection graphs stored in a database and selecting a layout associated with the matching connection graph in generating the layout of the design. | 03-05-2015 |
| 20150074628 | Enhanced Case-Splitting Based Property Checking - An approach is provided in which a model verification system partitions one of a design specification's circuit design properties into multiple unsolved cases. The model verification system then performs property checking on one of the unsolved cases against a corresponding circuit design model, which results in a property checked solved case and a subset of unsolved cases. In turn, the model verification system performs sequential equivalence checking on one or more of the subset of unsolved cases by checking their sequential equivalence against the property checked solved case. As a result, the model verification system stores the cases as sequentially equivalent solved cases and verifies of a portion of the design specification against a portion of the circuit design model. | 03-12-2015 |
| 20150082265 | DESIGN STRUCTURE FOR CHIP EXTENSION - One embodiment relates to a method of achieving an circuit dimension which is greater than a size of an exposure field of an illumination tool. A first area of a first reticle field and a second area of a second reticle field are defined. An extension zone is created as a region outside the first area, and includes a first layout shape formed on a first design level. A corresponding forbidden zone is created for the second reticle field as a region inside the second area where no layout shape on the first design level is permitted. A second layout shape is formed on a second design level within the forbidden zone. The first and second areas are then abutted. Upon abutment of the first and second areas, the second layout shape overlaps the first layout shape to form a connection between circuitry of the first and second reticle fields. | 03-19-2015 |
| 20150095864 | POWER RAIL FOR PREVENTING DC ELECTROMIGRATION - A method is disclosed that includes the operations outlined below. A first criteria is determined to be met when directions of a first current and a second current around a first end and a second end of a metal segment respectively are opposite, in which the metal segment is a part of a power rail in at least one design file of a semiconductor device and is enclosed by only two terminal via arrays. A second criteria is determined to be met when a length of the metal segment is not larger than a electromigration critical length. The metal segment is included in the semiconductor device with a first current density limit depending on the length of the metal segment when the first and the second criteria are met. | 04-02-2015 |
| 20150100935 | METHOD OF DETERMINING IF LAYOUT DESIGN IS N-COLORABLE - A method of determining if a layout design for fabricating a layer of features of an integrated circuit is N-colorable, comprising identifying a set of candidate cells among layout cells of a layout design. Each candidate cell of the set of candidate cells is one of the set of base layout cells, or one of the set of composite layout cells, and constituent layout cells of the one of the set of composite layout cells having been determined as N-colorable. Whether a first candidate cell of the set of candidate cell is N-colorable is determined. An abutment-sensitive conflict graph of the first candidate cell is generated when the first candidate cell is N-colorable and the first candidate cell is not the top layout cell. | 04-09-2015 |
| 20150135151 | Canonical Forms Of Layout Patterns - Aspects of the disclosed technology relate to techniques for determining canonical forms of layout patterns. Coordinates of vertices of geometric elements in a window of a layout design are first transformed into new coordinates of the vertices, wherein the coordinates of vertices do not comprise clipped coordinates and the transforming comprises: performing a translation on the coordinates of vertices based on differences between maximum and minimum X/Y coordinate values of the vertices. Based on sums of X/Y coordinate values of the new coordinates of the vertices, a canonical form of the geometric elements is determined. The canonical form coordinates of the vertices may then be determined and sorted. The sorted canonical form coordinates may be employed for pattern matching. | 05-14-2015 |
| 20150143311 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR DESIGNING SEMICONDUCTOR DEVICE - A method of designing a semiconductor device is performed by at least one processor. In the method, a first environment temperature for a first substrate is determined based on an operational temperature of a second substrate, the first and second substrates stacked one upon another in the semiconductor device. An operation of at least one first circuit element in the first substrate is simulated based on the first environment temperature. | 05-21-2015 |
| 20150143312 | METHOD OF DESIGNING PATTERNS OF SEMICONDUCTOR DEVICES - A method of designing patterns of semiconductor devices includes forming a plurality of tiles having patterns on a wafer, measuring the patterns of the plurality of tiles, analyzing the measurements of the patterns and determining a tile having such a size that the measurements linearly vary according to a design size and pattern density, and modifying the pattern density of the determined tile. | 05-21-2015 |
| 20150302133 | SYSTEMS AND METHODS FOR AUTOMATED FUNCTIONAL COVERAGE GENERATION AND MANAGEMENT FOR IC DESIGN PROTOCOLS - A new approach is proposed that contemplates systems and methods to support automated functional coverage generation and management for an IC design protocol. The proposed approach takes advantage of table-based high-level (e.g., transaction-level) specifications of the IC design protocol, wherein the state tables are readable and easily manageable (e.g., in ASCII format) in order to automatically generate functional coverage for the IC design protocol, which include but are not limited to, coverage points, protocol transitions, and/or transaction coverage. The automatically generated functional coverage is then verified via formal verification and simulated at the register-transfer level (RTL) during the coverage generation and management process. The coverage data from the formal verification and the simulation runs are then analyzed and used to guide and revise the IC design protocol in a coverage-based closed-loop IC design process. | 10-22-2015 |
| 20150339427 | INTEGRATED CIRCUIT HIERARCHICAL DESIGN TOOL APPARATUS AND METHOD OF HIERARCHICALLY DESIGNING AN INTEGRATED CIRCUIT - An integrated circuit hierarchical design tool apparatus comprises a processor arranged to support a block coupling reconfiguration unit. The block coupling reconfiguration unit is capable of receiving block layout data comprising block placement, terminal location data and intra-block connectivity data. The block coupling reconfiguration unit is arranged to identify from the block layout data a block placement level block having a terminal respectively coupled to a plurality of other block placement level blocks by a plurality of nets, and to provide the block with an additional terminal capable of providing the same function as the terminal. The block coupling reconfiguration unit is also arranged to replace a net of the plurality of nets that is coupled to the terminal with a replacement net coupled to the additional terminal. | 11-26-2015 |
| 20150363539 | STRUCTURE AND METHOD FOR DYNAMIC BIASING TO IMPROVE ESD ROBUSTNESS OF CURRENT MODE LOGIC (CML) DRIVERS - An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output pad and the voltage pad. A second driver is connected to the second output pad and the voltage pad. A first ESD circuit is connected to the voltage pad, the first output pad, and the first driver. A second ESD circuit is connected to the voltage pad, the second output pad, and the second driver. The first ESD circuit biases the first driver toward a voltage of the voltage pad when an ESD event occurs at the first output pad, and the second ESD circuit biases the second driver toward the voltage of the voltage pad when an ESD event occurs at the second output pad. | 12-17-2015 |
| 20160098508 | METHOD AND SYSTEM FOR DESIGNING SEMICONDUCTOR DEVICE - A method of designing a semiconductor device and system for designing a semiconductor device are provided. The method of designing a semiconductor device includes providing a standard cell layout which includes an active region and a dummy region; determining a first fin pitch between a first active fin and a second active fin in the active region and a second fin pitch between a first dummy fin and a second dummy fin in the dummy region; placing the first and second active fins in the active region and the first and second dummy fins in the dummy region using the first and second fin pitches; and verifying the standard cell layout. | 04-07-2016 |
| 20160125123 | Integrated Circuit Design Using Dynamic Voltage Scaling - Methods and systems for integrated circuit design using dynamic voltage scaling may comprise (a) designing an IC to meet a voltage dependent frequency specification, the IC design including feedback circuitry for controlling a power supply voltage to a fabricated instance of the IC design, (b) characterizing a fabrication process for corner lots for the IC design at a range of power supply voltage levels achievable by the feedback circuitry; (c) validating the IC design against the fabrication process if the frequency specification is achievable for essentially all instances of the IC design fabricated, wherein the feedback circuitry in each IC resulting from the IC design is operable to respectively adjust the power supply voltage of each IC resulting from the IC design by reducing the power supply voltage if the IC is from a fast corner lot and increasing power supply voltage if from a slow corner lot. | 05-05-2016 |
| 20160180002 | METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR GENERATING SEMICONDUCTOR CIRCUIT LAYOUTS | 06-23-2016 |
| 20160188778 | IMPLEMENTING SYSTEM IRRITATOR ACCELERATOR FPGA UNIT (AFU) RESIDING BEHIND A COHERENT ATTACHED PROCESSORS INTERFACE (CAPI) UNIT - A method and apparatus are provided for implementing system irritator accelerator field programmable gate array (FPGA) Units (AFUs) residing behind a Coherent Attached Processors Interface (CAPI) unit in a computer system. An AFU is implemented in an FPGA residing behind the CAPI unit, the AFU includes a system irritator accelerator. A processor configures the AFU and enables the AFU system irritator to execute. The AFU system irritator is replicated to create additional irritation and is re-programmable. | 06-30-2016 |
| 20160188779 | ESTIMATION OF CHIP FLOORPLAN ACTIVITY DISTRIBUTION - Simulation or calculation to estimate activity per unit in a chip design, combined with estimation of the specific location or region in which the unit logic will be finally placed, provides for calculation of an estimation of the activity distribution within the floorplan. Activity distribution estimation can be performed with fine granularity (at a gate level), at coarse granularity (at a macro level), or at an intermediate granularity (at a network-on-chip unit level). The estimation is displayed, visually, to a user of a design tool. Furthermore, the estimation is used to make manual or automatic optimizations of the floorplan and the location and configuration of units within the floorplan. | 06-30-2016 |
| 20160188780 | IMPLEMENTING SYSTEM IRRITATOR ACCELERATOR FPGA UNIT (AFU) RESIDING BEHIND A COHERENT ATTACHED PROCESSORS INTERFACE (CAPI) UNIT - A method and apparatus are provided for implementing system irritator accelerator field programmable gate array (FPGA) Units (AFUs) residing behind a Coherent Attached Processors Interface (CAPI) unit in a computer system. An AFU is implemented in an FPGA residing behind the CAPI unit, the AFU includes a system irritator accelerator. A processor configures the AFU and enables the AFU system irritator to execute. The AFU system irritator is replicated to create additional irritation and is re-programmable. | 06-30-2016 |
| 20160188784 | Alignment of Inspection to Design Using Built in Targets - Methods and systems for determining a position of output generated by an inspection subsystem in design data space are provided. One method includes selecting one or more alignment targets from a design for a specimen. At least a portion of the one or more alignment targets include built in targets included in the design for a purpose other than alignment of inspection results to design data space. At least the portion of the one or more alignment targets does not include one or more individual device features. One or more images for the alignment target(s) and output generated by the inspection subsystem at the position(s) of the alignment target(s) may then be used to determine design data space positions of other output generated by the inspection subsystem in a variety of ways described herein. | 06-30-2016 |
