Class / Patent application number | Description | Number of patent applications / Date published |
716115000 | Noise (e.g., crosstalk, electromigration, etc.) | 64 |
20110022999 | METHOD AND APPARATUS FOR LOW DELAY RECURSIVE FILTER DESIGN - A method and apparatus for low delay recursive filter design. The method includes determining a predefined filter template with higher magnitude specification than a target filter design, determining at least one relaxation bound on the filter specification utilizing the predefined filter template, specifying at least one constraint for the target filter design utilizing the at least one relaxation bound, and determining a low delay recursive filter design for minimizing the average group delay of the filter utilizing the at least one constraint. | 01-27-2011 |
20110066991 | SYSTEM AND METHOD FOR EXTRACTING PARASITIC ELEMENTS - A parasitic element extracting system includes: a classifying section configured to classify each of interconnection layers of a layout structure of a semiconductor device into one of an upper interconnection layer and an lower interconnection layer based on a predetermined criterion; and a marker producing section configured to generate a marker to indicate a via-contact connecting the upper interconnection layers and the lower interconnection layers. An upper layer parasitic element list producing section is configured to generate an upper layer parasitic element list by extracting parasitic elements in the upper interconnection layers based on a first criterion, and a lower layer parasitic element list producing section is configured to generate a lower layer parasitic element list by extracting parasitic elements in the lower interconnection layers based on a second criterion which is different from the first criterion. A parasitic element list producing section is configured to generate a parasitic element list of the layout by combining the upper layer parasitic element list and the lower layer parasitic element list by using the markers. | 03-17-2011 |
20110161905 | Layout Electromagnetic Extraction For High-Frequency Design And Verification - Embodiments of the present invention provide a method of circuit design and circuit simulation. A method for electromagnetic simulation of passive structures of a circuit design is disclosed. The method comprises recognizing one or more geometries of the passive structures having certain geometric properties and electromagnetic properties, converting the one or more geometries to one or more primitives based on the geometric properties and numerically equivalent electromagnetic properties of the passive structures, constructing a physical topology incorporating the converted primitives and unconverted geometries, and simulating the physical topology to generate electromagnetic modeling of the passive structures of the circuit design. | 06-30-2011 |
20110239175 | Method and device for estimating simultaneous switching noise in semiconductor device, and storage medium - The method comprises a number of simultaneously switching signals calculation step in which the number of simultaneously switching signals is calculated for each set of user setting information for the input and output signal on the basis of pin arrangement information and the user setting information of the pins in a neighboring area of a pin to be executed in the estimation process; and a simultaneous switching noise calculation step in which a difference is calculated between noise corresponding to an initial point and that to a terminal point in a range of the number of simultaneously switching signals calculated for each set of user setting information on the basis of a relationship between the number of simultaneously switching signals and the noise caused by the number of simultaneously switching signals for each set of user setting information. | 09-29-2011 |
20110239176 | DESIGN SUPPORT METHOD AND APPARATUS FOR PRINTED CIRCUIT BOARD - An orthogonal array is formed by performing electromagnetic field analysis only once and determining a range by using the mount position and type of a capacitor and the number of capacitors as parameters to perform circuit analysis a small number of times. An estimation equation is formed by using as an index a result of the absolute value of the calculated power source impedance, and a capacitor is disposed to reduce noises by using the estimation equation. | 09-29-2011 |
20110246957 | PIN PLACEMENT DETERMINING METHOD - A pin placement determining method includes calculating a waveform deterioration amount of wires from a noise amount of the wires and wiring loss of the wires, the wires being coupled to a connector on a printed board, comparing the calculated waveform deterioration amount of the wires to an evaluation criteria, evaluating the wires in which the waveform deterioration amount exceeds the evaluation criteria, and replacing corresponding pins of the connectors to which the wires that have been evaluated as exceeding the evaluation criteria are coupled with replacement pins of connectors that have a low noise amount. | 10-06-2011 |
20110320995 | Noise Analysis Designing Method - To provide a simulation technology of ending multiphysics analysis on heat, vibration, and EMC within a practical time and with a low-price computation process at an early stage of product designing, in a noise analysis designing method for an electric device, such as an inverter for automobile, this electric device includes one or more energy sources, a propagation path through which energy from the energy source propagates, and a noise occurring part where an electromagnetic radiated noise occurs due to the energy coming from the propagation path, the method has a step of estimating the occurring noise, such as a occurring radiated noise, by analyzing a path specified by a user by using a calculator, and the path specified by the user is a path of the energy flowing through the propagation path. | 12-29-2011 |
20120023471 | METHOD, APPARATUS, AND ARTICLE OF MANUFACTURE FOR PROVIDING IN SITU, CUSTOMIZABLE INFORMATION IN DESIGNING ELECTRONIC CIRCUITS WITH ELECTRICAL AWARENESS - Disclosed are a method, system, and computer program product for providing customizable information in designing electronic circuits with electrical awareness. The method or the system displays a portion of a physical design of an electronic circuit in a first display area. The method or the system receives or identifies a user's or a system's manipulation of the portion of the physical design of the electronic circuit. The method or the system then determines and displays an in situ response to the manipulation in the first display area. The method or the system may further display, in the first display area or in another display area, result(s) relating to the physical data of a component, electrical parasitic(s) associated with the physical data, electrical characteristic(s) associated with the physical data or the electrical characteristic(s), or other element(s) of the physical design that is impacted by the manipulation. | 01-26-2012 |
20120060137 | Method for designing wiring topology for electromigration avoidance and fabrication method of integrate circuits including said method - A method for designing wiring topology for electromigration avoidance, which is composed of multiple sources, multiple sinks and multiple wires, is disclosed. The steps of said method to get an optimal topology includes: 1. calculating the length of all the wires to choose one of the wires with the shortest length as a feasible wire, 2. deciding a capacity of the feasible wire, 3. deciding the capacities of the other wire according to the capacity of the feasible wire, a flow of the source of the feasible wire and a flow of the sink of the feasible wire, 4. comparing the length of the other wires to select another feasible wire, 5. repeating said steps until finding all feasible wires for constructing a feasible topology, 6. creating a flow network according to the feasible topology, 7. iteratively checking if a negative cycle exists in the flow network and removing it until no more negative cycles. | 03-08-2012 |
20120124540 | DESIGN ASSISTING APPARATUS, METHOD, AND PROGRAM - A design assisting apparatus includes a memory configured to store routing information representing first wire line from wire lines of a module belonging to a first layer of a semiconductor circuit having a plurality of layers, the first wire line likely to become either one of an aggressor net and a victim net in a crosstalk noise check performed on wire lines of a module belonging to a second layer hierarchically higher than the first layer, and a processor configured to perform a wire line identifying operation identifying second wire line within the module belonging to the second layer, and likely to become either one of an aggressor net and a victim net in the crosstalk noise check performed on the first wire line represented by the routing information stored on the memory. | 05-17-2012 |
20120131532 | Substrate Noise Assessment Flow In Mixed-Signal And SOC Designs - A substrate noise checking methodology is disclosed. A tool is provided that aggregates the noise effect of one or more of digital noise injectors on one or more receptors. The tool also provides a propagation macro-model for the noise from the digital noise injectors. With both models combined, full chip substrate noise assessment flow can be achieved. | 05-24-2012 |
20120204139 | DETERMINING MUTUAL INDUCTANCE BETWEEN INTENTIONAL INDUCTORS - Various methods for analyzing mutual inductance in an integrated circuit layout are disclosed. In one exemplary embodiment, for example, circuit design information indicative of a first inductor and a second inductor is received. A dipole moment associated with the first inductor is determined, where the magnetic field associated with the dipole moment is representative of magnetic fields created by respective turns in the first inductor. A mutual inductance between the first inductor and the second inductor is determined by determining a magnetic flux of the magnetic field of the dipole moment through surfaces bounded by respective wire segments of the second inductor. | 08-09-2012 |
20120254816 | NOISE REDUCTION USING FEEDBACK TO A WIRE SPREADER ROUTER - A computer implemented method, system, and/or computer program product reduce noise in a circuit. A level of noise imposed by an aggressor line on a victim line is determined. The aggressor line and the victim line are an aggressor/victim line pair from multiple aggressor/victim line pairs in a circuit. Determination of the noise level is conducted during a predetermined window of time during which a signal is being transmitted along the aggressor line. Each of the multiple aggressor/victim line pairs are ranked according to a level of noise being imposed by each aggressor line on each victim line. The spacing between a highest ranked aggressor/victim line pair is then expanded. | 10-04-2012 |
20120260225 | Accurate Parasitic Capacitance Extraction for Ultra Large Scale Integrated Circuits - A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC. | 10-11-2012 |
20120317530 | SOLUTIONS FOR ON-CHIP MODELING OF OPEN TERMINATION OF FRINGE CAPACITANCE - A computer-implemented method of generating a library object for an integrated circuit design is disclosed. In one embodiment, the method includes: analyzing a pair of integrated circuit design objects for fringe capacitance effects between the pair of integrated circuit design objects; and generating the library object accounting for the fringe capacitance effects prior to completion of a layout design for the integrated circuit design. | 12-13-2012 |
20120317531 | METHOD AND APPARATUS FOR PERFORMING VIA ARRAY MERGING AND PARASITIC EXTRACTION - Systems and techniques for performing parasitic extraction on a via array are described. If the via array is a single row or column via array, the system identifies a first via and a last via in the via array, and merges a set of vias between the first via and the last via into a center via. If the via array is a M×N (M≧2, N≧2) via array, the system merges the vias as follows: the first row and the last row of vias in the via array into a first row via and a last row via, respectively; the first column and the last column of vias in the via array into a first column via and a last column via, respectively; and a set of vias between the first and last rows and the first and last columns into a center via. | 12-13-2012 |
20130007686 | METHOD, SYSTEM AND PROGRAM STORAGE DEVICE FOR MODELING THE CAPACITANCE ASSOCIATED WITH A DIFFUSION REGION OF A SILICON-ON-INSULATOR DEVICE - Disclosed are embodiments of a method, system and program storage device for accurately modeling parasitic capacitance(s) associated with a diffusion region of a silicon-on-insulator (SOI) device and doing so based, at least in part, on proximity to adjacent conductive structures. In these embodiments, the layout of an integrated circuit design can be analyzed to determine, for the diffusion region, shape, dimension and proximity information. Then, a formula can be developed and used for determining the parasitic capacitance between the diffusion region and the substrate below (C | 01-03-2013 |
20130014070 | SYSTEMS AND METHODS FOR CREATING FREQUENCY-DEPENDENT NETLIST - A method includes creating a technology file including data for an integrated circuit including at least one die coupled to an interposer and a routing between the at least one die and the interposer, b) creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the at least one die and in the interposer based on the technology file, c) simulating a performance of the integrated circuit based on the netlist, d) adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and e) repeating steps c) and d) to optimize the at least one of the capacitive or inductive couplings. | 01-10-2013 |
20130024831 | SYSTEM-LEVEL METHOD FOR REDUCING POWER SUPPLY NOISE IN AN ELECTRONIC SYSTEM - In one embodiment, a method for reducing power supply noise within an electronic system that includes an integrated circuit (IC), a package, and a printed circuit board (PCB) connected by a plurality of power delivery networks (PDN) is disclosed. Power supply noise within the system is reduced by defining a voltage compression limit for each PDN of the electronic system; determining a voltage compression for each PDN of the electronic system during a plurality of switching events; comparing the voltage compression of each PDN of the electronic system to the voltage compression limit for each switching event; and in response to the voltage compression of each PDN of the electronic system exceeding the limit, modifying the electronic system to reduce the voltage compression below the limit. | 01-24-2013 |
20130132920 | NOISE ANALYSIS MODEL AND NOISE ANALYSIS METHOD - Provided is a noise analysis model and a noise analysis method that can analyze effects of substrate noise on each of elements included in a circuit to be analyzed. The noise analysis model includes first to third resistors. The first resistor serves as a substrate resistor in a semiconductor substrate between a first point set in the semiconductor substrate between a noise source and a transistor to which substrate noise from the noise source propagates through the semiconductor substrate and a second point set in the semiconductor substrate just below a back gate of the transistor. The second resistor serves as a substrate resistor in the semiconductor substrate between the second point and a fixed potential region near the transistor. The third resistor serves as a line resistor of a line connecting the fixed potential region and a power pad that supplies a ground potential. | 05-23-2013 |
20130145334 | DESIGN SUPPORTING APPARATUS AND INFORMATION PROCESSING METHOD THEREOF - Design information including layout information of a print circuit board associated with an electronic equipment, and component information is acquired, and a verification condition associated with crosstalk noise is input. Information of signal lines which should verify influence of the crosstalk noise are extracted from the design information. Based on the verification condition, a signal line, which crosses or overlaps a signal line other than the signal line corresponding to the extracted information planerly viewed from a laminating direction of layers of the print circuit board, of the signal lines corresponding to the extracted information is detected as a victim wiring. | 06-06-2013 |
20130159954 | DESIGN METHOD OF ON-BOARD WIRING - A design method of on-board wiring for a designed circuit includes determining a severity as a crosstalk prevention index for a pair of wires based on a generated noise level of a damaging side wire and a permissible noise level of a damaged side wire. The pair of wires is then assigned a severity class (SC) based on the severity determined. The SC is a pre-defined value range(s) for severity classification. Based on a preset SC specific permissible value list, one or more by-design permissible values belonging to the SC is generated for a design element of the pair of wires. A layout of the pair of wires on a board is constructed based on the by-design permissible value. | 06-20-2013 |
20130167099 | NOISE ANALYSIS USING TIMING MODELS - Various embodiments include apparatuses and methods to perform noise analysis on a circuit at a selected condition (e.g., process, voltage, and temperature) using a timing model of the circuit in which the timing model is associated with the selected condition. | 06-27-2013 |
20130198711 | POWER LAYOUT FOR INTEGRATED CIRCUITS - A method for a power layout of an integrated circuit. The method includes providing at least one unit power cell. The unit power cell includes at least one power grid cell. Each power grid cell has at least one first power layer configured to be coupled to a high power supply voltage and at least one second power layer configured to be coupled to a lower power supply voltage. The first power layer has conductive lines in at least two different directions and the at least one second power layer has conductive lines in at least two different directions. The method further includes filling a target area in the power layout by at least one unit power cell to implement at least one power cell. | 08-01-2013 |
20130305203 | MULTI-PASS ROUTING TO REDUCE CROSSTALK - An integrated circuit (IC) or a block of an IC is routed. The signals of the netlist to be routed are grouped according the signal properties. A signal property may be the time or clock used to initiate the switching of the signal. The signals of each group are routed successively. This causes the signals of later groups to be routed between the signals of previous groups thereby providing shielding between signals lines of the same group. | 11-14-2013 |
20130305204 | HIERARCHICAL FEATURE EXTRACTION FOR ELECTRICAL INTERACTION CALCULATIONS - A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions. | 11-14-2013 |
20130326452 | METHOD, DEVICE, AND A COMPUTER-READABLE RECORDING MEDIUM HAVING STORED PROGRAM FOR INFORMATION PROCESSING FOR NOISE SUPPRESSION DESIGN CHECK - A computer-readable recording medium having stored therein a program for causing a computer to execute a process for information processing comprising: performing, for a plurality of noise countermeasure design checks for a plurality of nets provided on a substrate, an initial noise countermeasure design check on each of the plurality of nets in an execution order determined, when one of the checks is passed, on the basis of other noise countermeasure design checks that may be skipped; and performing, if it is determined on the basis of at least a check result of a noise countermeasure design check which has been performed immediately before a corresponding check that there is a next noise countermeasure design check that may not be skipped in the execution order, the next noise countermeasure design check for each of the plurality of nets. | 12-05-2013 |
20130326453 | CIRCUIT LAYOUT METHOD FOR PRINTED CIRCUIT BOARD, ELETRONIC DEVICE AND COMPUTER READABLE RECORDING MEDIA - The present disclosure illustrates a circuit layout method for printed circuit board which is adapted for an electronic device. The circuit layout method includes the following steps. A parameters configuration interface is provided for receiving corresponding stack-up parameters and a plurality of layout parameters. A radio frequency layer, a first keep out layer, and a reference layer are determined based on the stack-up parameters. The first keep-out layer is placed between the radio frequency layer having a first signal trace disposed thereon and the reference layer. A first keep-out region on the first keep-out layer is formed in corresponding to the first signal trace. Circuit layouts disposed inside the first keep-out region are removed. Consequently, the corresponding keep-out region may be automatically generated in accordance to the signal requirements of the signal trace while designing the circuit layout thereby increase circuit layout quality and efficiency thereof. | 12-05-2013 |
20140019930 | SEMICONDUCTOR DEVICE DESIGN METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT - In a semiconductor device design method performed by at least one processor, at least one first parasitic parameter between electrical components inside a region of a layout of a semiconductor device and at least one second parasitic parameter between electrical components outside the region of the layout are extracted by different tools. The extracted parasitic parameters are incorporated into the layout. | 01-16-2014 |
20140040846 | CROSSTALK ANALYSIS METHOD - An embodiment of the disclosure provides a crosstalk analysis method executed by a computer. The method includes steps of: executing a layout program; executing a crosstalk analysis program; acquiring, by the crosstalk analysis program, a plurality of parameters from a layout result generated by the layout program; estimating a crosstalk value according to the parameters; determining whether the crosstalk value is larger than a predetermined value; generating a layout suggestion when the crosstalk value is larger than the predetermined value. | 02-06-2014 |
20140068538 | AUTOMATED NOISE CHARACTERIZATION AND COMPLETENESS AND CORRECTNESS OF NOISE DELIVERABLES - Methods, systems and processor-readable media for automatic self-tracking of input deliverables for noise characterization. A noise characterization run to generate a noise model thereof can be automatically initiated. The noise model can be delivered into a repository in response to completing the noise characterization run and generating the noise model. Data associated with the noise model can be tracked for subsequent analysis including checking completeness and a correctness of the noise model delivered into the repository, The data associated with the noise model can then be rendered for the subsequent analysis. Data associated with the noise model can include, for example, information regarding pending tasks, assignment information, and data contained in a noise database. | 03-06-2014 |
20140068539 | ELECTRONIC APPARATUS, METHOD OF OPTIMIZING DE-COUPLING CAPACITOR AND COMPUTER-READABLE RECORDING MEDIUM - An electronic apparatus may include a circuit board, a processor disposed on an upper surface of the circuit board, and a memory disposed on a lower surface of the circuit board, such that the lower surface of the circuit board where the processor is arranged overlaps an area corresponding to where the memory is disposed. | 03-06-2014 |
20140082578 | RC EXTRACTION METHODOLOGY FOR FLOATING SILICON SUBSTRATE WITH TSV - The present disclosure relates to methods and apparatuses for generating a through-silicon via (TSV) model for RC extraction that accurately models an interposer substrate comprising one or more TSVs. In some embodiments, a method is performed by generating an interposer wafer model having a sub-circuit that models a TSV. The sub-circuit can compensate for limitations in resistive and capacitive extraction of traditional TSV models performed by EDA tools. In some embodiments, the sub-circuit is coupled to a floating common node of the model. The floating common node enables the interposer wafer model to take into consideration capacitive coupling within the interposer. The improved interposer wafer model enables accurate RC extraction of an interposer with one or more TSVs, thereby providing for an interposer wafer model that is consistent between GDS and APR flows. | 03-20-2014 |
20140109030 | Method of Determining Electromigration (EM) Lifetimes and Lifetime Criteria - Methods are described for performing detailed Technology Computer Aided Design (TCAD) simulations of electromigration (EM) failure in a standard test structure suitable for the simulation of integrated circuit (IC) conductive interconnects. Methods are described for performing these simulation so as to extract from the results of these simulations criteria substantially underlying the EM lifetime of interconnects, thereby permitting rapid diagnosis of potential sites of EM failure early in the IC design and fabrication process, and thereby allowing more rapid development of reliable ICs robust against EM failure. Specific results for EM failure criteria in Cu interconnects are also presented. | 04-17-2014 |
20140137063 | CIRCUIT NOISE EXTRACTION USING FORCED INPUT NOISE WAVEFORM - Techniques for use in integrated circuit design systems for extracting noise threshold data for selected cells. For example, a method comprises the following steps. A cell is selected from one or more cells in a given collection of standardized cells. Each of the one or more cells represents one or more functional circuit design blocks that are usable as part of a design of an integrated circuit. A noise signal is generated or selected. The noise signal is applied to an input node of the selected cell. Noise threshold data is identified using a noise analysis module, for a given set of process, voltage and temperature variations, for an output node of the selected cell based on the noise signal applied to the input node of the selected cell. The noise threshold data is stored with the selected cell as part of the given collection of standardized cells such that the noise threshold data is subsequently usable during a post layout noise analysis operation of an integrated circuit design that includes the selected cell. | 05-15-2014 |
20140157219 | SUPPORT APPARATUS, DESIGN SUPPORT METHOD, AND COMPUTER-READABLE RECORDING MEDIUM - A design support apparatus calculates a crosstalk noise value when a power line does not run parallel, for each of a plurality of sections. Moreover, the design support apparatus calculates a coefficient Fshield that becomes larger with decrease in the area of the power line included in an area between two signal lines based on a relative positional relationship between the two signal lines and the power line in a section, for each of the plurality of sections. Moreover, the design support apparatus corrects the crosstalk noise value corresponding to a section, using the coefficient Fshield corresponding to the section, for each of the plurality of sections. Moreover, the design support apparatus calculates a total of the corrected crosstalk noise values corresponding respectively to the plurality of sections as a crosstalk noise value between the two signal lines. | 06-05-2014 |
20140173543 | PARASITIC EXTRACTION IN AN INTEGRATED CIRCUIT WITH MULTI-PATTERNING REQUIREMENTS - Systems and methods are provided for extracting parasitics in a design of an integrated circuit with multi-patterning requirements. The method includes determining resistance solutions and capacitance solutions. The method further includes performing parasitic extraction of the resistance solutions and the capacitance solutions to generate mean values for the resistance solutions and the capacitance solutions. The method further includes capturing a multi-patterning source of variation for each of the resistance solutions and the capacitance solutions during the parasitic extraction. The method further includes determining a sensitivity for each captured source of variation to a respective vector of parameters. The method further includes determining statistical parasitics by multiplying each of the resistance solutions and the capacitance solutions by the determined sensitivity for each respective captured source of variation. The method further includes generating as output the statistical parasitics in at least one of a vector form and a collapsed reduced vector form. | 06-19-2014 |
20140189628 | SYSTEM AND METHOD OF CROSSOVER DETERMINATION IN DIFFERENTIAL PAIR AND BONDWIRE PAIRS TO MINIMIZE CROSSTALK - A system is provided for use with circuit layout design data having a set of differential pairs and a set of bond wire pairs. A layout portion can receive the circuit layout design data. A crosstalk calculating portion can determine a first amount of crosstalk in a circuit corresponding to the circuit layout design data. A modifier can modify the circuit layout design data into modified circuit layout design data such that one of the set of differential pairs and the set of bond wire pairs includes a crossover. The crosstalk calculating portion can further determine a second amount of crosstalk in a circuit corresponding to the modified circuit layout design data. An optimizer can compare the first amount of crosstalk with the second amount of crosstalk to generate optimized circuit layout design data. A layout designer can output the optimized circuit layout design data. | 07-03-2014 |
20140223401 | HIGH-FREQUENCY VLSI INTERCONNECT AND INTENTIONAL INDUCTOR IMPEDANCE EXTRACTION IN THE PRESENCE OF A MULTI-LAYER CONDUCTIVE SUBSTRATE - Embodiments of methods, apparatus, and systems for extracting impedance for a circuit design are disclosed herein. Some of the disclosed embodiments are computationally efficient and can accurately compute the frequency-dependent impedance of VLSI interconnects and/or intentional inductors in the presence of multi-layer conductive substrates. In certain embodiments, the resulting accuracy and CPU time reduction are a result of a Green's function approach with the correct quasi-static limit, a modified discrete complex image approximation to the Green's function, and a continuous dipole expansion to evaluate the magnetic vector potential at the distances relevant to VLSI interconnects and intentional inductors. | 08-07-2014 |
20140250415 | CROSSTALK ANALYSIS METHOD - One implementation of the disclosure provides a crosstalk analysis method executed by a computer. The method includes steps of: executing a layout program; executing a crosstalk analysis program; acquiring, by the crosstalk analysis program, a plurality of parameters from a layout result generated by the layout program; estimating a crosstalk value according to the parameters; determining whether the crosstalk value is larger than a predetermined value; providing a layout suggestion table when the crosstalk value is larger than the predetermined value. | 09-04-2014 |
20140258958 | METHOD FOR CONVERSION OF COMMERCIAL MICROPROCESSOR TO RADIATION-HARDENED PROCESSOR AND RESULTING PROCESSOR - A method is provided to convert commercial microprocessors to radiation-hardened processors and, more particularly, a method is provided to modify a commercial microprocessor for radiation hardened applications with minimal changes to the technology, design, device, and process base so as to facilitate a rapid transition for such radiation hardened applications. The method is implemented in a computing infrastructure and includes evaluating a probability that one or more components of an existing commercial design will be affected by a single event upset (SEU). The method further includes replacing the one or more components with a component immune to the SEU to create a final device. | 09-11-2014 |
20140258959 | SUPPORT TECHNIQUE - A present design support method includes: arranging capacitance cells in an entire area of a cell arrangement area of a semiconductor integrated circuit , before arranging logic cells; upon detecting that a position at which a certain logic cell will be arranged is designated, calculating a total sum of capacitance for a first capacitance check area that includes the position among plural capacitance check areas that are included in the cell arrangement area, while assuming that a capacitance cell at the position is removed; calculating a total sum of necessary capacitance for the first capacitance check area, while assuming that the certain logic cell is arranged at the position and outputting information that represents a relationship between the total sum of capacitance and the total sum of necessary capacitance for the first capacitance check area. | 09-11-2014 |
20140282337 | SEMICONDUCTOR DEVICE DESIGN METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT - A semiconductor device design method performed by at least one processor comprises extracting, using a resistance and capacitance (RC) extraction tool, at least one first parasitic capacitance among electrical components inside one or more regions of a plurality of regions in a layout of a semiconductor device. The method also comprises extracting, using the RC extraction tool, at least one second parasitic capacitance among electrical components outside the regions of the plurality of regions. The method further comprises combining, using a netlist generator tool, the extracted first and second parasitic capacitances into a netlist representing the layout. The RC extraction tool is configured to extract the first parasitic capacitances inside at least one region of the plurality of regions using a methodology more accurate than that for extracting the second parasitic capacitances. | 09-18-2014 |
20140317585 | CROSSTALK ANALYSIS METHOD - An embodiment of the disclosure provides a crosstalk analysis method executed by a computer including: executing a layout program for a layout circuit; executing a crosstalk analysis program; acquiring, by the crosstalk analysis program, a plurality of parameters from a layout result generated by the layout program; estimating a crosstalk value according to the parameters; determining whether the crosstalk value is larger than a predetermined value; providing an interface for showing information of the layout result and adjusting a plurality of lines of the layout circuit. | 10-23-2014 |
20140351779 | INTEGRATED CIRCUIT (IC) DESIGN METHOD WITH ENHANCED CIRCUIT EXTRACTION MODELS - A method is provided for designing an IC chip. The method includes receiving data from a pre-layout design process for the IC chip, routing a plurality of interconnecting wires to connect various devices of the IC chip, and extracting various circuit parameters. The method also includes simulating the IC chip using the extracted various circuit parameters to detect logic or timing error in the IC chip. The extracting the various circuit parameters includes establishing a statistical interconnect technology profile (ITP) file containing at least interconnect parasitic parameters based on correlations of interconnect layer geometric parameter variations. | 11-27-2014 |
20140365986 | Method Of Optimizing Capacitive Couplings In High-Capacitance Nets In Simulation Of Post-Layout Circuits - A method of asymmetric asynchronous decoupling of capacitors in an integrated circuit design is provided for faster simulation by circuit simulators, e.g. FastSPICE circuit simulators. This method includes removing a coupling capacitor from a list, which includes coupling capacitors that capacitively couple two nets in the design. The two nets have capacitances C | 12-11-2014 |
20150046891 | Cross-Talk Noise Computation Using Mixed Integer Linear Program Problems And Their Solutions - A method includes forming a mixed integer linear problem (MILP) capturing at least a plurality of timing windows over which aggressor net(s), electromagnetically coupled to a victim net in a circuit, produce computed cross-talk noise pulses potentially contributing to a maximum noise for the victim net. The MILP is solved to determine the maximum noise at the victim net. Responsive to the maximum noise meeting one or more criteria, at least an indication of the victim net is output. Forming may include forming a linear problem using overlapping timing windows for which noise pulses contribute to the maximum noise and converting the linear problem to the mixed integer linear problem by introducing into the linear problem binary variables that determine whether individual ones of overlapping or non-overlapping noise pulses from the one or more aggressor nets contribute to the maximum noise. Apparatus and program products are also disclosed. | 02-12-2015 |
20150046892 | Cross-Talk Noise Computation Using Mixed Integer Linear Program Problems And Their Solutions - A method includes forming a mixed integer linear problem (MILP) capturing at least a plurality of timing windows over which aggressor net(s), electromagnetically coupled to a victim net in a circuit, produce computed cross-talk noise pulses potentially contributing to a maximum noise for the victim net. The MILP is solved to determine the maximum noise at the victim net. Responsive to the maximum noise meeting one or more criteria, at least an indication of the victim net is output. Forming may include forming a linear problem using overlapping timing windows for which noise pulses contribute to the maximum noise and converting the linear problem to the mixed integer linear problem by introducing into the linear problem binary variables that determine whether individual ones of overlapping or non-overlapping noise pulses from the one or more aggressor nets contribute to the maximum noise. Apparatus and program products are also disclosed. | 02-12-2015 |
20150095867 | SEMICONDUCTOR CIRCUIT DESIGN METHOD, MEMORY COMPILER AND COMPUTER PROGRAM PRODUCT - A method of designing a semiconductor circuit includes generating a model of the semiconductor circuit. The model includes a functional area corresponding to a first block of the semiconductor circuit, and a loading area corresponding to a second block of the semiconductor circuit, wherein the first block is connected to the second block by a signal line. The method further includes extracting, in the functional area, parasitic parameters of the signal line and a device of the first block. The method further includes extracting, in the loading area, parasitic parameters of the signal line, without extracting parasitic parameters of a device of the second block. | 04-02-2015 |
20150143317 | Determination Of Electromigration Features - For one or more geometric elements partitioned into a plurality of geometric element portions, the expected current directions through each geometric element portion are determined. Using the expected current directions, each expected current path through the geometric element portions is determined. Based upon the expected current paths, and the physical characteristics represented by the geometric element portions in those expected current paths, the electromigration features corresponding to the geometric element or elements are determined. For example, the length of the longest expected current path through the geometric element or elements can be identified based upon the lengths of the geometric element portions and the directions of their currents, and this length can then be compared with the Blech length for the geometric element or elements. | 05-21-2015 |
20150143318 | DETERMINATION OF ELECTROMIGRATION SUSCEPTIBILITY BASED ON HYDROSTATIC STRESS ANALYSIS - Aspects of the invention relate to techniques for determining the electromigration features corresponding to layout design data. According to various examples of the invention, a circuit design is analyzed to determine voltages of nodes in an interconnect tree. From the voltages of the nodes, current density values and current directions for the segments of the interconnect tree are determined. Based on the current density values and the current directions, hydrostatic stress values for the nodes are computed under a steady-state condition and conservation of the conductive material within the interconnect tree. The electromigration susceptibility of the interconnect tree is then determined based on the computed hydrostatic stress values. | 05-21-2015 |
20150324511 | FLOATING METAL FILL CAPACITANCE CALCULATION - A design layout is obtained that includes floating fill shapes and signal shapes. Capacitance of the signal shapes is calculated. A simple model is used to calculate a first subset of fill shapes which contribute capacitance to the signal shapes. A capacitance model selected to meet an acceptable error level using minimum computational requirements is then selected from a set of capacitance models. The selected capacitance model is then used to extract the capacitance contribution from the first subset of fill shapes. A second subset of fill shapes is then created based on the extracted capacitance values, and if the estimated capacitance contribution is significant, the capacitance of the second subset extracted using the selected capacitance model. Additional iterations are performed for additional signal shapes. | 11-12-2015 |
20150331987 | VIRTUAL SUB-NET BASED ROUTING - A method and system to route connections of sub-networks in a design of an integrated circuit and a computer program product are described. The method includes determining a baseline route for each of the connections of each of the sub-networks, identifying noise critical sub-networks in the design of the integrated circuit based on congestion, and setting a mean threshold length (MTL), the MTL indicating a maximum length of each segment of each connection. Each segment includes a wirecode which is different from a wirecode of an adjacent segment, each wirecode defining a width, a metal layer, and a spacing for each segment. The method also includes segmenting the connections of the noise critical sub-networks based on the MTL, and re-routing the baseline route based on the segmenting. | 11-19-2015 |
20150347665 | Cell-Level Signal Electromigration - A circuit design system includes a simulator that determines an average charging current provided by each current insertion point in a cell and an average charging current along a path in the cell between a reference pin position and a candidate pin position. A candidate pin placement tester updates the average charging current along the path by adding the average charging current of each insertion point to the average charging current along the path to produce an updated average charging current along the path and uses the updated average charging current along the path to determine a time to failure for the cell. | 12-03-2015 |
20150347668 | INFORMATION PROCESSING APPARATUS, METHOD, AND STORAGE MEDIUM - In a layout design of a printed circuit board, more accurate bypass capacitor arrangement that has taken into consideration a wiring within a package of an IC is implemented. An information processing apparatus according to the present invention includes: a die pad specifying unit configured to specify a power source pad of a die and a ground pad of the die from design information on a printed circuit board; a bypass capacitor specifying unit configured to specify a bypass capacitor that is arranged on the printed circuit board from the design information; and a unit configured to derive an evaluation value for evaluating the arrangement of the specified bypass capacitor based on the design information, information on the specified power source pad of the die and ground pad of the die, and information on the specified bypass capacitor. | 12-03-2015 |
20150356229 | PHYSICAL CELL ELECTROMIGRATION DATA GENERATION - Systems and methods for efficiently generating electromigration reliability data for physical cells in an integrated circuit cell library are disclosed. Data for tables of electromigration susceptibility can be iteratively generated for multiple capacitive loadings on a cell output and for multiple transition times of a cell input. Each iteration can include simulating electrical performance of the physical cell and identifying a region with the largest ratio of current density to electromigration reliability limit. Between iterations, the data period of the input signal is updated using the ratio of current density to electromigration reliability limit and a relationship between currents and data period. Iterations may end when the ratio is close to one. The result can be used to evaluate electromigration reliability of an integrated circuit design and modify the design accordingly. | 12-10-2015 |
20160004809 | POWER RAIL FOR PREVENTING DC ELECTROMIGRATION - A method is disclosed that includes the operations outlined below. A first criteria is determined to be met when directions of a first current and a second current around a first end and a second end of a metal segment respectively are opposite, in which the metal segment is a part of a power rail in at least one design file of a semiconductor device and is enclosed by only two terminal via arrays. A second criteria is determined to be met when a length of the metal segment is not larger than a electromigration critical length. The metal segment is included in the semiconductor device with a first current density limit depending on the length of the metal segment when the first and the second criteria are met. | 01-07-2016 |
20160034633 | Modeling TSV Interposer Considering Depletion Capacitance and Substrate Effects - In a method for modeling electromagnetic effects in a planar circuit that employs a plurality of through-silicon vias in a domain, a region around each through-silicon via is described in terms of a cylindrical accumulation mode basis function. The cylindrical accumulation mode basis function is incorporated into an equivalent circuit that describes selected electrical characteristics of each through-silicon via. A plurality of localized intervals around each through-silicon via is selected. A multilayer Green's function is approximated for I | 02-04-2016 |
20160147934 | DETERMINATION OF ELECTRONIC CIRCUIT ROBUSTNESS - Technologies are generally described that relate to analysis of circuits and that facilitate determination of electronic circuit robustness. An example method includes performing, for a cell device by a unit including a processor, statistical analysis to obtain statistical information for the cell device that is indicative of a robustness of the cell device. The robustness of the cell device pertains to a parameter variation of the cell device that is related to a noise of the cell device. The method also includes determining a characteristic of the cell device based on the statistical information. | 05-26-2016 |
20160154923 | METHOD OF ANALOG FRONT END OPTIMIZATION IN PRESENCE OF CIRCUIT NONLINEARITY | 06-02-2016 |
20160154924 | SEMICONDUCTOR DESIGN METHOD AND COMPUTER-READABLE RECORDING MEDIUM | 06-02-2016 |
20160161546 | COMPUTING DEVICE EXECUTING PROGRAM PERFORMING METHOD OF ANALYZING POWER NOISE IN SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE DESIGN METHOD, AND PROGRAM STORAGE MEDIUM STORING PROGRAM - A method of analyzing power noise in a semiconductor device includes; generating modified current information by modifying present current information based on a previous analysis result, updating a current vector based on the modified current information, and generating a present analysis result by calculating a voltage vector from the updated current vector. | 06-09-2016 |
20160180008 | METHOD OF DESIGNING CIRCUIT LAYOUT AND SYSTEM FOR IMPLEMENTING THE SAME | 06-23-2016 |
20160180014 | ENHANCING INTEGRATED CIRCUIT NOISE PERFORMANCE | 06-23-2016 |