| Entries |
| Document | Title | Date |
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| 20110041110 | METHOD OF DERIVING AN INTEGRATED CIRCUIT SCHEMATIC DIAGRAM - A method, computer-readable medium and system are described for deriving a schematic diagram representative of an integrated circuit ( | 02-17-2011 |
| 20110047522 | Hardware Description Language Editing Engine - Technologies for editing a circuit design implemented in a hardware description language are provided. A representation of a circuit design described by a syntactic description of the circuit is generated. Subsequently, a modification operation is carried out on the circuit design representation after which a modified syntactic description may be generated from the modified representation. | 02-24-2011 |
| 20110055782 | PROXIMITY-AWARE CIRCUIT DESIGN METHOD - A method for proximity-aware circuit design where a set of layout constraint values that satisfy predetermined performance or yield goals is determined in accordance with a layout effect model. One of the layout constraint values is then selected as a constraint input to layout design, and a design layout is performed with the selected layout constraint value to provide a semiconductor circuit design for the semiconductor circuit. The set of layout constraint values can be determined by varying an instance parameter of the layout effect model to determine a set of instance parameters that satisfy the at least one predetermined performance or yield goal in accordance with the layout effect model, and determining layout constraints associated with each instance parameter of the set of instance parameters, thus providing a number of candidates in a design space that can be evaluated according to performance and/or yield tradeoffs. | 03-03-2011 |
| 20110088006 | METHOD FOR LAYOUT VERIFICATION OF SEMICONDUCTOR INTEGRATED CIRCUIT - A method for verifying a match between layout patterns of elements provided in a semiconductor integrated circuit, includes a verification condition setting step of setting a verification condition including information about paired elements whose layout patterns should match each other, a layout data input step of inputting layout data including pattern information and arrangement information of the paired elements, and a mismatched pattern parameter calculation layout verifying step of comparing the layout patterns of the paired elements based on the verification condition and the layout data to calculate a distance between the paired elements and at least one mismatched pattern. | 04-14-2011 |
| 20110093826 | METHOD AND SYSTEM FOR MODEL-BASED ROUTING OF AN INTEGRATED CIRCUIT - Disclosed is a method, system, and computer program product for implementing model-based floorplanning, layout, placement, and routing. Models are used to guide the placement and routing of polygons on the IC layout based upon predictions of manufacturing variations. | 04-21-2011 |
| 20110145772 | Modular Platform For Integrated Circuit Design Analysis And Verification - A modular electronic design automation tool platform for analyzing and verifying an integrated circuit design. The platform may provide a single, unified database that can contain both logical information and physical information relating to an integrated circuit design, together with a plurality of electronic design automation operation execution modules for performing one or more desired electronic design automation operations. The platform may also provide export modules and import modules. An export module extracts relevant data from the database, and configures that data for use by a specific electronic design automation operation execution module. An import module then receives output data from a particular electronic design automation operation execution module, configures that data for integration into the unified database, and then imports the configured data into the database. | 06-16-2011 |
| 20110145773 | Method of Optimizing Automotive Electrical Wiring - A method is provided for selecting wiring components for a circuit including at least one predetermined load. A user identifies a fuse type. A target current needed to achieve a desired fuse blow time for the identified fuse type is obtained from a lookup table. A minimum wire size for supporting steady state operation of the circuit is also obtained from a lookup table. The user identifies one or more wire segments to be included in the circuit, including specifying each respective wire length. An aggregate circuit resistance including each identified wire segment is calculated, wherein when a wire segment is first identified it is assigned the minimum wire size and its resistance is determined based on its respective length. A provisional short circuit current is calculated in response to the aggregate circuit resistance. The provisional short circuit current is compared to the target current. If the provisional short circuit current is less than the target current, the user is prompted to select an increased wire size for at least one wire segment. Otherwise, an optimized circuit is indicated to the user. | 06-16-2011 |
| 20110145774 | TESTING EMBEDDED MEMORIES IN AN INTEGRATED CIRCUIT - Various new and non-obvious apparatus and methods for testing embedded memories in an integrated circuit are disclosed. One of the disclosed embodiments is an apparatus for testing an embedded memory in an integrated circuit. This exemplary embodiment comprises input logic that includes one or more memory-input paths coupled to respective memory inputs of the embedded memory, a memory built-in self-test (MBIST) controller, and at least one scan cell coupled between the input logic and the MBIST controller. The scan cell of this embodiment is selectively operable in a memory-test mode and a system mode. In memory-test mode, the scan cell can apply memory-test data to the memory inputs along the memory-input paths of the integrated circuit. Any of the disclosed apparatus can be designed, simulated, and/or verified (and any of the disclosed methods can be performed) in a computer-executed application, such as an electronic-design-automation (“EDA”) software tool. | 06-16-2011 |
| 20110154281 | OPTICAL LITHOGRAPHY CORRECTION PROCESS - A apparatus and method for correcting a process critical layout includes characterizing the influence of individual ones of a set of worst case process variations on a simulated nano-circuit layout design and then correcting layout geometries in the simulated nano-circuit layout based on such characterizations. | 06-23-2011 |
| 20110167397 | SYSTEM AND METHOD FOR MULTI-EXPOSURE PATTERN DECOMPOSITION - Some embodiments provide a method and system for identifying error markers for patterns within a design layout that do not meet the manufacturing constraints. Some embodiments extend a region from the error marked region to extract a pattern for decomposition analysis. Some embodiments compare the extracted pattern to known patterns stored in a library, which also stores at least one previously computed decomposition solution for each known pattern. For an extracted pattern existing within the library, some embodiments retrieve the previously computed decomposition solution from the library. For an extracted pattern that does not exist within the library, some embodiments use one or more simulations to determine a decomposition solution for the extracted pattern. The resulting decomposition solution replaces the extracted pattern within the design layout producing a variant of the original layout that contains the decomposed solution for the pattern. | 07-07-2011 |
| 20110167398 | DESIGN ASSISTANCE APPARATUS AND COMPUTER-READABLE RECORDING MEDIUM HAVING DESIGN ASSISTANCE PROGRAM STORED THEREIN - The present disclosure is directed to a technique that can be applied to a situation in which a single product is designed by multiple designers using a CAD. During a modification operation of feature data, portions that are referenced to are accumulated in a referenced portion accumulation unit. A portion that has been modified is obtained from new and old feature data, and a determination is made as to whether a reference to the modified portion has been made, based on the information accumulated in the referenced portion accumulation unit. Information about the modified portion that is determined as having been referenced to is displayed on a display. | 07-07-2011 |
| 20110185326 | NET LIST GENERATION METHOD AND CIRCUIT SIMULATION METHOD - Disclosed is a net list generation method of generating a net list based on layout data; stress map data indicating stress distribution on a silicon chip, the stress being generated due to packaging of the silicon chip; and standard curve data indicating a relationship between the stress and characteristic variation of a device. The method includes the steps of reading data items from the layout data; reading a value of stress at the position of the device from the stress map data; reading the characteristic variation of the device, the characteristic variation corresponding to the value of the stress, from the standard curve data corresponding to the device; and correcting characteristics of the device based on the characteristic variation. | 07-28-2011 |
| 20110202895 | VERIFICATION COMPUTER PRODUCT, METHOD, AND APPARATUS - A recording medium stores a verification program that causes a computer to execute detecting from a model circuit, a first circuit representing junction of a source region and a substrate region and including a junction resistance and a junction capacitance, a second circuit parallel to the first circuit, representing junction of a drain region and the substrate region, and including a junction resistance and a junction capacitance equivalent to the junction resistance and capacitance of the first circuit, and a connection resistance connecting the circuits and a substrate electrode; calculating, using the junction resistances and connection resistance, a first coefficient indicating impact of the junction resistances and connection resistance on amplitude variation; calculating, using the junction capacitances and connection resistance, a second coefficient indicating impact of the junction capacitances and connection resistance on phase variation; correcting the junction capacitances using a sum of the coefficients; and outputting a correction result. | 08-18-2011 |
| 20110214099 | CIRCUIT DIAGRAM GENERATION SYSTEM AND METHOD - In a method and system for automatically generating a circuit diagram for a wiring design of a circuit board, a preset output format of wiring attributes of the wiring design for the circuit board is received. A board file is created. Initial parameters of the wiring design for the circuit board are preset. The wiring attributes of the wiring design are determined by simulating and analyzing the wiring design, and be backed up into a document. The wiring attributes are imported into the board file according to the preset output format. A circuit diagram is generated according to the wiring design and the initial parameters, and is adjusted using the wiring attributes in the board file. | 09-01-2011 |
| 20110246955 | METHOD, PROGRAM, AND APPARATUS FOR AIDING WIRING DESIGN - A wiring-design aiding method for causing a computer to execute generating paths for buses so that the buses do not cross each other with respect to a wiring area including at least one wiring layer, the paths being represented by corresponding graphics The computer further executes verifying, for each bus, whether wires for nets belonging to the bus are successfully extracted from a component to which the bus is connected; and recording, in the wiring area, graphics representing the nets belonging to a bus for which it is determined in the verification that all the nets belonging to the bus are successfully extracted. The bus-path generation is re-executed with respect to the bus for which it is determined in the verification that at least one of the nets is not successfully extracted. | 10-06-2011 |
| 20110265054 | Design-Rule-Check Waiver - When a designer designates one or more errors identified in layout design data as false errors, waiver geometric elements corresponding to the designated false errors are created and added to the design. The waiver geometric element may be associated with a verification rule that generated its corresponding false error. When the design is subsequently analyzed using those verification rules in another verification rule check process, the waiver geometric elements are examined, and used to mask those errors associated with a waiver geometric element that would otherwise be displayed to the designer. | 10-27-2011 |
| 20110276935 | SYSTEMS AND METHODS FOR DETECTING DESIGN AND PROCESS DEFECTS ON A WAFER, REVIEWING DEFECTS ON A WAFER, SELECTING ONE OR MORE FEATURES WITHIN A DESIGN FOR USE AS PROCESS MONITORING FEATURES, OR SOME COMBINATION THEREOF - Various systems and methods for detecting design and process defects on a wafer, reviewing defects on a wafer, selecting one or more features within a design for use as process monitoring features, or some combination thereof are provided. | 11-10-2011 |
| 20110296362 | SEMICONDUCTOR DEFECT INTEGRATED PROJECTION METHOD AND DEFECT INSPECTION SUPPORT APPARATUS EQUIPPED WITH SEMICONDUCTOR DEFECT INTEGRATED PROJECTION FUNCTION - The present invention comprises: a design layout data read part that acquires design layout data including location information of design circuit patterns used in steps of semiconductor fabrication; a wafer-chip information read part that acquires, from among data concerning a wafer on which a plurality of the design circuit patterns are formed per chip, wafer-chip information including at least design cell location information; a defect data read part that acquires defect data including location information of defects that occurred in the steps; a design layout data tracing processing part that creates a design layout data defect integrated projection display view by performing, based on the design layout data and the wafer-chip information, an integrated projection process on, among the design layout data, design layout data for a step in which a defect occurred and the defect data; and a defect integrated projection display apparatus that displays the design layout data defect integrated projection display view. | 12-01-2011 |
| 20120011482 | MULTIPLE THRESHOLD VOLTAGE CELL FAMILIES BASED INTEGRATED CIRCUIT DESIGN - A method, system, and computer usable program product for multiple threshold voltage cell families (mVt families) based integrated circuit design are provided in the illustrative embodiments. The integrated circuit includes cells, and a cell includes an electronic component. A design process is initialized by using cells from the mVt families in the design. The cells from the mVt families are included in iterative manipulation of the design. The cells from the mVt families are further included in violation cleanup and subsequent steps of the design process. A version of the design is produced that is usable to implement the circuit with the cells from the mVt families. | 01-12-2012 |
| 20120023467 | METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR IMPLEMENTING ELECTRONIC CIRCUIT DESIGNS WITH ELECTRICAL AWARENESS - Disclosed are a method, system, and computer program product for implementing electronic circuit designs with electrical awareness. The method or the system updates the schematic level tool(s) and physical design tool(s) with electrical parasitic data or electrical characteristic data associated with electrical parasitics so both schematic and physical design tools are aware of the electrical parasitic or characteristic data in performing their functions such as extraction based simulations. The methods or systems are also aware of EM or IR-drop constraint(s) while implementing or creating a partial layout less than a complete layout. The method or the system also provides a user interface for a design tool to provide in situ, customizable, real-time information for implementing electronic circuit designs with electrical awareness. The methods or systems also support constraint verification for electronic circuit design implementation with electrical awareness. | 01-26-2012 |
| 20120023468 | METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR CONSTRAINT VERIFICATION FOR IMPLEMENTING ELECTRONIC CIRCUIT DESIGNS WITH ELECTRICAL AWARENESS - Disclosed are methods, systems, and articles of manufacture for constraint verification for implementing electronic circuit designs with electrical awareness. Some embodiments identify or set parasitic constraint(s) and compare the electrical parasitic(s) with corresponding parasitic constraint(s) to determine whether the parasitic constraints are met. Some embodiments first identify, determine, or update the physical data of a component of a partial layout and characterize the electrical parasitics associated with the physical data of the component. Some embodiments identify or determine some schematic level performance constraints and estimate parasitic constraints based on schematic simulation results and the performance constraints; the estimated parasitic constraints are then compared with the corresponding electrical parasitics to determine whether the constraints are satisfied. Some embodiments further map schematic level parasitic constraints to a physical design representation and then compares the mapped parasitic constraints with corresponding electrical constraints to determine whether the mapped constraints are met. | 01-26-2012 |
| 20120036489 | DESIGN AND VERIFICATION OF 3D INTEGRATED CIRCUITS - A method of designing and verifying 3D integrated circuits (3D IC) including providing a first layout corresponding to a first device of a 3D IC. The first layout includes a first interface layer. A second layout corresponding to a second device of the 3D IC is also provided. The second layout includes a second interface layer. A verification of the 3D is performed by verifying the first and second interface layers. The verification includes performing at least one of a design rule check (DRC) or a layout-versus-schematic (LVS) on the first and/or second interface layers. | 02-09-2012 |
| 20120047479 | Incremental Layout Analysis - Techniques for incrementally analyzing layout design data are disclose. With various implementations, a subsequent incremental analysis can be made for only portions of layout design data, using a subset of available analysis criteria, or some combination of both. For example, the analysis can be limited to errors identified in a previous analysis process, to changes in the layout design data made after a previous analysis process, to particular areas specified by a designer, or some combination thereof. Still further, the analysis process may be performed using only a subset of analysis criteria relevant to the portions of the design data being analyzed, a subset of the initial analysis criteria that the design data failed in a previous analysis process, a subset of the initial analysis criteria selected by the designer, or some combination thereof. Further, such an incremental analysis process can be initiated before a previous analysis process has completed. | 02-23-2012 |
| 20120066657 | METHOD OF DESIGNING AN INTEGRATED CIRCUIT BASED ON A COMBINATION OF MANUFACTURABILITY, TEST COVERAGE AND, OPTIONALLY, DIAGNOSTIC COVERAGE - Disclose are embodiments of an integrated circuit design method based on a combination of manufacturability, test coverage and, optionally, diagnostic coverage. Design-for manufacturability (DFM) modifications to the layout of an integrated circuit can be made in light of test coverage. Alternatively, test coverage of an integrated circuit can be established in light of DFM modifications. Alternatively, an iterative process can be performed, where DFM modifications to the layout of an integrated circuit are made in light of test coverage and then test coverage is altered in light of the DFM modifications. Alternatively, DFM modifications to the layout of an integrated circuit can be made in light of test coverage and also diagnostic coverage. In any case, after making DFM modifications and establishing test coverage, any unmodified and untested nodes (and, optionally, any unmodified and undiagnosable tested nodes) in the integrated circuit can be identified and tagged for subsequent in-line inspection. | 03-15-2012 |
| 20120072877 | LAYOUT VERIFICATION APPARATUS AND LAYOUT VERIFICATION METHOD - According to one embodiment, a layout verification apparatus includes a design section, a layout creation section, a first verification section and a second verification section. One of the first and second verification sections includes a filter processing section which executes a filter processing of a verification target element to be verified by a mask data used to a manufacture of the semiconductor integrated circuit, and the verification target element to be verified needs an ion implantation. The filter processing section comprises a first logic section which executes an logical AND of the verification target element to be verified, a mask data necessary in order to form the verification target element to be verified, and a data inverted a mask data unnecessary in order to form the verification target element to be verified. | 03-22-2012 |
| 20120072878 | AUTOMATED MANAGEMENT OF VERIFICATION WAIVERS - Automated management of verification waivers is disclosed. In one embodiment a method is provided comprising issuing a request to perform a verification run on a component of an electric circuit design, receiving configuration data specifying a list of waivers extracted from a plurality of waivers applicable to the electric circuit design as a whole where the list of waivers is extracted based on waiver validity period data and is applicable to the component rather than the electric circuit design as a whole. The described method further comprises identifying a potential design defect and generating a verification run result including a set of design defects of the component, the set including the potential design defect if no waiver of the list of waivers is determined to be applicable. | 03-22-2012 |
| 20120072879 | Method and Apparatus for Synthesis of Multimode X-Tolerant Compressor - Methods and apparatuses for synthesizing a multimode x-tolerant compressor are described. | 03-22-2012 |
| 20120079442 | CORRELATION OF DEVICE MANUFACTURING DEFECT DATA WITH DEVICE ELECTRICAL TEST DATA - Various embodiments related to correlating a location of a defect on a substrate for a semiconductor device to an electrical significance of a device structure at that location are disclosed. For example, one embodiment includes receiving a defect location for the location on the substrate where the defect was detected; receiving a physical representation of the semiconductor device for the defect location; generating a significance determination indicating whether the defect is located in an electrically significant region by correlating the defect location to logical and physical layout information included in the physical representation; and displaying the significance determination. | 03-29-2012 |
| 20120079443 | PRINTED CIRCUIT BOARD DESIGN ASSISTING DEVICE, METHOD, AND PROGRAM - A printed circuit board design assisting device includes a frame ground extraction section that extracts a ground pattern that is provided in a surface layer of a printed circuit board and that is to be connected to a metal component from design data on the printed circuit board stored in a design data storage section to store information for specifying the ground pattern in a data storage section, an electrostatic discharge determination section that performs a determination as to electrostatic discharge for the ground pattern specified from the information stored in the data storage section to store a determination result in a determination result storage section, and an output section that outputs the determination result stored in the determination result storage section. | 03-29-2012 |
| 20120110530 | COMPUTER SYSTEM AND METHOD OF PREPARING A LAYOUT - The present application discloses a method of preparing a layout for manufacturing an integrated circuit chip according to a circuit design. In at least one embodiment, a pattern for the layout based on the circuit design is generated. After the generation of the pattern, it is determined if at least one layout rule is violated in the layout, the at least one layout rule being specified according to a predetermined maximum value for at least one of an estimated voltage drop along a signal path in the layout or an estimated current density on the signal path. If the at least one layout rule is violated, a violation is indicated. | 05-03-2012 |
| 20120110531 | DEFECT AND YIELD PREDICTION FOR SEGMENTS OF AN INTEGRATED CIRCUIT - Defect prediction information is determined for a segment of an integrated circuit layout. Marker information is obtained, for example from user input into a computer design tool, where the marker information defines the segment. A segment can be defined to be any arbitrary portion of the layout and can include portions of multiple blocks. The marker information is used to extract layout information corresponding to the segment. The extracted segment layout information is analyzed to determine the defect prediction information. In one example, the determination involves performing a Critical Area Analysis such that the defect prediction information is a yield prediction value. This process is repeated for multiple segments, and the defect prediction information for the segments is compared to identify the segment most susceptible to defects. The user can modify the design of the segment, and repeat the process to improve yield in the manufacture of the integrated circuit. | 05-03-2012 |
| 20120124536 | METHOD AND SYSTEM FOR AUTOMATIC GENERATION OF SOLUTIONS FOR CIRCUIT DESIGN RULE VIOLATIONS - Some embodiments provide a method for automatically generating several design solutions that remedy a design rule violation committed by a set of shapes in an IC design layout. The method receives a marker that indicates the design rule violation and contains information about the violation. The marker in some embodiments can be rendered as a geometric shape in the IC design layout. Based on the marker, the method generates several solutions each of which will cause the set of shapes to meet the design rule when the solution is applied to the set. Each solution requires moving at least one edge of a shape in the set of shapes. | 05-17-2012 |
| 20120131528 | METHOD AND APPARATUS FOR ACHIEVING MULTIPLE PATTERNING TECHNOLOGY COMPLIANT DESIGN LAYOUT - A method and apparatus for achieving multiple patterning compliant technology design layouts is provided. An exemplary method includes providing a routing grid having routing tracks; designating each of the routing tracks one of at least two colors; applying a pattern layout having a plurality of features to the routing grid, wherein each of the plurality of features corresponds with at least one routing track; and applying a feature splitting constraint to determine whether the pattern layout is a multiple patterning compliant layout. If the pattern layout is not a multiple patterning compliant layout, the pattern layout may be modified until a multiple patterning compliant layout is achieved. If the pattern layout is a multiple patterning compliant layout, the method includes coloring each of the plurality of features based on the color of each feature's corresponding at least one routing track, thereby forming a colored pattern layout, and generating at least two masks with the features of the colored pattern layout. Each mask includes features of a single color. | 05-24-2012 |
| 20120131529 | SEMICONDUCTOR DEFECT CLASSIFYING METHOD, SEMICONDUCTOR DEFECT CLASSIFYING APPARATUS, AND SEMICONDUCTOR DEFECT CLASSIFYING PROGRAM - A defect is efficiently and effectively classified by accurately determining the state of overlap between a design layout pattern and the defect. This leads to simple identification of a systematic defect. A defective image obtained through defect inspection or review of a semiconductor device is automatically pattern-matched with design layout data. A defect is superimposed on a design layout pattern for at least one layer of a target layer, a layer immediately above the target layer, and a layer immediately below the target layer. The state of overlap of the defect is determined as within the pattern, over the pattern, or outside the pattern, and the defect is automatically classified. | 05-24-2012 |
| 20120137262 | METHOD FOR COMPUTING THE SENSITIVITY OF A VLSI DESIGN TO BOTH RANDOM AND SYSTEMATIC DEFECTS USING A CRITICAL AREA ANALYSIS TOOL - A method of estimating integrated circuit yield comprises providing an integrated circuit layout and a set of systematic defects based on a manufacturing process. Next, the method represents a systematic defect by modifying structures in the integrated circuit layout to create modified structures. More specifically, for short-circuit-causing defects, the method pre-expands the structures when the structures comprise a higher systematic defect sensitivity level, and pre-shrinks the structures when the structures comprise a lower systematic defect sensitivity level. Following this, a critical area analysis is performed on the integrated circuit layout using the modified structures, wherein dot-throwing, geometric expansion, or Voronoi diagrams are used. The method then computes a fault density value, random defects and systematic defects are computed. The fault density value is subsequently compared to a predetermined value, wherein the predetermined value is determined using test structures and/or yield data from a target manufacturing process. | 05-31-2012 |
| 20120144354 | PARAMETER VARIATION IMPROVEMENT - Variation of a parameter of interest is reduced over a field of interest in, for example, an object design, such as a circuit design. The field of interest is divided into tiles. A parameter value is found for each tile and for a group of tiles around each tile. Using these values, variation of the parameter is determined. An adjusted value of the parameter for each tile is determined taking limits into account, iterating until variation is below a threshold value. Parameter uniformity is improved in some applications by over 30% with runtime reduced by an order of magnitude. | 06-07-2012 |
| 20120144355 | HIGH PERFORMANCE DESIGN RULE CHECKING TECHNIQUE - Roughly described, a design rule data set is developed offline from the design rules of a target fabrication process. A design rule checking method involves traversing the corners of shapes in a layout region, and for each corner, populating a layout topology database with values that depend on respective corner locations. After the layout topology database is populated, the values are compared to values in the design rule data set to detect any design rule violations. Violations can be reported in real time, while the user is manually editing the layout. Preferably corner traversal is performed using scan lines oriented perpendicularly to edge orientations, and scanning in the direction of the edge orientations. Scans stop only at corner positions and populate the layout topology database with what information can be gleaned based on the current scan line. The different scans need not reach each corner simultaneously. | 06-07-2012 |
| 20120144356 | ANALYZING MULTIPLE INDUCED SYSTEMATIC AND STATISTICAL LAYOUT DEPENDENT EFFECTS ON CIRCUIT PERFORMANCE - A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to a separate systematic, parametric variation associated with semiconductor manufacturing of an integrated circuit layout; generating, for each variation model, a netlist update attributable to the associated variation, wherein the netlist update is an update with respect to an original netlist extracted from the integrated circuit layout; and storing the netlist updates generated for each of the processing conditions. | 06-07-2012 |
| 20120151428 | Pattern Shape Estimation Method and Pattern Measuring Device - The present invention aims at proposing a library creation method and a pattern shape estimation method in which it is possible, when estimating a shape based on comparison between an actual waveform and a library, to appropriately estimate the shape. | 06-14-2012 |
| 20120159413 | IMPEDANCE DESIGN METHOD - The invention discloses a chipset having N input/output (I/O) ports coupled to a voltage source which have an observation I/O port. The method includes calculating a first set of impedances at a predetermined frequency or the observation I/O port, if the voltage source is internally coupled to the N I/O ports within the chipset, and calculating a second set of impedances at the predetermined frequency for the observation I/O port, if the voltage source is externally coupled to the N I/O ports through a carrier coupling the core chip to the voltage source. The first set of impedances are compared to the second set of impedances, and the impedance of the power network or the impedance of the carrier is adjusted according to the comparison result. | 06-21-2012 |
| 20120167028 | DESIGN-RULE-CHECK WAIVER - When a designer designates one or more errors identified in layout design data as false errors, waiver geometric elements corresponding to the designated false errors are created and added to the design. The waiver geometric element may be associated with a verification rule that generated its corresponding false error. When the design is subsequently analyzed using those verification rules in another verification rule check process, the waiver geometric elements are examined, and used to mask those errors associated with a waiver geometric element that would otherwise be displayed to the designer. A designer may also designate a waiver region based on pattern matching, cell names or layout markers in which layout region one or more verification rules may be inapplicable. A waiver region identification item for the waiver region may be associated with a waiver geometric element and the one or more verification rules. | 06-28-2012 |
| 20120167029 | PHYSICAL DESIGN SYSTEM AND METHOD - A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency. | 06-28-2012 |
| 20120180014 | METHOD OF CONTEXT-SENSITIVE, TRANS-REFLEXIVE INCREMENTAL DESIGN RULE CHECKING AND ITS APPLICATIONS - A computer-implemented method to perform context-sensitive incremental design rule checking (DRC) for an integrated circuit (IC). An incremental DRC engine checks design rule violations between a set of environment shapes and a set of active shapes. If no design rule violations are found, the set of active shapes will be added into the set of environment shapes. Furthermore, the incremental DRC engine can be embedded into placement tools, routing tools, or interactive layout editing tools to check design rule violations and help generate DRC error free layouts. | 07-12-2012 |
| 20120185812 | SYSTEM, METHOD AND PROGRAM STORAGE DEVICE FOR DEVELOPING CONDENSED NETLISTS REPRESENTATIVE OF GROUPS OF ACTIVE DEVICES IN AN INTEGRATED CIRCUIT AND FOR MODELING THE PERFORMANCE OF THE INTEGRATED CIRCUIT BASED ON THE CONDENSED NETLISTS - A system and method for developing condensed netlists for sub-circuits within an integrated circuit and for modeling the performance of the integrated circuit based on the condensed netlists rather than full netlists. An IC layout is segmented into a plurality of sub-circuits, each comprising a group of one or more of a given type of active devices connected to (i.e., sharing) the same electrical sub-circuit terminals through a similar resistive network (i.e. such that they are subjected to approximately the same overall combined parasitic resistances). Full netlists corresponding to the sub-circuits are extracted from the layout and condensed. Each condensed netlist accounts for performance variations (e.g., as a function of variations in operating power supply voltages, operating temperatures and, optionally, self-heating and/or stress) exhibited by the active devices and resistive network in a sub-circuit. The condensed netlists for the sub-circuits are then simulated over the full range of operating temperatures and full range of operating power supply voltages for the integrated circuit in order to generate a performance model for the integrated circuit. | 07-19-2012 |
| 20120185813 | TOOL PERFORMANCE BY LINKING SPECTROSCOPIC INFORMATION WITH TOOL OPERATIONAL PARAMETERS AND MATERIAL MEASUREMENT INFORMATION - System(s) and method(s) are provided for adjustment and analysis of performance of a tool through integration of tool operational data and spectroscopic data related to the tool. Such integration results in consolidated data that enable, in part, learning at least one relationship amongst selected portions of the consolidated data. Learning is performed autonomously without human intervention. Adjustment of performance of the tool relies at least in part on a learned relationship and includes generation of process recipe parameter(s) that can adjust a manufacturing process in order to produce a satisfactory tool performance in response to implementation of the manufacturing process. A process recipe parameter can be generated by solving an inverse problem based on the learned relationship. Analysis of performance of the tool can include assessment of synthetic performance scenarios, identification of spectroscopic condition(s) that affect performance, and extraction of endpoints based at least on time dependence spectroscopic data. | 07-19-2012 |
| 20120185814 | INDICATOR CALCULATION METHOD AND APPARATUS - A method for calculating an indicator value includes: extracting features, which are mutually independent, by using data stored in a data storage unit storing, for each group of circuits implemented on a semiconductor device, the number of actual failures occurred in the group and a feature value of each feature that is a failure factor; generating an expression of a failure occurrence probability model, which represents a failure occurrence probability, which is obtained by dividing a total sum of the numbers of actual failures by the number of semiconductor devices, as a relation including a sum of products of the feature value of each of the extracted features and a corresponding coefficient, by carrying out a regression calculation using data stored in the data storage unit; and calculating an indicator value for design change of the semiconductor device from the generated expression of the failure occurrence probability model. | 07-19-2012 |
| 20120185815 | METHOD FOR EXTRACTING INFORMATION FOR A CIRCUIT DESIGN - The present disclosure is directed to a method for extracting information for a circuit design. The method may utilize an incremental extraction process for extracting information for a portion of the circuit design. Extracted results of this portion may be merged with a previously extracted result to obtain an integrated result that is equivalent to that of extracting the entire circuit design. The incremental extraction process may identify a set of changed shapes, a set of affected shapes, and a set of involved shapes for extraction. The method may also divide the circuit design into a plurality of regions, wherein two or more regions may be processed in parallel. | 07-19-2012 |
| 20120192134 | User Guided Short Correction And Schematic Fix Visualization - Techniques for assisting a designer in correcting discrepancies identified in layout design data. A user interface may be provided listing identified shorts and relevant information related to those shorts. Still further, the user interface may allow a designer to selectively choose a subset of the identified shorts, and to designate or otherwise provide correction data for use to correct the shorts before performing a short isolation process on the selected shorts. Alternately or additionally a user interface may provide a designer with graphical images showing the correction that should be made by a designer to address an identified discrepancy in layout design data. | 07-26-2012 |
| 20120198403 | MANUFACTURING FEATURES OF DIFFERENT DEPTH BY PLACEMENT OF VIAS - A methodology for varying the depth of a design feature on a semiconductor wafer. Vias are formed according to design requirements. Nonfunctioning vias may also be placed at a location with respect to a design feature. After vias are formed, the semiconductor wafer is caused to undergo an ashing process followed by the application of an organic planarizing layer. The design features are then formed. If the depth of the design features does not meet design requirements, another semiconductor wafer may be processed to meet design requirements by varying the ashing conditions, choice of organic planarizing layer and/or the nonfunctioning and/or functioning via placement. Design features having various depths on a single semiconductor wafer may be formed with a single lithographic process. | 08-02-2012 |
| 20120198404 | DEFECT INSPECTION SUPPORTING APPARATUS AND DEFECT INSPECTION SUPPORTING METHOD - According to one embodiment, layout patterns with defects are grouped based on similarity between the layout patterns, weight values of the groups are set based on formation difficulty of the layout patterns belonging to the groups, the number of defects of the layout pattern belonging to each group is calculated, and rankings of the groups are calculated based on the numbers of defects of the groups and the weight values of the groups. | 08-02-2012 |
| 20120198405 | METHOD AND APPARATUS FOR AMS SIMULATION OF INTEGRATED CIRCUIT DESIGN - A method to create an integrated circuit that includes digital and analog components comprising: displaying on a computer system display, user input to the computer system that specifies parameter information to determine a binding between an analog circuit design component and a digital circuit design component; saving the user specified parameter information within a file that also specifies at least a portion of the analog circuit design; associating the analog circuit design component a first design block of an integrated circuit that also includes a second digital design block coupled to the first design block; using parameter information to determine a binding between the first analog circuit design component and the first digital circuit design component; saving the determined binding in computer readable storage media. | 08-02-2012 |
| 20120210283 | ANALYSIS OF COMPENSATED LAYOUT SHAPES - The disclosure relates to the analysis of compensated layout shapes. A method in accordance with an embodiment includes: analyzing a semiconductor layout using a bucket structure, the layout including a semiconductor device; and applying a pattern template to a content of the bucket structure to identify a shape adjacent to the semiconductor device; wherein the pattern template is derived from layout groundrules. | 08-16-2012 |
| 20120210284 | Method and Apparatus for Characterizing and Reducing Proximity Effect on Cell Electrical Characteristics - Circuit elements are characterized for effects of proximity context on electrical characteristic. Based on the characterization, proximity context cell models, and corresponding modeled electrical characteristic values are obtained. Logic cells are characterized and modeled according to the proximity context cell models. Optionally the electrical characteristic can be time delay, leakage, dynamic power, or coupling noise among other parameters. | 08-16-2012 |
| 20120210285 | METHOD AND APPARATUS FOR THERMAL ANALYSIS OF THROUGH-SILICON VIA (TSV) - Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout. The IC design layout includes several wiring layers in some embodiments. The IC design layout includes a substrate that has at least one through-silicon via (“TSV”). The method divides the IC design layout into a set of elements. The method identifies a temperature distribution for the IC design layout by using the set of elements. In some embodiments, at least one element includes a metal component and a non-metal component. The non-metal component is silicon in some embodiments, and a dielectric in other embodiments. | 08-16-2012 |
| 20120216161 | Low-Resistance Electrode Design - A solution for designing a semiconductor device, in which two or more attributes of a pair of electrodes are determined to, for example, minimize resistance between the electrodes, is provided. Each electrode can include a current feeding contact from which multiple fingers extend, which are interdigitated with the fingers of the other electrode in an alternating pattern. The attributes can include a target depth of each finger, a target effective width of each pair of adjacent fingers, and/or one or more target attributes of the current feeding contacts. Subsequently, the device and/or a circuit including the device can be fabricated. | 08-23-2012 |
| 20120216162 | Method and Apparatus Used for the Physical Validation of Integrated Circuits - Disclosed herein are methods and devices used for the physical design validation of integrated circuits. One method used for the physical design validation of integrated circuits includes comparing the original circuit netlist of an integrated circuit and the layout data of the integrated circuit and assigning labels to the input and output terminals of the components in the integrated circuit based on the results of the comparison. | 08-23-2012 |
| 20120221989 | ELECTRONIC DEVICE AND METHOD OF AUTOMATICALLY TESTING TRANSMISSION LINES - An electronic device and method of automatically testing the transmission lines of a PCB. Design requirements of transmission lines are predetermined and a wiring diagram is acquired according to a designated wiring diagram storage path. Some basic parameters of each transmission line of the diagram are applied in excluding one or more transmission lines which may not meet the design requirements, then, the excluded transmission lines are marked and/or highlighted. A report of the transmission lines is generated using a report template. | 08-30-2012 |
| 20120221990 | METHOD AND SYSTEM FOR POWER DELIVERY NETWORK ANALYSIS - The subject application relates to a method and system for power delivery network analysis. The present disclosure is directed towards a computer-implemented method for displaying one or more results of a power delivery network (PDN) analysis associated with an electronic circuit design. The method may include extracting, using at least one processor, an electromagnetic (EM) model for each of one or more discontinuity structures associated with the electronic circuit design. The method may further include performing a power delivery network analysis of the electronic circuit design, the PDN analysis including a Method of Moments (MoM) calculation. The method may also include displaying a three dimensional image depicting one or more results of the PDN analysis. Numerous other features are also within the scope of the present disclosure. | 08-30-2012 |
| 20120221991 | Interactive Method and Apparatus for Detecting Texted Metal Short Circuits - Methods and devices are disclosed herein to test the texted metal short circuit. One such method comprises: To input a circuit design file, wherein the circuit design file comprises the data of the layout pattern of the circuit design, the file format of the circuit design is a generic data stream format; to input a set of design rules; to select a specific check rule based on the set of design rules, wherein the specific check rule is for testing the texted metal short circuit in the circuit design; to execute a verification program [procedure] on the circuit design based on the specific check rule so as to obtain a first test result, wherein the first test result comprises all short circuit paths in the circuit design; and, based on the first rest result, to execute a pseudo-texted program using fuzzy algorithm so as to obtain a second test result. | 08-30-2012 |
| 20120227023 | REAL TIME DRC ASSISTANCE FOR MANUAL LAYOUT EDITING - Roughly described, while manually dragging shapes during IC layout editing, editing operations determine which edges of which shapes are moving at what speed ratios. Based on the edge information and the DRC rules, the system calculates and keeps track of the minimum of the maximum distance the edges are allowed to move with the cursor without violating DRC rules, in four linear directions and all corner directions. Once a next cursor destination point is known, a DRC clean destination point is calculated based on the linear and corner bounds. If the next cursor position is beyond a the push-through distance ahead of the new DRC clean point, the editing objects are moved to the user's destination point. Otherwise, the editing objects are moved to the new DRC clean destination point, thereby stopping movement at that point. | 09-06-2012 |
| 20120227024 | LAYOUT VERSUS SCHEMATIC ERROR SYSTEM AND METHOD - According to various embodiments of the invention, systems and methods for presenting Layout Versus Schematic (LVS) errors within a layout using a visual circuit representation of the design and highlighting is provided. One embodiment includes overlaying the layout circuit representation on the schematic circuit representation with highlighting that indicates the LVS errors. The method of such an embodiment compares a layout netlist against a schematic netlist in order to identify the layout-versus-schematic errors, generates a graphical representation of the layout netlist and a graphical representation of the schematic netlist, displays an overlay of the graphical representation of the layout netlist with the graphical representation of the schematic netlist and then, highlights the identified layout-versus-schematic errors that are present. | 09-06-2012 |
| 20120233579 | METHOD FOR IMPROVING THE RADIO FREQUENCY LINEARITY OF SILICON-ON-INSULATOR MOSFET CIRCUITS - A method for improving the radio frequency linearity of SOI MOSFET circuits is disclosed. In particular, a method for determining output conductance transition-free body resistances (“R | 09-13-2012 |
| 20120266123 | COHERENT ANALYSIS OF ASYMMETRIC AGING AND STATISTICAL PROCESS VARIATION IN ELECTRONIC CIRCUITS - Coherent analysis of asymmetric aging and statistical process variation. A method of designing a circuit includes preparing an initial netlist of components in the circuit. A plurality of components is selected from the initial netlist by a first statistical process. Further, a process variation netlist is prepared by replacing a plurality of initial operating parameters of the plurality of components with a plurality of process variation operating parameters. A plurality of high stress components is then identified in the process variation netlist and an aged netlist is prepared by replacing a set of operating parameters of the plurality of high stress components with a set of degraded operating parameters. The circuit is simulated using the aged netlist. The method also includes modifying the initial netlist according to a result of simulation and repeating the foregoing steps until a desired circuit performance is obtained. | 10-18-2012 |
| 20120272199 | Method and Apparatus for Circuit Partitioning and Trace Assignment in Circuit Design - Methods and apparatuses for designing at least one integrated circuit (IC). In one embodiment, the method comprises partitioning a circuit into portions that represent a partitioning solution and assigning traces to interconnect the portions to generate a trace assignment solution. The method further comprises optimizing the circuit through a modification of at least one of the partitioning solution and the trace assignment solution, the optimizing based on evaluating a design parameter which is based at least in part on the trace assignment solution. | 10-25-2012 |
| 20120272200 | METHOD AND SYSTEM FOR MODEL-BASED DESIGN AND LAYOUT OF AN INTEGRATED CIRCUIT - A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers. | 10-25-2012 |
| 20120272201 | METHOD AND SYSTEM FOR MODEL-BASED DESIGN AND LAYOUT OF AN INTEGRATED CIRCUIT - A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers. | 10-25-2012 |
| 20120284678 | GENERATING PHYSICAL DESIGNS FOR ELECTRONIC CIRCUIT BOARDS - Generating a physical circuit board design. The physical circuit board is designed based on a design data set containing multiple electronic components. In a first step, the electronic components are classified by assigning them either to a group of so-called Core Components or to a group of Application Specific Components. Subsequently, a circuit board layer structure is generated. The layer structure includes a Core Layer Structure located in the center of this layer structure. The components are placed onto the board's layer structure in such a way that the Core Components are placed onto the Core Layer Structure. Finally, a design macro of the resulting physical design is generated and the circuit board is assembled. | 11-08-2012 |
| 20120297352 | METHOD AND APPARATUS FOR CREATING AND MANAGING WAIVER DESCRIPTIONS FOR DESIGN VERIFICATION - Methods are provided to facilitate automated creation and management of design rule checking or DRC waiver descriptions. Embodiments include receiving a plurality of first checksums corresponding to respective first geometric element violations waived in association with a block of an integrated circuit design, the first checksums being based on a first version of at least one design verification rule and/or of the block, receiving a second checksum corresponding to a second geometric element violation associated with the block, the second checksum being based on a second version of the design verification rule and/or of the block, determining whether the second checksum corresponds to at least one of the first checksums, and, if the second checksum does not correspond to at least one first checksum, generating a waiver request for the second geometric element error. | 11-22-2012 |
| 20120304140 | FULLY PARAMETERIZABLE REPRESENTATION OF A HIGHER LEVEL DESIGN ENTITY - A parameterizable design system is for use with semiconductor analog circuits and includes an interface unit connected to provide access to the system, a database unit connected to supply a library of parameterizable analog building blocks for a design entity, and a parameterization unit connected to select a parameter for one of the library of parameterizable analog building blocks to meet a design specification of the design entity. Additionally, the parameterizable design system may also include a simulation unit connected to simulate an operation of the design entity employing the parameter, and an analyzer unit connected to analyze a sensitivity of the parameter for the design entity based on the design specification. A method of designing a semiconductor analog circuit is also included. | 11-29-2012 |
| 20120311516 | Planar Lightwave Circuit, Design Method for Wave Propagation Circuit, and Computer Program - A planar lightwave circuit is provided which can be easily fabricated by an existing planar-lightwave-circuit fabrication process, which can lower the propagation loss of signal light and which can convert inputted signal light so as to derive desired signal light. A planar lightwave circuit having a core and a clad which are formed on a substrate, has input optical waveguide(s) ( | 12-06-2012 |
| 20120317528 | METHODS AND SYSTEMS FOR COMPUTER AIDED DESIGN OF 3D INTEGRATED CIRCUITS - Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed. | 12-13-2012 |
| 20130007683 | REDUCING OBSERVABILITY OF MEMORY ELEMENTS IN CIRCUITS - A method, apparatus and computer program product for modifying a circuit design. The method comprising: obtaining a design of a circuit, the design comprising at least a first memory element and a second memory element. The method further comprising selecting the second memory element to be a dominant memory element over the first memory element. The method further comprising modifying the design of the circuit by replacing usage of an output signal of the first memory element with usage of an output signal of the dominant memory element in one or more cycles in which values of the output signals of the first memory element and the dominant memory element are equal. Whereby a reduction in observabiltiy of the first memory element in the design is achieved. | 01-03-2013 |
| 20130007684 | AUTOMATED INLINE DEFECT CHARACTERIZATION - Defect characterization is a useful tool for analyzing and improving fabrication for semiconductor chips. By using layout and netlist in combination with images of semiconductors, defects can be identified and analyzed. Electrical simulation can be performed on the netlist, based on the presence of the defect that was detected. Layout geometries where the defect was detected can be binned and a search can be performed of the remainder of the layout for similar groupings of layout geometries. Various representations of the semiconductor can be cross mapped, including layout, schematic, and netlist. The presence of certain defects can be correlated to yield, performance, and other characteristics. | 01-03-2013 |
| 20130014068 | COMPUTER-AIDED DESIGN SYSTEM AND METHODS THEREOF FOR MERGING DESIGN CONSTRAINT FILES ACROSS OPERATIONAL MODES - In the field of integrated circuit (IC) design it is common to use a plurality of design constraints files to provide the appropriate operational mode when checking the design. Designers typically use the Synopsis® design constraint (SDC) format to describe the constraints in each operational mode. Each time an operational mode is tested a corresponding SDC is used. By merging a plurality of SDCs into a single most pessimistic SDC, designers are able to ensure that the device will properly operate in all the defined operational modes. Only a single run of the merged SDC in the hypothetical mode is required thereby saving time as well as avoiding potential errors from conflicting constraints in different operational modes. | 01-10-2013 |
| 20130014069 | Equivalent Device Statistical Modeling for Bitline Leakage Modeling - Mechanisms are provided for modeling a plurality of devices of an integrated circuit design as a single statistically equivalent wide device. An integrated circuit design is analyzed to identify a portion of the integrated circuit design having the plurality of devices. For the plurality of devices, a statistical model of a single statistically equivalent wide device is generated which has a statistical distribution of at least one operating characteristic of the single statistically equivalent wide device that captures statistical operating characteristic distributions of individual devices in the plurality of devices. At least one statistical operating characteristic of the single statistically equivalent wide device is a complex non-linear function of the statistical operating characteristics of the individual devices. The integrated circuit design is modeled using the single statistically equivalent wide device. | 01-10-2013 |
| 20130024829 | METHOD AND CIRCUITRY FOR DEBUGGING A POWER-GATED CIRCUIT - Described are a circuit and a method of analyzing and correcting a fault occurring in operation of the circuit during a power gating sequence. The method includes executing a modification of the power gating sequence that includes maintaining operation of a trace capture buffer (TCB); recording, in the TCB, events occurring during the executing; and correcting the fault based on analysis of the events recorded in the TCB. The circuit includes a plurality of components including a TCB, and a switch configured to maintain power to the TCB in a first state and turn off power to the TCB in a second state. | 01-24-2013 |
| 20130024830 | Fault Diagnosis Based On Design Partitioning - Aspects of the invention relate to techniques for fault diagnosis based on circuit design partitioning. According to various implementations of the invention, a circuit design of a failing die is first partitioned into a plurality of sub-circuits. The sub-circuits may be formed based on fan-in cones of observation points. Shared gate ratios may be used as a metric for adding fan-in cones of observation points into a sub-circuit. Based on test patterns and the sub-circuits, sub-circuit test patterns are determined. Fault diagnosis is then performed on the sub-circuits. The sub-circuit fault diagnosis comprises extracting sub-circuit failure information from the failure information for the failing die. The sub-circuit fault diagnosis may employ fault-free values for boundary gates in the sub-circuits. | 01-24-2013 |
| 20130031522 | HOTSPOT DETECTION BASED ON MACHINE LEARNING - Aspects of the invention relate to machine-learning-based hotspot detection techniques. These hotspot detection techniques employ machine learning models constructed using two feature encoding schemes. When two-level machine learning methods are also employed, a total four machine learning models are constructed: scheme-one level-one, scheme-one level-two, scheme-two level-one and scheme-two level-two. The four models are applied to test patterns to derive scheme-one hotspot information and scheme-two hotspot information, which are then used to determine final hotspot information. | 01-31-2013 |
| 20130036394 | Vectorless IVD Analysis Prior to Tapeout to Prevent Scan Test Failure Due to Voltage Drop - In one embodiment, a vectorless IVD methodology may be used to estimate IVD issues for an integrated circuit earlier in the design cycle of the integrated circuit, e.g. when corrective actions may still be taken to correct IVD failures. In the methodology, scan chains for various clusters in the integrated circuit may be identified, even though the scan chains may still be subject to change as the design evolves. A power integrity tool may analyze the scan chains based on a probability of transitions in the devices within the scan chain (e.g. flops) for a theoretical worst-case test vector. If the result of analysis identifies IVD failures in the clusters, corrective action may be taken such as modifying the design. Alternatively, the corrective action may include identifying one or more flops that experience failure as devices to be excluded from the test vector generation process for scan testing. | 02-07-2013 |
| 20130055184 | METHOD AND SYSTEM FOR PHYSICAL VERIFICATION USING NETWORK SEGMENT CURRENT - A data processing system determines current information corresponding to a node included at a device design. Physical layout information corresponding to the node is received, the physical layout information including one or more layout geometries, the one or more layout geometries providing a circuit network. The circuit network may be partitioned into two or more network segments. A current conducted at a network segment is identified based on the current information. Information representative of dimensions and metal layer of a layout geometry included at the network segment is received. The computer determines that the current exceeds a predetermined maximum threshold, the predetermined maximum threshold determined based on the dimensions and metal layer. | 02-28-2013 |
| 20130067425 | IDENTIFYING PARASITIC DIODE(S) IN AN INTEGRATED CIRCUIT PHYSICAL DESIGN - A method comprises tracing a first and second terminal of a junction through a circuit layout to associated power supplies to determine their respective defined bias values. The method further comprises comparing the defined bias values of each terminal in order to determine, based on the comparison, whether the junction is forward biased. | 03-14-2013 |
| 20130074023 | Test Functionality Integrity Verification for Integrated Circuit Design - Systems and methods are provided for verifying the integrity of test functionality for an integrated circuit design. This may be achieved, for example, by analyzing the integrated circuit design to identify a driver element that outputs a security signal for controlling the test functionality, analyzing the integrated circuit design to identify an input stage of one or more elements that feed the driver element, monitoring the security signal over a range of values for the input stage, and determining that an error exists in the test functionality if a change in the security signal is detected during the monitoring. | 03-21-2013 |
| 20130074024 | LOW-OVERHEAD MULTI-PATTERNING DESIGN RULE CHECK - Roughly described, a system enables quick and accurate depiction to a user of multi-patterning layout violations so that they may be corrected manually and in real time, and without interfering with normal manual editing process. In one embodiment, the system involves iteratively building tree structures with nodes identifying islands and arcs identifying multi-patterning spacing violations between the connected islands. The system detects coloring violations during the building of these tree structures, using the relationships previously inserted. The coloring violations preferably are reported to a user in the form of visual indications of the cycles among the candidate spacing violations, with the candidate spacing violations also themselves indicated visually and individually. The user can see intuitively how to move the islands around, and in which directions and by what distance, in order to remove a multi-patterning spacing violation and thereby break the cycle. | 03-21-2013 |
| 20130080984 | PROCESS AWARE METROLOGY - Systems and methods for process aware metrology are provided. | 03-28-2013 |
| 20130080985 | ELECTROSTATIC DAMAGE PROTECTION CIRCUITRY VERIFICATION - Techniques for efficiently determining whether an interconnect line has an impedance component value below a maximum specified value. A specified maximum impedance component value is used to limit the number of interconnect lines that are analyzed by a parasitic extraction analysis process. An analysis window is created based upon the characteristics of the interconnect lines and the specified maximum impedance component value. The size of the window corresponds to the minimum length of the interconnect line that would have the specified maximum impedance component value. Once the analysis window has been created, the interconnect lines are examined to determine if any of them reaches to (or beyond) the analysis window, whereby interconnect lines that exceed the specified maximum impedance component value can be identified. If there are any remaining interconnect lines that have not been determined to exceed the specified maximum impedance component value through the use of the analysis window, then the impedance component values of these remaining interconnect lines can be specifically determined using a parasitic extraction process. | 03-28-2013 |
| 20130086540 | SYSTEM AND METHOD OF AUTOMATED DESIGN AUGMENTATION FOR EFFICIENT HIERARCHICAL IMPLEMENTATION - A hierarchical interface module includes an assessment unit configured to identify a hierarchical implementation incompatibility of an integrated circuit (IC) partitioned block. Additionally, the hierarchical interface module includes an interface unit configured to substitute a directly registered hierarchical interface structure for the hierarchical implementation incompatibility of the IC partitioned block. A method of interfacing hierarchically and a hierarchical implementation system are also included. | 04-04-2013 |
| 20130086541 | SYSTEM AND METHOD FOR AUTOMATED REAL-TIME DESIGN CHECKING - Systems and methods for real-time design checking of an integrated circuit design, include the operations of receiving at a design tool, design elements of an integrated circuit design entered by an integrated circuit designer; the design tool performing real-time design checks on the design elements as they are entered by the integrated circuit designer to determine whether a design element violates a design rule; when the design tool detects a violation of a design rule based on the design checks alerting the integrated circuit designer; and the design tool presenting a correction to correct the violation of the design rule. The real-time design checks can include, comparing each design element to one or more known non-compliant design elements stored in a database to determine whether a non-compliant design element was entered or is being entered by the integrated circuit designer. | 04-04-2013 |
| 20130091478 | POWER GRID MOSAICING WITH DEEP-SUB-TILE CELLS - A computer aided design system can determine coverage of a metal layer mosaic. The system can apply a tile pattern to a design including at least one layer. Then, the system can identify at least one tile of the tile pattern that violates at least one first design rule. After that, the system can apply a sub-tile pattern to an area identified in the identifying the at least one tile of the tile pattern that violates the design rule. The system further can identify at least one sub-tile of the sub-tile pattern that violates at least one second design rule. Finally, the system can apply a deep-sub-tile pattern to an area identified in the identifying the at least one sub-tile of the sub-tile pattern that violates the second design rule. | 04-11-2013 |
| 20130091479 | Parameter Matching Hotspot Detection - Disclosed are techniques for detecting hotspots using parameter matching. According to various implementations of the invention, devices in an electronic circuit design are classified into device groups based on their values for one or more device parameters, which can be derived from layout data describing the devices. Representative electrical information for each of the device groups is determined and used as a basis for hotspot detection. | 04-11-2013 |
| 20130117723 | PATTERN SHAPE EVALUATION METHOD, PATTERN SHAPE EVALUATION DEVICE, PATTERN SHAPE EVALUATING DATA GENERATION DEVICE AND SEMICONDUCTOR SHAPE EVALUATION SYSTEM USING THE SAME - A pattern shape evaluation method and semiconductor inspection system having a unit for extracting contour data of a pattern from an image obtained by photographing a semiconductor pattern, a unit for generating pattern direction data from design data of the semiconductor pattern, and a unit for detecting a defect of a pattern, through comparison between pattern direction data obtained from the contour data and pattern direction data generated from the design data corresponding to a pattern position of the contour data. | 05-09-2013 |
| 20130132918 | Waiving Density Violations - Waiver regions may be identified by waiver identification items. The waiver identification items may be determined based on conducting a density check process. Additionally or alternatively, reference patterns for pattern matching, cell names or markers may serve as the waiver identification items. Waiver geometric items may be created for the waiver regions and added to the layout design. Based on an overlap of a density check window with the waiver geometric items and waiving threshold information, a density violation in that density check window is determined to be reported as a density violation or a waived density violation with some implementations of the invention. With some other implementations of the invention, pattern density of a density check window may not be checked if an overlap of the density check window with the waiver geometric items is above a waiving threshold value. | 05-23-2013 |
| 20130132919 | HIGH PERFORMANCE DESIGN RULE CHECKING TECHNIQUE - Roughly described, a design rule data set is developed offline from the design rules of a target fabrication process. A design rule checking method involves traversing the corners of shapes in a layout region, and for each corner, populating a layout topology database with values that depend on respective corner locations. After the layout topology database is populated, the values are compared to values in the design rule data set to detect any design rule violations. Violations can be reported in real time, while the user is manually editing the layout. Preferably corner traversal is performed using scan lines oriented perpendicularly to edge orientations, and scanning in the direction of the edge orientations. Scans stop only at corner positions and populate the layout topology database with what information can be gleaned based on the current scan line. The different scans need not reach each corner simultaneously. | 05-23-2013 |
| 20130139120 | COMPUTER IMPLEMENTED SYSTEM AND METHOD FOR LEAKAGE CALCULATION - A tool includes one or more machine readable storage mediums encoded with data. The data include a list of standard cells included in an integrated circuit (IC) design The data include a nominal leakage value approximating a respective median leakage value for each of the plurality of standard cells at a predetermined temperature and voltage. The data include at least one table including adjustment factors for calculating leakage based on voltage, temperature and process variations. The table includes a respective statistical scaling factor, for computing a mean leakage corresponding to a given median leakage. A processor is programmed to calculate and output a total IC leakage for the IC design at an input voltage and input temperature, based on the list, the nominal leakage values, the input voltage, the input temperature and at least one of the adjustment factors. | 05-30-2013 |
| 20130145332 | METHOD OF RESISTOR MATCHING IN ANALOG INTEGRATED CIRCUIT LAYOUT - A method of resistor matching in analog integrated circuit layout is disclosed. Shapes of mismatching resistor blocks are analyzed to obtain geometrical information for deforming the mismatching resistor blocks. The mismatching resistor blocks are deformed into centrosymmetrical blocks according to the obtained geometrical information, each mismatching resistor block being decomposed to a plurality of unit-resistors. The unit-resistors are placed into matching resistor blocks to return a resulting layout with improved matching quality by reducing centroid offset between a centroid of the unit-resistors and a centroid of the matching resistor block. | 06-06-2013 |
| 20130152032 | METHOD FOR INSPECTING A CHIP LAYOUT - A method is provided for inspecting a chip layout. The method includes providing a chip layout having a plurality of patterns designed according to a design rule and performing a first inspection to the plurality of patterns according to the design rule. The method also includes determining patterns violating the design rule, as violating patterns, and corresponding violation values, and determining violating patterns having a minimum violation value among the violating patterns. Further, the method includes classifying the violating patterns having the minimum violation value into at least one sub-category based on characteristics of the violating patterns having the minimum violation value, and performing a second inspection on a selected violating pattern from the sub-category to determine whether the selected violating pattern and other violating patterns in the sub-category satisfy fabrication process conditions. | 06-13-2013 |
| 20130152033 | TCAD Emulation Calibration Method of SOI Field Effect Transistor - The present invention provides a Technology Computer Aided Design (TCAD) emulation calibration method of a Silicon On Insulator (SOI) field effect transistor, where process emulation Metal Oxide Semiconductor (MOS) device structures with different channel lengths Lgate are obtained by establishing a TCAD process emulation program; based on the process emulation MOS device structures, the process emulation MOS device structures are calibrated according to a Transmission Electron Microscope (TEM) test result, a secondary ion mass spectrometer (SIMS) test result, a Capacitor Voltage (CV) test result, a WAT test result, and a square resistance test result of an actual device, so as to complete TCAD emulation calibration of key electrical parameters of an SOI field effect transistor. Through the calibration method consistent with the present invention, in the same SOI process, TCAD emulation results of key parameters Vt and Idsat of MOSFETs of different sizes all meet a high-precision requirement that an error is less than 10%; moreover, accurate and effective pretest can be implement in the case of multiple splits, thereby providing effective guidance for research, development and optimization of a new process flow. | 06-13-2013 |
| 20130159948 | LAYOUT-SPECIFIC CLASSIFICATION AND PRIORITIZATION OF RECOMMENDED RULES VIOLATIONS - A method, system, and computer program product for classifying and prioritizing a set of recommended rule (RR) violations in an integrated circuit (IC) design are provided in the illustrative embodiments. The set of RR violations is received. A layout corresponding to the IC design is received. A set of features is selected in the layout. A classification model corresponding to the set of features is selected. Using the set of features and the classification model, the first RR violation is classified into a classification from a set of classifications. The classification is prioritized in an order of priority such that the first RR violation in the classification is recommended for remedying in the order of priority. | 06-20-2013 |
| 20130159949 | HIGH PERFORMANCE DESIGN RULE CHECKING TECHNIQUE - Roughly described, a design rule data set is developed offline from the design rules of a target fabrication process. A design rule checking method involves traversing the corners of shapes in a layout region, and for each corner, populating a layout topology database with values that depend on respective corner locations. After the layout topology database is populated, the values are compared to values in the design rule data set to detect any design rule violations. Violations can be reported in real time, while the user is manually editing the layout. Preferably corner traversal is performed using scan lines oriented perpendicularly to edge orientations, and scanning in the direction of the edge orientations. Scans stop only at corner positions and populate the layout topology database with what information can be gleaned based on the current scan line. The different scans need not reach each corner simultaneously. | 06-20-2013 |
| 20130167098 | POWER ESTIMATION USING ACTIVITY INFORMATION - A method of estimating power consumption of an electronic device is performed by a processing device. The estimating includes estimating a power consumption of a gate-level implementation of an electronic device design. The estimating further includes independently calculating for each of a plurality of implementation-invariant nodes of the design an incremental power dissipation associated with that node. | 06-27-2013 |
| 20130174109 | DEVICE MISMATCH CORNER MODEL - A device mismatch corner model for semiconductor device simulation is provided. A method of providing the device mismatch corner model for semiconductor device simulation, includes selecting a type of electric performance target F for a type of device, determining a number N of semiconductor devices for which mismatches among electric performance targets of the semiconductor devices are simulated, and determining a desired k-sigma mismatch corner value among N(N−1)/2 pairs of the electric performance targets. The method further includes identifying at least one electric parameter P of the semiconductor devices that has a mismatch component and contributes to the mismatches among the electric performance targets of the semiconductor devices, determining a plurality of corner values for the at least one electrical parameter P, and running at most N circuit simulations based on the determined plurality of corner values which are recalculated for each of the circuit simulations. | 07-04-2013 |
| 20130174110 | CIRCUIT ASSEMBLY YIELD PREDICTION WITH RESPECT TO FORM FACTOR - Embodiments of the invention include systems and methods for automatically predicting production yield for a circuit assembly according to attributes of its components and defect data mapped thereto. Embodiments receive a proposed design specification for a circuit assembly, including bill of materials (BOM) and schematic data, at a yield prediction environment. The yield prediction environment maps a set of attributes to each component in the BOM and maps a set of possible defects to each component according to its attributes. Defects may be further mapped to a manufacturing process assigned to populate each component in the circuit assembly. The defects are associated with predicted frequencies of occurrence, which can be used to roll up a yield prediction for the circuit assembly. Embodiments further allow “what-if” analyses to be performed so that different yield prediction results can be compared according to different form factor options and/or different manufacturing process options. | 07-04-2013 |
| 20130174111 | CIRCUIT ASSEMBLY YIELD PREDICTION WITH RESPECT TO MANUFACTURING PROCESS - Embodiments of the invention include systems and methods for automatically predicting production yield for a circuit assembly according to attributes of its components and defect data mapped thereto. Embodiments receive a proposed design specification for a circuit assembly, including bill of materials (BOM) and schematic data, at a yield prediction environment. The yield prediction environment maps a set of attributes to each component in the BOM and maps a set of possible defects to each component according to its attributes. Defects may be further mapped to a manufacturing process assigned to populate each component in the circuit assembly. The defects are associated with predicted frequencies of occurrence, which can be used to roll up a yield prediction for the circuit assembly. Embodiments further allow “what-if” analyses to be performed so that different yield prediction results can be compared according to different form factor options and/or different manufacturing process options. | 07-04-2013 |
| 20130185688 | OVER STRESS VERIFY DESIGN RULE CHECK - Some aspects of this disclosure provide for electronic design automation (EDA) techniques that check whether individual blocks, such as transistors or other semiconductor devices, are connected to their correct power domains during design. In this way, the disclosed EDA techniques can limit or prevent overstress conditions applied to blocks and help to improve reliability of integrated circuits, when manufactured. | 07-18-2013 |
| 20130185689 | METHOD OF AND SYSTEM FOR GENERATING OPTIMIZED SEMICONDUCTOR COMPONENT LAYOUT - A method of generating an optimized layout of semiconductor components in conformance with a set of design rules includes generating, for a unit cell including one or more semiconductor components, a plurality of configurations each of which satisfies some, but not all, of the design rules. For each configuration, it is checked whether a layout, which is a repeating pattern of the unit cell, satisfies the remaining design rules. Among the configurations which satisfy all of the design rules, the configuration providing an optimal value of a property is selected for generating the optimized layout of the semiconductor components. | 07-18-2013 |
| 20130191802 | Automatically Modifying a Circuit Layout to Perform Electromagnetic Simulation - A system and method for automatically modifying a first layout of a circuit. The first layout may describe a plurality of layers used in a fabrication process to manufacture the circuit. When performed, the fabrication process may result in a vertical electrical connection between two of the layers. However, the vertical electrical connection may not be directly specified by the first layout. The system and method may operate to apply a set of rules to the first layout to automatically generate a modified layout directly specifying a vertical electrical connection between the two layers. The set of rules may be based on knowledge of the fabrication process, and may be designed to modify the geometry of the first layout to more closely model the real geometry of the circuit that will result from the fabrication process. The modified layout may enable an electromagnetic (EM) simulation of the circuit to be accurately performed. | 07-25-2013 |
| 20130198710 | SEMICONDUCTOR DEVICE FEATURE DENSITY GRADIENT VERIFICATION - A method for verifying that acceptable device feature gradients and device feature disparities are present in a semiconductor device layout, is provided. The method provides for dividing a device layout into a plurality of windows and measuring or otherwise determining the device feature density within each window. The device layout includes various device regions and the method provides for comparing an average device feature density within one region to surrounding areas or other regions and also for determining gradients of device feature densities. The gradients may be monitored from within a particular device region to surrounding regions. Instructions for carrying out the method may be stored on a computer readable storage medium and executed by a processor. | 08-01-2013 |
| 20130212548 | METHODS FOR ANALYZING DESIGN RULES - Methods and apparatus are provided for analyzing impact of design rules on a layout. One exemplary method involves generating variants of the layout for different values for the rule, determining values of a device metric for each of the layout variants, and identifying the relationship between rule and the device metric based on the values for the device metric corresponding to the different values for the rule. In one embodiment, the layout variants are generated by using the different values for the rule to perform layout compaction on an initial layout generated in accordance with an initial value for the rule. | 08-15-2013 |
| 20130232460 | Power State Transition Verification For Electronic Design - Various implementations of the invention may be applied to generate an auxiliary verification statement. The auxiliary verification statement defines properties that check if the power domains are active at appropriate times is generated. Particularly, the auxiliary verification statement checks to ensure that power domain transitions do not interfere with the operation of the device design. With various implementations of the invention, an auxiliary verification statement may be generated by first determining a set of properties instantiated in a verification statement and then synthesizing the auxiliary verification statement based upon the determined properties, the corresponding device design and the power domains. In some implementations, the auxiliary verification statement instantiates properties that check if the power domains related to the properties in the verification statement are active when the verifications statement is exercised. In various implementations, this is accomplished by substituting select ones of the properties in the verification statement with select properties corresponding to the power domain. | 09-05-2013 |
| 20130246990 | SYSTEM AND METHOD FOR MODELING THROUGH SILICON VIA - A computer implemented system comprises a processor programmed to analyze a circuit to determine a response of the circuit to an input radio frequency (RF) signal, for at least one of designing, manufacturing, and testing the circuit. An interposer model is tangibly embodied in a non-transitory machine readable storage medium to be accessed by the processor. The interposer model is processed by the computer to output data representing a response of a though substrate via (TSV) to the radio frequency (RF) signal. The interposer model comprises a plurality of TSV models. Each TSV model has a respective three-port network. One of the ports of each three-port network is a floating node. The floating nodes of each of the three-port networks are connected to each other. | 09-19-2013 |
| 20130254729 | DEVICE AND METHOD FOR CHECKING SIGNAL TRANSMISSION LINES OF PCB LAYOUT FILES - A device and a method reads a circuit printed circuit (PCB) layout file, extracts arrangement information of all the interference source components and signal transmission lines of the PCB layout file, and selects a interference source component from the PCB layout file, then determines if there is any signal transmission line is laid under the selected interference source component. | 09-26-2013 |
| 20130254730 | LAYOUT SYSTEM AND METHOD OF CREATING DIFFERENTIAL PAIR ON PRINTED CIRCUIT BOARD - A layout method for the creation of a differential pair for the transmission of signals generates a differential pair between a differential signal sender and a differential signal receiver in a layout of a PCB. Differential signals are transmitted via two wires. A plurality of vertical lines are created on the differential pair. Junctions of the vertical lines and the two wires are defined as pairs of points. A first length between one terminal of the differential signal sender and one point of each pair of points and a second length between the other terminal of the differential signal sender and the other point of each pair of points are calculated. If any difference between the first length and the second length does not fall within an allowable range, the lengths of the two wires are adjusted. | 09-26-2013 |
| 20130263073 | COMPUTER SYSTEM AND METHOD FOR PERFORMING A ROUTING SUPPLY AND DEMAND ANALYSIS DURING THE FLOOR PLANNING STAGE OF AN INTEGRATED CIRCUIT DESIGN PROCESS - A floor planning tool is provided that performs the functions that are typically performed by floor planning tools, but in addition, determines the supply of routing resources and the demand on routing resources for all routing channels while applying variable routing rules and static timing estimations to arrive at a preliminary routed floor plan. This drastically reduces the number of iterations that subsequently will need to be performed by the floor planning tool and by routing and static timing analysis tools to arrive at a final routed floor plan. | 10-03-2013 |
| 20130263074 | Analog Rule Check Waiver - When a designer designates one or more errors identified in layout design data as false errors, waiver geometric elements corresponding to the designated false errors are created and added to the design. The waiver geometric element may be associated with a verification rule that generated its corresponding false error. When the design is subsequently analyzed using those verification rules in another verification rule check process, the waiver geometric elements are examined, and used to mask those errors associated with a waiver geometric element that would otherwise be displayed to the designer. | 10-03-2013 |
| 20130283221 | METHOD FOR INPUT/OUTPUT DESIGN OF CHIP - Method for input/output (IO) design of a chip, including: according to a signal IO pin sequence and associated driving parameters, sequentially placing a signal IO cell in the IO design associated with each of the signal IO pins; after a signal IO cell is placed, performing a simultaneous switching output (SSO) verification step according to physical layout parameters and locations of the signal IO cells placed in the IO design, so as to check whether an SSO specification is violated; if not violated, continuing to place a signal IO cell of a next signal IO pin; if violated, including a decoupling capacitor, an IO power cell and/or an IO ground cell in the IO design. | 10-24-2013 |
| 20130298094 | Methods and Apparatus for Layout Verification - Methods and apparatus of performing layout-versus-layout (LVL) comparison are disclosed. A layout may be in various formats such as GDSII or OASIS, for different circuits, and represented by a basic layout element, a hierarchical cell or a plurality of independent cells in various layers. A basic layout element, a hierarchical cell, and a layout with a plurality of independent cells may have a signature generated according to the embodiment methods. The signature of a basic layout element may be generated based on values of a center and a circumference, and a hashed trace value generated by a hash function of a trace of the basic layout element. The signature of a hierarchical cell can be generated recursively. A signature of a first layout may be compared to a signature of a second layout to determine whether the first layout matches the second layout. | 11-07-2013 |
| 20130298095 | METHOD FOR CHECKING I/O CELL CONNECTIONS AND ASSOCIATED COMPUTER READABLE MEDIUM - A computer readable medium includes a program code for checking whether an I/O cell of a chip design has a connection error or not, where the chip design includes a plurality of I/O cells and a plurality of blocks, and when the program code is executed by a processor, the program code executes following steps: checking a connection between the I/O cell and a block by utilizing a check item corresponding to an attribute of the I/O cell to generate a checking result; and determining whether the I/O cell has a connection error according to the checking result. | 11-07-2013 |
| 20130298096 | REAL TIME DRC ASSISTANCE FOR MANUAL LAYOUT EDITING - Roughly described, while manually dragging shapes during IC layout editing, editing operations determine which edges of which shapes are moving at what speed ratios. Based on the edge information and the DRC rules, the system calculates and keeps track of the minimum of the maximum distance the edges are allowed to move with the cursor without violating DRC rules, in four linear directions and all corner directions. Once a next cursor destination point is known, a DRC clean destination point is calculated based on the linear and corner bounds. If the next cursor position is beyond a the push-through distance ahead of the new DRC clean point, the editing objects are moved to the user's destination point. Otherwise, the editing objects are moved to the new DRC clean destination point, thereby stopping movement at that point. | 11-07-2013 |
| 20130305202 | MISMATCH VERIFICATION DEVICE AND METHODS THEREOF - A method can include identifying a device design comprising first and second instantiations of a device, identifying a layer of the device design, identifying a first region of the device design for the first instantiation based on the layer of the first instantiation, and a second region of the device design for the second instantiation based on the layer of the second instantiation. identifying a first compare layer of the device design that comprises a plurality of first compare features including a first compared feature within the first region and a second compared feature within the second region, determining a difference between the first compared feature and the second compared feature, and determining if the difference meets a tolerance to determine if the first instantiation matches the second instantiation. | 11-14-2013 |
| 20130311963 | SUB-CIRCUIT MODELS WITH CORNER INSTANCES FOR VLSI DESIGNS - An approach for providing sub-circuit models with corner instances for VLSI designs is disclosed. Embodiments include: determining a circuit design that includes a plurality of sub-circuit models having a plurality of characteristics; and associating, by a processor, a sub-circuit model of the plurality of sub-circuit models with a corner instance value, and another sub-circuit model of the plurality of sub-circuit models with another corner instance value. Other embodiments include analyzing, by the processor, the circuit design according to the corner instance value and the other corner instance value. | 11-21-2013 |
| 20130326445 | Categorization of Design Rule Errors - Embodiments of the invention include a method for categorizing and displaying design rule errors. The method may include receiving, from a design rule checker, more than one violation of a design rule within a design layout. The method may also include determining distinct categories of the design rule violations by comparing parameters associated with the design rule violations. | 12-05-2013 |
| 20130326446 | TECHNIQUES FOR CHECKING COMPUTER-AIDED DESIGN LAYERS OF A DEVICE TO REDUCE THE OCCURRENCE OF MISSING DECK RULES - A technique for computer-aided design layer checking of an integrated circuit design includes generating a representation of a device (e.g., a parameterized cell). Computer-aided design (CAD) layers are sequentially removed from the parameterized cell and a determination is made as to whether expected errors are detected or missed by an associated deck. The associated deck is then modified to detect the expected errors that are missed. | 12-05-2013 |
| 20130326447 | METHOD AND SYSTEM FOR LAYOUT PARASITIC ESTIMATION - A system comprises an electronic design automation (EDA) tool, for generating a schematic design of an integrated circuit (IC), generating a layout from the schematic design, editing the layout, and verifying the schematic design and layout. At least one non-transitory, computer readable storage medium, is provided for storing data representing the schematic design and the layout, the layout having a network of routing paths connecting at least two active layer devices of the IC design. An RC tool is provided for computing estimated parasitic capacitances of the routing paths of the network before verifying the schematic design and layout, and for inserting a capacitor corresponding to the estimated parasitic capacitance into the data representing the schematic design of the IC. A first device level simulation tool for simulating performance of the network based on the at least two active layer devices and the estimated parasitic capacitances. | 12-05-2013 |
| 20130326448 | Techniques for Electromigration Stress Determination in Interconnects of an Integrated Circuit - In one or more embodiments, one or more methods, processes, and/or systems described can determine stress failures in interconnect segments of integrated circuit designs and correct those failure via modifying the interconnect segments of the integrated circuit designs with one or more additions to the interconnect segments of the integrated circuit designs. Potentials can be received from a simulation, and one or more failures of an interconnect segment can be determined via the potentials from the simulation. For example, a failure can be determined via a comparison with a potential from the simulation and a critical potential. An interconnect segment can be modified with a stub such that a comparison with a potential from the simulation and a critical potential to provide a non-failing, modified interconnect segment. | 12-05-2013 |
| 20130346933 | PROTOTYPE VERIFICATION SYSTEM AND VERIFICATION METHOD FOR HIGH-END FAULT-TOLERANT COMPUTER - A prototype verification system and method are provided for a high-end fault-tolerant computer. The system includes multiple single junction prototype verification systems and an interconnection router chipset. The single junction prototype verification systems are interconnected through the interconnection router chipset. Each single junction prototype verification system includes a computer board which is a four-path tightly-coupled computer board, and a chip verification board including two junction controller chipsets. Each junction controller chipset includes two field-programmable gate array (FGPA) chips which bear a logic of one junction controller together, and an interconnection board including two FGPA chips. Each FPGA chip provides a high speed interconnection port used to achieve protocol interconnection between two paths of the computer board and one of the junction controller chipsets. | 12-26-2013 |
| 20130346934 | HIGH-END FAULT-TOLERANT COMPUTER SYSTEM AND METHOD FOR SAME - The present invention provides a high-end fault-tolerant computer system and an implementation method. The system includes N single junction prototype verification systems and M crossbar-switch interconnection router chipsets. Each crossbar-switch interconnection router chipset is used to achieve the interconnection among the N single junction prototype verification systems. Switching is not performed among all crossbar-switch interconnection router chipsets, and both M and N are positive integers greater than or equal to 2. The single junction includes: a computer board, which is 4-path tightly-coupled computer board, and a junction controller for controlling 2 paths of CPUs on the computer board. The present invention can effectively realize the global memories sharing, balance the system transmission bandwidth and delay, and solve the problem of the integration reliability of multi-path CPU system. | 12-26-2013 |
| 20130346935 | SEMICONDUCTOR DEVICE FEATURE DENSITY GRADIENT VERIFICATION - A method for verifying that acceptable device feature gradients and device feature disparities are present in a semiconductor device layout, is provided. The method provides for dividing a device layout into a plurality of windows and measuring or otherwise determining the device feature density within each window. The device layout includes various device regions and the method provides for comparing an average device feature density within one region to surrounding areas or other regions and also for determining gradients of device feature densities. The gradients may be monitored from within a particular device region to surrounding regions. Instructions for carrying out the method may be stored on a computer readable storage medium and executed by a processor. | 12-26-2013 |
| 20140007030 | INTEGRATED DESIGN ENVIRONMENT FOR NANOPHOTONICS | 01-02-2014 |
| 20140007031 | SEMICONDUCTOR DEVICE DESIGN METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT | 01-02-2014 |
| 20140007032 | INTEGRATED DESIGN ENVIRONMENT FOR NANOPHOTONICS | 01-02-2014 |
| 20140007033 | DEVICE FOR AND METHOD OF GENERATING WIRING DATA, AND IMAGING SYSTEM | 01-02-2014 |
| 20140019927 | WAFERLESS MEASUREMENT RECIPE - Embodiments relate to a method for manufacturing and processing semiconductor devices or integrated circuits (IC) and in particular to the generation of measurement recipes in the manufacturing of the semiconductor devices or ICs. The method comprises defining a sampling plan, mapping target locations of a device contained in the sampling plan to an article/a wafer having a plurality of said devices, verifying the mapping file and processing the verification to produce a measurement recipe. In one embodiment, the measurement recipe is created without having the actual processed wafer. | 01-16-2014 |
| 20140019928 | CIRCUIT ANALYZER SYSTEMS AND METHODS - Structures of a circuit are identified. Voltages are propagated to the identified structures. Additionally, internal node voltages for the identified structures are obtained. Asymmetrical operating conditions are identified. | 01-16-2014 |
| 20140019929 | Partial Instruction-by-instruction checking on acceleration platforms - A method, apparatus, and product for partial instruction-by-instruction checking on acceleration platforms. The method comprising: obtaining a trace from an hardware accelerator, wherein the trace is generated by the hardware accelerator during simulation of an execution of a test case on a circuit design; identifying a synchronization point in the trace; simulating execution of the test case by a reference model until reaching the synchronization point; and performing instruction-by-instruction checking in order to identify an error in the circuit design based on the simulated execution by the hardware accelerator, wherein the instruction-by-instruction checking is performed with respect to a portion of the trace that relates to operation after executing the synchronization point, wherein the instruction-by-instruction checking utilizes the reference model to determine an expected outcome of each event recorded in the portion of the trace. | 01-16-2014 |
| 20140026109 | COMPUTING DEVICE AND METHOD FOR AUTOMATICALLY CHECKING WIRING INFORMATION - In a computing device, a computerized method and a non-transitory storage medium are applied in checking whether the transmission lines in a stored wiring diagram meet a certain criterion in relation to vias in the routes of differential pairs. A transmission line is selected to determine whether or not the line belongs to a differential pair and passes through at least one via. Another transmission line of the differential pair is obtained for analysis when the selected transmission line passes through at least one via. Sizes of vias in the respective routes of the differential pair are compared and a distance between the vias of the differential pair is compared. The differential pair, and the sizes of vias which comply or do not comply with the criterion are recorded and displayed in a list of results. | 01-23-2014 |
| 20140033148 | ELASTIC MODULUS MAPPING OF A CHIP CARRIER IN A FLIP CHIP PACKAGE - A computer-implemented method provides an elastic modulus map of a chip carrier of a flip chip package. Design data including dielectric and conductive design elements of each of vertically aligned sub-areas of each of the layers of the chip carrier are modeled as springs to provide the elastic modulus map. Determining the elastic modulus of the sub-areas of the chip carrier identifies probable mechanical failure sites during chip-join and cools down of the flip chip package. Modifying a footprint of solder bumps to the chip carrier reduces stresses applied to the identified probable mechanical failure sites. Modifying the chip carrier design to reduce a stiffness of sub-areas associated with identified probable mechanical failure sites also reduces stresses from chip-join and cool-down. | 01-30-2014 |
| 20140033149 | CAPTURING MUTUAL COUPLING EFFECTS BETWEEN AN INTEGRATED CIRCUIT CHIP AND CHIP PACKAGE - Systems and methods are provided for capturing mutual coupling effects between an integrated circuit chip and chip package using electronic design automation (EDA) tools. Specifically, a method is provided that is implemented in a computer infrastructure for designing an integrated circuit chip. The method includes compiling process technology parameters that describe electrical behavior for a chip-package coupling and a package of the integrated circuit chip. The method also includes generating a parasitic technology file to include the compiled process technology parameters. | 01-30-2014 |
| 20140033150 | FORMAL VERIFICATION OF BIT-SERIAL DIVISION AND BIT-SERIAL SQUARE-ROOT CIRCUIT DESIGNS - Methods and apparatuses are described for formally verifying a bit-serial division circuit design or a bit-serial square-root circuit design. Some embodiments formally verify a bit-serial division circuit design using a set of properties that can be efficiently proven using a bit-level solver. In some embodiments, the set of properties that are used for verifying a bit-serial division circuit design does not include any terms that multiply a w-bit partial quotient with the divisor. Some embodiments formally verify a bit-serial square-root circuit design using a set of properties that can be efficiently proven using a bit-level solver. In some embodiments, the set of properties that are used for verifying a bit-serial square-root circuit design does not include any terms that compute a square of a w-bit partial square-root. | 01-30-2014 |
| 20140033151 | EQUIVALENCE CHECKING BETWEEN TWO OR MORE CIRCUIT DESIGNS THAT INCLUDE DIVISION AND/OR SQUARE ROOT CIRCUITS - Methods and apparatuses are described for proving equivalence between two or more circuit designs that include one or more division circuits and/or one or more square-root circuits. Some embodiments analyze the circuit designs to determine an input relationship between the inputs of two division (or square-root) circuits. Next, the embodiments determine an output relationship between the outputs of two division (or square-root) circuits based on the input relationship. The embodiments then prove equivalence between the circuit designs by using the input and output relationships. | 01-30-2014 |
| 20140040843 | LOW-VOLTAGE SWING CIRCUIT MODIFICATIONS - Electronic design automation (EDA) technologies are disclosed that analyze a circuit design for candidate low-voltage swing (LVS) modifications, report the impact of the candidate LVS modifications on circuit characteristics (such as area, timing and energy) and implement selected LVS modifications based on their impact on the circuit characteristics. Candidate LVS modifications comprise replacing existing standard low-voltage swing drivers and receivers, or inserting low-voltage swing drivers and receivers. | 02-06-2014 |
| 20140059506 | METHOD AND APPARATUS FOR APPLYING POST GRAPHIC DATA SYSTEM STREAM ENHANCEMENTS - An approach is provided for applying post graphic data system (GDS) stream enhancements back to the design stage. Embodiments include receiving a data stream of an integrated circuit design layout from a design stage, determining one or more design constructs based on an analysis of the data stream, determining one or more instructions to implement the one or more design constructs at the design stage, and sending the instructions to the design stage to implement the one or more design constructs. | 02-27-2014 |
| 20140059507 | Defect Injection For Transistor-Level Fault Simulation - Aspects of the invention relate to techniques of defect injection for transistor-level fault simulation. A circuit element in a circuit netlist of a circuit is first selected for defect injection. Next, a defect is determined based on whether the selected circuit element is a design-intent circuit element or a parasitic circuit element. After the defect is determined, the defect is injected into the circuit netlist and then the circuit is simulated. | 02-27-2014 |
| 20140075402 | Method of Fast Analog Layout Migration - A computer implemented method for forming an integrated circuit (IC) layout is presented. The method includes forming a constraint tree when a computer is invoked to receive a first layout of the IC and generating a second layout of the IC in accordance with the constraint tree. | 03-13-2014 |
| 20140082575 | METHOD FOR PLACING DECOUPLING CAPACITORS - A method comprises selecting a region from a layout pattern of an integrated circuit, wherein the region comprises a plurality of functional units, and wherein the functional units are not coupled to each other through a variety of connection components, identifying hot spots in the region using a first threshold and inserting a plurality of decoupling capacitors adjacent to the hot spots. | 03-20-2014 |
| 20140089874 | Method and Apparatus for Optimizing Memory-Built-In-Self Test - Testing of memories is done using an optimized memory built-in-self-test (MBIST) approach, including the generation of compact models for memory. Cost functions are constructed from estimated parameters affecting MBIST, and a user is able to assign relative weights to the parameters. Estimated parameters include MBIST area, wiring congestion, and timing overhead, as well as power consumption and timing. The cost functions are minimized using optimization techniques, resulting in an optimized grouping of memory devices and an optimized schedule for MBIST testing. The estimated parameters may be derived from a compact model constructed from data experimentally-derived from various memory devices. This approach allows a circuit designer to generate and revise groupings and schedules prior to running a full design flow, saving time and cost, while still achieving high-quality results. | 03-27-2014 |
| 20140089875 | Method and Apparatus for Optimizing Memory-Built-In-Self Test - Testing of memories is done using an optimized memory built-in-self-test (MBIST) approach, including the generation of compact models for memory. Cost functions are constructed from estimated parameters affecting MBIST, and a user is able to assign relative weights to the parameters. Estimated parameters include MBIST area, wiring congestion, and timing overhead, as well as power consumption and timing. The cost functions are minimized using optimization techniques, resulting in an optimized grouping of memory devices and an optimized schedule for MBIST testing. The estimated parameters may be derived from a compact model constructed from data experimentally-derived from various memory devices. This approach allows a circuit designer to generate and revise groupings and schedules prior to running a full design flow, saving time and cost, while still achieving high-quality results. | 03-27-2014 |
| 20140089876 | Thermal Analysis of Integrated Circuit Packages - A method includes retrieving a first component information of a secured portion of a package, wherein the first component information is encrypted. The step of retrieving includes decrypting the first component information. A thermal resistance-network (R-network) is generated from the decrypted first component information. A temperature map of the package is generated using the thermal R-network and a second component information of an unsecured portion of the package, wherein the secured portion and the unsecured portion are bonded to each other. | 03-27-2014 |
| 20140089877 | Electrical Hotspot Detection, Analysis And Correction - Aspects of the invention relate to techniques for detecting and correcting electrical hotspots in a layout design for a circuit design comprising an analog circuit. Layout parameters for device instances associated with electrical constraints are first extracted. Based on the extracted layout parameters, electrical parameter variations for the device instances may be computed to identify one or more electrical hotspots in the layout design. A sensitivity analysis of the one or more electrical hotspots is performed to generate repair hints. Based on the repair hints, the layout design is adjusted. | 03-27-2014 |
| 20140089878 | DETERMINING APPARATUS, DETERMINING METHOD, AND COMPUTER PRODUCT - A determining apparatus includes a processor configured to detect from among a group of sectional areas obtained by dividing layout data indicating a design area concerning a circuit-under-design and stored in a storage device, adjacent sectional areas that are adjacent to sectional areas in a design change area and outside the design change area; count with respect to the sectional areas that are outside the design change area and among the group of sectional areas, number of detections as the adjacent sectional area; judge whether the number of detections counted is at least a predetermined number of two; and determine as an area for extraction for wiring parasitic capacitance, the sectional areas for which the number of detections is judged to be at least the predetermined number. | 03-27-2014 |
| 20140096098 | USING ENTIRE AREA OF CHIP IN TDDB CHECKING - A method for checking for reliability problems of an integrated circuit that includes determining a total MOS transistor gate area for an entire integrated circuit. Based on the total MOS transistor gate area, a time dependent dielectric breakdown lifetime (TDDB) is calculated. | 04-03-2014 |
| 20140101630 | COMPUTER SYSTEM FOR GENERATING AN INTEGRATED AND UNIFIED VIEW OF IP-CORES FOR HIERARCHICAL ANALYSIS OF A SYSTEM ON CHIP (SOC) DESIGN - In order to realize some of the advantages described above, there is provided a computer system for verification of an intellectual property (IP) core in a system-on-chip (SoC). The system generates a plurality of verification specific abstracted views of the IP core, each of the plurality of verification specific abstracted views having a plurality of verification specific attributes at an input/output (I/O) interface of each of the abstracted view of the IP-core. A unified abstracted view'of the IP-core is generated. | 04-10-2014 |
| 20140109029 | MIXED SIGNAL IP CORE PROTOTYPING SYSTEM - A system for prototyping an integrated circuit (IC) that has a mixed signal intellectual property (IP) core includes implementing the IP core using discrete programmable digital ICs and discrete analog ICs by partitioning the IP core into a digital IP portion and an analog IP portion. | 04-17-2014 |
| 20140115550 | COMPUTING DEVICE AND METHOD FOR CHECKING LENGTH OF SIGNAL TRACE - In a method for checking the length of a signal trace between a coupling capacitor and a via in a printed circuit board (PCB) design using a computing device, a PCB file is obtained from a storage device to simulate a PCB design. The signal trace between the coupling capacitor and the via is filtered on the PCB design, and a real length of the signal trace between the coupling capacitor and the via is calculated. If the real length is greater than a specified length, the method locates a position of the via on the PCB design and generates a design report indicating that the signal trace between the coupling capacitor and the via is unqualified. The method further displays information of the signal trace on a display device of the computing device. | 04-24-2014 |
| 20140115551 | Correlation of Device Manufacturing Defect Data with Device Electrical Test Data - Various embodiments related to correlating a location of a defect on a substrate for a semiconductor device to an electrical significance of a device structure at that location are disclosed. For example, one embodiment includes receiving a defect location for the location on the substrate where the defect was detected; receiving a physical representation of the semiconductor device for the defect location; generating a significance determination indicating whether the defect is located in an electrically significant region by correlating the defect location to logical and physical layout information included in the physical representation; and displaying the significance determination. | 04-24-2014 |
| 20140130001 | Method of Reducing Parasitic Mismatch - A method of reducing parasitic mismatches comprises generating a first net list file from a first layout through a resistance-inductance-capacitance (RLC) extraction mechanism using a first simulation tool, performing a V/I test on a network through a second simulation tool, determining whether a mismatch exists based upon a result of the V/I test and modifying a connection trace of the network to generate a second layout. | 05-08-2014 |
| 20140130002 | METHOD AND SYSTEM FOR USING A BREADBOARD - A method for using a breadboard involves receiving a circuit wiring connection layout, in which the circuit wiring connection layout includes a visual representation of circuit elements. The method further involves sending, to the breadboard, the circuit wiring connection layout, receiving a selection of a circuit element from the circuit elements to obtain a selected circuit element, sending, to the breadboard and based on the selected circuit element, a signal to activate an alert device on the breadboard indicating where a user should place the selected circuit element on the breadboard, receiving a circuit characteristic to measure from the selected circuit element, sending, to the breadboard, the circuit characteristic to measure from the selected circuit element, receiving, from the breadboard, a measurement of the circuit characteristic to obtain a measured circuit characteristic, and displaying the measured circuit characteristic. | 05-08-2014 |
| 20140137060 | METHOD FOR DUMMY METAL AND DUMMY VIA INSERTION - A method of inserting dummy metal and dummy via in an integrated circuit design includes inserting, by a computer, dummy metals using a place and route tool, wherein the place and route tool has timing-awareness to improve a timing performance of the integrated circuit design, and the dummy metals have a length less than or equal to a predetermined maximum length. The method further includes inserting, by the computer, dummy vias using a design-rule-checking utility separately from the inserting of the dummy metals. | 05-15-2014 |
| 20140137061 | METHODS AND SYSTEMS FOR COMPUTER AIDED DESIGN OF 3D INTEGRATED CIRCUITS - Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed. | 05-15-2014 |
| 20140149953 | REDUCTION OF METAL FILL INSERTION TIME IN INTEGRATED CIRCUIT DESIGN PROCESS - Techniques for use in integrated circuit design systems for reducing metal fill insertion time in the integrated circuit design process. In one example, a method includes the following steps. Metal fill data associated with a given layout from a placement and routing database of an integrated circuit design system is stored. The metal fill data is purged from the placement and routing database. At least one change to layout data in the placement and routing database is implemented. The stored metal fill data is loaded into the placement and routing database after the at least one change is implemented to the layout data. A check is performed for an existence of one or more violations associated with the metal fill data due to implementing the at least one change to the layout data in the placement and routing database. A correction procedure is performed on the metal fill data when one or more violations exist. | 05-29-2014 |
| 20140149954 | STRESS EFFECT MODEL OPTIMIZATION IN INTEGRATED CIRCUIT SPICE MODEL - A method and apparatus for stress effect model optimization in IC SPICE model and an IC fabrication method are disclosed. The method for optimizing a stress effect model in an integrated circuit model including obtaining values of at least one layout parameter for a plurality of layout areas in an integrated circuit layout; obtaining values of at least one processing parameter for a plurality of wafer areas corresponding to the layout areas; based on the obtained values of the layout parameter and the obtained values of the process parameter, establishing a function representative of dependency of the process parameter on the layout parameter; and applying the function as a process model parameter to the stress effect model. | 05-29-2014 |
| 20140149955 | LOW-OVERHEAD MULTI-PATTERNING DESIGN RULE CHECK - Roughly described, a system enables quick and accurate depiction to a user of multi-patterning layout violations so that they may be corrected manually and in real time, and without interfering with normal manual editing process. In one embodiment, the system involves iteratively building tree structures with nodes identifying islands and arcs identifying multi-patterning spacing violations between the connected islands. The system detects coloring violations during the building of these tree structures, using the relationships previously inserted. The coloring violations preferably are reported to a user in the form of visual indications of the cycles among the candidate spacing violations, with the candidate spacing violations also themselves indicated visually and individually. The user can see intuitively how to move the islands around, and in which directions and by what distance, in order to remove a multi-patterning spacing violation and thereby break the cycle. | 05-29-2014 |
| 20140157218 | MODEL-BASED RETIMING WITH FUNCTIONAL EQUIVALENCE CONSTRAINTS - A system and method tests for functional equivalence prior to automatically retiming a high-level specification. An Intermediate Representation (IR) includes one or more graphs or trees based on the high-level specification. A functional equivalence (FE) analyzer determines whether one or more components in the graph meet certain value and state conditions and thus is a candidate for retiming. A bounded scheduler then retimes only those components that pass the FE analysis. | 06-05-2014 |
| 20140165016 | DATA LOADING METHOD, DESIGN SUPPORT DEVICE, AND RECORDING MEDIUM RECORDING DATA LOADING PROGRAM - A data loading method of loading part information of parts, includes; calculating, by a computer, a connection distance between the parts having a connection relationship based on design information including locations of first parts of the parts which have been placed by a design work or a connection relationship between the parts; calculating a distance judgment value based on a distance reference value and the connection distance; acquiring work information including work contents and a work location of the design work; identifying a part with the connection distance greater than or equal to the distance judgment value from second parts of the parts which have been placed and have not been wired when a placement work status based on the work information exceeds a placement reference value; and loading the part information of the identified part from a storage. | 06-12-2014 |
| 20140165017 | PHYSICS-BASED RELIABILITY MODEL FOR LARGE-SCALE CMOS CIRCUIT DESIGN - This disclosure relates generally to systems and methods for simulating physical active semiconductor components using in silico active semiconductor components. To simulate charge degradation effect(s) in a circuit simulation, a simulated defect signal level is produced. More specifically, the simulated defect signal level simulates at least one charge degradation effect in the in silico active semiconductor component as a function of simulation time and a simulated input signal level of a simulated input signal. As such, the charge degradation effect(s) are simulated externally with respect to the in silico active semiconductor component. In this manner, the in silico active semiconductor component does not need to be reprogrammed in order to simulate charge degradation effects. | 06-12-2014 |
| 20140173542 | METHOD FOR AUTOMATIC DESIGN OF AN ELECTRONIC CIRCUIT, CORRESPONDING SYSTEM, AND COMPUTER PROGRAM PRODUCT - A method for automatic design of an electronic circuit, includes: generating ( | 06-19-2014 |
| 20140181770 | PRINTED SUBSTRATE DESIGN SYSTEM, AND PRINTED SUBSTRATE DESIGN METHOD - A printed substrate design system designs a substrate configuration of a printed substrate on which an IC and a passive component are mounted, and a cable is connected to the printed substrate. The printed substrate design system includes: an input unit that receives input of printed substrate design information; an EMI characteristic derivation unit that derives an EMI characteristic from the input printed substrate design information received by the input unit, the EMI characteristic being a characteristic of EMI occurring from the printed substrate; a determination criteria storage unit that stores an EMI allowable condition being a condition of an allowable EMI characteristic of the printed substrate; an EMI condition determination unit that compares the EMI characteristic derived by the EMI characteristic derivation unit with the EMI allowable condition stored in the determination criteria storage unit, the EMI condition determination unit determining whether the EMI characteristic of the printed substrate satisfies the EMI allowable condition; a substrate configuration change unit that changes an internal configuration of the printed substrate in a case where the EMI condition determination unit has determined that the EMI allowable condition is not satisfied, the substrate configuration change unit setting design information of the printed substrate with the re-changed structure to design information for deriving the EMI characteristic in the EMI characteristic derivation unit; and an output unit that outputs a printed substrate configuration that satisfies the EMI allowable condition in a case where the EMI condition determination unit has determined the EMI allowable condition is satisfied. | 06-26-2014 |
| 20140189626 | CIRCUIT WIDTH THINNING DEFECT PREVENTION DEVICE AND METHOD OF PREVENTING CIRCUIT WIDTH THINNING DEFECT - The present invention relates to a circuit width thinning defect prevention device and a method of preventing a circuit width thinning defect, and can prevent a circuit width thinning defect, that is, a reduction in circuit width due to excessive etching on a specific portion by including a storage means for storing dam design information classified according to the type of a weak portion; an analysis means for analyzing first design information to deduce the type and position of the weak portion; a matching means for extracting the dam design information corresponding to the type of the weak portion from the dam design information stored in the storage means; and a change means for changing the first design information to add a dam according to the dam design information extracted by the matching means to the position of the weak portion deduced by the analysis means. | 07-03-2014 |
| 20140208280 | MODELING MECHANICAL BEHAVIOR WITH LAYOUT-DEPENDENT MATERIAL PROPERTIES - Computer-implemented techniques for modeling the mechanical behavior of integrated circuits using layout-dependent material properties are disclosed. The back end of line wiring that connects an integrated circuit to a substrate undergoes stresses and strains due to many heating and cooling cycles during a chip's packaging and lifecycle. Depending on integrated circuit design style, there may be vastly different thermal profiles across the integrated circuit. The mechanical behavior caused by the thermal cycles of the wire, vias, and insulators comprising the BEOL materials is simulated. Extraction of the integrated circuit structural information, regarding the BEOL materials, yields anisotropic information. Layout-dependent material volume fractions are computed using integrated circuit structural information. Anisotropic mechanical properties are determined based on the structural information. Mechanical responses are calculated based on the anisotropic material properties and the calculated material-volume fractions. | 07-24-2014 |
| 20140208281 | REAL-TIME DISPLAY OF ELECTRONIC DEVICE DESIGN CHANGES BETWEEN SCHEMATIC AND/OR PHYSICAL REPRESENTATION AND SIMPLIFIED PHYSICAL REPRESENTATION OF DESIGN - A logical design component permits an electronic device design to be modified from a logical perspective on a schematic of the device showing device components in logical form, and displays a logical window of the schematic. A physical design component permits the design to be modified from a circuit board perspective on a circuit board representation of the device the showing the components in physical form, and displays a physical window of the circuit board representation. A real-time component permits the design to be modified from a simplified circuit board perspective on a simplified view of the circuit board representation, and displays a simplified window of the simplified view. Changes made to the design within the logical and/or physical window are automatically displayed within the simplified window in real-time; changes made to the design within the simplified window are automatically displayed within the logical and/or physical window in real-time. | 07-24-2014 |
| 20140208282 | CONFLICT DETECTION FOR SELF-ALIGNED MULTIPLE PATTERNING COMPLIANCE - Among other things, one or more techniques and systems for performing design layout are provided. An initial design layout is associated with an electrical component, such as a standard cell. A conflict graph is generated based upon the initial design layout. The conflict graph comprises one or more nodes, representing polygons within the initial design layout, connected by one or more edges. A same-process edge specifies that two nodes are to be generated by the same pattern process, while a different-process edge specified that two nodes are to be generated by different pattern processes, such as a mandrel pattern process and a passive fill pattern process. The conflict graph is evaluated to identify a conflict, such as a self-aligned multiple pattering (SAMP) conflict, associated with the initial design layout. The conflict is visually displayed so that the initial design layout can be modified to resolve the conflict. | 07-24-2014 |
| 20140215421 | SELF-ALIGNED MULTIPLE PATTERNING LAYOUT DESIGN - Among other things, one or more techniques and systems for performing design layout are provided. An initial design layout is associated with an electrical component, such as a standard cell. The initial design layout comprises a first pattern, such as a mandrel pattern, and a second pattern, such as a passive fill pattern. An initial cut pattern is generated for the initial design layout. Responsive to identifying a design rule violation associated with the initial cut pattern, the initial design layout is modified to generate a modified initial design layout. An updated cut pattern, not resulting in the design rule violation, is generated based upon the modified initial design layout. The updated cut pattern is applied to the modified initial design layout to generate a final design layout. The final design layout can be verified as self-aligned multiple patterning (SAMP) compliant. | 07-31-2014 |
| 20140215422 | METHOD AND APPARATUS FOR DERIVED LAYERS VISUALIZATION AND DEBUGGING - A computer-implemented method, system and computer program product for visualizing derived layer shapes of an integrated circuit design are disclosed. The computer-implemented method, system and computer program product include visualizing the derived layer shapes on a layout canvas; providing a step by step process for visualizing each derived layer shape as each derived layer shape is generated; and providing a hierarchy of intermediate derived layers based upon the step by step process. | 07-31-2014 |
| 20140237440 | METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR IMPLEMENTING ELECTRONIC CIRCUIT DESIGNS WITH SIMULATION AWARENESS - Disclosed are methods, systems, and articles of manufacture for implementing electronic designs with simulation awareness. A schematic is identified or created and simulated at the schematic level to characterize the functional behavior of the circuit or to ensure the circuit design meets the required design specifications. Physical data of a component of the design is identified, created, or updated, and the electrical parasitic associated with physical data is characterized. One or more electrical characteristics associated with the parasitic is further characterized and mapped to the simulator to re-simulate the circuit design to analyze the impact of parasitics. Some embodiments re-run the same simulation process incrementally in an interactive manner by accepting incremental design or parameter changes from the design environment. | 08-21-2014 |
| 20140245245 | STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING - Methods, layouts and chip design layouts that use annotations for communicating gate-length biasing amounts to post-layout tools are disclosed. One method includes receiving a chip design layout designed to includes select ones of a plurality of nominal cell layouts and an annotated cell layout. The chip design layout is defined by a plurality of layers and the plurality of nominal cell layouts define transistors, wherein each of the plurality of nominal cell layouts define nominal length transistors, and the annotated cell layout also defines transistors. The annotated cell layout is associated with an annotation layer that identifies a gate-length biasing to be applied to at least one transistor of the annotated cell layout. The gate-length biasing identifies an amount of change for a gate length and not width-sizing of a gate width of the at least one transistor of the annotated cell layout. The annotation layer is used to communicate design-specific directives that require implementation. The method uses a processor to process the chip design layout, with reference to the annotation layer, to apply the gate-length biasing to the annotated cell of the chip design layout. | 08-28-2014 |
| 20140258950 | DERIVING EFFECTIVE CORNERS FOR COMPLEX CORRELATIONS - Systems and methods are described for simultaneously deriving an effective x-sigma corner for multiple, different circuit and/or process metrics for a semiconductor device. The result is an effective sigma that is representative of design intent. Some implementations account for covariance, and use joint probability as the criteria for the effective x-sigma corner (e.g., as opposed to a unique sigma level of each individual metric). Analysis results for each metric can be transformed to metric distributions in a common distribution framework, and a correlation matrix can be calculated. The transformed metric distributions can be input to a joint probability distribution set to achieve a target joint sigma level. The joint probability distribution and correlation matrix values can be used to back-calculate scaled x-sigma corners for each metric distribution. Simulation of the device can be performed at one or more of the scaled x-sigma corners. | 09-11-2014 |
| 20140258951 | Prioritized Design for Manufacturing Virtualization with Design Rule Checking Filtering - An approach is provided to generate a number of virtualized circuit designs by applying design-for-manufacturing (DFM) processes to a circuit design. The virtualized circuit designs are checked using design rule checks (DRCs), with the checking resulting in a design rule error quantity that corresponds to each of the virtualized circuit designs. One of the virtualized circuit designs is selected for use in manufacturing the circuit design with the selection based each of the design's design rule error quantities. | 09-11-2014 |
| 20140258952 | Cell Having Shifted Boundary and Boundary-Shift Scheme - An embodiment cell shift scheme includes abutting a first transistor cell against a second transistor cell and shifting a place and route boundary away from a polysilicon disposed between the first transistor cell and the second transistor cell. In an embodiment, the cell shift scheme includes shifting the place and route boundary to prevent a mismatch between a layout versus schematic (LVS) netlist and a post-simulation netlist. | 09-11-2014 |
| 20140258953 | HIGH PERFORMANCE DESIGN RULE CHECKING TECHNIQUE - Roughly described, a design rule data set is developed offline from the design rules of a target fabrication process. A design rule checking method involves traversing the corners of shapes in a layout region, and for each corner, populating a layout topology database with values that depend on respective corner locations. After the layout topology database is populated, the values are compared to values in the design rule data set to detect any design rule violations. Violations can be reported in real time, while the user is manually editing the layout. Preferably corner traversal is performed using scan lines oriented perpendicularly to edge orientations, and scanning in the direction of the edge orientations. Scans stop only at corner positions and populate the layout topology database with what information can be gleaned based on the current scan line. The different scans need not reach each corner simultaneously. | 09-11-2014 |
| 20140282327 | CUTTER IN DIAGNOSIS (CID) A METHOD TO IMPROVE THE THROUGHPUT OF THE YIELD RAMP UP PROCESS - A method for producing candidate fault circuitry in an integrated circuit (IC) is disclosed. The method comprises tracing back from at least one failing output of the IC to determine a corresponding fan-in cone for each failing output using simulation values obtained from a fault free simulation of a design of the IC. Further, it comprises determining a first set of suspect fault candidates for each failing output, wherein each suspect fault candidate potentially corresponds to a defective element in the IC. Next, it comprises tracing forward from each suspect in the first set to determine a second set of suspects, which is a narrower subset of the first set. Finally, it comprises identifying a failing block from the IC design, wherein the failing block comprises suspect fault candidates from the second set and can be simulated independently of the full design. | 09-18-2014 |
| 20140282328 | DESIGN RULE CHECKS IN 3-D VIRTUAL FABRICATION ENVIRONMENT - A virtual fabrication environment that enables 3D Design Rule Checks (DRCs) or Optical Rule Checks (ORCs) on 3D structural models of semiconductor devices to be performed is discussed. The virtual fabrication environment may perform 3D design rule checks, such as minimum line width, minimum space between features, and minimum contact area between adjacent materials, directly in 3D without making assumptions about the translation from 2D design data to a 3D structure effected by an integrated process flow for semiconductor devices. The required number of 3D design rule checks may therefore be significantly reduced from the number of design rule checks required in 2D environments. Embodiments may also perform the 3D design rule checks for a range of statistical variations in process and design parameters. | 09-18-2014 |
| 20140282329 | AUTOMATED DESIGN RULE CHECKING (DRC) TEST CASE GENERATION - Approaches for generating test cases for design rule checking are provided. A method includes extracting coordinates of an error marker in an integrated circuit design. The method also includes creating an error polygon using the coordinates. The method additionally includes selecting polygons in the design that touch the error polygon. The method further includes identifying a rectangle that encloses the selected polygons. The method also includes generating a test case based on data of the design contained within the rectangle. The extracting, the creating, the selecting, the identifying, and the generating are performed using a computer device. | 09-18-2014 |
| 20140282330 | PRIORITY BASED LAYOUT VERSUS SCHEMATIC (LVS) - An approach for methodology, and an associated system, enabling a prioritizing of devices, circuits, and modules of interest is disclosed. Embodiments include: determining a first electrical layout indicating an electrical performance of a physical layout of an IC design, the first electrical layout indicating a plurality of devices of the physical layout; selecting a subset of the plurality of the devices based on one or more connections of the devices; and generating a second electrical layout indicating the electrical performance of the physical layout, the second electrical layout indicating the selected devices without at least one of the plurality of devices. | 09-18-2014 |
| 20140282331 | UNIVERSAL DESIGN LAYOUT COMPLIANCE - Among other things, one or more techniques and systems for generating a common design rule check (DRC) rule set for verification of a design layout and for generating a common dummy insertion utility for design layout processing are provided. That is, the common DRC rule set comprises a set of design rules having design rule constraint values corresponding to a restriction threshold, such as a most restrictive value. The common dummy insertion utility is used to insert dummy polygons into a design layout according to a dummy size constraint and a dummy spacing constraint. The design layout is verified as compliant with the common DRC rule set. Once verified, the design layout can be converted from a universal design layout format to a target metal scheme to create a transformed design layout. In this way, design layouts, formatted according to the universal design layout, can be transformed to other formats. | 09-18-2014 |
| 20140282332 | FAULT INJECTION OF FINFET DEVICES - Defect-describing (or “cut”) layer(s) for describing defects associated with different sides of a 3-dimensional (3D) structure enable fault modeling to determine the effect of position and location of defects on transistor performance. One or more defect-describing layers are used to identify the coordinates and sides of the 3D structures of the defects. The defect-describing layer(s) enables fault-modeling for 3D structures to understand the effects of faults on different locations, especially for defects associated with the fins of the finFET devices. Faults are injected to different locations and sides of fins and are modeled with different test vectors, test parameters and testing devices to identify detectable faults. The fault modeling would help identify the sources of defects and also improve layout design of finFET device structures. | 09-18-2014 |
| 20140282333 | DESIGN SUPPORT APPARATUS AND DESIGN SUPPORT METHOD - A design support apparatus includes a detecting unit and a removing unit. The detecting unit detects a resistor whose terminals are open except one terminal and which has a resistance less than or equal to a threshold, from among resistors included in a circuit model representing a circuit. The removing unit removes the detected resistor from the circuit model. | 09-18-2014 |
| 20140282334 | Method and Apparatus for Extracting Systematic Defects - The present disclosure provides a method of systematic defect extraction. Primary and secondary areas are defined in a wafer layout. A plurality of defects is identified by a first wafer inspection for an outside-process-window wafer. Defects located in the secondary area are removed. Defects associated with non-critical semiconductor features are also removed via a grouping process. Sensitive regions are defined around defects associated with critical semiconductor features. A second inspection is then performed on the sensitive regions for an inside-process-window wafer, thereby identifying a plurality of potentially systematic defects. Thereafter, a Scanning Electron Microscopy (SEM) process is performed to determine whether the defects in the sensitive regions of the inside-process-window wafer are true systematic defects. | 09-18-2014 |
| 20140289688 | METHOD AND SYSTEM FOR TESTING DIRECT CURRENT TRANSMISSION LAYOUT OF PRINTED CIRCUIT BOARD - An system for testing direct current (DC) layout of a printed circuit board, the system includes a layout information obtaining module, a rule loading module, a test script building module, a script executing module, and a report generating module. The layout information obtaining module obtains layout information of the printed circuit board. The rule loading module load DC transmission rules. The test script building module builds a DC transmission test scrip of the printed circuit board according to one of the DC transmission rules. The script executing module executes the DC transmission test script to determine whether the layout information of the printed circuit board complies with the one of the DC transmission rules. The report generating module generates a DC transmission testing report depicting whether the layout information of the printed circuit board complies with the one of the DC transmission rules and displays the testing report. | 09-25-2014 |
| 20140310669 | PAD OVER INTERCONNECT PAD STRUCTURE DESIGN - A design rule checker that performs a maximum pattern density check in a first intermediary metallization layer that underlies a top metallization layer and a pad opening in an integrated circuit. The maximum pattern density check is performed at least under some circumstances if a modulus of the primary metallization material is less than a modulus of a surrounding dielectric material. The maximum pattern density check verifies that the pattern density within the underlying portion is below a maximum pattern density that depends on the thickness of the access pad. A maximum metal width check may also be performed in this portion. | 10-16-2014 |
| 20140310670 | FAILURE ANALYSIS AND INLINE DEFECT CHARACTERIZATION - Defect characterization and failure analysis are useful tools for analyzing and improving fabrication for semiconductor chips. By using a layout and a netlist in combination with images of semiconductors, defects can be identified and analyzed. Electrical simulation can be performed on the netlist, based on the presence of the defect that was detected. Layout geometries where the defect was detected can be binned, and a search can be performed of the remainder of the layout for similar groupings of layout geometries. Various representations of the semiconductor can be cross-mapped, including layout, schematic, and netlist. The presence of certain defects can be correlated to yield, to performance, and to other characteristics. | 10-16-2014 |
| 20140325464 | CONFLICT DETECTION FOR SELF-ALIGNED MULTIPLE PATTERNING COMPLIANCE - Among other things, one or more techniques and systems for performing design layout are provided. An initial design layout is associated with an electrical component, such as a standard cell. A conflict graph is generated based upon the initial design layout. The conflict graph comprises one or more nodes, representing polygons within the initial design layout, connected by one or more edges. A same-process edge specifies that two nodes are to be generated by the same pattern process, while a different-process edge specified that two nodes are to be generated by different pattern processes, such as a mandrel pattern process and a passive fill pattern process. The conflict graph is evaluated to identify a conflict, such as a self-aligned multiple pattering (SAMP) conflict, associated with the initial design layout. The conflict is visually displayed so that the initial design layout can be modified to resolve the conflict. | 10-30-2014 |
| 20140380258 | METHOD AND APPARATUS FOR PERFORMING INTEGRATED CIRCUIT LAYOUT VERIFICATION - A method of performing layout verification for an integrated circuit (IC) layout is described. The method comprises receiving layout information for the IC layout, identifying at least one IC component within the IC layout, extracting localised layout information for the at least one IC component from the received layout information, defining the localised layout information for the at least one IC component within at least one component instance parameter therefor, and performing at least one layout verification check for the at least one component based at least partly on the at least one component instance parameter. | 12-25-2014 |
| 20150012900 | Methods and Systems for Detecting Repeating Defects on Semiconductor Wafers Using Design Data - Systems and methods for detecting defects on a wafer are provided. One method includes determining locations of all instances of a weak geometry in a design for a wafer. The locations include random, aperiodic locations. The weak geometry includes one or more features that are more prone to defects than other features in the design. The method also includes scanning the wafer with a wafer inspection system to thereby generate output for the wafer with one or more detectors of the wafer inspection system. In addition, the method includes detecting detects in at least one instance of the weak geometry based on the output generated at two or more instances of the weak geometry in a single die on the wafer. | 01-08-2015 |
| 20150020041 | METHOD AND SYSTEM FOR ENHANCED INTEGRATED CIRCUIT LAYOUT - An integrated circuit (IC) design method includes providing a design layout of the IC and placing a first cell and a second cell into the design layout. The second cell is a minor of the first cell. The method further includes dividing the first cell into a first plurality of segments and dividing the second cell into a second plurality of segments. A third cell is formed by connecting a first portion of the first plurality of segments with a first portion of the second plurality of segments. A fourth cell is formed by connecting a second portion of the first plurality of segments with a second portion of the second plurality of segments. The first, second, third and fourth cells each have substantially the same function. | 01-15-2015 |
| 20150026655 | DETERMINING A SET OF TIMING PATHS FOR CREATING A CIRCUIT ABSTRACTION - Systems and techniques for determining a set of timing paths for creating a circuit abstraction are described. During operation, an embodiment can receive a set of circuit elements in the circuit design that are candidates for optimization. Next, the embodiment can determine a set of timing paths by identifying critical timing paths in the circuit design whose delay is affected by a change in an input capacitance of a circuit element in the set of circuit elements. The embodiment can then identify a set of side loads based on the set of timing paths, and can create the circuit abstraction by retaining circuit elements and nets on each timing path in the set of timing paths, and retaining an identifier for each side load in the set of side loads. The circuit abstraction can then be used to update timing information during optimization of the circuit element. | 01-22-2015 |
| 20150040088 | HYBRID DESIGN RULE FOR DOUBLE PATTERNING - Among other things, one or more systems and techniques for generating or implementing a hybrid design rule set are provide herein. A set of color design rules and a set of color agnostic design rules are generated and exposed for selective design rule assignment. In an embodiment, a first color design rule is assigned to a first polygon. In an embodiment, a first color agnostic design rule is assigned to a second polygon. In this way, color design rules and color agnostic design rules are selectively applied to polygons of a design layout. Color design rules are selected for space and design efficiency. Color agnostic rules are selected for conservative design layout for design ease. A design rule checking stage and a design rule fixing stage are performed such that the design layout is compliant after color decomposition without a second design rule fixing stage. | 02-05-2015 |
| 20150067627 | RAPID EXPRESSION COVERAGE - This application discloses simulating a circuit design with a test bench and determining an expression coverage in the circuit design by the test bench with a rapid expression coverage process. The rapid expression coverage process can include dividing an expression in the circuit design into multiple sub-expressions, and separately evaluating each of the multiple sub-expressions during simulation of the circuit design to detect whether first operands in the corresponding sub-expressions receive each available input state, while second operands in the corresponding sub-expressions are in a non-masking state. The rapid expression coverage can generate an expression coverage metric to indicate whether expressions in the circuit design were covered by the test bench during the simulation of the circuit, for example, without having to generate truth-tables that include each possible input vector for each expression. | 03-05-2015 |
| 20150067628 | Layout Content Analysis For Source Mask Optimization Acceleration - The invention provides for the acceleration of a source mask optimization process. In some implementations, a layout design is analyzed by a pattern matching process, wherein sections of the layout design having similar patterns are identified and consolidated into pattern groups. Subsequently, sections of the layout design corresponding to the pattern groups may be analyzed to determine their compatibility with the optical lithographic process, and the compatibility of these sections may be classified based upon a “cost function.” With further implementations, the analyzed sections may be classified as printable or difficult to print, depending upon the particular lithographic system. The compatibility of various sections of a layout design may then be utilized to optimize the layout design during a lithographic friendly design process. For example, during the design phase, sections categorized as difficult to print may be flagged for further optimization, processing, or redesign. In further implementations, the difficult-to-print sections may be subjected to a source mask optimization process. Subsequently, the entire layout design may receive a conventional resolution enhancement treatment using the optimized source. | 03-05-2015 |
| 20150074629 | PARASITIC COMPONENT LIBRARY AND METHOD FOR EFFICIENT CIRCUIT DESIGN AND SIMULATION USING THE SAME - A method for circuit design includes a parasitic aware library embedded with one or more parameterized cells. The parasitic aware library is used to insert nets representing some but not all parasitic effects of a circuit into a circuit schematic enabling a single circuit schematic to be used for simulation of the circuit, parasitic verification of the circuit and LVS (Layout Versus Schematic) check. Only the single circuit schematic is required for the circuit design process and to form a mask set. Critical paths of the single circuit schematic are identified and parasitic effects are extracted and inserted into the schematic, enabling a pre-estimation of parasitic verification to be carried out and the LVS check to be carried out using a circuit schematic with some parasitic effects prior to the post-layout simulation in which all parasitic components of the layout are included. | 03-12-2015 |
| 20150089464 | SYSTEM AND METHOD FOR GENERATING A FIELD EFFECT TRANSISTOR CORNER MODEL - Disclosed are a system, method and computer program product for generating a field effect transistor (FET) corner model for a performance target (e.g., delay) that accurately preserves partial correlations among involved statistical model parameters (e.g., channel lengths, threshold voltages, overlap capacitance, etc.) of different types of field effect transistors within an integrated circuit. To accomplish this, an initial simulation run is performed to determine a nominal performance value with all statistical model parameters set at their nominal values. Then, multiple additional simulation runs are performed to determine corner performance values. In each successive additional simulation run, statistical model parameters of the different types of field effect transistors are offset from their nominal model parameters values in correlated ways. Then, based on performance differences between each of the corner performance values and the nominal performance value, a standard deviation for the performance target is determined. | 03-26-2015 |
| 20150089465 | SEPARATION AND MINIMUM WIRE LENGTH CONSTRAINED MAZE ROUTING METHOD AND SYSTEM - A computer implemented method for routing a first path in a circuit design is presented. The method includes iteratively building a multitude of partial-paths to route the first path by adding an incremental length to a selected previously built partial-path when the computer is invoked to route the first path in the circuit design, the adding being performed in accordance with at least a first design rule. The multitude of partial-paths start at a first location. The method further includes comparing each of the multitude of partial-paths to each other when the multitude of partial-paths end on a common second location different from the first location, and saving one of the multitude of partial-paths that leads to a shortest first path. The method further includes eliminating one of the multitude of partial-paths that are not selected to lead to the shortest first path. | 03-26-2015 |
| 20150095865 | Legalizing a Multi-patterning Integrated Circuit Layout - In a method for legalizing a multi-patterning integrated circuit layout including a plurality of islands, a set of multi-patterning constraints is generated on the basis of multi-patterning conflicts identified between the plurality of islands. Based on general design rule constraints and the multi-patterning constraints a combined set of layout constraints is generated. Feasibility of the set of layout constraints is checked, which then is provided to a Linear Program solver for generating an output circuit layout. | 04-02-2015 |
| 20150113489 | DRC FORMAT FOR STACKED CMOS DESIGN - The present disclosure relates a method of performing a design rule checking (DRC) procedure on a multi-tiered integrated chip. In some embodiments, the method is performed by defining layer databases for a plurality of tiers within a multi-tiered integrated chip. The layer databases respectively identify design layers within an associated tier. A DRC (design rule checking) deck is then generated, which defines one or more individual design layer definitions as a function of a plurality of layer databases, so that the one or more individual design layer definitions are defined for a plurality of tiers. One or more design rules for the one or more individual design layer definitions are defined within the DRC deck. Since the individual design layer definitions are defined as functions of the plurality of layer databases, the design rules apply to the plurality of tiers. | 04-23-2015 |
| 20150113490 | CONGESTION ESTIMATION TECHNIQUES AT PRE-SYNTHESIS STAGE - An apparatus includes a memory device that includes instructions for analyzing RTL code to determine congestion of a logic design without completing a synthesis phase of a chip design process. The instructions can include receiving RTL code, and identifying a statement in the RTL code. The instructions can include determining that the statement in the RTL code corresponds to a structured device group in a component library, wherein the structured device group includes logic devices configured to occupy an area in a predefined spatial arrangement and with predetermined connectivity between the logic devices. The instructions can include determining congestion associated with the structured device group by performing operations including determining a congestion figure. The instructions can also include providing, based on the congestion figure, an indication of the congestion associated with the structured device group. | 04-23-2015 |
| 20150113491 | COMPUTER-BASED MODELING OF INTEGRATED CIRCUIT CONGESTION AND WIRE DISTRIBUTION FOR PRODUCTS AND SERVICES - A computer-based system and method for modeling integrated circuit congestion and wire distribution determines a boundary where a tile congestion corresponding to a first layer group is equivalent to a first blockage ratio corresponding to a second layer group, formulates a piece-wise linear formula that relates the tile congestion to a number of wires of a two-dimensional tile, and distributes a portion of the number of wires to a layer of the tile based on the tile congestion. | 04-23-2015 |
| 20150143313 | Grouping Layout Features For Directed Self Assembly - Aspects of the invention relate to techniques of grouping layout features for directed self-assembly (DSA). Via-type features in a layout design are separated into via-type feature groups and isolated via-type features. The derived via-type feature groups are analyzed to determine whether the via-type feature groups are DSA-compliant. The layout design may be modified if one or more via-type feature groups in the via-type feature groups are non-DSA-compliant. | 05-21-2015 |
| 20150143314 | METHOD OF DESIGNING FIN FIELD EFFECT TRANSISTOR (FINFET)-BASED CIRCUIT AND SYSTEM FOR IMPLEMENTING THE SAME - A method of designing a fin field effect transistor (FinFET)-based circuit includes designing, using a processor, a first circuit schematic design based on a performance specification, the first circuit schematic design is free of artificial elements, wherein the artificial elements are used to simulate electrical performance of the FinFET-based circuit. The method further includes modifying, using the processor, at least one device within the first circuit schematic design to form a second circuit schematic design taking the artificial elements into consideration. The method further includes performing a pre-layout simulation using the second circuit schematic and taking the artificial elements into consideration. The method further includes generating a layout, wherein the layout does not take the artificial elements into consideration, and performing a post-layout simulation, wherein the post-layout simulation does not take the artificial elements into consideration | 05-21-2015 |
| 20150143315 | FAULT INJECTION OF FINFET DEVICES - A device layout tool includes a gate electrode layer, wherein the gate electrode layer is configured to define a three dimensional gate structure over a fin structure, wherein the fin structure has three exposed surfaces. The device layout tool further includes a defect-describing layer, wherein the defect-describing layer is configured to define locations of gate defects relative to the three exposed surfaces of the fin structure. | 05-21-2015 |
| 20150294061 | Graphical Design Verification Environment Generator - A graphical tool creates design-verification environments. The tool includes a graphical environment builder that allows for the drag and drop addition of verification IP (“VIP”) modules to a graphical verification environment. The tool assigns connector signals associated with source code that simulates a connection between a VIP module and the device under test (“DUT”). The tool learns which connection signals are suitable to connect a VIP to the DUT and facilitates selecting of the suitable signals in the environment development process. The tool converts the graphical environment to source code that can be executed to simulate testing on the DUT. The tool also allows a user to navigate between view modes that display the verification environment graphically, and that display the source code associated with components of the verification environment. | 10-15-2015 |
| 20150302134 | Design Rule Checking - There is provided a computer-implemented method for verification of a layout of an integrated circuit according to a design intent with a selected manufacturing process. The method comprises defining corner points of a first circuit part | 10-22-2015 |
| 20150302135 | METHOD FOR DESIGNING AND MANUFACTURING AN INTEGRATED CIRCUIT, SYSTEM FOR CARRYING OUT THE METHOD, AND SYSTEM FOR VERIFYING AN INTEGRATED CIRCUIT - A method of manufacturing an integrated circuit, a system for carrying out the method, and a system for verifying an integrated circuit may use a standard cell layout including a first layout region that may violate design rules. The method for designing an integrated circuit may comprise receiving a data file that includes a scaling enhanced circuit layout, and designing a first standard cell layout using design rules and the data file. The designing the first standard cell layout may include designing a first layout region of the first standard cell layout using the data file, and designing a second region of the first standard cell layout using the design rules. | 10-22-2015 |
| 20150310159 | COMPUTER-IMPLEMENTED VERIFICATION SYSTEM FOR PERFORMING A FUNCTIONAL VERIFICATION OF AN INTEGRATED CIRCUIT - A computer-implemented verification system for performing a system level or a system on chip level functional verification of integrated circuit is provided. The computer-implemented system includes one or more processors and a memory storing instructions defined by one or more modules of including a scenario compiler, a verification component and a software library component. The scenario compiler receives a set of verification scenario intents including at least one of test-application intents, constraints, device-programming intents and scenario-control intents. The scenario compiler generates one or more open verification methodology (OVM) and/or universal verification methodology (UVM) compliant test bench sequences and one or more scenario software implementations based on the set of verification scenario intents. The verification component interacts with the integrated circuit using the OVM and/or UVM compliant test bench sequences. The software library component enables execution of the scenario software implementations on a processing unit core of the integrated circuit. | 10-29-2015 |
| 20150317425 | METHOD AND APPARATUS FOR DUMMY CELL PLACEMENT MANAGEMENT - A method for manipulating a circuit design includes receiving multiple dummy cell modification parameters, selecting, by a computer processor and based on the dummy cell modification parameters, a dummy cell insertion region on a circuit design, and generating, in the dummy cell insertion region, multiple dummy cells. The method further includes selecting a first dummy cell from the dummy cells, determining, by the computer processor and based on a location of the first dummy cell, an illegal overlap with the first dummy cell, and removing, by the computer processor and from the dummy cells, the first dummy cell. The method further includes inserting, by the computer processor, on the circuit design, and after removing the first dummy cell, the dummy cells to obtain a modified circuit design, and presenting the modified circuit design. | 11-05-2015 |
| 20150317427 | INTEGRATED CIRCUIT DESIGN SYSTEM AND METHOD OF USING THE SAME - A system for designing an integrated circuit includes at least one processor and at least one memory including computer program code for one or more programs. The at least one memory and the computer program code are configured to, with the at least one processor, cause the system to receive a proposed device array layout from a device array design module. The device array design module is configured to generate the proposed device array layout free from a set of system design rule constraints. The system is also caused to revise a schematic of the integrated circuit including the proposed device array layout. The system is further caused to determine whether the revised schematic violates one or more system design rule constraints. | 11-05-2015 |
| 20150324510 | GENERIC DESIGN RULE CHECKING (DRC) TEST CASE EXTRACTION - A computer-aided testing is provided for design verification of integrated circuits. More specifically, a method of generating a test case in design rule checking is provided for that includes extracting coordinates of an error marker for a first error identified in an integrated circuit design. The method further includes identifying a first rectangle that encloses the error marker. The method further includes generating a first test case based on data of the integrated circuit design contained within the rectangle. The method further includes determining whether the first test case is representative of the first error. The method further includes in response to determining the first test case is not representative of the first error, identifying a second rectangle that is between the first rectangle and a third rectangle. The method further includes generating a second test case based on data of the integrated circuit design contained within the second rectangle. | 11-12-2015 |
| 20150339430 | VIRTUAL HIERARCHICAL LAYER USAGE - Layout simulation and verification of a semiconductor chip can require extensive design rule checking (DRC) and design rules for manufacturing (DRM) analysis of the design in order to ensure proper operation. DRC and DRM can be expensive in terms of computational time and resource usage. To mitigate some of the cost, a virtual layer can be constructed for a cell instance identified in the semiconductor design. Shapes including rectangles and polygons can be determined which traverse the cell instance and are from other hierarchical layers of the design. The shapes can be combined to generate a virtual layer used for simulation, validation, DRC, DRM, etc. The virtual layer can be augmented with traversing shape information from other instances of the cell. The rectangles, polygons, and complex polygons can be combined to simplify the virtual layer. Multiple virtual layers can be generated for the simulation and validation processes. | 11-26-2015 |
| 20150339431 | VIRTUAL HIERARCHICAL LAYER PATTERNING - Identifying the interactions of a selected cell across a hierarchical diagram of an integrated circuit and mapping the ways in which the cell can interact with other structures in the hierarchy reduces the computational load for design rule checking (DRC) and design rules for manufacturing (DRM). To this end, a cell and multiple instances of the cell are identified within hierarchical design levels of the chip. The interactions between the cell and other cells within the hierarchy are subtracted from the cell boundary, and the results of the subtracting are merged in the cell boundary. By subtracting the results of the merging, identical interactions are identified across the multiple instances of the cell. The results of the subtracting are used to generate a virtual hierarchical layer identical (VHLi) which aids in the simulation and verification of the chip. | 11-26-2015 |
| 20150339434 | VIRTUAL HIERARCHICAL LAYER PROPAGATION - Simulation and verification are critical to analyzing a semiconductor design using design rule checking (DRC) to verify design rules for manufacturing (DRM). The efficient use of computational resources including runtimes and resource requirements is a key component of the analysis. A virtual hierarchical layer (VHL) with shapes is generated for the design analysis of a design, including cells and hierarchical design levels. A cell and multiple instances of the cell are identified in the design. A VHL based on polygons overlapping the cell is generated in response to an algorithmic operation. The VHL shapes are propagated to subsequent algorithmic operations. The algorithmic operations update the VHL shapes. Shapes are filtered out of the VHL shapes as part of the updating. The VHL shapes are propagated through a chain of operations. | 11-26-2015 |
| 20150339435 | METHOD FOR FINDING NON-ESSENTIAL FLIP FLOPS IN A VLSI DESIGN THAT DO NOT REQUIRE RETENTION IN STANDBY MODE - The invention relates to a method for reducing the number of flip-flops in a VLSI design that require data retention, thereby eliminating the respective backup cells for those flip flops, the method comprises the steps of: (a) defining one or more criteria for non-essentiality of backup cells! (b) during the physical design stage, analyzing the VLSI design based on said one or more criteria for non-essentiality, and finding those flip-flops that meet these criteria, wherein said analysis is performed at the gate level, independent from any higher level representation of the design; and (c) eliminating from the VLSI design those backup cells for all non-essential flip-flops that meet one or more of said criteria for non-essentiality, thereby leaving in the design only those backup cells for those flip-flops that do not meet any of said criteria. | 11-26-2015 |
| 20150347664 | SYSTEM FOR AND METHOD OF SEMICONDUCTOR FAULT DETECTION - A method of detecting one or more faults in a semiconductor device that includes generating a first test pattern set from a primary node list and a fault list. The primary node list includes one or more nodes and the fault list identifies one or more faults. The method also includes generating one or more secondary node lists from the primary node list and generating a second test pattern set from at least the first test pattern set and the secondary node list. Each node of the one or more nodes of the primary node list is associated with a corresponding secondary node list of the one or more secondary node lists. | 12-03-2015 |
| 20150347667 | METHOD OF CHECKING THE LAYOUT INTEGRITY - Checking the layout integrity includes the steps of receiving inputs defining a plurality of devices for a layout, generating a signature for each device in the layout, when created, from one or more parameters of the device, storing the generated signatures with the layout, receiving the stored layout and signatures, regenerating each signature for each device in the stored layout, and comparing each regenerated signature with the corresponding stored signature. | 12-03-2015 |
| 20150363537 | Extracting Comprehensive Design Guidance for In-Line Process Control Tools and Methods - Methods and systems for extracting comprehensive design guidance for in-line process control of wafers are provided. One method includes automatically identifying potential marginalities in a design for a device to be formed on a wafer. The method also includes automatically generating information for the potential marginalities. The automatically generated information is used to set up process control for the wafer. | 12-17-2015 |
| 20150370957 | LAYOUT DESIGN METHOD AND SYSTEM - A layout design method is disclosed. The layout design method includes: (a) providing an original layout file; (b) performing a redundant via (RV) filling on the original layout file so as to generate a second layout file; (c) merging the second layout file with the original layout file to generate a third layout file; (d) performing a design rule check (DRC) verification on the third layout file by directly invoking a DRC code in a Process Design Kit (PDK); (e) generating, based on a result of the DRC verification, a fourth layout file including DRC errors; (f) performing a layout operation to remove DRC errors from the second layout file using the fourth layout file, so as to generate a fifth layout file; and (g) merging the fifth layout file with the original layout file to generate a sixth layout file. | 12-24-2015 |
| 20150379179 | FAST AND ACCURATE CAPACITANCE CHECKER - Switching cells and decoupling capacitors in an integrated circuit design may be assessed to ensure voltage stability during high-speed switching events. Assessment of the switching cells and decoupling capacitors may include identifying the locations of the switching cells and the decoupling capacitors and dividing the integrated circuit design into a number of equally sized bins. Selected bins for each switching cell may be identified. The selected bin for each switching cell may be assessed, along with one or more bins neighboring the selected bin, to determine if a sufficient number of decoupling capacitors are available in these bins to provide voltage stability for each switching cell in the integrated circuit design. | 12-31-2015 |
| 20160004808 | SYSTEM AND METHOD FOR TRACING A NET - A system and method for tracing a net includes comparing an IC design against a marked portion of the IC design, and extracting a traced net that includes the marked portion from the IC design file. The method also includes displaying the traced net and storing at least one indicator along with information identifying the traced net. | 01-07-2016 |
| 20160012174 | METHODS OF DETECTING STRESSES, METHODS OF TRAINING COMPACT MODELS, METHODS OF RELAXING STRESSES, AND COMPUTING SYSTEMS | 01-14-2016 |
| 20160012176 | METHODS FOR DESIGNING PHOTONIC DEVICES | 01-14-2016 |
| 20160012177 | EQUIVALENCE CHECKING BETWEEN TWO OR MORE CIRCUIT DESIGNS THAT INCLUDE SQUARE ROOT CIRCUITS | 01-14-2016 |
| 20160055283 | STANDARD CELL LIBRARY, METHOD OF USING THE SAME, AND METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT - A method of designing a semiconductor integrated circuit (IC) is provided as follows. A standard cell library is generated. The standard cell library includes characteristic information for a plurality of standard cells. The characteristic information includes a characteristic of each standard cell. A characteristic change region is detected. The characteristic change region includes at least one of the plurality of standard cells by comparing characteristics of standard cells to be placed adjacent to the characteristic change region, based on the standard cell library. A characteristic of the at least one standard cell included in the detected characteristic change region is changed to one of the characteristics of the standard cells to be placed adjacent to the characteristic change region to update the standard cell library. A plurality of standard cells of the updated standard cell library is placed. | 02-25-2016 |
| 20160055289 | Verification Of Photonic Integrated Circuits - Techniques and mechanisms for the use of layout-versus-schematic (LVS) design tools to validate photonic integrated circuit designs. Various implementations employ alternate analysis techniques with LVS analysis tools to perform one or more LVS analysis processes on photonic integrated circuits. These analysis processes may include curvilinear design validation and the associated flow implementations. | 02-25-2016 |
| 20160070841 | METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR IMPLEMENTING HIGH CURRENT CARRYING INTERCONNECTS IN ELECTRONIC DESIGNS - Various embodiments implement additional connectivity for electronic designs by identifying one or more regions for a route in normal connectivity of an electronic design, identifying a plurality of seeding segments from the route based at least in part upon the one or more regions, identifying a plurality of additional nodes in the plurality of seeding segments, and generating one or more additional routes connecting the plurality of additional nodes in the plurality of seeding segments. The one or more additional routes are generated without disturbing the normal connectivity including a plurality of Steiner points and the route. Additional nodes differ from Steiner points and are used to implement additional routes that belong to a different route type. | 03-10-2016 |
| 20160092627 | METHOD FOR ORGANIZING, CONTROLLING, AND REPORTING ON DESIGN MISMATCH INFORMATION IN IC PHYSICAL DESIGN DATA - Systems and methods allow an IC design process to continue in the face of errors while those errors are being investigated and fixed in the actual design data. Potential mismatches can be categorized and a user can choose which action (if any) to take when a specific mismatch is discovered. A set of potential mismatches and their action settings can be aggregated into a higher level setting that the end user of the system can choose during different stages of a design project. A record of the mismatches that have been encountered, the design elements that are involved in each mismatch, and what action where taken to repair the mismatch is kept and maintained. | 03-31-2016 |
| 20160103942 | SYSTEM FOR AND METHOD OF DESIGNING AN INTEGRATED CIRCUIT - A method of designing an integrated circuit, that includes receiving a first list corresponding to at least one circuit component in a layout, generating a condensed layout from the layout and performing an electrostatic discharge (ESD) check of the condensed layout. The condensed layout is generated by a processor. The ESD check is configured to verify compliance with one or more ESD design rules. The condensed layout includes at least one circuit component. The at least one circuit component includes an ESD circuit and an associated ESD current path. | 04-14-2016 |
| 20160117435 | TIMING MATCHING METHOD OF TIMING ANALYZER AND METHOD OF DESIGNING INTEGRATED CIRCUIT USING THE SAME - A timing-matching method, executed by a timing analyzer, that includes computing a slew or load of a cell, determining whether the slew or load exists in an extrapolation region of a standard cell look-up table, and swapping the cell with a virtual standard cell of a virtual standard cell look-up table when the slew or load exists in the extrapolation region. | 04-28-2016 |
| 20160117437 | Electrostatic Damage Protection Circuitry Verification - Techniques for efficiently determining whether an interconnect line has an impedance component value below a maximum specified value. A specified maximum impedance component value is used to limit the number of interconnect lines that are analyzed by a parasitic extraction analysis process. An analysis window is created based upon the characteristics of the interconnect lines and the specified maximum impedance component value. The size of the window corresponds to the minimum length of the interconnect line that would have the specified maximum impedance component value. Once the analysis window has been created, the interconnect lines are examined to determine if any of them reaches to or beyond the analysis window, whereby interconnect lines that exceed the specified maximum impedance component value can be identified. If there are any remaining interconnect lines that have not been determined to exceed the specified maximum impedance component value through the use of the analysis window, then the impedance component values of these remaining interconnect lines can be specifically determined using a parasitic extraction process. | 04-28-2016 |
| 20160171143 | CIRCUIT DESIGN LAYOUT IN MULTIPLE SYNCHRONOUS REPRESENTATIONS | 06-16-2016 |
| 20160171144 | THREE-DIMENSIONAL COMPOSITE SOLID COMPONENT MODELING | 06-16-2016 |
| 20160180006 | CYCLE ACCURATE STATE ANALYSIS WITH PROGRAMMABLE TRIGGER LOGIC | 06-23-2016 |
| 20160180010 | Transistor Plasma Charging Evaluator | 06-23-2016 |
| 20160180011 | Transistor Plasma Charging Metal Design Rule Generator | 06-23-2016 |
| 20160188783 | COMPUTER-AIDED CARD DESIGN VALIDATION - A method for computer-aided validation of a card design is disclosed, the method comprising the steps of detecting a plurality of design elements related to a card design via an image recognition device and encoding the design elements into data elements; comparing the data elements against design requirement encoded as design requirement data; validating the card design by determining if each of the data elements are compliant with the design requirement; wherein the comparison of the data elements and the validation of the card design is performed at a processor; and providing a result of the validation via a user interface. | 06-30-2016 |
| 20160203253 | MODULARIZED STACKED IC PHYSICAL DESIGN FRAMEWORK | 07-14-2016 |
| 20180025106 | VOID AVOIDANCE VERIFICATIONS FOR ELECTRONIC CIRCUIT DESIGNS | 01-25-2018 |
| 20180025107 | SYMMETRY VERIFICATIONS FOR DIFFERENTIAL SIGNAL VIAS OF AN ELECTRONIC CIRCUIT DESIGN | 01-25-2018 |
