| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 716105000 | With partitioning | 26 |
| 20110035711 | Method and System for Repartitioning a Hierarchical Circuit Design - The invention relates to a method and a system for repartitioning a formalized hardware description of a hierarchically structured electronic circuit design unit comprising a plurality of macros in terms of latch macros and combinatorial macros. In a first step, each macro is dissected into latch macros and signal cones in such a way that
| 02-10-2011 |
| 20110035712 | Method and System for Placement of Electronic Circuit Components in Integrated Circuit Design - The invention relates to a method and a system for placing macros of a multilevel hierarchical description of a design unit on a chip. The method starts off by repartitioning the macro structure of the design unit into a set of latch macros and a set of combinatorial macros. By definition, a combinatorial macro is constructed in such a way that it contains no latches, and a latch macro contains latches and is constructed in such a way that each primary input/output of the latch macro coincides with an input or an output of a latch within said latch macro. After repartitioning the macro structure, the latch macros are synthesized within temporary boundaries and placed on the chip. Subsequently, the combinatorial macros are sequentially placed within a temporary boundary and synthesized one by one. | 02-10-2011 |
| 20110231806 | METHOD FOR PARTITIONING ELECTRONIC UNITS - A method for partitioning electronic units and a system for implementing the method are provided. In the method, a plurality of function modules are distributed to the electronic units, for which purpose different inputs are input into an optimizer, which produces a set of comparable distributions. | 09-22-2011 |
| 20120089956 | Automated Bottom-Up and Top-Down Partitioned Design Synthesis - An embodiment of the present invention includes a partitioner, a synthesizer, and an optimizer. The partitioner partitions a design into a hierarchy of partitions having a top-level partition and lower partitions. The lower partitions include a bottom-level partition. The top-level partition has top-level constraints. The synthesizer synthesizes the lower partitions hierarchically from the bottom-level partition to create lower partition netlists based on the top-level constraints. The optimizer optimizes a top-level netlist corresponding to the top-level partition from the lower partition netlists to satisfy the top-level constraints. | 04-12-2012 |
| 20120192132 | METHOD FOR MANIPULATING AND REPARTITIONING A HIERARCHICAL INTEGRATED CIRCUIT DESIGN - A hardware description language representation of an original circuit block containing one or more hierarchies may be obtained. Some, or all of the hierarchies may be dissolved to access each circuit component within the original circuit block at a same level of hierarchy. Designated circuit components may then be grouped together to create new circuit blocks at a new level of hierarchy. Components and signals within each new circuit block may be renamed to match logically corresponding components and signals within each other new circuit block. Missing pins may be added for each new circuit block, and connected to respective associated signals within the new circuit block, and logically equivalent pins may be given the same name to ensure the new circuit blocks are logically equivalent to each other and have identical interfaces. One of the new circuit blocks may be selected for physical build to obtain one or more physical instances corresponding to the selected new circuit block, and a top-level build may link each new circuit block instance to one of those one or more physical instances. | 07-26-2012 |
| 20120233577 | Using Synthesis to Place Macros - In one embodiment, a design methodology is described in which a functional description of each macro may be synthesized along with the other logic in a block. The resulting circuitry, including synthesized circuitry corresponding to each macro, may be placed within an area designated for the integrated circuit. The result may be analyzed, determining a location for the macro based on the location of the corresponding synthesized circuitry. For example, the geometric center of the synthesized circuitry may be located, and the geometric center of the custom circuitry associated with the macro may be placed at the same point as the geometric center of the synthesized circuitry. Because the macros are not placed in advance, the location of the macro may be controlled by other factors such as timing, space, wiring congestion, etc. | 09-13-2012 |
| 20130239075 | METHOD AND SYSTEM FOR REPARTITIONING A HIERARCHICAL CIRCUIT DESIGN - The invention relates to a method and a system for repartitioning a formalized hardware description of a hierarchically structured electronic circuit design unit comprising a plurality of macros in terms of latch macros and combinatorial macros. In a first step, each macro is dissected into latch macros and signal cones in such a way that
| 09-12-2013 |
| 20130239076 | DESIGN METHOD, DESIGN APPARATUS, AND PROGRAM PRODUCT FOR INCREMENTAL DESIGN SPACE EXPLORATION - A design apparatus generates an optimal design condition by design space exploration. The apparatus including a source code parsing ( | 09-12-2013 |
| 20130268905 | Circuit Partitioning and Trace Assignment in Circuit Design - Methods and apparatuses for circuit design are described. In one embodiment, the method comprises determining a distribution of nets of a circuit, the distribution of the nets comprising numbers of blocks that each of the nets has in each of a plurality of partitions of the circuit in a partitioning solution, moving a first block of the circuit from a source partition to a destination partition to modify the partitioning solution, and updating the distribution of the nets after the moving. | 10-10-2013 |
| 20140007027 | Decision Modules | 01-02-2014 |
| 20140013289 | GENERATING A CONVERGENT CIRCUIT DESIGN FROM A FUNCTIONAL DESCRIPTION USING ENTITIES HAVING ACCESS TO THE FUNCTIONAL DESCRIPTION AND TO PHYSICAL DESIGN INFORMATION - A method of designing a circuit is described. In an embodiment, a physical design implementation for the circuit is created using a plurality of entities. These entities are named “genomes”. Each entity includes a portion of a functional description of the circuit that has been synthesized into a gate-level implementation. An entity is selected to facilitate the physical design implementation meeting a plurality of design constraints. Several steps (e.g., beginning with selection of an entity) of this method are repeated several times to meet the design constraints. As a consequence, the physical design implementation provides more accurate information for use in a final physical design implementation. Moreover, the physical design implementation can be created faster than prior techniques while still allowing a global view of the physical design implementation in meeting design constraints. | 01-09-2014 |
| 20140143744 | SYSTEMS AND METHODS FOR REDUCING LOGIC SWITCHING NOISE IN PARALLEL PIPELINED HARDWARE - A method of configuring a hardware design for a pipelined parallel stream processor includes obtaining a scheduled graph representing a processing operation in the time domain as a function of clock cycles. The graph includes a data path to be implemented in hardware as part of the stream processor, an input, an output, and parallel branches to enable data values to be streamed therethrough from the input to the output as a function of increasing clock cycle. The data path is partitioned into a plurality of discrete regions, each region operating on a different clock phase and having discrete control logic elements. Phase transition registers to align data separated by a boundary between regions having different clock phases are introduced into the data path at the boundary. The graph and control logic elements define a hardware design for the pipelined parallel stream processor. | 05-22-2014 |
| 20140157215 | SYSTEM AND METHOD OF EMULATING MULTIPLE CUSTOM PROTOTYPE BOARDS - An emulation system integrates multiple custom prototyping boards for emulating a circuit design. A first custom prototyping board including at least one FPGA and an interface connected to a first set of wires coupling to the at least one FPGA. A second custom prototyping board includes at least one second FPGA and an interface connected to a second set of wires coupling to the at least second FPGA. An adaptor board connects to the first custom prototyping board and the second custom prototyping board through the first interface and the second interface. The adapter board controls emulation of the circuit design and controls communication through the partitioned circuit using at least one of the first set of wires and at least one the second set of wires. | 06-05-2014 |
| 20140189622 | PARTITIONING DESIGNS TO FACILITATE CERTIFICATION - This disclosure relates generally to field-programmable gate arrays (FPGAs). Some implementations relate to methods and systems for partitioning FPGA circuit designs to facilitate certification. In one aspect, a method includes generating a hardware description language (HDL) implementation of a circuit design. The method additionally includes partitioning the design into a first portion and a second portion. In some implementations, the second portion corresponds to a safety-critical portion of the design while the first portion corresponds to a non-safety-critical portion. The method additionally includes generating first configuration settings for the first portion and generating second configuration settings for the second portion. The method additionally includes verifying, or providing to a third-party certification body for verification, the first configuration settings for the first portion and the second configuration settings for the second portion. The method further includes providing the configuration settings for the second portion for programming into a PLD. | 07-03-2014 |
| 20140245243 | COMPUTING DEVICE AND METHOD FOR GENERATING COMPONENT MODULE FILES OF CIRCUIT DIAGRAM - A circuit diagram includes a plurality of components. Each component corresponds to a module number and a component number. The components corresponding to a same module number are classified into a same function module. Each function module corresponds to a component module file. The component module file of each function module is generated according to the classified function modules. The component module file includes the module number of the function module and the component numbers of the components which are included in the function module. The component module files of the circuit diagram can be imported in a printed circuit board (PCB) drawing software. | 08-28-2014 |
| 20140325462 | PARTITIONING DESIGNS TO FACILITATE CERTIFICATION - This disclosure relates generally to field-programmable gate arrays (FPGAs). Some implementations relate to methods and systems for partitioning FPGA circuit designs to facilitate certification. In one aspect, a method includes generating a hardware description language (HDL) implementation of a circuit design. The method additionally includes partitioning the design into a first portion and a second portion. In some implementations, the second portion corresponds to a safety-critical portion of the design while the first portion corresponds to a non-safety-critical portion. The method additionally includes generating first configuration settings for the first portion and generating second configuration settings for the second portion. The method additionally includes verifying, or providing to a third-party certification body for verification, the first configuration settings for the first portion and the second configuration settings for the second portion. The method further includes providing the configuration settings for the second portion for programming into a PLD. | 10-30-2014 |
| 20150012898 | Automated Bottom-Up and Top-Down Partitioned Design Synthesis - An embodiment of the present invention includes a partitioner, a synthesizer, and an optimizer. The partitioner partitions a design into a hierarchy of partitions having a top-level partition and lower partitions. The lower partitions include a bottom-level partition. The top-level partition has top-level constraints. The synthesizer synthesizes the lower partitions hierarchically from the bottom-level partition to create lower partition netlists based on the top-level constraints. The optimizer optimizes a top-level netlist corresponding to the top-level partition from the lower partition netlists to satisfy the top-level constraints. | 01-08-2015 |
| 20150082261 | Method and Apparatus for Decomposing Functions in a Configurable IC - Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of multiplexers that each has a set of input terminals, a set of output terminals, and a set of select terminals. The set of multiplexers includes a group of multiplexers, where at least one input terminal of each multiplexer in the group is a permanently inverting input terminal. During at least a set of cycles during the operation of the configurable IC, several multiplexers in the group of multiplexers are used to implement a particular function. | 03-19-2015 |
| 20150089462 | CONCURRENT OPTIMIZATION OF TIMING, AREA, AND LEAKAGE POWER - Systems and techniques are described for performing circuit synthesis. Some embodiments create a lookup table based on information contained in a cell library. The lookup table is then used during circuit synthesis. Specifically, some embodiments optimize cells in a reverse-levelized cell ordering. For a given cell, a table lookup is performed to obtain a set of optimal cell configurations, and the cell is replaced with a cell configuration selected from the set of optimal cell configurations. Some embodiments concurrently optimize cells for timing, area, and power leakage based on the timing criticality of the cells. | 03-26-2015 |
| 20150135147 | Generating a Circuit Description for a Multi-die Field-programmable Gate Array - A method for generating a circuit description for a multi-die field-programmable gate array, FPGA, comprising a first FPGA die and at least one further FPGA die is described. The method is performed in an FPGA design tool and comprises automatically evaluating a first and a second partition of a partitioned circuit description, the partitions being associated with respective ones of the FPGA dies. At least one multiplexing element is inserted into the first partition and a corresponding de-multiplexing element is inserted into the second partition based on the automated evaluation. | 05-14-2015 |
| 20150135148 | DECISION MODULES - An abstract decision module primitive for placement within a logical representation (i.e., a netlist) of a circuit design is described. The decision module primitive receives as inputs alternative solutions for a given function or segment of a netlist. The alternative solutions include functionally equivalent, but structurally different implementations of the function or segment of the netlist. The decision module primitive alternatively selects between connecting one of the inputs to the netlist to provide a complete functional definition for the netlist based on constraint information. | 05-14-2015 |
| 20150149972 | METHOD, DESIGN APPARATUS, AND PROGRAM PRODUCT FOR INCREMENTAL DESIGN SPACE EXPLORATION - A design apparatus generates an optimal design condition by design space exploration. The apparatus including a source code parsing ( | 05-28-2015 |
| 20150347644 | DESIGNING APPARATUS AND DESIGNING METHOD - A designing apparatus generates a logic cone and calculates an area ratio between a first triangle and a second triangle. The first triangle has a logic cell as an angle in an m-th stage between input and output stages and input-side FFs as the other angles at both ends of the input stage, the FFs connected to input of the cell. The second triangle has an output-side FF as an angle in the output stage and logic cells as the other angles at both ends of the m-th stage, the cells connected to input of the FF in the output stage. The apparatus sets, when the ratio matches a predetermined ratio, a first logic cone block between the input and m-th stages and a second logic cone block between the output and m-th stages as logic synthesis units and performs logic synthesis by using the logic synthesis units. | 12-03-2015 |
| 20150356724 | INFORMATION PROCESSING APPARATUS, METHOD OF OUTPUTTING CIRCUIT IMAGE, AND STORAGE MEDIUM STORING CIRCUIT IMAGE OUTPUT PROGRAM - An information processing apparatus includes a processor and a memory configured to store therein correspondence information defining an association relationship between position of the connection point of circuits and information of wiring which has one end located at the position of the connection point. The processor is configured to identify a first circuit from a group of multiple images representing an overall circuit, acquire, based on the correspondence information, information of a first position of a connection point of a second circuit at which the identified first circuit is coupled and information of a first wiring which one end is located at the first position, extract, from the second image, a partial image that includes images of the first wiring and the connection point at the first position based on the acquired information of the first position and the first wiring, and output the extracted partial image. | 12-10-2015 |
| 20160048623 | Generating a Circuit Description for a Multi-Die Field-Programmable Gate Array - A method for generating a circuit description for a multi-die field-programmable gate array, FPGA, comprising a first FPGA die and at least one further FPGA die is described. The method is performed in an FPGA design tool and comprises automatically evaluating a first and a second partition of a partitioned circuit description, the partitions being associated with respective ones of the FPGA dies. At least one multiplexing element is inserted into the first partition and a corresponding de-multiplexing element is inserted into the second partition based on the automated evaluation. | 02-18-2016 |
| 20160188759 | INFORMATION PROCESSING APPARATUS, STATE MACHINE DIVIDING METHOD, AND COMPUTER-READABLE RECORDING MEDIUM - A non-transitory computer-readable recording medium stores a state machine dividing program that causes a computer to execute a process including: determining whether a design value based on circuit information that indicates a circuit that controls a computation process by using a state machine is greater than a predetermined reference value; and dividing, when the design value is greater than the reference value, the state machine into a plurality of state machines. | 06-30-2016 |
