| Entries |
| Document | Title | Date |
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| 20100281450 | METHOD AND SYSTEM FOR MAPPING A BOOLEAN LOGIC NETWORK TO A LIMITED SET OF APPLICATION-DOMAIN SPECIFIC LOGIC CELLS - A method and system is described for mapping a system-level description of an integrated system directly to a technology-specific set of logic cells that are comprised primarily of large complex cells (bricks). The invention is based on applying aggressive Boolean operations that would be of impractical runtime complexity for a large library, but are applicable for the targeted brick libraries which typically contain a small number of complex cells, along with a much smaller number of simple cells. This invention is modular such that it can be applied in the context of incremental netlist optimization as well as optimization during physical synthesis. | 11-04-2010 |
| 20100293518 | Nanoscale interconnection interface - One embodiment of the present invention provides a demultiplexer implemented as a nanowire crossbar or a hybrid nanowire/microscale-signal-line crossbar with resistor-like nanowire junctions. The demultiplexer of one embodiment provides demultiplexing of signals input on k microscale address lines to 2 | 11-18-2010 |
| 20100318945 | METHOD FOR N-VARIANT INTEGRATED CIRCUIT (IC) DESIGN, AND IC HAVING N-VARIANT CIRCUITS IMPLEMENTED THEREIN - Techniques are generally described for designing an integrated circuit (IC). In various embodiments, the techniques include designing, at a functional specification level, N-variants of a particular circuit. The various embodiments may then implement the designed N-variants as hardware in the IC. Additional variants and embodiments may also be disclosed. | 12-16-2010 |
| 20100318946 | VARIOUS METHODS AND APPARATUSES FOR ESTIMATING CHARACTERISTICS OF AN ELECTRONIC SYSTEMS DESIGN - Methods and apparatuses are described for an Intellectual Property (IP) Generator for estimating timing, area, and power characteristics of an electronic system design. The IP Generator receives a user-supplied file having data describing a configuration of an IP design having multiple levels of hierarchy. The IP Generator also receives user-supplied technology parameters and data-flow information. The IP generator correlates estimated timing, area, and power characteristics for each IP sub component based on the user supplied technology parameters, data-flow information and configuration parameters. The IP generator reports the timing, area, and power estimates to a user via a graphic user interface prior to a transformation of a Register Transfer Level (RTL) design into the gate-level circuit design. | 12-16-2010 |
| 20100318947 | METHOD FOR THE DEFINITION OF A LIBRARY OF APPLICATION-DOMAIN-SPECIFIC LOGIC CELLS - The present invention provides in one aspect a method of defining a logic cell library composed of complex functions and simple functions, with some of the complex functions obtained from identifying logic function patterns. In another aspect the present invention provides a method of designing a representation of an integrated circuit that uses complex functions and simple functions, with the complex functions including a plurality of non-standard complex Boolean logic functions that are determined to collectively provide for logic pattern minimization. | 12-16-2010 |
| 20100325593 | INTEGRATED CIRCUIT ANALYSIS SYSTEMS AND METHODS - The current invention uses structural data mining methods and systems, combined with partitioning hints and heuristics, to locate high level library functional blocks in a gate level netlist of an integrated circuit (IC). In one embodiment of the invention, the library is created by synthesizing various design blocks and constraints. The method supports characterization matching between a netlist and a library, between libraries and between netlists. The data mining method described herein uses a subgraph growing method to progressively characterize the graph representation of the netlist of the IC. In one embodiment of the invention, alternative hashing is used to perform subgraph characterization. Further, the located high level functional blocks may be used to substitute the corresponding portions of the target netlist having the matched characterizations, and may be annotated accordingly in the resulting netlist. | 12-23-2010 |
| 20110004857 | LOGIC DIFFERENCE SYNTHESIS - A computer executed method is disclosed which accepts an original circuit with an original logic, accepts a modified circuit, and synthesizes a difference circuit. The difference circuit represents changes that implement the modified circuit's logic for the original circuit. The synthesis may locate an output-side boundary in the original logic in such a manner that the original logic is free of logic changes inbetween the output-side boundary and the primary output elements of the original circuit. The disclosed synthesis may also locate an input-side boundary in the original logic in such a manner that the original logic is free of logic changes inbetween the input-side boundary and the primary input elements of the original circuit. A computer program products are also disclosed. The computer program product contains a computer useable medium having a computer readable program code embodied therein. The computer readable program code when executed on a computer causes the computer to carry out the methods of finding input and output side boundaries in an original logic, and synthesizing inbetween those boundaries a difference circuit representing logic changes. | 01-06-2011 |
| 20110010680 | Apparatus and Method of Delay Optimization - Aspect of the technology are a method of designing a circuit layout and corresponding computer systems and nontransitory computer media. The circuit layout is for use in forming a lithographic mask set for use in fabricating an integrated circuit. In the method the computer system divides a synthesized circuit design into cell partitions along critical paths of the synthesized circuit design. The computer system associates pins of the plurality of cell partitions with normalized pin timing values. The normalized pin timing values store magnitude differences between a reference timing slack and timing slacks of the plurality of pins. After optimizing the synthesized circuit design, the computer system repeats the method, and then the computer system determines whether to further optimize the plurality of cell partitions by comparing: (i) the pre-optimization normalized pin timing values of the plurality of cell partitions with (ii) the post-optimization normalized pin timing values of the plurality of cell partitions. | 01-13-2011 |
| 20110010681 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS CIRCUIT INSERTING METHOD - A semiconductor integrated circuit device is disclosed. The semiconductor integrated circuit device includes a first circuit whose output never or seldom changes when the output from an Enable generator is off, a second circuit whose output frequently changes, an input controller which receives the respective outputs from the second circuit and the Enable generator and passes through the input from the second circuit only when the output from the Enable generator is on, a combination circuit which receives the respective outputs from the first circuit and the input controller, and a memory which receives the output from the combination circuit and is driven by the output from the clock controller. | 01-13-2011 |
| 20110016439 | RESET MECHANISM CONVERSION - Methods, circuits, and systems for converting reset mechanisms in a synchronous circuit design into a corresponding asynchronous representation are described. These may operate to convert synchronous state holding blocks that include reset signals to corresponding asynchronous dataflow logic blocks. A replicated reset token at a fraction of the operational frequency of the reset signal may be distributed to the locations of the asynchronous dataflow logic blocks. Additional methods, circuits, and systems are disclosed. | 01-20-2011 |
| 20110022996 | METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING CONTEXT-SENSITIVE AND PROGRESSIVE RULES AND AN APPARATUS EMPLOYING ONE OF THE METHODS - Methods of designing an IC and an apparatus are disclosed. In one embodiment, a method includes: (1) creating a functional circuit for a functional block of an IC design, (2) verifying said functional circuit satisfies a rule-set for said IC design, wherein said rule-set is context-based with respect to said design flow, (3) synthesizing a logical circuit based on the functional circuit; (4) verifying the logical circuit satisfies the rule set; (5) implementing a physical layout of the logical circuit; and (6) verifying the physical layout satisfies the rule set, wherein each step of the method is carried out by at least one EDA tool. | 01-27-2011 |
| 20110061032 | HIGH-LEVEL SYNTHESIS APPARATUS, HIGH-LEVEL SYNTHESIS METHOD, AND COMPUTER READABLE MEDIUM COMPRISING HIGH-LEVEL SYNTHESIS PROGRAM - A high-level synthesis apparatus includes an input unit inputting a behavioral description indicating a behavior of a semiconductor integrated circuit comprising a plurality of functional units, an internal representation generator generating an internal representation based on the behavioral description, the internal representation showing a data flow in the behavioral description and an order in which operations are to be performed in the behavioral description, a scheduler performing scheduling for the operations in the internal representation generated in such a manner that non-operating cycles of the functional units continue, a binder performing binding for determining a configuration of the semiconductor integrated circuit operates scheduled operations on the internal representation generated, a circuit description generator generating a circuit description based on a scheduled result and a bound result, and an output unit outputting the internal representation and the circuit description. | 03-10-2011 |
| 20110061033 | REDUNDANT LOGIC CIRCUIT DETECTION METHOD AND DEVICE AND COMPUTER-READABLE RECORDING MEDIUM - A redundant logic circuit detection method includes storing unit-logic-circuit information, waveform data and a limiting condition in a storage section. The unit-logic-circuit information indicates a plurality of unit-logic-circuits synthesized based on logic design information. The waveform data indicates a logic simulation result with respect to the plurality of unit-logic-circuits. The limiting condition defines a comparison condition of the waveform data. The method selects a first unit-logic-circuit from the plurality of unit-logic-circuits. The method detects a second unit-logic-circuit having a substantially identical sequence of the waveform data to the first unit-logic-circuit based on the limiting condition. The method outputs the first unit-logic-circuit and the second unit-logic-circuit as redundant circuit information. | 03-10-2011 |
| 20110061034 | METHOD AND SYSTEM FOR IMPLEMENTING GRAPHICALLY EDITABLE PARAMETERIZED CELLS - Disclosed is an improved mechanism and method for implementing electronic designs. According to some approaches, a method, mechanism, and compute program product is disclosed for implementing electronic designs that allows visual editing of complex objects with advanced editing features, which also provides for automated correspondence of the editing results to parametric values for a programmable object in the design. | 03-10-2011 |
| 20110066987 | LAYOUT METHOD, LAYOUT DEVICE, AND NON-TRANSITORY COMPUTER READABLE MEDIUM STORING LAYOUT PROGRAM - A layout method in accordance with an exemplary aspect of the present invention performs layout of a semiconductor integrated circuit, the layout method including: performing logic synthesis without inserting at least one clock gating cell among clock gating cells inserted in the semiconductor integrated circuit; laying out a cell according to a result of the logic synthesis; inserting the clock gating cell not inserted in the logic synthesis after the cell is laid out; and laying out the inserted clock gating cell, and structuring a clock tree. | 03-17-2011 |
| 20110099528 | HIGH-LEVEL SYNTHESIS APPARATUS, HIGH-LEVEL SYNTHESIS METHOD, AND COMPUTER READABLE MEDIUM - In one embodiment, a high-level synthesis apparatus is disclosed for design of semiconductor integrated circuits. The apparatus can include a parser, a scheduler, a binder, a circuit description generator, and a margin information generator. The parser parses a behavioral description representing behavior of the semiconductor integrated circuits. The scheduler schedules operations to determine operation timing. The binder conducts binding to determine a quantity of hardware resources and a circuit configuration of the semiconductor integrated circuits based on a result of the scheduler. The circuit description generator generates a circuit description of the semiconductor integrated circuits based on results of the scheduler and the binder. The margin information generator generates margin information including a margin time indicative of a period during which there is no arithmetic operation depending on input and output signals in the semiconductor integrated circuits based on the result of the scheduler and the constraint. | 04-28-2011 |
| 20110138344 | QUANTUM KARNAUGH MAP - Techniques for determining and a computing device configured to determine a quantum Karnaugh map through decomposing a quantum circuit into a multiple number of sub-circuits are provided. Also, techniques for obtaining and a computing device configured to obtain a quantum circuit which includes the minimum number of gates among possible quantum circuits corresponding to a quantum Karnaugh map are also provided. | 06-09-2011 |
| 20110173581 | HARDWARE SYNTHESIS USING THERMALLY AWARE SCHEDULING AND BINDING - Technologies are generally described for hardware synthesis using thermally aware scheduling and binding. Multiple versions of a hardware design may be generated, each having variations of schedule and binding results. The scheduling and binding may be performed such that thermal profiles of the multiple versions have thermal peaks that are distant between the versions. The increased physical distance between the thermal peaks of the versions can give the versions unique thermal characteristics. A schedule of rotation between the multiple versions of the design may be constructed such that the thermal profile of the integrated circuit balances out during operation. A linear programming framework may be used to analyze the multiple designs and construct a thermally aware rotation scheduling and binding. For example, the K most efficient versions may be selected and then durations for operating each version within a rotation may be determined. | 07-14-2011 |
| 20110231805 | Increasing PRPG-Based Compression by Delayed Justification - An improved compression technique can increase PRPG-based compression by modifying test generation so that justification of certain decision nodes, called xheadlines, is delayed and merged with PRPG seed computation. Xheadlines are defined by gate modification restrictions, dynamic value considerations, and fanout allowance. Before mapping, the xheadlines can be preprocessed. This preprocessing can include transforming XOR xheadlines having shared inputs, augmenting AND/OR xheadlines, and reducing AND/OR xheadlines with common inputs. Mapping can include determining which xheadlines are satisfied by a current seed, which xheadlines can be satisfied by a future seed, and which xheadlines can opportunistically be satisfied by the current seed. | 09-22-2011 |
| 20120005638 | Race Logic Synthesis for Large-Scale Integrated Circuit Designs - Techniques for performing race logic synthesis on an integrated circuit (IC) are described herein. According to one aspect of the invention, HDL (hardware description language) and/or ESL (electronic system level) design source files of an IC design are compiled into a common design database. Race logic analysis is performed on the IC design, either by a third-party tool or by the same EDA (electronic design automation) tool that also performing race logic synthesis, if the latter has built-in race logic audit functions. Based on the race logic audit results, race logic synthesis is performed on the common design database, and getting rid of all identified race logic in the IC design. This renders the EDA tool can perform concurrent analysis of the IC design, via the race-free common design database, using multi-CPU/core computers and the results will be the same as if the EDA tool had performed serial analysis of the IC design using a single-CPU/core computer. Another aspect of the invention is outputting the re-synthesized logic in the common design database to new HDL/ESL source files. User may use these revised source files to analyze the IC design using other third-party EDA design/verification tools. | 01-05-2012 |
| 20120005639 | LOGIC CIRCUIT AND METHOD OF LOGIC CIRCUIT DESIGN - A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a high-voltage terminal configured for connection to a high constant voltage a low-voltage terminal configured for connection to a low constant voltage, a p-type transistor, and an n-type transistor. The p-type transistor has an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection. The n-type transistor has an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection. The first dedicated logic terminal is connected to the outer diffusion connection of the p-type transistor, the second dedicated logic terminal is connected to the outer diffusion connection of the n-type transistor, the inner diffusion connection of the p-type transistor and the inner diffusion connection of the n-type transistor is connected to form a common diffusion logic terminal, the high-voltage terminal is connected to the bulk connection of the p-type transistor, and the low-voltage terminal is connected to the bulk connection of the n-type transistor. | 01-05-2012 |
| 20120017185 | AUTOMATIC OPTIMAL INTEGRATED CIRCUIT GENERATOR FROM ALGORITHMS AND SPECIFICATION - Systems and methods are disclosed to automatically design a custom integrated circuit includes receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically devising a processor architecture and generating a processor chip specification uniquely customized to the computer readable code which satisfies the constraints; and synthesizing the chip specification into a layout of the custom integrated circuit. | 01-19-2012 |
| 20120017186 | SPECIFYING CIRCUIT LEVEL CONNECTIVITY DURING CIRCUIT DESIGN SYNTHESIS - Exemplary embodiments include a method for modifying a circuit synthesis flow having automated instructions, the method including receiving circuit design input for a circuit design, receiving custom specifications to the circuit design input, synthesizing high level logic from the circuit design input, placing logic on the circuit design, refining the circuit design and generating a circuit description from the circuit design. | 01-19-2012 |
| 20120042292 | METHOD OF SYNTHESIS OF AN ELECTRONIC CIRCUIT - A method of synthesis of at least one logic device coupled between first and second supply voltages and having a plurality of inputs and an output, the logic device including a plurality of transistors having a standard gate length, the method including: identifying, in the at least one logic device, one or more transistors connected between the first or second supply voltage and the output node; and increasing the gate length of each of the identified one or more transistors. | 02-16-2012 |
| 20120047476 | CIRCUIT DESIGN OPTIMIZATION - A method comprises generating a first behavioral model of a circuit describing a physical circuit in a first configuration. The first configuration comprises a first master latch, a first fanout path, and a logic cone. The first master latch couples to the first fanout path and is configured to receive a first data input signal. The first fanout path comprises a plurality of output sinks, each coupled to the logic cone. The first behavioral model is modified to generate a second behavioral model describing the physical circuit in a second configuration. The second configuration comprises an error circuit and an abstract latch clone based on the first master latch. A configuration file is generated based on the second behavioral model. The configuration file comprises information representing a plurality of instantiated latch clones based on the abstract latch clone, each configured to couple to the first data input signal and to one or more output sinks of the plurality of output sinks. The second behavioral model and the configuration file are together configured for input to a synthesis tool. | 02-23-2012 |
| 20120084744 | Methods and Systems for Debugging Equivalent Designs Described at Different Design Levels - Methods for debugging designs are provided. First, signal correlation information for signals of a design at least two design level is obtained. Then, design descriptions corresponding to the design at the at least two design levels are loaded and presented in at least two sets of windows or at least two debugging processes which controls the respective set of windows. A selection of a first signal in a first set of windows or a first debugging process is received. In response to the selection, a second signal corresponding to the first signal is queried according to the signal correlation information, and the second signal in a second set of windows or a second debugging process is automatically selected. | 04-05-2012 |
| 20120089955 | IMPLEMENTING ROUTING FIRST FOR RAPID PROTOTYPING AND IMPROVED WIRING OF HETEROGENEOUS HIERARCHICAL INTEGRATED CIRCUITS - A method, system and computer program product are provided for implementing routing first for rapid prototyping and improved wiring of heterogeneous hierarchical integrated circuit chips. Placement for each of a plurality of random logic macros (RLMs) is identified. Predefined wiring shapes are created for each of the identified RLMs. Full chip wire routing is defined responsive to the created predefined wiring shapes for each of the identified RLMs. | 04-12-2012 |
| 20120096418 | BEHAVIORAL SYNTHESIS APPARATUS, METHOD, AND PROGRAM HAVING TEST BENCH GENERATION FUNCTION - Disclosed is a behavioral synthesis apparatus for generating a test bench where the same test vector can be used in both the behavioral simulation and the RTL simulation. The apparatus includes input application/output signal observation timing signal generation means that generates an input application timing signal, an output observation timing signal, and logic circuits for the input application timing signal and the output observation timing signal; and test bench generation means that generates a test bench that observes the signals, applies inputs, and observes outputs. | 04-19-2012 |
| 20120110526 | Method and Apparatus for Tracking Uncertain Signals - A method and an apparatus for tracking uncertain signals in the simulation of chip design are provided. The method comprises: generating a directed graph which contains sequential logic devices and IO devices from the netlist of chip design, wherein the directed graph illustrates the signal association among the sequential logic devices and IO devices; obtaining the signals related with the sequential logic devices and IO devices from the simulation results, wherein the signals contain a plurality of uncertain signals; and back tracing at least a part of the plurality of uncertain signals along the directed graph to determine the device which firstly generates an uncertain signal. The corresponding apparatus is also provided. With the above method and apparatus, uncertain signals can be traced and their source can be determined, which improves the debugging efficiency. | 05-03-2012 |
| 20120124532 | IMPLEMENTING VERTICAL DIE STACKING TO DISTRIBUTE LOGICAL FUNCTION OVER MULTIPLE DIES IN THROUGH-SILICON-VIA STACKED SEMICONDUCTOR DEVICE - A method and circuit for implementing die stacking to distribute a logical function over multiple dies, die identification and sparing in through-silicon-via stacked semiconductor devices, and a design structure on which the subject circuit resides are provided. Each die in the die stack includes predefined functional logic for implementing a respective predefined function. The respective predefined function is executed in each respective die and a respective functional result is provided to an adjacent die in the die stack. Each die in the die stack includes logic for providing die identification. An operational die signature is formed by combining a plurality of selected signals on each die. A die signature is coupled to a next level adjacent die using TSV interconnections where it is combined with that die signature. | 05-17-2012 |
| 20120159408 | IMPLEMENTATION OF FACTOR GRAPHS - The process of implementing a belief propagation network in software and/or hardware can begin with a factor-graph-designer who designs a factor graph that implements that network. A development system provides a user with a way to specify a factor graph at a high or abstract level, and then solve the factor graph, or make an instance of the factor graph in software and/or hardware based on the specification. Factor graphs enable designers to create a graphical model of complicated belief propagation networks such as Markov chains, hidden Markov models, and Bayesian networks. | 06-21-2012 |
| 20120167023 | METHOD FOR SYNTHESIZING TILE INTERCONNECTION STRUCTURE OF FIELD PROGRAMMABLE GATE ARRAY - A method for synthesizing a tile interconnection structure of a field programmable gate array (FPGA) includes: receiving an interconnection structure specification of the FPGA; constructing a tile interconnection graph based on the interconnection structure specification; converting the interconnection structure specification into a connection diagram between two points on the tile interconnection graph; searching for a shortest path for connection requirements between two points from the connection diagram between two points, and building a bundle structure; and synthesizing a tile interconnection structure from the bundle structure. | 06-28-2012 |
| 20120167024 | METHOD AND SYSTEM FOR SCALABLE REDUCTION IN REGISTERS WITH SAT-BASED RESUBSTITUTION - A method, system, and computer program product for reducing the size of a logic network design, prior to verification of the logic network design. The method includes eliminating registers to reduce the size of the logic network design; thereby, increasing the speed and functionality of the verification process, and decreasing the size of the logic network design. The system identifies one or more compatible resubstitutions of a selected register, wherein the compatible resubstitution expresses the selected register as one or more pre-existing registers of fixed initial state. The resubstitutions are refined utilizing design invariants. When one more resubstitutions are preformed, the system eliminates the selected registers to reduce the size of the logic network design. As a result of the resubstitution process, a logic network design of reduced size is generated. | 06-28-2012 |
| 20120185809 | ARCHITECTURE OPTIMIZER - Systems and methods are disclosed to automatically generate a custom integrated circuit (IC) described by a computer readable code or model. The IC has one or more timing and hardware constraints. The system extracts parameters defining the processor architecture from a static profile and a dynamic profile of the computer readable code; iteratively optimizes the processor architecture by changing one or more parameters of the architecture in a hierarchical manner until all timing and hardware constraints expressed as a cost function are met using an architecture optimizer (AO); and synthesizes the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication. | 07-19-2012 |
| 20120240088 | SYSTEMS AND METHODS OF DESIGNING INTEGRATED CIRCUITS - A method of designing an integrated circuit includes defining at least one dummy layer covering at least one of a portion of a first metallic layer and a portion of a second metallic layer of an integrated circuit. The second metallic layer is disposed over the first metallic layer. The first metallic layer, the second metallic layer and a gate electrode of the integrated circuit have a same routing direction. A logical operation is performed to a file corresponding to the at least one of the portion of the first metallic layer and the portion of the second metallic layer covered by the dummy layer so as to size at least one of the portion of the first metallic layer and the portion of the second metallic layer. | 09-20-2012 |
| 20120284676 | DECOUPLING CAPACITOR INSERTION USING HYPERGRAPH CONNECTIVITY ANALYSIS - Decoupling capacitors (dcaps) are placed in an IC design by assigning different dcap utilization rates to logic cones, applying the rates to corresponding dcap regions surrounding cells in the cones, identifying any overlap of regions from different logic cones, and inserting a dcap at the overlapping region having the highest dcap utilization rate. The best location for the dcap is computed using a hypergraph wherein the cells are edges and the regions are nodes. Any node that is dominated by another node is removed and its edge is extended to the dominating node. The dcap is inserted in the region having the most edges (the edges can be weighted). The process is repeated iteratively, updating the hypergraph by removing nodes connected to dcap location, and inserting the next dcap at a region corresponding to the node which then has the greatest number of connected edges. | 11-08-2012 |
| 20120304135 | METHOD AND APPARATUS FOR PRECISION TUNABLE MACRO-MODEL POWER ANALYSIS - A method for estimating power consumption of a target device upon designing the target device, includes: preparing a hybrid power library having a regression power library part and lookup-table power library part, the hybrid power library storing power characteristics for each of basic building blocks which will constitute the target device; and estimating power consumption of the target device by applying the hybrid power library to a design description of the target device. | 11-29-2012 |
| 20120311512 | Display and automatic improvement of timing and area in a network-on-chip - A method and NoC design tool is disclosed that automatically maps the paths listed in a timing report and the unit size in an area report to the topology of a NoC and displays the paths and unit sizes in a GUI. The tool can also automatically add pipeline stages, separated by the maximum delay allowed in the timing budget, in order to achieve timing closure in an automated way. | 12-06-2012 |
| 20130007678 | INTEGRATED CIRCUIT MODULE AND MANUFACTURING METHODS AND APPLICATION THEREOF - An exemplary integrated circuit module includes a first transistor and a second transistor. The first transistor has a first channel length and a first threshold voltage. The second transistor is electrically coupled to the first transistor and has a second channel length and a second threshold voltage. The second channel length is greater than the first channel length, the absolute value of the second threshold voltage is smaller than the absolute value of the first threshold voltage, and the first transistor and the second transistor have a same threshold voltage implant concentration. Moreover, a manufacturing method of such integrated circuit module, and an application of such integrated circuit module to computer aided design of logic circuit also are provided. | 01-03-2013 |
| 20130042215 | Methods and Apparatuses for Automated Circuit Design - Methods and apparatuses to automatically synthesize circuits. In one aspect of an embodiment, a method implemented on a data processing system for circuit synthesis comprises determining a Read Only Memory (ROM) of a design of a circuit, the ROM having predefined data when the circuit is initialized, and automatically generating an initialization circuit and a Random Access Memory (RAM) to implement the ROM, the initialization circuit to load the predefined data into the RAM when the circuit is initialized. | 02-14-2013 |
| 20130047128 | Method and Apparatus for Using Entropy in An Colony Optimization Circuit Design from High Level Synthesis - A method for designing an integrated circuit is described. The method comprises converting behavioral descriptions of the integrated circuit to register transfer level (RTL) descriptions. The method comprises at least one of the behavioral descriptions including frame synthesis with an input frame and a corresponding output frame. In one embodiment, the method further comprises providing at least two solutions for performing partial and complete operations for simulations as hardware component combinations, associating each solution with a cost, and selecting the solution with the lowest cost as the hardware component combination for a final design of the integrated circuit. | 02-21-2013 |
| 20130055176 | SOFT HIERARCHY-BASED PHYSICAL SYNTHESIS FOR LARGE-SCALE, HIGH-PERFORMANCE CIRCUITS - In one embodiment, the invention is a method and apparatus for soft hierarchy-based synthesis for large-scale, high-performance circuits. One embodiment of a method for physically synthesizing a design of an integrated circuit includes compiling a logical description of the design into a flattened netlist, extracting a soft hierarchy from the flattened netlist, wherein the soft hierarchy defines a boundary on a die across which cells of the integrated circuit are permitted to move, and placing a cell of the integrated circuit on the die in accordance with the soft hierarchy. | 02-28-2013 |
| 20130055177 | SYSTEMS AND METHODS FOR INCREASING DEBUGGING VISIBILITY OF PROTOTYPING SYSTEMS - User's RTL design is analyzed and instrumented so that signals of interest are preserved and can be located in the net list after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the net list to ensure that signal values can be accessed at runtime. After that, a P&R process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations in FPGAs. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names. | 02-28-2013 |
| 20130091477 | DESIGN SUPPORT APPARATUS AND DESIGN SUPPORT METHOD - A first generation unit generates, with reference to logical connection information of a semiconductor integrated circuit to be designed, first information indicating logical connection information where a test circuit used for testing the operation of the semiconductor integrated circuit is not to be inserted. A second generation unit generates second information where a test circuit is to be inserted, by excluding the logical connection information indicated by the first information generated by the first generation unit from logical connection information included in test difficulty information whose parameters indicate difficulties of controllability and observability of a signal that propagates in the semiconductor integrated circuit. | 04-11-2013 |
| 20130111425 | POWER BALANCED PIPELINES | 05-02-2013 |
| 20130132916 | BEHAVIORAL SYNTHESIS METHOD, BEHAVIORAL SYNTHESIS PROGRAM AND BEHAVIORAL SYNTHESIS APPARATUS - A behavioral synthesis method according to the present invention includes generating a scheduled CDFG based on behavioral description information, generating a lifetime for each variable based on the scheduled CDFG, selecting m variables whose lifetimes do not overlap on a time axis, allocating a first register to a first variable having a first bit width and bits of the first bit width within another variable, allocating a second register to bits other than the bits of the first bit width within another variable, and outputting circuit information of a synthesized circuit including the first and second registers. | 05-23-2013 |
| 20130145329 | Incorporating Synthesized Netlists as Subcomponents in a Hierarchical Custom Design - Mechanisms are provided for generating a physical layout of an integrated circuit design. A logic description of the integrated circuit design is received that comprises a first logic description of an irregular logic block of the integrated circuit design and a second logic description of a regular logic block of the integrated circuit design. A manual design of the regular logic block of the integrated circuit design is performed based on user input and an automated design of the irregular logic block of the integrated circuit design is performed without user input. The manual design of the regular logic block and the automated design of the irregular logic block are then integrated into the integrated circuit design to generate a hybrid integrated circuit design. | 06-06-2013 |
| 20130152029 | DISTRIBUTING SPARE LATCH CIRCUITS IN INTEGRATED CIRCUIT DESIGNS - Methods for allocating spare latch circuits to logic blocks in an integrated circuit design are provided. A method includes determining logic blocks in the design and determining and determining an allocation of spare latch circuits among the logic blocks based on respective attributes of the logic blocks. The method further include placing the spare latch circuits in the design in accordance with the determined allocation based on local clock buffers corresponding with the logic blocks. | 06-13-2013 |
| 20130152030 | Method and Apparatus for Performing Formal Verification of Polynomial Datapath - A method and apparatus are provided for use in synthesis of RTL integrated circuit design to determine the functional equivalence of designs. For example, the receiver receives a plurality of designs for synthesis in RTL and a data flow graph is derived for each design. Internal bit widths in the data flow graph representations are restricted ( | 06-13-2013 |
| 20130152031 | METHOD AND APPARATUS FOR MANAGING THE CONFIGURATION AND FUNCTIONALITY OF A SEMICONDUCTOR DESIGN - A method of managing the configuration, design parameters, and functionality of an integrated circuit (IC) design using a hardware description language (HDL). Instructions can be added, subtracted, or generated by the designer interactively during the design process, and customized HDL descriptions of the IC design are generated through the use of scripts based on the user-edited instruction set and inputs. The customized HDL description can then be used as the basis for generating “makefiles” for purposes of simulation and/or logic level synthesis. The method further affords the ability to generate an HDL model of a complete device, such as a microprocessor or DSP. A computer program implementing the aforementioned method and a hardware system for running the computer program are also disclosed. | 06-13-2013 |
| 20130185684 | INTEGRATED CIRCUIT DESIGN METHOD AND SYSTEM - Disclosed is an integrated circuit design method that determines maximum direct currents for metal components and uses them as design constraints in the design flow in order to avoid/minimize electromigration failures. Short and long metal components are treated differently for purposes of establishing the design constraints. For a short metal component, the maximum direct current as a function of a given temperature for a given expected lifetime of the integrated circuit is determined, another maximum direct current is determined based on the Blech length, and the higher of these two is selected and used as the design constraint for that short metal component. For a long metal component, only the maximum direct current as a function of the given temperature for the given expected lifetime is determined and used as the design constraint. Also disclosed herein are associated system and program storage device embodiments for designing an integrated circuit. | 07-18-2013 |
| 20130191800 | TIMING CONSTRAINT GENERATING SUPPORT APPARATUS AND METHOD OF SUPPORTING GENERATION OF TIMING CONSTRAINT - A timing constraint generating support apparatus includes a propagation unit that propagates, through a wire connecting the logic circuits, timing constraints set for the logic circuits by using circuit information that represents information relating to the logic circuits and connection information that represents information of the wire, a determination unit that determines whether or not a plurality of timing constraints different from each other are propagated through the wire by the propagation unit, and an output unit that outputs information representing that the timing constraints propagated through the wire overlap each other in a case where the plurality of timing constraints different from each other are determined to be propagated through the wire by the determination unit. | 07-25-2013 |
| 20130191801 | DISTRIBUTING SPARE LATCH CIRCUITS IN INTEGRATED CIRCUIT DESIGNS - Methods for allocating spare latch circuits to logic blocks in an integrated circuit design are provided. A method includes determining logic blocks in the design and determining and determining an allocation of spare latch circuits among the logic blocks based on respective attributes of the logic blocks. The method further include placing the spare latch circuits in the design in accordance with the determined allocation based on local clock buffers corresponding with the logic blocks. | 07-25-2013 |
| 20130232458 | Increasing PRPG-Based Compression By Delayed Justification - An improved compression technique can increase PRPG-based compression by modifying test generation so that justification of certain decision nodes, called xheadlines, is delayed and merged with PRPG seed computation. Xheadlines are defined by gate modification restrictions, dynamic value considerations, and fanout allowance. Before mapping, the xheadlines can be preprocessed. This preprocessing can include transforming XOR xheadlines having shared inputs, augmenting AND/OR xheadlines, and reducing AND/OR xheadlines with common inputs. Mapping can include determining which xheadlines are satisfied by a current seed, which xheadlines can be satisfied by a future seed, and which xheadlines can opportunistically be satisfied by the current seed. | 09-05-2013 |
| 20130263068 | RELATIVE ORDERING CIRCUIT SYNTHESIS - Systems and methods for relative ordering circuit synthesis are provided herein. One aspect provides for generating at least one circuit design via at least one processor accessible by a computing device; wherein generating at least one circuit design comprises: generating at least one relative order structure based on at least one circuit design layout, the at least one relative order structure comprising at least one placement constraint associated with at least one circuit element; placing the at least one circuit element associated with the at least one placement constraint within a circuit design according to the at least one placement constraint; and placing circuit elements not associated with the at least one placement constraint within the circuit design. Other embodiments and aspects are also described herein. | 10-03-2013 |
| 20130263069 | OPTIMIZING LOGIC SYNTHESIS FOR ENVIRONMENTAL INSENSITIVITY - Roughly described, a method for synthesizing a circuit design from a logic design includes developing candidate solutions for a particular signal path, a first candidate solution identifying a first library cells followed immediately downstream thereof by a first set of zero or more buffers, and a second candidate solution identifying a second library cell followed immediately downstream thereof by a second set of zero or more buffers, the first library cell and first set of buffers in combination being different from the second library cell and second set of buffers in combination. The computer system selects among the candidate solutions at least in part in dependence upon sensitivity of the solution to load capacitance in the particular path, and stores the selected solution in the storage for subsequent use in further developing and fabricating an integrated circuit device. | 10-03-2013 |
| 20130263070 | Method and Apparatus For Implementing Periphery Devices On A Programmable Circuit Using Partial Reconfiguration - A programmable circuit includes a physical interface at an input output (IO) periphery of the programmable circuit. The programmable circuit also includes a partial reconfigurable (PR) module, at the IO periphery of the programmable circuit, to implement a sequencer unit operable to configure the physical interface during a first instance of the PR module, and a controller unit operable to translate commands to the physical interface during a second instance of the PR module. | 10-03-2013 |
| 20130268903 | Display and automatic improvement of timing and area in a network-on-chip - A method and NoC design tool is disclosed that automatically maps the paths listed in a timing report and the unit size in an area report to the topology of a NoC and displays the paths and unit sizes in a GUI. The tool can also automatically add pipeline stages, separated by the maximum delay allowed in the timing budget, in order to achieve timing closure in an automated way. | 10-10-2013 |
| 20130268904 | LAYOUT LIBRARY OF FLIP-FLOP CIRCUIT - Provided is a layout library having a plurality of unit layouts in which the same flip-flop circuit is implemented. In the layout library, at least two unit layouts have mutually different arrangement structures. Therefore, coupling capacitances seen at an equal node with respect to the two flip-flop circuits appear to be different from each other. A semiconductor designer can select a layout in which a desired coupling capacitance is set through wiring, and through this, can adopt a required flip-flop circuit. | 10-10-2013 |
| 20130275929 | LSI DESIGN SUPPORT DEVICE AND LSI DESIGN METHOD - In an LSI designing support device and method, in which in an LSI circuit is designed including a logic gate and an FET, a possibility that a steady-state flow-through current from a power source to a ground is generated is determined. In an inputted netlist including a logic gate and an FET, extraction is made of a flow-through condition function which expresses, in terms of a Boolean expression, on/off of an FET arranged in a path from a power source to a ground or a path from the output of a logic gate to the power source or to the ground. A flow-through condition determining Boolean expression of a logic circuit which supplies an input to the flow-through condition function is extracted. The Boolean expression is degenerated with logic equivalence maintained, and the existence or nonexistence of a possibility of satisfying a flow-through condition is determined. | 10-17-2013 |
| 20130275930 | SYNTHESIZING VHDL MULTIPLE WAIT FSMS INTO RT LEVEL FSMS BY PREPROCESSING - Preprocessing parallel sequences of “wait” statements and synthesizing these multiple “wait” statements to construct support for RTL tools. This is accomplished by preprocessing a VHDL process with multiple wait statements (referred to as BehFSM) into an equivalent register transfer. | 10-17-2013 |
| 20130290918 | CONSTRUCTING INDUCTIVE COUNTEREXAMPLES IN A MULTI-ALGORITHM VERIFICATION FRAMEWORK - A computer-implemented method simplifies a netlist, verifies the simplified netlist using induction, and remaps resulting inductive counterexamples via inductive trace lifting within a multi-algorithm verification framework. The method includes: a processor deriving a first unreachable state information that can be utilized to simplify the netlist; performing a simplification of the netlist utilizing the first unreachable state information; determining whether the first unreachable state information can be inductively proved on an original version of the netlist; and in response to the first unreachable state information not being inductively provable on the original netlist: projecting the first unreachable state information to a minimal subset; and adding the projected unreachable state information as an invariant to further constrain a child induction process. Adding the projected state information as an invariant ensures that any resulting induction counterexamples can be mapped to valid induction counterexamples on the original netlist before undergoing the simplification. | 10-31-2013 |
| 20130305198 | CIRCUIT DESIGN SUPPORT DEVICE, CIRCUIT DESIGN SUPPORT METHOD AND PROGRAM - A processing part inputs a behavior description code in which a write access array to be accessed to write and a read access array to be accessed to read are used. The processing part analyzes the behavior description code, and determines an order of using each write access address and an order of using each read access address when the behavior description code is executed. Further, the processing part performs either one of a write access order changing process to change the order of using the write access addresses when the behavior description code is executed based on the order of using the read access addresses and a read access order changing process to change the order of using the read access addresses when the behavior description code is executed based on the order of using the write access addresses. | 11-14-2013 |
| 20130305199 | IN-PLACE RESYNTHESIS AND REMAPPING TECHNIQUES FOR SOFT ERROR MITIGATION IN FPGA - In-place resynthesis for static memory (SRAM) based Field Programmable Gate Arrays (FPGAs) toward reducing sensitivity to single event upsets (SEUs). Resynthesis and remapping are described which have a low overheard and improve FPGA designs without the need of rerouting LUTs of the FPGA. These methods include in-place reconfiguration (IPR), in-place X-filling (IPF), and in-place inversion (IPV), which reconfigure LUT functions only, and can be applied to any FPGA architecture. In addition, for FPGAs with a decomposable LUT architecture (e.g., dual-output LUTs) an in-place decomposition (IPD) method is described for remapping a LUT function into multiple smaller functions leveraging the unused outputs of the LUT, and making use of built-in hard macros in programmable-logic blocks (PLBs) such as carry chain or adder. Methods are applied in-place to mapped circuits before or after routing without affecting placement, routing, and design closure. | 11-14-2013 |
| 20130339913 | Semi-automated method of FPGA timing closure - The invention describes a semi-automated method and system for Field Programmable Gate Array (FPGA) timing closure. The method is used to achieve timing closure by storing all previous results of design synthesis, place & route, tool options, and area constraints in a database, applying a set of analysis algorithms on the entire build history, and applying a decision engine to determine set of synthesis and place & route tool options and area constraints for the next build iteration. The aim of the inventive method is to eliminate most of the manual steps during design timing closure. The inventive method further makes the process faster, requiring fewer build iterations, and more robust to small design changes that can affect timing results. The desired outcome is achieved by making decisions based on the analysis of all the previous build results. | 12-19-2013 |
| 20130339914 | TECHNOLOGY MAPPING FOR THRESHOLD AND LOGIC GATE HYBRID CIRCUITS - A method of mapping threshold gate cells into a Boolean network is disclosed. In one embodiment, cuts are enumerated within the Boolean network. Next, a subset of the cuts within the Boolean network that are threshold is identified. To minimize power, cuts in the subset of the cuts are selected. | 12-19-2013 |
| 20130346929 | BEHAVIORAL SYNTHESIS APPARATUS, BEHAVIORAL SYNTHESIS METHOD, DATA PROCESSING SYSTEM INCLUDING BEHAVIORAL SYNTHESIS APPARATUS, AND NON-TRANSITORY COMPUTER READABLE MEDIUM STORING BEHAVIORAL SYNTHESIS PROGRAM - A behavioral synthesis apparatus includes a determination unit that determines whether or not a loop description should be converted into a pipeline, and a synthesis unit that performs behavioral synthesis while setting a stricter delay constraint for a loop description that is converted into a pipeline than a loop description that is not converted into a pipeline. | 12-26-2013 |
| 20130346930 | BEST CLOCK FREQUENCY SEARCH FOR FPGA-BASED DESIGN - Searching for desired clock frequency for integrated circuit-based design may receive timing result of a hardware synthesis job executed based on a code specifying hardware design. One or more different timing constraints specifying respective one or more different clock frequencies than used in the hardware synthesis job may be automatically generated without modifying the code. One or more instances of the hardware synthesis job to run with the respective one or more different timing constraints may be automatically spawned. The automatic generation and spawning may repeat until a termination criterion is met, and/or a desired successful timing constraint is identified for the hardware design from the different timing constraints based on whether the one or more instances of the hardware synthesis job met their respective timing constraints. | 12-26-2013 |
| 20140019922 | OPTIMIZATION METHOD AND DEVICE FOR NETLIST USED IN LOGIC CIRCUIT DESIGN FOR SEMICONDUCTOR INTEGRATED CIRCUIT - A method, device, and article for assisting in the design of a logic circuit. The method can be such that: logic circuit description data is acquired, a first netlist is generated which is logically integrated with a first frequency based on the acquired logic circuit description data, and a second netlist is generated which is logically integrated with a second frequency higher than the first frequency based on the acquired logic circuit description data, logical operation elements and the wiring for the logical operation elements are arranged based on the first netlist, and a timing report is outputted which is related to the execution timing for each block divided into a predetermined wiring unit, and any block not satisfying the desired operational speed based on the outputted timing report is extracted, the first netlist is replaced with the second netlist for any extracted block, and placement and routing is performed. | 01-16-2014 |
| 20140019923 | TEST BENCH HIERARCHY AND CONNECTIVITY IN A DEBUGGING ENVIRONMENT - This application discloses a design verification tool to collect messages generated by a test bench during elaboration of the test bench. The messages can identify connectivity corresponding to library components in the test bench. A debug tool can generate a schematic representation of the test bench having circuit symbols corresponding to at least portions of the library components, which are interconnected with trace lines based, at least in part, on the messages. The debug tool can prompt display of the schematic representation of the test bench. | 01-16-2014 |
| 20140047400 | LOGIC CIRCUIT DESIGN METHOD, LOGIC CIRCUIT DESIGN PROGRAM, AND LOGIC CIRCUIT DESIGN SYSTEM - According to one embodiment, a logic circuit design method of an embodiment includes generating logical data corresponding to register transfer level description, based on design data containing the register transfer level description, and generating constraint conditions designating circuit data which satisfies a predetermined condition among plural gate level circuit data logically equivalent to the logical data, based on the design data, and generating gate level circuit data based on the logical data under the constraint conditions. | 02-13-2014 |
| 20140053120 | ARCHITECTURAL PHYSICAL SYNTHESIS - The present invention discloses methods and apparatuses to design an integrated circuit. According to one aspect, a method of designing an integrated circuit comprises determining a state of a design of the integrated circuit at a high level design representation of the integrated circuit, wherein the state of the design of the integrated circuit comprises a netlist with at least one of timing data, resource information, placement information, routing information, and power data. The method further comprises determining a first transform for the state, changing the state of the design at the high level design representation of the integrated circuit using the first transform, and determining a second transform based on the changed state. | 02-20-2014 |
| 20140096095 | DATA PROCESSING APPARATUS INCLUDING RECONFIGUARABLE LOGIC CIRCUIT - There is provided a data processing apparatus ( | 04-03-2014 |
| 20140173538 | FEC DECODER DYNAMIC POWER OPTIMIZATION - A computing device is configured to analyze a logic gate design having logic gates. The computing device is configured further to identify logic gates that are affected by toggling activity associated with an input of one or more of the logic gates. The computing device is configured further to replace, within the logic gate design, the identified logic gates with different logic gates that are not affected by the toggling activity; and output a new logic gate design based on replacing the identified logic gates with the different logic gates, the application specific integrated circuit, with the new logic gate design, producing a same output as the application specific integrated circuit with the logic gate design, based on same inputs. | 06-19-2014 |
| 20140181765 | LOOK-UP BASED BUFFER TREE SYNTHESIS - Systems and techniques are described for performing buffer tree synthesis. Some embodiments create a lookup table based on information contained in a cell library. The lookup table is then used during buffer tree synthesis. | 06-26-2014 |
| 20140181766 | MULTI-MODE SCHEDULER FOR CLOCK TREE SYNTHESIS - Techniques and systems for performing clock tree synthesis (CTS) across multiple modes are described. Some embodiments traverse one or more clock trees from the root of each clock tree to a set of sinks of the clock tree. During the traversal, each clock gate can be marked with a traversal level, and each sink can be marked with one or more clocks and one or more modes that are associated with the sink. A task queue can then be created based on the information collected during the clock tree traversal and populated with different types of tasks based on skew balancing requirements across different modes, and the task queue can be provided to a CTS engine to achieve high-quality skew-balanced clock trees across all modes. | 06-26-2014 |
| 20140223397 | Automatic Generation of Wire Tag Lists for a Metal Stack - Mechanisms are provided for pruning a layer trait library for use in wire routing in an integrated circuit design process. The mechanisms receive a plurality of wirecodes and a metal stack definition. The mechanisms generate a verbose layer trait library based on all possible combinations of the wirecodes and layers of the metal stack definition. The mechanisms generate a pruned layer trait library by pruning the verbose layer trait library to remove redundant layer traits from the verbose layer trait library. In addition, the mechanisms store the pruned layer trait library for performing wire routing of an integrated circuit design. | 08-07-2014 |
| 20140237437 | LOOK-UP BASED FAST LOGIC SYNTHESIS - Systems and techniques are described for performing circuit synthesis. Some embodiments create a lookup table based on information contained in a cell library. The lookup table is then used during circuit synthesis. Specifically, some embodiments optimize cells in a reverse-levelized cell ordering. For a given cell, a table lookup is performed to obtain a set of optimal cell configurations, and the cell is replaced with a cell configuration selected from the set of optimal cell configurations. Some embodiments concurrently optimize cells for timing, area, and power leakage based on the timing criticality of the cells. | 08-21-2014 |
| 20140245242 | VARIATION FACTOR ASSIGNMENT - One or more embodiments of techniques or systems for variation factor assignment for a device are provided herein. In some embodiments, a peripheral environment is determined for a device. A peripheral environment is a layout structure or an instance. When the peripheral environment is the layout structure, a variation factor is assigned to the device based on an architecture associated with the layout structure. When the peripheral environment is the instance, the variation factor is assigned to the device based on a bounding window created for the instance. In this manner, variation factor assignment is provided, such that a first device within a first block of a die has a different variation factor than a second device within a second block of the die, thus giving finer granularity to variation factor assignments. | 08-28-2014 |
| 20140258947 | FINITE-STATE MACHINE ENCODING DURING DESIGN SYNTHESIS - Technology for finite-state machine (FSM) encoding during design synthesis for a circuit is disclosed. The encoding of the FSM may include determining values of a multi-bit state register that are to represent particular states of the FSM. These values may be determined based on possible states of the FSM, possible transitions between the states, probabilities of particular transitions occurring, amounts of false switching associated with particular transitions, area estimates for logic respectively associated with states of the FSM, and/or the like. The values may also be determined based on power considerations, such as estimated power consumption for the circuit. The design synthesis may include generation of a structural description of the encoded FSM. | 09-11-2014 |
| 20140258948 | DESIGN SYNTHESIS OF CLOCK GATED CIRCUIT - Technology for synthesizing a behavioral description of a circuit into a structural description of the circuit is disclosed. The behavioral description may describe the circuit in terms of the circuit's behavior, or other functionality, via multiple statements, including a conditional statement. The technology includes analyzing statements upstream and/or downstream from the conditional statement, identifying one or more statements having dependency relationships with the conditional statement and inferring one or more potential clock domains for logic associated with the identified statements. | 09-11-2014 |
| 20140282311 | NETWORK SYNTHESIS DESIGN OF MICROWAVE ACOUSTIC WAVE FILTERS - A method of designing an acoustic microwave filter in accordance with frequency response requirements. The method comprises selecting an initial filter circuit structure including a plurality of circuit elements comprising at least one resonant element and at least one other reactive circuit element, selecting lossless circuit response variables based on the frequency response requirements, selecting a value for each of the circuit elements based on the selected circuit response variables to create an initial filter circuit design, transforming the resonant element(s) and the other reactive circuit element(s) of the initial filter circuit design into at least one acoustic resonator model to create an acoustic filter circuit design, adding parasitic effects to the acoustic filter circuit design to create a pre-optimized filter circuit design, optimizing the pre-optimized filter circuit design to create a final filter circuit design, and constructing the acoustic microwave filter based on the final filter circuit design. | 09-18-2014 |
| 20140298278 | GRAPHICAL METHOD AND PRODUCT TO ASSIGN PHYSICAL ATTRIBUTES TO ENTITIES IN A HIGH LEVEL DESCRIPTIVE LANGUAGE USED FOR VLSI CHIP DESIGN - A layout for an integrated circuit is designed by assigning physical design attributes including locations to a selected subset of placeable objects in the circuit netlist, prior to any physical synthesis. A layout abstract is displayed in a graphical user interface to allow the designer to visually inspect a layout abstract which shows the selected objects at their assigned locations. After making any desired modifications to the object locations, the location information can be formatted as a synthesis input file. Physical synthesis is then carried out while maintaining fixed locations for the selected objects according to the assigned locations. Physical design attributes can include coordinates and an orientation. The selected subset of placeable objects can constitute an identified datapath of the integrated circuit design. | 10-02-2014 |
| 20140317583 | MANAGING AND CONTROLLING THE USE OF HARDWARE RESOURCES ON INTEGRATED CIRCUITS - Disclosed herein are representative embodiments of methods and apparatus for managing and allocating hardware resources during RTL synthesis. For example, in one exemplary method disclosed herein, an RTL description of a circuit to be implemented in a target architecture is received. The target architecture of this embodiment comprises a fixed number of hardware resources in a class of hardware resources. One or more operator instances are determined from the RTL description received, where at least some of the operator instances are implementable by the hardware resources in the class of hardware resources. In this embodiment, and prior to initially synthesizing the RTL description into a gate-level netlist, assignment information indicative of how the operator instances are to be implemented using the hardware resources in the class of hardware resources is automatically determined. A graphical user interface is also provided that allows a user to view and modify the assignment information. | 10-23-2014 |
| 20140325461 | METHOD AND APPARATUS FOR GENERATING GATE-LEVEL ACTIVITY DATA FOR USE IN CLOCK GATING EFFICIENCY ANALYSIS - A mechanism for generating gate-level activity data for use in clock gating efficiency analysis of an integrated circuit (IC) design is provided. Generating the gate-level activity data includes generating a signal behaviour description for inter-register signals, generating a gate-level netlist for the IC design, generating gate-level stimuli based at least partly on the generated signal behaviour description, and performing gate-level simulation using the generated gate-level stimuli to generate gate-level activity data for the IC design. In one embodiment, generating the signal behaviour description includes performing Register Transfer Level (RTL) simulation of the IC design, and generating the gate-level netlist includes performing RTL synthesis. The RTL simulation and RTL synthesis are performed on RTL data for the IC design. | 10-30-2014 |
| 20140331195 | TEST BENCH HIERARCHY AND CONNECTIVITY IN A DEBUGGING ENVIRONMENT - This application discloses a design verification tool to collect messages generated by a test bench during elaboration of the test bench. The messages can identify connectivity corresponding to library components in the test bench. A debug tool can generate a schematic representation of the test bench having circuit symbols corresponding to at least portions of the library components, which are interconnected with trace lines based, at least in part, on the messages. The debug tool can prompt display of the schematic representation of the test bench. | 11-06-2014 |
| 20140337811 | SUB-MODULE PHYSICAL REFINEMENT FLOW - A computer system is provided that enables a designer of a circuit design to fracture and reconstitute a larger design for both computer modeling of the functionality and the physical implementation or rendering of the circuit design. More particularly, the designer may refine or re-work a sub-module of the larger sub-circuit without having to create a corresponding sub-module in the physical implementation. This capability thus avoids the significant complexity required for sub-module refinement in the current state of the art, and provides the designer with a much simpler flow. | 11-13-2014 |
| 20150046889 | STATE GROUPING FOR ELEMENT UTILIZATION - Embodiments of a system and method for generating an image configured to program a parallel machine from source code are disclosed. One such parallel machine includes a plurality of state machine elements (SMEs) grouped into pairs, such that SMEs in a pair have a common output. One such method includes converting source code into an automaton comprising a plurality of interconnected states, and converting the automaton into a netlist comprising instances corresponding to states in the automaton, wherein converting includes pairing states corresponding to pairs of SMEs based on the fact that SMEs in a pair have a common output. The netlist can be converted into the image and published. | 02-12-2015 |
| 20150100930 | Sustainable Differentially Reliable Architecture for Dark Silicon - For mapping a sustainable, differentially reliable architecture for dark silicon, a calculation module calculates an expected energy efficiency for a prior mapping of process threads for a plurality of cores. The calculation module further calculates a workload acceptance capacity (WAC) from degradation rates for the plurality of cores. A map module maps the process threads to the plurality of cores based on at least one of the expected energy efficiency and the WAC to satisfy a mapping policy. A specified number of the plurality of cores is not powered. | 04-09-2015 |
| 20150100931 | Adaptive Clock Management In Emulation - Aspects of the invention relate to techniques for adaptive clock management in emulation. A clock suspension request signal, indicating when a suspension of design clock signals in an emulator is needed, is generated based on activity status information of the emulator with one or more emulator resources such as software environment. A clock suspension allowance signal, indicating whether a suspension of design clock signals is permitted considering dynamic targets in the emulator, is generated based on slack information related to one or more clock signals associated with one or more dynamic targets of the emulator. Based on the clock suspension request signal and the clock suspension allowance signal, a clock suspension signal is generated for enabling temporary design clock suspensions. | 04-09-2015 |
| 20150121324 | CELL LIBRARY AND METHOD FOR DESIGNING AN ASYNCHRONOUS INTEGRATED CIRCUIT - The invention relates to a rocket engine with an extendable divergent which includes an exhaust nozzle for the gases coming from a combustion chamber, the nozzle having a longitudinal axis (ZZ′) including a first portion defining a nozzle throat and a first fixed divergent section ( | 04-30-2015 |
| 20150143307 | SEQUENTIAL CLOCK GATING USING NET ACTIVITY AND XOR TECHNIQUE ON SEMICONDUCTOR DESIGNS INCLUDING ALREADY GATED PIPELINE DESIGN - The circuit design process requires ways to reduce the power consumption of large integrated circuits and system-on-chip designs. This is typically done by introducing a process of clock gating thereby enabling or disabling flip-flops associated with specific functional blocks within the circuit. However, such changes in the circuit require synthesis and verification to ensure correctness of design and operation as sequential clock gating changes the state function dynamically. It is therefore necessary to define synthesis methods adapted to such dynamic changes in the design. According to an embodiment a sequential clock gating method uses an exclusive-OR technique to overcome the deficiencies of the prior art methods. | 05-21-2015 |
| 20150294040 | METHOD OF DETERMINING DEVICE TYPE AND DEVICE PROPERTIES AND SYSTEM OF PERFORMING THE SAME - A method of determining a device type and device properties includes receiving an input file including information related to a device, and identifying at least one layer set within the input file. The method further includes identifying at least one feature present in layer set. The method further includes analyzing a relationship between the at least one feature formed by the first layer and at least one feature formed by the second layer to determine at least one layer set relationship. The method further includes comparing the layer set relationship with at least one template layer set relationship. The method further includes determining the device type of the device based on the comparison between the layer set relationship and the template layer set relationship. The method further includes determining the device properties of the device based on the layer set relationship, the device type or the at least one feature. | 10-15-2015 |
| 20150294055 | SYSTEMS AND METHODS FOR INCREASING DEBUGGING VISIBILITY OF PROTOTYPING SYSTEMS - User's register transfer level (RTL) design is analyzed and instrumented so that signals of interest are preserved and can be located in the netlist after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the netlist to ensure that signal values can be accessed at runtime. After that, a place and route (P&R) process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations is field programmable gate array (FPGA) devices. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names. | 10-15-2015 |
| 20150324497 | Approximate Circuits for Increased Reliability - Embodiments of the invention describe a Boolean circuit having a voter circuit and a plurality of approximate circuits each based, at least in part, on a reference circuit. The approximate circuits are each to generate one or more output signals based on values of received input signals. The voter circuit is to receive the one or more output signals generated by each of the approximate circuits, and is to output one or more signals corresponding to a majority value of the received signals. At least some of the approximate circuits are to generate an output value different than the reference circuit for one or more input signal values; however, for each possible input signal value, the majority values of the one or more output signals generated by the approximate circuits and received by the voter circuit correspond to output signal result values of the reference circuit. | 11-12-2015 |
| 20150339413 | METHOD AND APPARATUS FOR PERFORMING LOGIC SYNTHESIS - A method of performing logic synthesis of at least a part of an integrated circuit design. The method comprises identifying a first and at least one further module within the IC design that are mutually exclusive, selecting at least one register element within the first identified module and at least one register element within the at least one further identified module to be shared, and merging the first and at least one further mutually exclusive modules such that at least one common register element is shared between the first and at least one further mutually exclusive modules for the register elements selected to be shared. | 11-26-2015 |
| 20150347640 | PHYSICAL AWARE TECHNOLOGY MAPPING IN SYNTHESIS - A method of performing physical aware technology mapping in a logic synthesis phase of design of an integrated circuit and a system to perform physical aware technology mapping are described. The method includes subdividing a core area representing a sub-block of the integrated circuit into equal-sized grids. The method also includes determining a location of each of one or more latches in the logic design based on an algorithm, determining a location of each of one or more combinational logic gates in the logic design based on the locations of the one or more latches, and obtaining the technology mapping based on the locations of the one or more latches, one or more input ports, or one or more output ports, the locations of the one or more combinational logic gates, and associated path delays. | 12-03-2015 |
| 20150347641 | Synthesis Tuning System for VLSI Design Optimization - In one aspect, a method for tuning input parameters to a synthesis program is provided which includes the steps of: (a) selecting a subset of parameter settings for the synthesis program based on a tuning optimization cost function; (b) individually running synthesis jobs in parallel for each of the parameter settings in the subset; (c) analyzing results from a current iteration and prior iterations, if any, using the cost function; (d) using the results from the current iteration and the prior iterations, if any, to create combinations of the parameter settings; (e) running synthesis jobs in parallel for the combinations of the parameter settings in a next iteration; and (f) repeating the steps (c)-(e) for one or more additional iterations or until an exit criteria has been met. | 12-03-2015 |
| 20150347643 | PHYSICAL AWARE TECHNOLOGY MAPPING IN SYNTHESIS - A method of performing physical aware technology mapping in a logic synthesis phase of design of an integrated circuit and a system to perform physical aware technology mapping are described. The system includes a memory device to store a logic design of the integrated circuit, and a processor to subdivide a core area representing a sub-block of the integrated circuit into equal-sized grids, the core area including one or more input ports and one or more output ports, to determine a location of each latch in a logic design based on an algorithm, to determine a location of each combinational logic gate in the logic design, and to obtain the technology mapping based on the locations of the one or more latches, the locations of the one or more combinational logic gates, and associated path delays. | 12-03-2015 |
| 20150370941 | HOLDTIME CORRECTION USING INPUT/OUTPUT BLOCK DELAY - Various techniques are provided to correct for hold time violations using input/output (I/O) block hardware of a programmable logic device (PLD) without requiring additional mapping, placement, or routing operations. In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD. The method also includes assigning components of the PLD to perform the operations. The method also includes routing a signal path among the components. The method also includes detecting a hold time violation for the signal path at an I/O block of the PLD. The method also includes selectively adjusting a variable delay cell of the I/O block to correct the hold time violation. | 12-24-2015 |
| 20150379164 | MIXED-WIDTH MEMORY TECHNIQUES FOR PROGRAMMABLE LOGIC DEVICES - Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD and synthesizing the design into a plurality of PLD components. The synthesizing includes detecting a mixed-mode memory operation in the design. The mixed-mode memory operation specifies memory access having different read and write data widths using a plurality of embedded memory blocks each having a fixed data width. The synthesizing further includes determining a reduced number of embedded memory blocks to implement the mixed-mode memory operation, and modifying the mixed-mode memory operation to remap the memory access to the reduced number of embedded memory blocks. | 12-31-2015 |
| 20150379165 | SUB-MODULE PHYSICAL REFINEMENT FLOW - A computer system is provided that enables a designer of a circuit design to fracture and reconstitute a larger design for both computer modeling of the functionality and the physical implementation or rendering of the circuit design. More particularly, the designer may refine or re-work a sub-module of the larger sub-circuit without having to create a corresponding sub-module in the physical implementation. This capability thus avoids the significant complexity required for sub-module refinement in the current state of the art, and provides the designer with a much simpler flow. | 12-31-2015 |
| 20160034609 | SUPERCONDUCTING CIRCUIT PHYSICAL LAYOUT SYSTEM AND METHOD - Systems and methods are provided for physical layout of superconductor circuits. The physical layout system and method is configured to place and route the superconducting circuits by first placing the gates in the form of gate tiles within unoccupied areas of a predetermined circuit design based on a netlist. Each gate tile type includes a particular gate type and a plurality of unassigned Josephson junctions that can be employed in the gates and/or the active interconnects. Inductive wires are then routed between gates incorporating and assigning the Josephson junctions to produce active interconnects between the I/O terminals of the gates based on connections defined in the netlist. | 02-04-2016 |
| 20160034627 | METHOD AND PROGRAM FOR DESIGNING INTEGRATED CIRCUIT - A method of designing an integrated circuit includes a processor receiving input data initially-defining the integrated circuit using a plurality of first standard cells designed to optimize a performance or yield characteristic. The processor substitutes at least one second standard cell designed to optimize a different performance or yield characteristic from that for which the first standard cells were optimized for a corresponding one of the first standard cells. The processor generates output data defining the integrated circuit including the second standard cell. The substituted second standard cell has the same function as the corresponding first standard cell for which it was substituted. | 02-04-2016 |
| 20160042098 | BOUNDARY BASED POWER GUIDANCE FOR PHYSICAL SYNTHESIS - A method and system to obtain a physical design of an integrated circuit from a logical design are described. The method includes performing a baseline synthesis to obtain a baseline physical design using timing constraints and an overall power budget. The method also includes computing power assertions, performing a re-synthesis using the timing constraints and the power assertions to obtain a new physical design, comparing the new physical design with the baseline physical design to determine a degradation of the new physical design in comparison with the baseline physical design, and reducing a weighting of the power assertions relative to the timing constraints based on the degradation. The executing the performing the re-synthesis, the comparing, and the reducing are done iteratively until the degradation is below a threshold value. | 02-11-2016 |
| 20160042099 | BEHAVIORAL SYNTHESIS APPARATUS, BEHAVIORAL SYNTHESIS METHOD, DATA PROCESSING SYSTEM INCLUDING BEHAVIORAL SYNTHESIS APPARATUS, AND NON-TRANSITORY COMPUTER READABLE MEDIUM STORING BEHAVIORAL SYNTHESIS PROGRAM - A behavioral synthesis apparatus includes a determination unit that determines whether or not a loop description should be converted into a pipeline, and a synthesis unit that performs behavioral synthesis while setting a stricter delay constraint for a loop description that is converted into a pipeline than a loop description that is not converted into a pipeline. | 02-11-2016 |
| 20160055270 | LOGIC CIRCUIT AND SYSTEM AND COMPUTER PROGRAM PRODUCT FOR LOGIC SYNTHESIS - A logic circuit includes first and second input, an output, an input acknowledgement node, an output acknowledgement node, a logic evaluation block, a pre-charging circuit, and a completion detection circuit. The logic evaluation block performs a logic evaluation of first and second input signals at the first and second inputs, and to output an output signal corresponding to the logic evaluation. The pre-charging circuit pre-charges the logic evaluation block in response to the first input signal and an acknowledgement signal at the input acknowledgement node. The completion detection circuit generates an acknowledgement signal at the output acknowledgement node in response to the second input signal and the output signal. | 02-25-2016 |
| 20160055271 | DATA STRUCTURE OF DESIGN DATA OF SEMICONDUCTOR INTEGRATED CIRCUIT AND APPARATUS AND METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT - The present invention is directed to easily change design of RTL circuit data according to design specifications such as power consumption and operation frequency. RTL circuit data of a semiconductor integrated circuit includes a first description expressing a specific module or specific circuit element and a second description with which at least a part of the first description is replaced, thereby adding a new function to a specific module or circuit element. When a computer performs logic synthesis on the RTL circuit data, either logic synthesis is performed on the first description as it is, or a part of the first description is replaced with the second description and the logic synthesis is performed on the resultant is determined on the basis of selection information. | 02-25-2016 |
| 20160070827 | NETWORK SYNTHESIS DESIGN OF MICROWAVE ACOUSTIC WAVE FILTERS - A method of designing an acoustic microwave filter in accordance with frequency response requirements. The method comprises selecting an initial filter circuit structure including a plurality of circuit elements comprising at least one resonant element and at least one other reactive circuit element, selecting circuit response variables based on the frequency response requirements, selecting a value for each of the circuit elements based on the selected circuit response variables to create an initial filter circuit design, transforming the resonant element(s) and the other reactive circuit element(s) of the initial filter circuit design into at least one acoustic resonator model to create an acoustic filter circuit design, adding parasitic effects to the acoustic filter circuit design to create a pre-optimized filter circuit design, optimizing the pre-optimized filter circuit design to create a final filter circuit design, and constructing the acoustic microwave filter based on the final filter circuit design. | 03-10-2016 |
| 20160078153 | SUBTHRESHOLD STANDARD CELL LOGIC LIBRARY - A subthreshold standard cell library addresses the energy efficiency of electronic systems, thereby significantly reducing power consumption. Recent energy performance requirements are causing the next-generation system manufacturers to explore approaches to lower power consumption. Subthreshold operation has been examined and implemented in designing ultra low power standard cell designs that operate beyond the normal modes of operation, with the potential for large energy savings. Operation of CMOS (Complementary Metal Oxide Semiconductor) transistors in the subthreshold regime, where the supply voltage used in operation is orders of magnitude below the normal operating voltage of typical transistors, has proven to be very beneficial for energy constrained systems as it enables minimum energy consumption in Application Specific Integrated Circuits (ASICs). | 03-17-2016 |
| 20160085886 | ORGANIZATION FOR VIRTUAL-FLAT EXPANSION OF PHYSICAL DATA IN PHYSICALLY-HIERARCHICAL IC DESIGNS - In Integrated Circuit (IC) Physical Design, the shapes and other geometric objects that are used to represent the mask data have physical coordinates expressed in a Cartesian plane. When the designs are hierarchical, each level of physical hierarchy has its own coordinate system. When viewed from the top level of a hierarchical design, lower-level shapes must be transformed in order to understand their location from the point of view of the top block. Users and algorithms that manipulate physical data across these hierarchy boundaries must go through the tedious task of transforming data, sometimes multiple times, as it is being changed. | 03-24-2016 |
| 20160092609 | Optimizing Designs of Integrated Circuits - Methods and systems for optimizing and/or designing integrated circuits. In one embodiment, a method for dynamically routing a net from equivalent resources is described, comprising identifying a critical load, determining whether a driver driving the critical load drives other components, and whether the critical load requires an improvement in slack, replicating the driver, to create a replicated driver, when the critical load requires an improvement in slack, coupling the replicated driver to the load; and tagging the replicated driver. | 03-31-2016 |
| 20160098497 | BOUNDARY BASED POWER GUIDANCE FOR PHYSICAL SYNTHESIS - A method and system to obtain a physical design of an integrated circuit from a logical design are described. The system includes a memory device to store a logical design, and a processor to execute a synthesis engine. The processor performs a baseline synthesis to obtain a baseline physical design using timing constraints and an overall power budget, computes power assertions, performs a re-synthesis using the timing constraints and the power assertions to obtain a new physical design, compares the new physical design with the baseline physical design to determine a degradation of the new physical design in comparison with the baseline physical design, reduces a weighting of the power assertions relative to the timing constraints based on the degradation, and iteratively performs the re-synthesis, compares the new physical design with the baseline physical design, and reduces the weighting until the degradation is below a threshold value. | 04-07-2016 |
| 20160117421 | REGION-BASED SYNTHESIS OF LOGIC CIRCUITS - Techniques for synthesized circuit design are described herein. The techniques include identifying a region of a synthesized logical circuit design, and un-mapping gates of the identified region. A logical resynthesis is performed on the unmapped gates based on a predetermined optimization for the identified region. | 04-28-2016 |
| 20160117422 | REGION-BASED SYNTHESIS OF LOGIC CIRCUITS - Techniques for synthesized circuit design are described herein. The techniques include identifying a region of a synthesized logical circuit design, and un-mapping gates of the identified region. A logical resynthesis is performed on the unmapped gates based on a predetermined optimization for the identified region. | 04-28-2016 |
| 20160147916 | ENHANCED PARAMETER TUNING FOR VERY-LARGE-SCALE INTEGRATION SYNTHESIS - A method and system are provided for tuning parameters of a synthesis program for a design description. The method includes (a) ranking individual parameter impact by evaluating a design-cost function of each of the parameters. The method further includes (b) creating a set of possible parameter combinations that is ordered by an estimated-cost function. The method additionally includes (c) selecting, from the set of possible parameter combinations, top-k scenarios having best estimated costs to form a potential set, and running at least some of the top-k scenarios in parallel through the synthesis program. The method also includes (d) repeating steps (b)-(c) for one or more iterations until at least one of a maximum iteration limit is reached and an exit criterion is satisfied. | 05-26-2016 |
| 20160154904 | DESIGN METHOD AND DESIGN APPARATUS | 06-02-2016 |
| 20160154905 | TIMING VIOLATION RESILIENT ASYNCHRONOUS TEMPLATE | 06-02-2016 |
| 20160188760 | PHASE ALGEBRA FOR SPECIFYING CLOCKS AND MODES IN HIERARCHICAL DESIGNS - A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of waveforms without simulating the individual waveforms. The tool can determine a first sequence of signal transition representations of a first signal of a first module of a register level circuit design. The second module of the register level circuit design comprises the first module, arranged in a hierarchical order. The tool can determine a second sequence of signal transition representations of the first signal of the first module. The signal transition representations of a second signal are propagated from the second module to the first module using the first signal. The tool can determine whether a first mapping can be determined between the first sequence and the second sequence, where the second sequence is propagated through the first module. | 06-30-2016 |
| 20160188785 | PHASE ALGEBRA FOR VIRTUAL CLOCK AND MODE EXTRACTION IN HIERARCHICAL DESIGNS - A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of waveforms without simulating the individual waveforms. The tool can determine that a first sequence of signal transition representations of a first signal of the first module comprises a null sequence. The first module of a register level circuit design comprises a second module, the first module and the second module arranged in a hierarchical order. The tool can determine a second sequence of signal transition representations of a second signal of the second module. Signal transition representations of the first signal are for propagation from the first module to the second module using the second signal. The tool can extract a non-null sequence for the first sequence based on the second sequence to generate an extracted first sequence. | 06-30-2016 |
| 20160196364 | INTEGRATED CIRCUIT DESIGN AND OPERATION | 07-07-2016 |
| 20160203242 | CIRCUIT PLACEMENT BASED ON FUZZY CLUSTERING | 07-14-2016 |
| 20160203243 | Subthreshold Standard Cell Library | 07-14-2016 |
| 20160253438 | DESIGN OF A CIRCUIT SUITABLE FOR GENERATING RANDOM BITS AND CIRCUIT FOR GENERATING RANDOM BITS | 09-01-2016 |
| 20160253439 | Methods For Converting Circuits In Circuit Simulation Programs | 09-01-2016 |
| 20160253445 | PREDICTIVE MULTI-USER CLIENT-SERVER ELECTRONIC CIRCUIT DESIGN SYSTEM UTILIZING MACHINE LEARNING TECHNIQUES | 09-01-2016 |
| 20160378889 | SYNTHESIS OF DC ACCURATE NOISE COMPATIBLE REDUCED NETLIST - In one embodiment, a circuit analysis method includes obtaining a netlist of a circuit, generating a reduced model from the netlist, using the reduced model to synthesize a noise compatible netlist, ensuring accurate DC behavior, and simulating the circuit using the synthesized netlist. | 12-29-2016 |
| 20160378905 | SYNTHESIS OF REDUCED NETLIST HAVING POSITIVE ELEMENTS AND NO CONTROLLED SOURCES - In one embodiment, a circuit analysis method includes obtaining a netlist of a circuit, generating a reduced model from the netlist, using the reduced model to synthesize a positive netlist having no controlled current or voltage sources, unstamping the synthesized positive netlist, and simulating the circuit using the unstamped synthesized positive netlist. | 12-29-2016 |
| 20180025101 | SYSTEMS AND METHOD FOR OPTIMIZING STATE ENCODING | 01-25-2018 |
