| Entries |
| Document | Title | Date |
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| 20110022995 | CIRCUIT DESIGN INFORMATION GENERATING EQUIPMENT, FUNCTION EXECUTION SYSTEM, AND MEMORY MEDIUM STORING PROGRAM - A design information generating equipment is provided. A control component of the design information generating equipment, when a basic function of the plurality of functions constitutes a requested function, and design information that corresponds to the basic function is stored in a second memory area, uses the stored design information, and, when the design information that corresponds to the basic function of the plurality of functions is not stored in the second memory area, uses a source program corresponding to the basic function of the plurality of functions stored in a first memory area, and performs control so as to generate design information corresponding to the basic function of the plurality of functions and stores the generated design information in the second memory area, and, using the generated design information, reconfigures a design configured to execute the requested function, and executes the requested function with the reconfigurable design information. | 01-27-2011 |
| 20110029941 | MULTI-LEVEL DOMINO, BUNDLED DATA, AND MIXED TEMPLATES - Techniques are described for generating asynchronous circuits (e.g., in the form of one or more netlists) for implementation, e.g., in integrated circuitry/chips. Embodiments are directed to asynchronous multi-level domino design template and several variants including a mixture of domino and single-rail data logic. The templates can provide high throughput, low latency, and area efficiency. A multi-level domino template is partitioned into pipeline stages in which each stage consists of potentially multiple-levels of domino logic controlled by a single controller that communicates with other controllers via handshaking. Each stage is composed of two parts: a data path and a control path. The data path implements the computational logic, both combinational and sequential using efficient dual-rail domino logic. The control path implements a unique four-phase handshake to ensure correctness and the preservation of logical dependencies between pipeline stages. The data path and controller interact through a small number of key control signals. | 02-03-2011 |
| 20110320989 | MINIMAL LEAKAGE-POWER STANDARD CELL LIBRARY - A minimal leakage power Standard Cell Library is provided. The minimal leakage power Standard Cell Library provides minimal leakage power cells with improved speed characteristics. The minimal leakage power Standard Cell Library includes cells from an existing Standard Cell Library and a set of minimal leakage power cells for a selected set of logic functions. The minimal leakage power Standard Cell Library is formed by identifying a set of logic functions. For each logic function in the identified set, a base case for an unfolded implementation of the logic function is determined. Widths for transistors in a transistor topology used in the unfolded implementation of the logic function are determined based on the non-linear leakage power characteristics for the transistor topology to achieve minimal leakage power. The determined widths are then assigned to the transistors and the minimal leakage cell is added to the library. | 12-29-2011 |
| 20120084742 | METHOD AND APPARATUS FOR USING ENTROPY IN ANT COLONY OPTIMIZATION CIRCUIT DESIGN FROM HIGH LEVEL SYNTHESIS - A method and apparatus for using entropy in ant colony optimization circuit design from high level synthesis is described. In one example, an operation to be performed by a circuit is selected. A plurality of hardware components for performing the operation are represented with a data flow graph having edges and nodes. A plurality of solutions for performing the operation are simulated as hardware component combinations represented as paths on the data flow graph. For each solution the cost including a number of edges and nodes traversed on the data flow graph and a supplemental sub-integer cost is determined and a solution is selected with the lowest cost as a hardware component combination for a circuit. | 04-05-2012 |
| 20120096415 | ASICS HAVING MORE FEATURES THAN GENERALLY USABLE AT ONE TIME AND METHODS OF USE - A present ASIC may include functionality exceeding that which will be operative at one given time (e.g., when the chip is packaged and inserted into a broader circuit. The excess ASIC functionality may be chosen in anticipation of changing market environments, and/or differing product requirements in various market spaces (e.g., in different countries where different interoperability standards are chosen). In such cases, and an appropriate subset of the excessive ASIC functionality may be programmably activated for each market space after manufacture. | 04-19-2012 |
| 20120180008 | ELECTRONIC COMPONENT PROTECTION POWER SUPPLY CLAMP CIRCUIT - Electronic component protection power supply clamp circuits comprising a plurality of p-type channel metal-oxide-semiconductor (PMOS) and n-type channel metal-oxide-semiconductor (NMOS) transistors are described. These clamp circuits use a feedback latching circuit to retain an electrostatic discharge (ESD)-triggered state and efficiently conduct ESD current that has been diverted into the power supply, in order to dissipate ESD energy. The feedback latching circuit also maintains a clamp transistor in its off state if the clamp circuit powers up untriggered, thus enhancing the clamp circuit's immunity to noise during normal operation. Passive resistance initialization of key nodes to an untriggered state, as well as passive resistance gate input loading of a large ESD clamping transistor, further enhances the clamp circuit's immunity to false triggering. This also lengthens the time that the clamp circuit remains in the ESD-triggered state during human body model (HBM) or other long duration detected ESD events. | 07-12-2012 |
| 20120180009 | Automated Pad Ring Generation for Programmable Logic Device Implementation of Integrated Circuit Design - In an embodiment, a method to automatically generate a pad ring for a programmable logic device implementation of an integrated circuit is contemplated. The pad ring that will be used in the integrated circuit itself may include pad logic (e.g. to support boundary scan and other forms of testing), custom driver/receiver circuitry, etc. The pad ring in the programmable logic device, on the other hand, may be predetermined as part of the production of the programmable logic device. The generation may include removing the pad logic and other pad-related circuitry from one or more design files that represent the integrated circuit, as well as mapping the input, output, and input/output signals of the integrated circuit to the available programmable logic device pads. | 07-12-2012 |
| 20120216158 | STRAINED DEVICES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES - Strained Si and strained SiGe on insulator devices, methods of manufacture and design structures is provided. The method includes growing an SiGe layer on a silicon on insulator wafer. The method further includes patterning the SiGe layer into PFET and NFET regions such that a strain in the SiGe layer in the PFET and NFET regions is relaxed. The method further includes amorphizing by ion implantation at least a portion of an Si layer directly underneath the SiGe layer. The method further includes performing a thermal anneal to recrystallize the Si layer such that a lattice constant is matched to that of the relaxed SiGe, thereby creating a tensile strain on the NFET region. The method further includes removing the SiGe layer from the NFET region. The method further includes performing a Ge process to convert the Si layer in the PFET region into compressively strained SiGe. | 08-23-2012 |
| 20120221987 | VERTICAL HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE - Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance, as well as fabrication methods for vertical heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The vertical heterojunction bipolar transistor includes a barrier layer between the intrinsic base and the extrinsic base that blocks or reduces diffusion of a dopant from the extrinsic base to the intrinsic base. The barrier layer has at least one opening that permits direct contact between the intrinsic base and a portion of the extrinsic base disposed in the opening. | 08-30-2012 |
| 20120266115 | PHASE CHANGE MEMORY CYCLE TIMER AND METHOD - A phase change memory (PCM) cycle timer and associated method are disclosed. A system includes at least one reference phase change element (PCE). The system also includes a circuit that performs a write operation on the at least one reference PCE and substantially immediately thereafter continuously senses and returns a value of a resistance of the at least one reference PCE throughout a settling time of the at least one reference PCE. | 10-18-2012 |
| 20120266116 | INTEGRATED MILLIMETER WAVE ANTENNA AND TRANSCEIVER ON A SUBSTRATE - A semiconductor chip integrating a transceiver, an antenna, and a receiver is provided. The transceiver is located on a front side of a semiconductor substrate. A through substrate via provides electrical connection between the transceiver and the receiver located on a backside of the semiconductor substrate. The antenna connected to the transceiver is located in a dielectric layer located on the front side of the substrate. The separation between the reflector plate and the antenna is about the quarter wavelength of millimeter waves, which enhances radiation efficiency of the antenna. An array of through substrate dielectric vias may be employed to reduce the effective dielectric constant of the material between the antenna and the reflector plate, thereby reducing the wavelength of the millimeter wave and enhance the radiation efficiency. A design structure for designing, manufacturing, or testing a design for such a semiconductor chip is also provided. | 10-18-2012 |
| 20130007676 | METHOD FOR THE DEFINITION OF A LIBRARY OF APPLICATION-DOMAIN-SPECIFIC LOGIC CELLS - The present invention provides in one aspect a method of defining a logic cell library composed of complex functions and simple functions, with some of the complex functions obtained from identifying logic function patterns. In another aspect the present invention provides a method of designing a representation of an integrated circuit that uses complex functions and simple functions, with the complex functions including a plurality of non-standard complex Boolean logic functions that are determined to collectively provide for logic pattern minimization. | 01-03-2013 |
| 20130019213 | Method and Apparatus of Hardware Acceleration of EDA Tools for a Programmable Logic Device - Disclosed is a hardware accelerator for development engineering processes for a programmable logic device, such as for an FPGA. | 01-17-2013 |
| 20130019214 | THREE-DIMENSIONAL INTEGRATED CIRCUIT DESIGN DEVICE, THREE-DIMENSIONAL INTEGRATED CIRCUIT DESIGN, METHOD, AND PROGRAMAANM Morimoto; TakashiAACI OsakaAACO JPAAGP Morimoto; Takashi Osaka JPAANM Hashimoto; TakashiAACI FukuokaAACO JPAAGP Hashimoto; Takashi Fukuoka JP - A worst-case temperature calculation unit | 01-17-2013 |
| 20140026107 | METHOD AND SYSTEM FOR OPTIMAL DECOMPOSITION OF SINGLE-QUBIT QUANTUM CIRCUITS USING STANDARD QUANTUM GATES - The current application is directed to methods and systems which produce a design for an optimal approximation of a target single-qubit quantum operation comprising a representation of a quantum-circuit generated from a discrete, quantum-gate basis. The discrete quantum-gate basis comprises standard, implementable quantum gates. The methods and systems employ a database of canonical-form quantum circuits, an efficiently organized canonical-form quantum-circuit, and efficient searching to identify a minimum-cost design for decomposing and approximating an input target quantum operation. | 01-23-2014 |
| 20140075400 | READ-CHANNEL DESIGN AND SIMULATION TOOL HAVING A CODEWORD-CLASSIFICATION MODULE - A computer-aided design method for developing, simulating, and testing a read-channel architecture to be implemented in a VLSI circuit. The method uses codeword/waveform classification to accelerate simulation of the read-channel's error-rate characteristics, with said classification being generated using a first read-channel simulator having a limited functionality. A second read-channel simulator having an extended functionality is then run only for some of the codewords, with the latter having been identified based on said codeword/waveform classification. The acceleration is achieved, at least in part, because the relatively highly time-consuming processing steps implemented in the second read-channel simulator are applied to fewer codewords than otherwise required by conventional simulation methods. | 03-13-2014 |
| 20150121319 | METHODS AND TOOLS FOR DESIGNING INTEGRATED CIRCUITS WITH AUTO-PIPELINING CAPABILITIES - A circuit designer may use computer-aided design (CAD) tools to implement an integrated circuit design. The CAD tools may include auto-pipelining capabilities to improve the performance of the integrated circuit design. Auto-pipelining may modify the number of pipeline registers in a path within a given range. A description of the integrated circuit design may include different implementation alternatives of a path each having a different number of pipeline registers, and the CAD tools may select one of these implementation alternatives. The CAD tools may further evaluate the performance of a particular implementation alternative and iteratively select a different implementation alternative until a given objective is met. The CAD tool may update a test environment according to the selected implementation alternative once the objective is met and validate the selected implementation alternative using the updated test environment. | 04-30-2015 |
| 20160110486 | SYSTEMS AND METHODS FOR FLEXIBLY OPTIMIZING PROCESSING CIRCUIT EFFICIENCY - Circuit design equipment may design logic for a circuit. The design equipment may discover optimized design constraints and an optimized clock signal frequency for the circuit. The design equipment may output the discovered optimized clock signal frequency and design constraints to circuit fabrication equipment for fabricating the corresponding circuit. The design equipment may discover the optimized clock signal frequency and design constraints by populating a cost function with different clock signal frequencies and different design constraint values. The cost function may be, for example, a multi-dimensional surface. The design equipment may identify a global minimum of the cost function and may identify the clock signal frequency and design constraint values that correspond to the global minimum as the optimized clock frequency and optimized design constraints to provide to circuit fabrication equipment. The fabrication equipment may fabricate the circuit to implement the optimized design constraint values and clock frequency. | 04-21-2016 |
| 20160125118 | COMPUTING RESOURCE ALLOCATION BASED ON FLOW GRAPH TRANSLATION - Systems and methods are disclosed for computing resource allocation based on flow graph translation. First, a high-level description of logic circuitry is obtained and translated to generate a flow graph representing sequential operations. Using the flow graph, similar processing elements in an array are interchangeably allocated to perform computational, communication, and storage tasks as needed. The sequential operations are executed using the array of interchangeable processing elements. Data is provided from the storage elements through the communication elements to the computational elements. Computational results are stored in the storage elements. Outputs from some of the computational elements provide inputs to other computational elements. Execution of the instructions can be controlled with time stepping. The processors are reallocated as needed, based on changes to the flow graph. | 05-05-2016 |
