| Entries |
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| 20100313174 | Systems and Methods for Improving the PN Ratio of a Logic Gate by Adding a Non-Switching Transistor - Systems and methods for improving a PN ratio of a logic gate by adding a non-switching transistor. In one embodiment, the logic gate includes a plurality of PMOS switching transistors and a plurality of NMOS switching transistors that are switched on and off by received input signals. The PMOS and NMOS switching transistors are interconnected to perform a logic operation on the input signals and produce a corresponding output signal. The non-switching transistor is inserted in the circuit to improve the ratio of PMOS and NMOS transistors between the power nodes of the logic gate. The non-switching transistor is either a PMOS transistor or an NMOS transistor as needed to make the PN ratio closer to 1. The non-switching transistor is biased to keep it switched on and does not affect the logic functions of the gate. | 12-09-2010 |
| 20100333050 | ANALOG/DIGITAL PARTITIONING OF CIRCUIT DESIGNS FOR SIMULATION - For increasing user control and insight into preparing a mixed-signal semiconductor design specification for simulation, there are provided methods responsive to commands that provide control over resolution of disciplines and partitioning of the design into analog and digital portions. In some aspects, the methods provide block-based assignment of disciplines, as well as design partitioning. In other aspects, the methods provide for resolving a discipline to apply in a block from among multiple possible disciplines. In some aspects, error flagging may be available for detecting disciplines different from what provided for assignment in a block. Assignments may be indicated based on instance, cell, terminal, or library names and may be specified with wild cards. In still other aspects, the methods may be embodied by instructions on computer readable media, and in systems comprising general and special purpose computer hardware that may communicate with various storage facilities and over various networks. | 12-30-2010 |
| 20110029942 | Soft Constraints in Scheduling - A method for implementing soft constraints in scheduling comprises receiving a description of circuit behavior. The description is un-timed. A scheduling solution is generated for use in scheduling the description. The scheduling solution includes scheduling variables and an objective function. The scheduling variables schedule the time of at least one operation. The objective function includes a penalty term and constraints comprising at least one hard constraint and at least one soft constraint. The constraints are created on the scheduling variables. The penalty term comprises a slack variable representing violations of the constraints. The penalty term measures the design cost of violating the soft constraint. Following generation of the scheduling solution, the description is scheduled by applying the scheduling solution to the description. Timing information of the description is provided as an output of the scheduling. | 02-03-2011 |
| 20110078640 | PARAMETERIZED CONFIGURATION FOR A PROGRAMMABLE LOGIC DEVICE - The invention relates to a method and a tool for generating a parameterized configuration for a Field Programmable Gate Array from a Boolean function, the Boolean function comprising at least one parameter argument, comprising the steps generating at least one tunable logic block from the Boolean function and from at least one parameter argument, and mapping the at least one tunable logic block to the Field Programmable Gate Array. This is advantageous since a parameterized configuration can be generated faster than with conventional tools. | 03-31-2011 |
| 20110113392 | PROTECTION OF INTELLECTUAL PROPERTY (IP) CORES THROUGH A DESIGN FLOW - One embodiment provides a method for protecting an integrated circuit chip design. The method can include storing in memory a circuit description of an integrated circuit core comprising a set of nodes and selecting a plurality of modification nodes from the set of nodes. A sequential structure can be inserted into the circuit description to provide a modified circuit description, the sequential structure utilizing the plurality of modification nodes as inputs. The modified circuit description can be stored in memory. | 05-12-2011 |
| 20110119645 | DESIGN VERIFICATION DEVICE - A disclosed device includes a verification unit which performs a data verification of chip design data, an obtaining unit which obtains encryption IP and a verification result output unit which outputs a result of the data verification. The chip design data is designed by using the box IP, the box IP being data which can be disclosed to a chip designer in hardware IP. The encryption IP is the IP including part or all of data of the hardware IP being encrypted. The verification unit decrypts the encryption IP to the hardware IP and replaces the box IP of the chip design data with the decrypted hardware IP so as to perform the data verification, in the storage area such as RAM where storage data is hidden from outside. | 05-19-2011 |
| 20110119646 | Integrated circuits design - This invention concerns an automated method of generating a design for an I/O fabric of a target integrated circuit having a core and pins. A process tool executes algorithms to generate a synthesizable representation of the I/O fabric ring in hardware description language. It imports integrated circuit design data, and from it captures I/O specification data for a circuit core, library of cells, pin, I/O control, BSR and I/O cell chaining, and die. The tool validates the specification data, and generates the I/O fabric design by configuring and inter-connecting a pin multiplexing and control matrix structures according to constraints for signal control, and timing. The structures includes on both the input and output paths of each pin a functional multiplexer matrix structure, a test multiplexer matrix structure, an override matrix structure, a multiplex select and control matrix structure, and an I/O Cell control logic. A required pin output circuit is configurable by modification of the I/O specification data, and/or, modification of a manner of wiring the algorithms, and/or by modification of the algorithms. The tool wires algorithms according to a wiring framework, and said wiring framework is modifiable. | 05-19-2011 |
| 20110145770 | Device Annotation - An electronic design automation process, such as a layout-verses-schematic analysis process, may recognize a representation of a device from physical layout design data. Information, such as geometric information separately obtained from the physical layout design data, is then associated with the recognized device representation. The associated information can subsequently be used in a later electronic design automation operation involving the recognized device representation. | 06-16-2011 |
| 20110161896 | BACK-END-OF-LINE RESISTIVE SEMICONDUCTOR STRUCTURES - In one embodiment, a back-end-of-line (BEOL) resistive structure comprises a second metal line embedded in a second dielectric layer and overlying a first metal line embedded in a first dielectric layer. A doped semiconductor spacer or plug laterally abutting sidewalls of the second metal line and vertically abutting a top surface of the first metal line provides a resistive link between the first and second metal lines. In another embodiment, another BEOL resistive structure comprises a first metal line and a second metal line are embedded in a dielectric layer. A doped semiconductor spacer or plug laterally abutting the sidewalls of the first and second metal lines provides a resistive link between the first and second metal lines. | 06-30-2011 |
| 20110161897 | METHOD AND APPARATUS FOR SIMULATING BEHAVIORAL CONSTRUCTS USING INDETERMINATE VALUES - One embodiment of the present invention provides a system that simulates behavioral constructs of a register transfer level design using indeterminate values. The system may receive hardware description language code which includes a construct that behaves differently depending on the value of an expression, e.g., the construct may execute different portions of code based on the value of a control expression, or it may store data in different storage locations based on the value of an index expression, etc. In response to determining that the expression's value is indeterminate, the system can execute two or more alternatives that are controlled by the expression, and then merge the results in some prescribed way. An embodiment of the present invention can enable a user to reduce the discrepancy between the results generated by a register transfer level simulation and the results generated by the associated gate level simulation. | 06-30-2011 |
| 20110173580 | Nonlinear Driver Model For Multi-Driver Systems - A precharacterized cell library for EDA tools includes driver model data includes output current signals indexed by output voltages. The driver model can then generate a model output by interpolating the output current signals using the output voltage to generate an output current. The output current can then be used to generate an updated output voltage across a predetermined time increment. The output current signals can then be interpolated using the updated output voltage to generate a new output current, when can be used to update the output voltage once again across the next time increment. By repeating this process across a time frame for the model output signal, a model output current and output voltage signals can be generated that match the actual output current and voltage signals from a driver in a multi-driver system. | 07-14-2011 |
| 20110209108 | Device, Method, and Computer Program for LSI Design, and LSI - The LSI design apparatus | 08-25-2011 |
| 20110214095 | DECOMPOSITION BASED APPROACH FOR THE SYNTHESIS OF THRESHOLD LOGIC CIRCUITS - Systems and methods for identifying a Boolean function as either a threshold function or a non-threshold function are disclosed. In one embodiment, in order to identify a Boolean function as either a threshold function or a non-threshold function, a determination is first made as to whether the Boolean function satisfies one or more predefined conditions for being a threshold function, where the one or more predefined conditions include a condition that both a positive cofactor and a negative cofactor of the Boolean function are threshold functions. If the one or more predefined conditions are satisfied, a determination is made as to whether weights for the positive and negative cofactors are equal. If the weights for the cofactors are equal, then the Boolean function is determined to be a threshold function. Further, in one embodiment, this threshold function identification process is utilized in a threshold circuit synthesis process. | 09-01-2011 |
| 20110219343 | Converting Portions of a Software Program Executing on a Processing System to Hardware Descriptions - System and method for developing an ASIC. A software program may be stored which includes program instructions which implement a function. The software program may be executed on a processing system at a desired system speed and may be validated based on the execution. A first hardware description of at least a portion of the processing system may be stored and may specify implementation of at least a portion of the processing system. A second hardware description may be generated that corresponds to a first portion of the first hardware description. The second hardware description may specify a dedicated hardware implementation of a first portion of the software program executing on the processing system. Generation of the second hardware description may be performed one or more times to fully specify the ASIC. An ASIC may be created which implements the function of the software program. | 09-08-2011 |
| 20110246954 | METHOD AND APPARATUS FOR ANALYZING FAULT BEHAVIOR - An apparatus for analyzing a fault behavior, includes a satisfiability modulo theories (SMT) conversion block for performing SMT conversion with respect to a protocol state machine diagram and a sequence diagram of a software design model. Further, the apparatus for analyzing the fault behavior includes an SMT processing block for performing a SMT processing using respective logic formulas corresponding to the protocol state machine diagram and the sequence diagram and outputted from the SMT conversion block, and determining whether the result of the SMT processing is satisfied to output an occurrable behavior scenario when the result of the SMT processing is satisfied. | 10-06-2011 |
| 20110271241 | JOINT IMPLEMENTATION OF INTELLECTUAL PROPERTIES (IPs) IN A SYSTEM-ON-A-CHIP (SOC) - A method includes jointly implementing a number of Intellectual Property (IP) sub-systems in a virtual design associated with one or more System-on-a-Chip(s) (SoC(s)) utilizing a design platform. Each sub-system of the number of IP sub-systems is associated with an IP configured to be a deliverable to the one or more SoC(s). The method also includes maintaining each sub-system of the number of IP sub-systems as an independent entity in the virtual design through an appropriate handling of a design closure and a timing closure. IPs associated with two or more IP sub-systems of the virtual design are related or unrelated to one another. ea | 11-03-2011 |
| 20110276929 | DESIGNING APPARATUS, DESIGNING METHOD, AND COMPUTER READABLE MEDIUM STORING DESIGNING PROGRAM - A designing apparatus is used with a simulator simulating a behavior description describing behavior of a semiconductor integrated circuit, and a high-level synthesis apparatus allocating a variable described in the behavior description to a register and generating a register transfer level description based on the allocated variable. The apparatus includes an input module, a calculation module, and an estimation module. The input module inputs a simulation result of the simulator and a binding result comprising a variable name of the allocated variable to be stored into the register. The calculation module calculates a rate of change of the allocated variable to be stored into the register in one clock cycle based on the simulation result and the binding result. The estimation module estimates power consumption of the semiconductor integrated circuit corresponding to the behavior description based on the rate. | 11-10-2011 |
| 20110314432 | METHOD AND SYSTEM FOR IMPLEMENTING EFFICIENT LOCKING TO FACILITATE PARALLEL PROCESSING OF IC DESIGNS - Disclosed is an improved method and system for implementing parallelism for execution of electronic design automation (EDA) tools, such as layout processing tools. Examples of EDA layout processing tools are placement and routing tools. Efficient locking mechanism are described for facilitating parallel processing and to minimize blocking. | 12-22-2011 |
| 20110320990 | LOGIC-DRIVEN LAYOUT VERIFICATION - A check for determining the appropriateness of physical design data is provided, where the check includes both a physical component and a logical component. Based upon the logical component of the check, portions of the physical design data that correspond to the logical component are identified and selected. After the portions of the physical design data corresponding to the logical component have been selected, this physical design data can be provided to a physical design analysis tool, along with the physical component of the design check. The physical design analysis tool can then use the physical component of the design check to perform an analysis of the selected physical design data. | 12-29-2011 |
| 20120023465 | METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR IMPLEMENTING ELECTRONIC CIRCUIT DESIGNS WITH SIMULATION AWARENESS - Disclosed are methods, systems, and articles of manufacture for implementing electronic designs with simulation awareness. A schematic is identified or created and simulated at the schematic level to characterize the functional behavior of the circuit or to ensure the circuit design meets the required design specifications. Physical data of a component of the design is identified, created, or updated, and the electrical parasitic associated with physical data is characterized. One or more electrical characteristics associated with the parasitic is further characterized and mapped to the simulator to re-simulate the circuit design to analyze the impact of parasitics. Some embodiments re-run the same simulation process incrementally in an interactive manner by accepting incremental design or parameter changes from the design environment. | 01-26-2012 |
| 20120066654 | STABILITY-DEPENDENT SPARE CELL INSERTION - Spare cells are placed in an IC design using stability values associated with logic cones of the design. A desired spare cell utilization rate is assigned to a cone based on its stability value, and an actual spare cell utilization rate for the cone bounding box is calculated. If the actual utilization rate is less than the desired utilization rate, additional spare cells are inserted as needed to attain the desired utilization rate. The stability value is provided by a logic or circuit designer, or derived from historical information regarding the logic cone in a previous design iteration. Spare cells are placed for each logic cone in the design until a global spare cell utilization target is exceeded. The spare cell placement method can be an integrated part of a placement directed synthesis which is followed by early mode padding and design routing. | 03-15-2012 |
| 20120066655 | ELECTRONIC DEVICE AND METHOD FOR INSPECTING ELECTRICAL RULES OF CIRCUIT BOARDS - An electronic device and method for inspecting electrical rules of circuit boards includes selecting at least two design files that record electrical rules of the circuit boards and searching the electrical rules in the selected design files using preset parameter keywords. Same electrical rules of the selected design files are acquired by comparing the electrical rules in the selected design files. The same electrical rules and corresponding parameter values are input to a comparison table, and the comparison table is output. | 03-15-2012 |
| 20120072876 | METHOD AND APPARATUS FOR REDUCING X-PESSIMISM IN GATE-LEVEL SIMULATION AND VERIFICATION - Methods and apparatuses are described for reducing or eliminating X-pessimism in gate-level simulation and/or formal verification. A system can identify a set of reconvergent inputs of a combinational block in a gate-level design. Next, the system can determine whether or not the combinational block is expected to exhibit X-pessimism during gate-level simulation. If the combinational block is expected to exhibit X-pessimism during gate-level simulation, the system can modify the gate-level design to reduce X-pessimism during gate-level simulation. In some embodiments, the system can build a model for the gate-level design by using unique free input variables to represent sources of indeterminate values. The system can then use the model to perform formal verification. | 03-22-2012 |
| 20120079437 | CIRCUIT DESIGN SYSTEMS FOR REPLACING FLIP-FLOPS WITH PULSED LATCHES - A circuit design system, methodology, and software are disclosed for generating circuit capable of consuming less dynamic power. In particular, the circuit design methodology entails modifying an initial circuit design including a clock network coupled to a plurality of edge-triggered flip-flops to generate a modified circuit design that uses pulsed latches driven by pulse generators in place of at least some of the flip-flops. Since pulsed latches use less dynamic power than edge-triggered flip-flops, the modified circuit may consume less dynamic power. The circuit design methodology may further entail adding delay cells for balancing the clock network to compensate for timing effects caused by the insertion of pulse generators. Additionally, the methodology may further include cloning of forbidden clock paths to make more flip-flops eligible for pulsed latch replacement. | 03-29-2012 |
| 20120084743 | METHOD AND APPARATUS FOR IMPROVING THE INTERCONNECTION AND MULTIPLEXING COST OF CIRCUIT DESIGN FROM HIGH LEVEL SYNTHESIS USING ANT COLONY OPTIMIZATION - A method and apparatus for improving the interconnection and multiplexing cost of circuit design from high level synthesis using ant colony optimization is described. In one example, a plurality of hardware components for performing an operation is represented with a data flow graph having edges and nodes. A plurality of solutions are simulated for performing the operation as hardware component and schedule combinations represented as paths on the data flow graph. For each solution, cost including a number of edges and nodes traversed on the data flow graph and an interconnection cost related to the number of different hardware components in the path is determined. A pheromone trail is associated with each path, the pheromone trail including a cost of the respective scheduling solution, and a solution is selected with the highest value pheromone trail as a hardware component and schedule combination for a circuit. | 04-05-2012 |
| 20120089954 | METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCT FOR PARALLELIZING TASKS IN PROCESSING AN ELECTRONIC CIRCUIT DESIGN - Disclosed are a method, a system, and a computer program product for implementing compact manufacturing model during various stages of electronic circuit designs. In some embodiments, the method loads the full design database information on the master; distributes the tasks to be processed in parallel; loads a full design on a master; spawns a plurality of slave sessions; sends to at least one slave a nutshell representation of the electronic circuit design; identifies a task to perform in parallel and sends the task to be performed in parallel; and receives execution results or processing results from some of the plurality of slaves and updates one or more databases to incorporate the execution or processing results. In some embodiments, the method allows speeding up the applications without major rewrite without a need for design partition, and without memory penalty. | 04-12-2012 |
| 20120096416 | HIGH-TEMPERATURE DEVICES ON INSULATOR SUBSTRATES - Semiconductor devices, logic devices, libraries to represent logic devices, and methods for designing and fabricating the same are disclosed. The semiconductor devices include a substrate comprising sapphire or diamond, an active layer disposed on the substrate, the active layer having a thickness tSi and comprising a channel region having a length L, where L/tSi is above 7 and an oxide layer disposed on the active layer. | 04-19-2012 |
| 20120110525 | HYBRID ELECTRONIC DESIGN SYSTEM AND RECONFIGURABLE CONNECTION MATRIX THEREOF - A hybrid electronic design system and a reconfigurable connection matrix thereof are disclosed. The electronic design system includes a virtual unit, a hybrid unit and a communication channel. The virtual unit further includes a plurality of proxy units, a plurality of virtual components and a driver. The virtual components are connected with the driver via the proxy units. The hybrid unit further includes an emulate unit, a physical unit and a chip level transactor. The chip level transactor is connected with the emulate unit and the physical unit. The communication channel is connected with the driver of the virtual unit and the chip level transactor of the hybrid unit. | 05-03-2012 |
| 20120117524 | REUSABLE STRUCTURED HARDWARE DESCRIPTION LANGUAGE DESIGN COMPONENT - A method includes removing a code segment from a hardware description language design to create a modified hardware description language design. The code segment represents at least one time sensitive path in the hardware description language design. The method includes creating a delta list of differences between the modified hardware description language design and a physical hardware representation that is logically equivalent to the hardware description language design. The method includes extracting a portion of the physical hardware representation that corresponds to the time sensitive path based, at least in part, on the delta list. The method also includes creating a structured hardware description language design of the time sensitive path using the extracted portion of the physical hardware representation, wherein the structured hardware description language design comprises structural information of the extracted portion of the physical hardware representation. | 05-10-2012 |
| 20120131523 | METHOD OF GENERATING AN INTELLECTUAL PROPERTY BLOCK DESIGN KIT, METHOD OF GENERATING AN INTEGRATED CIRCUIT DESIGN, AND SIMULATION SYSTEM FOR THE INTEGRATED CIRCUIT DESIGN - The present application discloses a method of generating an intellectual property (IP) block design kit including an IP block circuit design and a system-level characteristics table for manufacturing an integrated circuit. According at least one embodiment, the IP block circuit design is generated. The IP block circuit design is simulated based on predetermined configuration sets, and each configuration set has manufacturing options and/or operating conditions. A plurality of system-level models for the predetermined configuration sets are generated based on the simulation of the IP block circuit design. The system-level characteristics table is generated by arranging the predetermined configuration sets and the system-level models in compliance with a system-level characteristics table template of a system-level characteristics modeling device. Then the IP block circuit design and the system-level characteristics table are stored as the IP block design kit. | 05-24-2012 |
| 20120144352 | CIRCUIT DESIGN APPROXIMATION - A circuit design, responsive the input signals, may be obtained and processed. The circuit design may define connections between combinational elements, memory elements, and input signals. Identification of cut-off points may be performed with respect to predetermined combinational logic input signals. The cut-off points may be connections whose values are not dependant on the value of the predetermined combinational logic input signals. An approximated circuit design may be synthesized by relaxing the logic associated with the cut-off points. Based on the approximated circuit design, processing may be performed. In some exemplary embodiments, a clock gating function of a memory element may be determined by approximating the circuit design with respect to the output signal of the memory element. The clock gating function may be determined based on the approximated circuit design and introduced to the circuit design, with or without additional refinement. | 06-07-2012 |
| 20120180010 | METHOD OF FABRICATING A DEVICE USING LOW TEMPERATURE ANNEAL PROCESSES, A DEVICE AND DESIGN STRUCTURE - A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device. | 07-12-2012 |
| 20120185808 | Method and System for Automatic Generation of Processor Datapaths - Systems and method for automatically generating a set of shared processor datapaths from the description of the behavior of one or more ISA operations is presented. The operations may include, for example, the standard operations of a processor necessary to support an application language such as C or C++ on the ISA. Such operations, for example, may represent a configurable processor ISA. The operations may also include one or more extension operations defined by one or more designers. Thus, a description of the behaviors of the various standard and/or extension operations that compose the ISA of an instance of a standard or configurable processor is used to automatically generate a set of shared processor datapaths that implement the behavior of those operations. | 07-19-2012 |
| 20120192128 | Compiler for Closed-Loop 1xN VLSI Design - Embodiments that design integrated circuits using a 1×N compiler in a closed-loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a first generator to generate a behavioral representation of a design for an integrated circuit, a second generator to generate a logical representation of the design, and a third generator to generate a physical design representation of the design, wherein the representation generators may create updated versions of the representations which reflect alterations made to 1×N building block elements. | 07-26-2012 |
| 20120192129 | Compiler for Closed-Loop 1xN VLSI Design - Embodiments that design integrated circuits using a 1×N compiler in a closed-loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a first generator to generate a behavioral representation of a design for an integrated circuit, a second generator to generate a logical representation of the design, and a third generator to generate a physical design representation of the design, wherein the representation generators may create updated versions of the representations which reflect alterations made to 1×N building block elements. | 07-26-2012 |
| 20120192130 | CIRCUIT DESIGN APPROXIMATION - A circuit design, responsive the input signals, may be obtained and processed. The circuit design may define connections between combinational elements, memory elements, and input signals. Identification of cut-off points may be performed with respect to predetermined combinational logic input signals. The cut-off points may be connections whose values are not dependant on the value of the predetermined combinational logic input signals. An approximated circuit design may be synthesized by relaxing the logic associated with the cut-off points. Based on the approximated circuit design, processing may be performed. In some exemplary embodiments, a clock gating function of a memory element may be determined by approximating the circuit design with respect to the output signal of the memory element. The clock gating function may be determined based on the approximated circuit design and introduced to the circuit design, with or without additional refinement. | 07-26-2012 |
| 20120192131 | Partial Hardening of a Software Program from a Software Implementation to a Hardware Implementation - System and method for developing an ASIC. A software program may be stored which includes program instructions which implement a function. The software program may be executed on a processing system at a desired system speed and may be validated based on the execution. A first hardware description of at least a portion of the processing system may be stored and may specify implementation of at least a portion of the processing system. A second hardware description may be generated that corresponds to a first portion of the first hardware description. The second hardware description may specify a dedicated hardware implementation of a first portion of the software program executing on the processing system. Generation of the second hardware description may be performed one or more times to fully specify the ASIC. An ASIC may be created which implements the function of the software program. | 07-26-2012 |
| 20120198397 | ABSTRACTION-BASED LIVELOCK/DEADLOCK CHECKING FOR HARDWARE VERIFICATION - Some embodiments of the present invention provide systems and techniques for checking a livelock in a circuit design. During operation, the system can identify a finite state machine (FSM) in the circuit design, wherein the FSM comprises a first set of state variables. The system can then construct an abstract machine of the circuit design, wherein the abstract machine includes the FSM and a second set of state variables. Next, the system can search for one or more livelocks in the abstract machine. If a livelock is found in the abstract machine, the system can verify that the livelock is a livelock in a concrete machine of the circuit design, wherein the concrete machine includes the FSM and a third set of state variables, wherein the second set of state variables is a subset of the third set of state variables. | 08-02-2012 |
| 20120198398 | Equivalence Checking for Retimed Electronic Circuit Designs - Techniques and technology for formally verifying a first electronic design with a second electronic design that has been synthesized from the first electronic design, wherein the synthesis process included structural transformation operations, is provide herein. In various implementations, a first design and a second design are received. The second design having been synthesized from the first design, where no structural transformation operations were performed during synthesis of the second design. Additionally, a third design and a structural transformation guidance file are received. The third design having also been synthesized from the first design, but, where structural transformation operations were performed during synthesis of the third design. The structural transformation guidance file specifies what transformations where made during synthesis. Subsequently, a first formal verification process is implemented to verify the equivalence of the first design to the second design using conventional formal verification proofs. A modified second design is then generated, by applying changes to the second design to correspond to the structural transformations detailed in the structural transformation guidance file. After which, a second formal verification process is implemented to verify the equivalence of the third design and the modified second design. | 08-02-2012 |
| 20120240087 | Voltage Drop Effect On Static Timing Analysis For Multi-Phase Sequential Circuit - In the present invention a method to address voltage drop effect in the path based timing analysis for multi-phase sequential circuit is proposed. In calculating the new delay of the gate along the specified path the fact that stored discrete arrival times with respect to different clock phases at each node is used to determine a set of gates that can have transitions overlapping with that of the said gate. Furthermore, the said set is reduced by the logic verification step. Two step approach is adopted, the first is to evaluate the power currents for the said reduced set of gates by using pre-characterized timing library, then use these currents to calculate new VDD of the said gate along the path and obtain new delay for this gate. Some cell may have several internal transitions, the process of modeling power currents in terms of several triangles is discussed. | 09-20-2012 |
| 20120254814 | HIGH-FREQUENCY VLSI INTERCONNECT AND INTENTIONAL INDUCTOR IMPEDANCE EXTRACTION IN THE PRESENCE OF A MULTI-LAYER CONDUCTIVE SUBSTRATE - Embodiments of methods, apparatus, and systems for extracting impedance for a circuit design are disclosed herein. Some of the disclosed embodiments are computationally efficient and can accurately compute the frequency-dependent impedance of VLSI interconnects and/or intentional inductors in the presence of multi-layer conductive substrates. In certain embodiments, the resulting accuracy and CPU time reduction are a result of a Green's function approach with the correct quasi-static limit, a modified discrete complex image approximation to the Green's function, and a continuous dipole expansion to evaluate the magnetic vector potential at the distances relevant to VLSI interconnects and intentional inductors. | 10-04-2012 |
| 20120278771 | Logic modification synthesis for high performance circuits - A method for IC modification is disclosed. The method recognizes an original HDL file prescribing an original logic, an original netlist incorporating the original logic, and a new HDL file prescribing a new logic. The new logic comprises desired logic changes relative to the original logic. If a signal is different between the new HDL file and the original HDL file the method adds a user hint to both the original HDL file and the new HDL file. Using the original HDL file, the original netlist, the new HDL file, and the user hints, the method synthesizes a delta netlist for inserting into the original netlist, whereupon this insertion the original netlist will incorporate the new logic. | 11-01-2012 |
| 20120290991 | SYSTEM AND METHOD FOR BLOCK INSTANTIATION - Systems and methods for block instantiation are provided. In one embodiment, a system includes a processor and a visual instantiation facility executable by the processor. The visual instantiation facility is configured to read a device definition (DD) file including at least one function block and to visually display function block instantiation information of the at least one function block in a visual display. The visual instantiation facility is further configured to instantiate the at least one function block in a field device. | 11-15-2012 |
| 20120297350 | CHIP SIZE ESTIMATING APPARATUS FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND CHIP SIZE ESTIMATING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT - A chip size estimating apparatus for a semiconductor integrated circuit of an embodiment has an input section configured to input a minimum number of functional gates that is a minimum number of gates necessary for realization of a function of a circuit, a set value holding section in which a performance-considered number-of-gates coefficient that is a ratio of a number of gates to be necessary for achievement of a predetermined operation speed to the minimum number of functional gates is set in advance for each cell library, and a calculating section configured to estimate a total area of the circuit by using a number of gates that is calculated from the minimum number of functional gates and the performance-considered number-of-gates coefficient. | 11-22-2012 |
| 20120317525 | IDENTIFYING HIERARCHICAL CHIP DESIGN INTELLECTUAL PROPERTY THROUGH DIGESTS - One method implementation disclosed includes detecting matching leaf cells that are functionally identical (optionally, functionally similar) and assigning matching names for the matching leaf cells to replace original, non-matching names. Optionally, digests can be calculated for the leaf cells and used to detect similarities and/or differences. The matching names are propagated to at least some higher-level cells in the hierarchical design, in place of the original names. The method can further include calculating digests for at least some of the higher level cells after the propagating of the matching names into the higher level cells. Various design matching technologies can be used in combination with cell renaming and new name propagation, not limited to use of digests. Dependency chains can be calculated to improve propagation of names through the hierarchy. | 12-13-2012 |
| 20120324408 | System and Method for a Chip Generator - A chip generator according to an embodiment of the present invention codifies designer knowledge and design trade-offs into a template that can be used to create many different chips. Like reconfigurable designs, an embodiment of the present invention fixes the top level system architecture, amortizes software and validation and design costs, and enables a rich system simulation environment for application developers. Meanwhile, below the top level, the developer can “program” the individual inner components of the architecture. Unlike reconfigurable chips, a chip generator according to an embodiment of the present invention, compiles the program to create a customized chip. This compilation process occurs at elaboration time—long before silicon is fabricated. The result is a framework that enables more customization of the generated chip at the architectural level because additional components and logic can be added if the customization process requires it. | 12-20-2012 |
| 20120331431 | Symbolic Switch/Linear Circuit Simulator Systems and Methods - Interactive and real time web-based electrical circuit symbolic solvers and simulators. The invention includes an interactive and innovative graphical user interface (GUI) for creating circuit schematics and generating netlists, circuits symbolic solving and instant simulated solutions, their systems and methods. Users such as students can use GUI interfaces to remotely access a remote server controlled by educational institutions such as universities, or electronic book publishers, in order to draw, symbolically solve, and instantly simulate electrical circuits. | 12-27-2012 |
| 20130007677 | Method of implementing IEC 61131-3 control specification through verilog HDL description for modeling, simulation and synthesis of control logic configuration for integrated circuit implementation - The present invention relates to a method of implementing an IEC 61131-3 control specification through Verilog HDL description comprising the steps of (a) creating user interface for the control specification including languages covered under the IEC 61131-3, particularly ladder diagram, functional block diagram, sequential flow charts, structured text or instruction set listing; (b) generating a list of network interconnections with reference to the above referred languages; (c) generating logic equations using the aforesaid list of network interconnections generated at step (b) above; (d) generating Verilog HDL code snippets in accordance with the IEC 61131-3; (e) generating Verilog HDL code representing hardware with PLC functionality through said control specification by using the Verilog HDL code snippets generated at step (d), the logic equations at step (c) and the network interconnections at step (b). | 01-03-2013 |
| 20130019215 | SYSTEMS AND METHODS FOR OPTIMIZING BOOLEAN LOGIC USING ORGANICALLY-GROWN KARNAUGH MAPS - Systems and methods for optimizing Boolean logic are provided. The systems generate a one-dimensional array having a plurality of values corresponding to a plurality of indices, and determine a first location of a Karnaugh map in a first dimension thereof. The first location is determined using a first value of the one-dimensional array corresponding to a first index of the one-dimensional array. The systems also determine a second location of the Karnaugh map in a second dimension thereof. The second location is determined using a second value of the one-dimensional array corresponding to a second index of the one-dimensional array. The systems evaluate a target location within the Karnaugh map corresponding to the first and second indices in the first and second dimensions of the Karnaugh map, respectively, and search for at least one of a simplified minterm and a simplified implicant having the target location using the one-dimensional array. | 01-17-2013 |
| 20130024826 | PROFILING OF SOFTWARE AND CIRCUIT DESIGNS UTILIZING DATA OPERATION ANALYSES - The present invention is a method, system, software and data structure for profiling programs, other code, and adaptive computing integrated circuit architectures, using a plurality of data parameters such as data type, input and output data size, data source and destination locations, data pipeline length, locality of reference, distance of data movement, speed of data movement, data access frequency, number of data load/stores, memory usage, and data persistence. The profiler of the invention accepts a data set as input, and profiles a plurality of functions by measuring a plurality of data parameters for each function, during operation of the plurality of functions with the input data set, to form a plurality of measured data parameters. From the plurality of measured data parameters, the profiler generates a plurality of data parameter comparative results corresponding to the plurality of functions and the input data set. Based upon the measured data parameters, portions of the profiled code are selected for embodiment as computational elements in an adaptive computing IC architecture. | 01-24-2013 |
| 20130061189 | TECHNIQUES FOR OPTIMIZING STRINGING OF SOLAR PANEL MODULES - Embodiments of the present invention include systems and methods for performing design automation on a mobile computer system. In one example embodiment the present invention includes a computer-implemented method comprising storing design automation data on a mobile device, displaying a plurality of design automation process steps to a user, the plurality of design automation process steps guiding the user through a design automation process for a project, receiving design automation input data from the user in the mobile device for a plurality of the design automation process steps, executing one or more data processing algorithms specific to at least one of the design automation process steps, and generating output data for the design project. | 03-07-2013 |
| 20130111422 | MANAGING CONSISTENCY OF MULTIPLE-SOURCE FABRICATION DATA IN AN ELECTRONIC DESIGN ENVIRONMENT | 05-02-2013 |
| 20130125071 | CIRCUIT COMPONENT MIGRATION APPARATUS, CIRCUIT COMPONENT MIGRATION PROGRAM, AND CIRCUIT COMPONENT MIGRATION METHOD - An circuit-component-migration-apparatus includes a storage unit that stores correspondence information indicating a circuit component of a migration destination corresponding to a circuit component of a migration source, an identification unit that identifies a circuit component of the migration destination corresponding to a circuit component that is a target to be migrated based on the correspondence information, a comparison unit that compares a shape of a symbol representing the circuit component identified by the identification unit of the migration destination with a shape of a symbol representing the circuit component that is a target to be migrated, and a registration unit that associates the symbol representing the circuit component that is a target to be migrated with the identified circuit component of the migration destination and registers the associated symbol and identified circuit component in component information indicating a circuit component of the migration destination when the shapes are different. | 05-16-2013 |
| 20130132915 | NETWORK FLOW BASED DATAPATH BIT SLICING - The present disclosure relates to a computer-based method and apparatus for determining datapath bit slices. A first two-way search is performed between an input vector and an output vector to identify gates in a datapath. A network flow is then constructed including the gates identified, and a min-cost max-flow algorithm is applied to the network flow to derive matching bit pairs between the input vector and the output vector. Next, the datapath bit slices are determined by performing a second two-way search between each of a starting bit in the input vector and an ending bit in the output vector of each of the matching bit pairs. | 05-23-2013 |
| 20130145328 | AUTOMATED SCALABLE VERIFICATION FOR HARDWARE DESIGNS AT THE REGISTER TRANSFER LEVEL - A system and methods are provided for verifying a hardware design for an electronic circuit. The method may include: providing a hardware design description for the electronic circuit; extracting a set of design constraints from the hardware design description, where the set of design constraints represents the electronic circuit in terms of signals and logical operations performed on the signals; creating an abstraction model from the set of design constraints, where the abstraction model abstracts one or more of the logical operations in the set of design constraints by replacing the abstracted logical operations with uninterpreted functions; and property checking the abstraction model in relation to one or more design properties. When a violation in the electronic circuit is detected by the property checking step, the feasibility of the violation is then checked and, if the violation is deemed infeasible, the abstraction model is refined. | 06-06-2013 |
| 20130152028 | NATIVE THRESHOLD VOLTAGE SWITCHING - A computer-implemented method of determining threshold voltage levels within a macro of integrated circuit cells. In one embodiment, the method includes: referencing a library of the integrated circuit cells in the macro; estimating a leakage power and a dynamic power for a first integrated circuit cell in the macro; comparing the leakage power with the dynamic power; switching the first integrated circuit cell to a low threshold voltage level in response to determining the dynamic power is greater than the leakage power; and updating the library with a voltage level of the first integrated circuit cell. | 06-13-2013 |
| 20130174107 | DESIGN TOOL FOR GLITCH REMOVAL - Embodiments of an electronic design automation system are generally described herein. In some embodiments, glitch-sensitive nodes in an integrated circuit design are identified. For each glitch-sensitive node, a circuit fanin cone is analyzed to look for circuit structures that can produce glitches. The integrated circuit design can be simulated and modified if the simulation indicates that a glitch would occur in the integrated circuit design. | 07-04-2013 |
| 20130179849 | Automated Circuit Design For Generation of Stability Constraints for Generically Defined Electronic System with Feedback - A method is described that involves accepting a description of an electronic system having feedback. The method further includes expressing a real root of the electronic system's transfer function and expressing a real part of a complex root of the electronic system's transfer function. The method further includes expressing a time parameter as a maximum of the real root and the real part of a complex root. The method further involves expressing a settling time of the electronic system with the time parameter and using the settling time to automatically generate a design for the electronic system. | 07-11-2013 |
| 20130185682 | SYSTEM AND METHOD FOR INFERRING HIGHER LEVEL DESCRIPTIONS FROM RTI TOPOLOGY BASED ON NAMING SIMILARITIES AND DEPENDENCY - A system and methods are disclosed for inferring higher level descriptions of circuit connectivity from register transfer level (RTL) netlists in order to provide more understandable and manageable design descriptions for complex System-on-Chip (SOC) designs. In particular, rule-based interface matching is automatically performed by analyzing actual port names on instances of functional elements and blocks to form signal groupings that comprise a higher-level abstracted description. An example syntax is provided for defining rules that are used to define how various analysis are performed. Data describing standard interfaces on common Intellectual Property (IP) blocks is optionally made available to facilitate interface matching. Also, a facility is included to allow user-guided mapping on instantiated interfaces with respect to actual port names in an RTL-level design. | 07-18-2013 |
| 20130191797 | METHOD AND APPARATUS OF DESIGNING SEMICONDUCTOR CHIP - Disclosed are a method and an apparatus of designing a semiconductor chip. The disclosed method includes the steps of: storing a plurality of EMS (Electro Magnetic Susceptibility) semiconductor IPs (Intellectual Property) and a plurality of EMI (Electro Magnetic Interference) semiconductor IPs; selecting a proper semiconductor IP from among the plurality of EMS shielding semiconductor IPs in a case of an input pin, and selecting a proper semiconductor IP from among the plurality of EMI shielding semiconductor IPs in a case of an output pin; and designing the semiconductor chip by disposing the selected semiconductor IP. | 07-25-2013 |
| 20130198701 | Single Event Upset Mitigation for Electronic Design Synthesis - Technology is disclosed herein that provides for modifying a circuit design to reduce the potential occurrence of single event upset errors during operation of a device manufactured from the synthesized design. After a circuit design has been synthesized to a particular abstraction level, a static timing analysis procedure is run on the design. The slack values for paths within the design are determined based upon the static timing analysis procedure. Subsequently, delays are added to selected paths within the design based upon the slack values. | 08-01-2013 |
| 20130205268 | VALIDATING INTERCONNECTIONS BETWEEN LOGIC BLOCKS IN A CIRCUIT DESCRIPTION - Disclosed is a program for creating a checking-statement which can be subsequently used to validate interconnections between logic blocks in a circuit design. The checking-statement is created by taking a description of how logic blocks in a circuit design are associated to one another (if at all), and cross referencing the description with rule statements specific to each logic block defining the allowable connections between the specific logic block and other logic blocks. | 08-08-2013 |
| 20130205269 | SYSTEM AND METHOD FOR MANAGING TIMING MARGIN IN A HIERARCHICAL INTEGRATED CIRCUIT DESIGN PROCESS - A system for, and method of, generating block timing constraints and a timing model. In one embodiment, the system includes a hierarchical modeling tool configured to: (1) generate a model file, (2) receive at least one abstracted view margin, at least one timing environment margin and at least one operational margin for inclusion in the model file, (3) generate block implementation timing constraints employing the at least one timing environment margin and the at least one operational margin and (4) generate a block timing model employing the at least one abstracted view margin and the at least one operational margin. | 08-08-2013 |
| 20130205270 | EDITING SYSTEM - An editing system includes a database server apparatus having product specification management data stored therein; and a terminal apparatus including: a display part displaying a function tree and an IO table, the function tree hierarchically indicating elements along with attributes of each of the elements based on the product specification management data and having a product name as a root of the function tree, and the IO table indicating connection data between each pin of the elements based on the product specification management data, an accepting part accepting an operation to connect one element to another element, an operation to display connection data between the elements, and an operation to edit each item of the connection data of the IO table, and an updating part updating the connection data of the product specification management data in accordance with the operations accepted by the operation accepting part. | 08-08-2013 |
| 20130227501 | SEMICONDUCTOR DEVICE DESIGN METHOD, SYSTEM AND COMPUTER-READABLE MEDIUM - In a semiconductor device design method performed by at least one processor, first and second electrical components are extracted from a layout of a semiconductor device. The semiconductor device has a semiconductor substrate and the first and second electrical components in the semiconductor substrate. Parasitic parameters of a coupling in the semiconductor substrate between the first and second electrical components are extracted using a first tool. Intrinsic parameters of the first and second electrical components are extracted using a second tool different from the first tool. The extracted parasitic parameters and intrinsic parameters are combined into a model of the semiconductor device. The parasitic parameters of the coupling are extracted based on a model of the coupling included in the second tool. | 08-29-2013 |
| 20130227502 | ALGORITHM OF CU INTERCONNECT DUMMY INSERTING - The present invention disclosed an algorithm of Cu interconnect dummy inserting, including: divide the surface of semiconductor chip into several square windows with an area of A, each of which is non-overlap; perform a logic operation on each square window; and divide the window into two parts: {circle around (1)} the area to-be-inserted; {circle around (2)} the non-inserting area; determine the metal density of the dummy pattern that should be inserted to each square window and the line width; determine the dummy pattern that should be inserted to the windows according to the metal density, line width, the pre-set dummy pattern and the layouting rules. The beneficial effects of the present invention is: avoided the shortcomings of fill density maximization in the rule-based filling method by using reasonable metal density and line width. And with a combination of the influence of line width and density to the copper plating process and chemical mechanical polishing morphology in model-based filling method, it can achieve a better planarization effect. | 08-29-2013 |
| 20130239074 | APPARATUS, METHOD AND MEDIUM STORING PROGRAM FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT - According to one embodiment, a designing apparatus includes a register position determining module, a net list generator, and a layout data generator. The register position determining module determines a register position on a layout of a semiconductor integrated circuit from a hardware description. The net list generator generates a net list according to the register position. The layout data generator generates layout data based on the net list. The layout data indicates the layout of the semiconductor integrated circuit. | 09-12-2013 |
| 20130246984 | PROPRIETARY CIRCUIT LAYOUT IDENTIFICATION - A method is provided for identifying use of a proprietary circuit layout. A representation of a layout of a circuit is input and the locations of a set of predetermined physical features of the circuit are identified. This set of locations is then compared with a previously generated characteristic pattern file, the characteristic pattern file comprising a representation of relative locations of a set of these predetermined physical features in the proprietary circuit layout. If the set of locations matches the relative locations of the characteristic pattern file, then an output is generated indicating that use of the proprietary circuit design has been found. | 09-19-2013 |
| 20130254727 | SYSTEM AND METHODS FOR HANDLING VERIFICATION ERRORS - Systems, apparatus and methods for handling verification violations are disclosed. In one aspect, a method stores a list of fix information in addition to geometric shapes for each layer during verification, such as design rule checking For each primitive operation step performed during verification, two tasks are performed. First, if the primitive operation is a dimensional checking operation (i.e., width, spacing or enclosure), then for each violation, the first task creates fix information containing violation edge pairs and adds the created fix information to the fix information list on the output layer. Second, for all operations and after the output shapes on the output layer are generated, a second task passes the fix information on input layers which overlap any output shape of the output layer to the output layer's fix information list. Finally, fix guides for the final violation results are generated and drawn based on the final fix information list. | 09-26-2013 |
| 20130263067 | AUTOMATIC OPTIMAL INTEGRATED CIRCUIT GENERATOR FROM ALGORITHMS AND SPECIFICATION - Systems and methods are disclosed to automatically design a custom integrated circuit by receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically generating a computer architecture with programmable processor and one or more co-processors for the computer readable code that best fits the constraints; automatically determining an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operation over one or more processing blocks to reduce hot spots; automatically generating associated test suites and vectors for the computer readable code on the custom integrated circuit; and automatically synthesizing the designed architecture and generating a computer readable description of the custom integrated circuit for semiconductor fabrication. | 10-03-2013 |
| 20130283220 | Developing a Hardware Description Which Performs a Function by Partial Hardening of a Software Program on a Multi-Processor System - System and method for developing an ASIC. A software program may be stored which includes program instructions which implement a function. The software program may be executed on a processing system at a desired system speed and may be validated based on the execution. A first hardware description of at least a portion of the processing system may be stored and may specify implementation of at least a portion of the processing system. A second hardware description may be generated that corresponds to a first portion of the first hardware description. The second hardware description may specify a dedicated hardware implementation of a first portion of the software program executing on the processing system. Generation of the second hardware description may be performed one or more times to fully specify the ASIC. An ASIC may be created which implements the function of the software program. | 10-24-2013 |
| 20130290916 | SYSTEM AND METHOD FOR REDUCING LAYOUT-DEPENDENT EFFECTS - A method includes extracting a first netlist from a first layout of a semiconductor circuit and estimating layout-dependent effect data based on the first netlist. A first simulation of the semiconductor circuit is performed based on the first netlist using an electronic design automation tool, and a second simulation of the semiconductor circuit is performed based on a circuit schematic using the electronic design automation tool. A weight and a sensitivity of the at least one layout-dependent effect are calculated, and the first layout of the semiconductor circuit is adjusted based on the weight and the sensitivity to provide a second layout of the semiconductor circuit. The second layout is stored in a non-transient storage medium. | 10-31-2013 |
| 20130298090 | NETWORK RESISTOR MODEL ANALYSIS TOOL - The invention may be embodied in a network resistor model analysis tool for an Electrical Rule Checking (ERC) system. The network resistor model analysis tool typically includes, but need not be limited to, (i) a recursive, deterministic resistor path algorithm that identifies all valid resistor paths from a start net to a stopping net in a netlist corresponding to an analog circuit, (ii) a programming representation algorithm complete for representing the resistor paths in a programmatic format accessible through an application program interface, and (iii) a recursive, deterministic resistance value algorithm that solves the programmatically represented network to determine a total resistance value for each valid path and each resistor leg in each valid path. | 11-07-2013 |
| 20130298091 | METHOD OF PERFORMING CIRCUIT SIMULATION AND GENERATING CIRCUIT LAYOUT - A method of generating a circuit layout of an integrated circuit includes generating layout geometry parameters for at least a predetermined portion of an original netlist of the integrated circuit. A consolidated netlist including information from the original netlist and the layout geometry parameters is generated. Then, the circuit layout is generated based on the consolidated netlist. | 11-07-2013 |
| 20130298092 | METHOD AND SYSTEM FOR AUTOMATICALLY ESTABLISHING HIERARCHICAL PARAMETERIZED CELL (PCELL) DEBUGGING ENVIRONMENT - A system and method are provided for establishing an automated debugging environment in an Electronic Design Automation (EDA) work flow for the debugging of parameterized cells (PCELLS/PyCELLS) in a layout. A user may merely select a particular PCELL within a hierarchical PCELL and the system and method will determine dependencies thereof. The source code for the selected PCELL and its dependencies may be located and loaded. At least one breakpoint may be set in the source code of the selected PCELL. The source code for the selected PCELL and its dependencies may be executed to be arrested at the set breakpoints. Upon the arrest of execution, a debugging environment may be established and the located source code of the selected PCELL may be displayed along with values for parametric components thereof and progression control tools. | 11-07-2013 |
| 20130305196 | SYSTEMS AND METHODS FOR CREATING FREQUENCY-DEPENDENT NETLIST - A method includes creating a technology file including data for an integrated circuit including at least one die including at least one metal layer to be formed using at least one of a single patterning process or a multi-patterning process, creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the metal layer of at least one die based on the technology file, simulating a performance of the integrated circuit based on the netlist, adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and repeating the simulating and adjusting to optimize the at least one of the capacitive or inductive couplings. | 11-14-2013 |
| 20130318484 | Third Party Component Debugging For Integrated Circuit Design - The application is directed towards facilitating the debugging of suspected errors in a proprietary component when the proprietary component is incorporated into a larger electronic design. Various implementations provide for the generation of a reference model for an integrated circuit design, where the reference model includes the proprietary component and sufficient information about the rest of the design to allow for the debugging of the proprietary component over a period of verification where the error in the proprietary component is suspected. | 11-28-2013 |
| 20130318485 | Design Alteration for Wafer Inspection - Methods and systems for binning defects on a wafer are provided. One method includes identifying areas in a design for a layer of a device being fabricated on a wafer that are not critical to yield of fabrication of the device and generating an altered design for the layer by eliminating features in the identified areas from the design for the layer. The method also includes binning defects detected on the layer into groups using the altered design such that features in the altered design proximate positions of the defects in each of the groups are at least similar. | 11-28-2013 |
| 20130326440 | ANALOG/DIGITAL PARTITIONING OF CIRCUIT DESIGNS FOR SIMULATION - For increasing user control and insight into preparing a mixed semiconductor design specification for simulation, there are provided methods responsive to commands that provide control over resolution of disciplines and partitioning of the design into analog and digital portions. In some aspects, the methods provide block-based assignments of disciplines, as well as design partitioning. In other aspects, the methods provide for resolving a discipline to apply in a block from among multiple possible disciplines. In some aspects, error flagging may be available for detecting disciplines different from what provided for assignment in a block. Assignments may be indicated based on instance, cell, terminal, or library names and may be specified with wild cards. In still other aspects, the methods may be embodied by instructions on computer readable media, and in systems comprising general and special purpose computer hardware that may communicate with various storage facilities and over various networks. | 12-05-2013 |
| 20130332895 | METHOD OF MANAGING ELECTRO MIGRATION IN LOGIC DESIGNS AND DESIGN STRUCTURE THEREOF - A method of designing an integrated circuit includes modifying a design attribute-variable electromigration (EM) limit for each pre-defined circuit based on at least one reliability constraint in order to avoid EM violations of an integrated circuit. The method further includes synthesizing the integrated circuit from a high level description to at least a subset of the pre-defined circuit devices using the modified design—variable EM limit of each pre-defined circuit. | 12-12-2013 |
| 20130339912 | HIERARCHICAL DESIGN FLOW GENERATOR - A hierarchical design flow generator for designing integrated circuits is disclosed. In one embodiment, the hierarchical design flow generator includes: (1) a partitioner configured to partition a hierarchical design flow for designing an IC into a late design flow portion and an early design flow portion, (2) a timing budgeter configured to provide a timing budget for the IC design based on initial timing constraints and progressive time constraints generated from the late design flow portion and the early design flow portion and (3) a modeler configured to develop a model for a top level implementation of the IC design based on the timing budget and block implementations generated during the late design flow portion. | 12-19-2013 |
| 20130346925 | INTEGRATED CIRCUIT COMPILATION - Systems and methods for increasing speed and reducing processing power of a compile process of programmable logic of an integrated circuit (IC) are provided. For example, in one embodiment, a method includes obtaining a high level program, comprising computer-readable instructions for implementation on programmable logic of an integrated circuit (IC); translating the high level program into low level code representative of functional components needed to execute functionalities of the high level program; generating a host program comprising computer-readable instructions for implementing the low level code based upon the high level program; obtaining modifications to the high level program; determining whether the modifications can be implemented by a new host program utilizing the low level code; and generating the new host program to implement the modifications, when the modifications can be implemented by the new host program utilizing the low level code. | 12-26-2013 |
| 20130346926 | Automatic optimal integrated circuit generator from algorithms and specification - Systems and methods are disclosed to automatically design a custom integrated circuit based on algorithmic process or code as input and using highly automated tools that requires virtually no human involvement is disclosed. | 12-26-2013 |
| 20140026108 | METHOD AND SYSTEM FOR DECOMPOSING SINGLE-QUBIT QUANTUM CIRCUITS INTO A DISCRETE BASIS - The current application is directed to methods and systems which transform a given single-qubit quantum circuit expressed in a first quantum-gate basis into a quantum-circuit expressed in a second, discrete, quantum-gate basis. The discrete quantum-gate basis comprises standard, implementable quantum gates. The given single-qubit quantum circuit is expressed as a normal representation. The normal representation is generally compressed, in length, with respect to equivalent non-normalized representations. The method and systems additionally provide a mapping from normal representations to canonical-form representations, which are generally further compressed, in length, with respect to normal representations. The normal and canonical-form representations can be used to implement methods and systems for search-based quantum-circuit design. Neither this section nor the sections which follow are intended to either limit the scope of the claims which follow or define the scope of those claims. | 01-23-2014 |
| 20140033147 | VERIFICATION FOR FUNCTIONAL INDEPENDENCE OF LOGIC DESIGNS THAT USE REDUNDANT REPRESENTATION - Computer-implemented techniques are disclosed for verifying functional independence of logic designs that make use of redundant representations. Initially, the design of a logic component is obtained. Two representations of the component are computed, one in redundant form and another in non-redundant form. A randomness factor based on a time-varying value is injected into the second representation. The value from the second form is then constrained to the context of the logic component within a digital system. It is then possible to analyze the component using the first deterministic representation and the constrained second representation. This analysis allows verification of the component with downstream logic. | 01-30-2014 |
| 20140047399 | SYSTEM AND METHOD FOR INFERRING HIGHER LEVEL DESCRIPTIONS FROM RTL TOPOLOGY BASED ON NAMING SIMILARITIES AND DEPENDENCY - A system and methods are disclosed for inferring higher level descriptions of circuit connectivity from register transfer level (RTL) netlists in order to provide more understandable and manageable design descriptions for complex System-on-Chip (SOC) designs. In particular, rule-based interface matching is automatically performed by analyzing actual port names on instances of functional elements and blocks to form signal groupings that comprise a higher-level abstracted description. An example syntax is provided for defining rules that are used to define how various analysis are performed. Data describing standard interfaces on common Intellectual Property (IP) blocks is optionally made available to facilitate interface matching. Also, a facility is included to allow user-guided mapping on instantiated interfaces with respect to actual port names in an RTL-level design. | 02-13-2014 |
| 20140053119 | EXTRACTION AND SHARING IN HIGH LEVEL SYNTHESIS - Technology for translating a behavioral description of a circuit into a structural description of the circuit is disclosed. The behavioral description may describe the circuit in terms of the behavior, or other functionality, of multiple circuit portions, with at least some of the multiple circuit portions having multiple components. The technology includes determining components across the multiple circuit portions of the behavioral description that have commonalities, and synthesizing the structural description with a description of a shared circuit portion instead of individual structural descriptions of the components having the determined commonality. The synthesized structural description may be organized according to a different hierarchical structure than that of the behavioral description. | 02-20-2014 |
| 20140089872 | METHOD OF PROVING FORMAL TEST BENCH FAULT DETECTION COVERAGE - Some aspects of the present disclosure provide for a system and method to discover which parts of a design a formal test suite can detect faults in, and thus how much of a design structure is covered by a property set. A mutatable RTL design is defined which allows for modification of a part of an RTL design from its intended behavior to a non-intended behavior, thus introducing unwanted effects. The mutatable RTL design can then be synthesized to produce a functional representation of the design. The property set can be re-run on the synthesized design to see whether the functional representation of the design is sensitive to the unwanted effect and thus whether formal verification can detect the modification. | 03-27-2014 |
| 20140096093 | RELIABILITY DETERMINATION TAKING INTO ACCOUNT EFFECT OF COMPONENT FAILURES ON CIRCUIT OPERATION - A method includes testing to failure a plurality of semiconductor test structures, measuring a parameter of each semiconductor test structure after experiencing a failure, and generating a cumulative probability distribution function (CPDF) of cumulative probability versus the measured parameter after failure for the plurality of semiconductor test structures. The method further includes performing simulations for a circuit having an area using a model of a transistor that mimics the failure to determine a parameter threshold value that defines a minimum acceptable performance level of the circuit, determining a cumulative probability value from the CPDF that a transistor will not have the parameter at a level below the parameter threshold value, adjusting a value of the area of the circuit based on the cumulative probability value, and computing a first reliability value based on the adjusted area value. | 04-03-2014 |
| 20140101626 | SYSTEM AND METHOD OF ELECTROMIGRATION MITIGATION IN STACKED IC DESIGNS - A computer implemented method comprises accessing a 3D-IC model stored in a tangible, non-transitory machine readable medium, processing the model in a computer processor to generate a temperature map containing temperatures at a plurality of points of the 3D-IC under the operating condition; identifying an electromigration (EM) rating factor, and calculating and outputting from the processor data representing a temperature-dependent EM current constraint at each point. | 04-10-2014 |
| 20140115547 | Method of Generating Parameterized Units - The present invention relates to a method of method of generating parameterized integrated circuit units in a plurality of platforms. The said method comprising: (1) designing parameterized units in a graphic user interface and defining their constrain relations; (2) transforming the parameterized units to scripts. The invention providing a method of designing parameterized units in a graphical user interface without editing parameterized unit scripts, reducing the complexity of the design process and the design cycle; in addition, it is very easy for users to design and maintenance; at the same time, increasing the portability. | 04-24-2014 |
| 20140123085 | SYSTEMS AND METHODS FOR DETERMINING AGING DAMAGE FOR SEMICONDUCTOR DEVICES - A method includes generating a circuit design and executing a simulation of the circuit design at a plurality of time slices. Type 1 damage and type 2 damage are determined for each time slice. A total type 1 damage is provided as a sum of the type 1 damage for all of the slices in which type 1 damage is greater than type 2 damage. A total type 2 damage is similarly added for the slices where the type 2 damage is dominant. A type 1 aging effect is determined based on the total type 1 damage. A type 2 aging effect is determined based on the total type 2 damage. The type 1 aging effect is added to the type 2 aging effect to obtain a total aging effect. The circuit design is tested using the total aging effect to determine if the circuit design provides adequate lifetime performance. | 05-01-2014 |
| 20140123086 | PARASITIC EXTRACTION IN AN INTEGRATED CIRCUIT WITH MULTI-PATTERNING REQUIREMENTS - Systems and methods are provided for extracting parasitics in a design of an integrated circuit with multi-patterning requirements. The method includes determining resistance solutions and capacitance solutions. The method further includes performing parasitic extraction of the resistance solutions and the capacitance solutions to generate mean values for the resistance solutions and the capacitance solutions. The method further includes capturing a multi-patterning source of variation for each of the resistance solutions and the capacitance solutions during the parasitic extraction. The method further includes determining a sensitivity for each captured source of variation to a respective vector of parameters. The method further includes determining statistical parasitics by multiplying each of the resistance solutions and the capacitance solutions by the determined sensitivity for each respective captured source of variation. The method further includes generating as output the statistical parasitics in at least one of a vector form and a collapsed reduced vector form. | 05-01-2014 |
| 20140157214 | QUANTUM KARNAUGH MAP - Techniques for determining and a computing device configured to determine a quantum Karnaugh map through decomposing a quantum circuit into a multiple number of sub-circuits are provided. Also, techniques for obtaining and a computing device configured to obtain a quantum circuit which includes the minimum number of gates among possible quantum circuits corresponding to a quantum Karnaugh map are also provided. | 06-05-2014 |
| 20140173536 | COMPUTER-IMPLEMENTED METHODS AND SYSTEMS FOR AUTOMATIC GENERATION OF LAYOUT VERSUS SCHEMATIC (LVS) RULE FILES AND REGRESSION TEST DATA SUITES - A system, a computer program product, and a computer-implemented method are provided for automatically generating a LVS rule file, and/or for automatically generating a regression test data suite. | 06-19-2014 |
| 20140189617 | DISPLAYING A CONGESTION INDICATOR FOR A CHANNEL IN A CIRCUIT DESIGN LAYOUT - Methods and apparatuses are described for creating, editing, and viewing a floorplan of a circuit design. Specifically, some embodiments enable a user to perform a graphical operation at an inference point in a circuit design layout, wherein the location of the inference point is determined based on existing graphical objects in the circuit design layout. Some embodiments substantially instantaneously update a congestion indicator in a circuit design layout in response to modifying the circuit design layout. Some embodiments substantially instantaneously update pin locations of a block or partition in response to changing the size or shape of the block or partition. Some embodiments enable a user to view a circuit design layout based on the logical hierarchy, and also based on at least one additional attribute type such as voltage, power, or clock domain. | 07-03-2014 |
| 20140189618 | WIRING DESIGN SUPPORT APPARATUS, METHOD AND COMPUTER-READABLE RECORDING MEDIUM - A wiring design support apparatus includes: an input device with which input data about a wiring design content in a multilayered printed circuit board is input; a storage device includes a stab length limitation value table and a back drill application table stored therein, wherein the stab length limitation value table includes set data of a limitation value about a stab length of a through hole of the printed circuit board, and the back drill application table includes set data of information about whether a conductor of a stab of the printed circuit board can be removed or not; and a processor configured to determine, based on the stab length limitation value table and the back drill application table, whether a wiring design of the input data is appropriate. | 07-03-2014 |
| 20140189619 | Multiprocessor Computer System and Method Having at Least One Processor with a Dynamically Reconfigurable Instruction Set - An innovative realization of computer hardware, software and firmware comprising a multiprocessor system wherein at least one processor can be configured to have a fixed instruction set and one or more processors can be statically or dynamically configured to implement a plurality of processor states in a plurality of technologies. The processor states may be instructions sets for the processors. The technologies may include programmable logic arrays. | 07-03-2014 |
| 20140201693 | AUTOMATING INTEGRATED CIRCUIT DEVICE LIBRARY GENERATION IN MODEL BASED METROLOGY - Various embodiments include computer-implemented methods, computer program products and systems for generating an integrated circuit (IC) library for use in a scatterometry analysis. In some cases, approaches include: obtaining chip design data about at least one IC chip; obtaining user input data about the at least one IC chip; and running an IC library defining program using the chip design data in its original format and the user input data in its original format, the running of the IC library defining program including: determining a process variation for the at least one IC chip based upon the chip design data and the user input data; converting the process variation into shape variation data; and providing the shape variation data in a text format to a scatterometry modeling program for use in the scatterometry analysis. | 07-17-2014 |
| 20140282308 | METHOD OF RADIO-FREQUENCY AND MICROWAVE DEVICE GENERATION - The present disclosure relates to an apparatus and method to generate a device library, along with layout versus schematic (LVS) and parasitic extraction set-up files for connecting with official tools of a design window supported by a process design kit (PDK). The device library comprises passive devices which can be utilized at any point in an end-to-end design flow from pre-layout verification to post-layout verification of an integrated circuit design. The device library allows for a single schematic view for pre-layout verification but also post-layout verification, thus allowing for pole or pin comparison, and prevents double-counting of parasitic effects from passive design elements by directly instantiating a device from the device library for a verification step. An LVS and parasitic extraction graphical user interface (GUI) allows for incorporation of the generated device library into a pre-existing PDK without any modification to the PDK. Other devices and methods are also disclosed. | 09-18-2014 |
| 20140282309 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR CONSTRUCTING A DATA FLOW AND IDENTIFYING A CONSTRUCT - A system, method, and computer program product are provided for creating a hardware design. In use, one or more parameters are received, where at least one of the parameters corresponds to an interface protocol. Additionally, a data flow is constructed based on the one or more parameters. Further, an indication of one or more control constructs is received, where a hardware design is capable of being created, utilizing the constructed data flow and the one or more control constructs. | 09-18-2014 |
| 20140282310 | METHOD OF PERFORMING CIRCUIT SIMULATION AND GENERATING CIRCUIT LAYOUT - A method of generating, based on a first netlist of an integrated circuit, a second netlist includes generating layout geometry parameters for at least a portion of the first netlist of the integrated circuit, the portion including a first device. A third netlist is generated based on the first netlist and the layout geometry parameters. A description in the third netlist for modeling the first device is decomposed into a description in a fourth netlist for modeling a plurality of secondary devices. The second netlist is generated based on the fourth netlist. | 09-18-2014 |
| 20140289685 | DYNAMIC POWER DRIVEN CLOCK TREE SYNTHESIS (CTS) - Dynamic power driven clock tree synthesis is described. Some embodiments can select one or more cells from a cell library based on power ratios of cells in the cell library. The embodiments can then construct a clock tree based on the one or more cells. | 09-25-2014 |
| 20140310664 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR TRANSLATING A SOURCE DATABASE INTO A COMMON HARDWARE DATABASE - A system, method, and computer program product are provided for translating a hardware design. In use, a hardware design is received that is a graph-based intermediate representation of a hardware design stored in a source database. An instance of each unique module in the source database is determined and a hardware module node is generated for each unique module. Additionally, a list of one or more instances is associated with each hardware module node and a graph-based common representation of the hardware design that includes one or more of the generated hardware module nodes is stored. | 10-16-2014 |
| 20140310665 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR TRANSLATING A COMMON HARDWARE DATABASE INTO A LOGIC CODE MODEL - A system, method, and computer program product are provided for translating a hardware design. In use, a hardware design is received that is a graph-based common representation of a hardware design stored in a hardware model database. Logic code is generated for each hardware module node of the graph-based common representation of the hardware design. Additionally, flow control code is generated for each hardware module node of the graph-based common representation of the hardware design. A logic code model of the hardware design that includes the generated logic code and the generated flow control code is stored. | 10-16-2014 |
| 20140310666 | METHODS FOR IMPLEMENTING VARIABLE SPEED SCAN TESTING - In an embodiment of the invention, variable test clock circuitry is provided within an integrated circuit desired to be tested. The variable test clock frequency implements a test clock control register that receives serial test data from a device tester and is configured to serially pass the received test data to scan test chains within the integrated circuit. The test clock control register stores test clock information. The test clock information is provided to a test clock generator where the test clock generator then produces test clock signals at a predetermined frequency. The test clock signal is then provided as a test clock frequency for the scan test chains within the integrated circuit. Methods are also disclosed for operating the variable test clock frequency. | 10-16-2014 |
| 20140317582 | Race Logic Synthesis for ESL-based Large-Scale Integrated Circuit Designs - Techniques for performing race logic synthesis on an integrated circuit (IC) are described herein. According to one aspect of the invention, ESL (electronic system level) and any HDL (hardware description language) design source files of an IC design are compiled into a design database. Race logic analysis is performed on the IC design to detect race logic, including race logic for IPC (inter-process communication) and IPS (inter-process synchronization) objects in the IC design, by a third-party tool and/or by the same host EDA (electronic design automation) tool that will be performing race logic synthesis on the IC design, if the latter has built-in race logic audit functions. Based on the race logic audit results, race logic synthesis is performed on the design database, and getting rid of all identified race logic in the IC design, including IPC- and IPS-related race logic. This renders the EDA tool can perform concurrent analysis of the IC design, via the race-free IC design database, using multi-CPU/core computers and the results will be the same as if the EDA tool had performed serial analysis of the IC design using a single-CPU/core computer. Another aspect of the invention is outputting the re-synthesized logic in the design database to new ESL/HDL source files. User may use these revised source files to analyze the IC design using any other third-party EDA tools. | 10-23-2014 |
| 20140351774 | SYSTEM AND METHOD FOR UNIVERSAL CONTROL OF ELECTRONIC DEVICES - A system and method for providing an integrated circuit that integrates with and controls a device wherein the integrated circuit design is developed based on a selection of characteristics of the device. The system and method also provide software for establishing interoperability between the integrated circuit and a controller. | 11-27-2014 |
| 20140351775 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR PROVIDING A DEBUGGER USING A COMMON HARDWARE DATABASE - A hardware model database is identified which stores a graph-based common representation of a hardware design that includes hardware module nodes each representative of a unique module of the hardware design and associated with one or more instances of the unique module. Additionally, a signal dump resulting from a simulation of a logic code model of the hardware design is identified. Each instance of each unique module is identified using the hardware model database, and for each assertion condition included therein, a corresponding value for the assertion condition is determined from the signal dump. Further, a construct of the hardware design corresponding to each instance of each unique module is conditionally displayed by a debugger application, based on the determined values of the corresponding assertion conditions included in the instance of the unique module. | 11-27-2014 |
| 20140380257 | HIERARCHICAL PUSHDOWN OF CELLS AND NETS TO ANY LOGICAL DEPTH - A technique for generating pushdown data comprises performing logical pushdown of circuit elements and nets and detecting physical pushdown based on partition boundary crossings. Geometry associated with one logical level may be used as a keep-out region for the same physical layer when generating physical design of a different logical level. The technique may advantageously enable concurrent design in both top-level and low-level physical design phases, thereby reducing overall design cycle time in developing an integrated circuit. | 12-25-2014 |
| 20150040085 | System and Method for Series and Parallel Combinations of Electrical Elements - A method and system for generating and matching complex series and/or parallel combinations of nominally identical initial elements to achieve an arbitrary compound value is disclosed. A recursive algorithm successively adds one or more similar nominal two-terminal elements to generate a series and/or parallel compound combination of nominal elements, the compound combination having a desired impedance. The compound value, and thus the ratio between two compound values, can be determined to almost any desired degree of accuracy, with potential errors greatly reduced from those typical in the construction of individual elements of different values. Since the initial elements are nominally identical, the compound value, and the ratio between values, depends primarily upon the connections of the initial elements, rather than their geometry, and thus remain virtually constant regardless of variations in the manufacturing process. | 02-05-2015 |
| 20150089461 | METHODS FOR GENERATING SCHEMATIC DIAGRAMS AND APPARATUSES USING THE SAME - An embodiment of the invention introduces a method for generating schematic diagrams, executed by a processing unit of an apparatus, which comprises the following steps. A pin-editing interface comprising a data table is generated to assist a user to configure pin settings. A user setting is obtained via the pin-editing interface, and a schematic diagram is generated on a display unit according to the obtained user setting. | 03-26-2015 |
| 20150100928 | COMPLEX LAYOUT-BASED TOPOLOGICAL DATA ANALYSIS OF ANALOG NETLISTS TO EXTRACT HIERARCHY AND FUNCTIONALITY - A system and method for reverse synthesizing an integrated circuit from a netlist. A netlist extracted from a device under review is received and converted to a connected graph. Blocks of cells are identified within the connected graph and a circuit model is formed from the blocks of cells, wherein forming includes iteratively building more complex blocks of cells from simpler blocks of cells. | 04-09-2015 |
| 20150106774 | HIGH-LEVEL SYNTHESIS DATA GENERATION APPARATUS, HIGH-LEVEL SYNTHESIS APPARATUS, AND HIGH-LEVEL SYNTHESIS DATA GENERATION METHOD - An analysis unit analyzes a source code representing design data of a semiconductor device, and generates information (CDFG information) indicating the data and control flow of the semiconductor device. A high-level synthesis data generation unit acquires intermediate data (an object file), which is obtained by compiling the source code, generates intermediate data (an object file) by incorporating the CDFG information generated by the analysis unit into the acquired intermediate data, and outputs the generated intermediate data as high-level synthesis data. | 04-16-2015 |
| 20150113487 | AUTOMATED INTEGRATED CIRCUIT DESIGN DOCUMENTATION - A method of creating a datasheet includes obtaining integrated circuit data from at least one data source, creating a data structure including the integrated circuit data obtained from the at least one data source, and creating a datasheet using data contained in the data structure. The datasheet is created in a human-readable format. | 04-23-2015 |
| 20150121320 | System And Method For Universal Control Of Electronic Devices - A system and method for providing an integrated circuit that integrates with and controls a device wherein the integrated circuit design is developed based on a selection of characteristics of the device. The system and method also provide software for establishing interoperability between the integrated circuit and a controller. | 04-30-2015 |
| 20150121321 | CONFIGURING A PROGRAMMABLE DEVICE USING HIGH-LEVEL LANGUAGE - A method of preparing a programmable integrated circuit device for configuration using a high-level language includes compiling a plurality of virtual programmable devices from descriptions in said high-level language. the compiling includes compiling configurations of configurable routing resources from programmable resources of said programmable integrated circuit device, and compiling configurations of a plurality of complex function blocks from programmable resources of said programmable integrated circuit device. A machine-readable data storage medium may be encoded with a library of such compiled configurations. A virtual programmable device may include a stall signal network and routing switches of the virtual programmable device may include stall signal inputs and outputs. | 04-30-2015 |
| 20150339420 | DESIGN OF DUAL MODE LOGIC CIRCUITS - A method for designing a dual-mode logic circuit which is selectably operational in static and dynamic modes is performed as follows. A basis library with a DML inverter and dual-mode logic (DML) bicells is provided. Each DML bicell includes a type-A DML logic gate with a clock input and a type-B DML logic gate with an inverted clock input. A pseudo-static library is formed from the basis library by modifying each bicell of the basis library and specifying at least one dynamic timing parameter. A dynamic library is formed from the basis library by specifying dynamic timing parameters for the basis library DML inverter and bicells. Logic behavior of the required logic circuit is defined. An initial logic circuit design synthesized from the pseudo-static library and the defined logic behavior. Finally, a dynamic circuit design is formed by replacing modified bicells with corresponding bicells from the dynamic library. | 11-26-2015 |
| 20150347642 | LOGIC ABSORPTION TECHNIQUES FOR PROGRAMMABLE LOGIC DEVICES - Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a programmable logic device (PLD). The computer-implemented method also includes synthesizing the design into a plurality of PLD components comprising a first logic block cascaded into a second logic block. In the computer-implemented method, the second logic block implements a multiplexer adapted to selectively pass a first multi-bit input signal received from the first logic block or a second multi-bit input signal. The computer-implemented method also includes further synthesizing the design to absorb the multiplexer into the first logic block. | 12-03-2015 |
| 20150347645 | CORRELATION OF TEST RESULTS AND TEST COVERAGE FOR AN ELECTRONIC DEVICE DESIGN - A device simulation system performs a set of tests by applying, for each test in the set, a corresponding test stimulus to a simulation of the electronic device. In response to each test stimulus, the simulation generates corresponding output information which the device simulation system compares to a specified expected outcome to identify a test result for that test stimulus. In addition, for each test stimulus, the device simulation system generates test coverage information indicating the particular configuration of the simulated electronic device that resulted from the stimulus. The device simulation system correlates the coverage information with the test results to identify correlation rules that indicate potential relationships between test results and configurations of the simulated device. | 12-03-2015 |
| 20150347654 | EXTRACTING SYSTEM ARCHITECTURE IN HIGH LEVEL SYNTHESIS - Extracting a system architecture in high level synthesis includes determining a first function of a high level programming language description and a second function contained within a control flow construct of the high level programming description. The second function is determined to be a data consuming function of the first function. Within a circuit design, a port including a local memory is automatically generated. The port couples a first circuit block implementation of the first function to a second circuit block implementation of the second function within the circuit design. | 12-03-2015 |
| 20150363528 | CIRCUIT ARRANGEMENT FOR MODELING - One or more circuit arrangements and techniques for modeling are provided. In some embodiments, a circuit arrangement includes at least one of a first current source, a second current source, a first diode, a second diode, and a switching component. In some embodiments, the switching component includes a bipolar junction transistor (BJT). In some embodiments, the circuit arrangement is integrated into a metal oxide semiconductor (MOS) device. When the circuit arrangement is integrated into a MOS device, at least one of a substrate current leakage, a junction breakdown, or a diode reverse recovery (DRR) effect is predictable for the MOS device. | 12-17-2015 |
| 20150379176 | SYSTEM AND METHOD FOR VIEWING AND MODIFYING CONFIGURABLE RTL MODULES - A configurable module editor and viewer (CMVE) reads the RTL description of a configurable module keeping track of all possible configuration options. Configuration options include pre-processor macros that are normally removed by RTL parsers. The CMVE allows users to view multiple configurations simultaneously. The CMVE assists users in editing the configurable module by presenting a simplified view of interest, while automatically propagating changes and maintaining consistency in the configurable module. The CMVE outputs updated RTL that maintains all configuration options. | 12-31-2015 |
| 20160004797 | CIRCUIT DESIGNING SUPPORT APPARATUS AND PROGRAM - In circuit designing of a semiconductor integrated circuit or the like, reworks accompanying returning from the backend layout design are reduced, so that efficiency improvement (time reduction) of the entire development can be achieved. A high-level synthesis processing part conducts high-level synthesis of behavioral description. The synthesis result analyzing part acquires a layout designing condition being a condition concerning layout designing of a designing target circuit, and compares the layout designing condition with a high-level synthesis result. If any one element included in the high-level synthesis result is different from the layout designing condition, the synthesis result analyzing part decides a changing method of changing the hierarchical structure of the behavioral description. A hierarchy changing part changes the hierarchical structure of the behavioral description in accordance with the changing method decided by the synthesis result analyzing part. | 01-07-2016 |
| 20160034623 | SYSTEM AND METHOD FOR DISPLAYING A DEVICE USING AN AUTOMATED TOOL - A method comprises receiving, in a computer, an input indicative of a drawing of at least a portion of at least one layer of a semiconductor device. The at least one portion of the at least one layer is compared to corresponding portions in corresponding layers of a plurality of previously defined devices stored in a non-transitory machine readable storage medium. Each layer of at least one of the plurality of previously defined devices for which the corresponding portion in the corresponding layer matches the at least one portion of the at least one layer of the semiconductor device is displayed on a display device. | 02-04-2016 |
| 20160042107 | Circuit Design Generator - Systems and methods for designing reconfigurable integrated circuits receive target data and training data; and generate a circuit design for implementing the target data which is over-provisioned with respect to the target data according to the training data. | 02-11-2016 |
| 20160055287 | METHOD FOR DECOMPOSING A HARDWARE MODEL AND FOR ACCELERATING FORMAL VERIFICATION OF THE HARDWARE MODEL - Described is a method performed by a computing device, the method comprises: deriving a hierarchal structure of hardware instances of a hardware block, wherein the hardware block is described in a register transfer language (RTL); determining complexity of at least one hardware instance, in the hierarchal structure, with reference to a complexity metric; identifying, in response to the determined complexity of the at least one hardware instance, whether the at least one hardware instance is to be modeled; and modifying the hierarchal structure with information about the to be modeled hardware instance. | 02-25-2016 |
| 20160078154 | DIGITAL CIRCUIT DESIGN METHOD AND ASSOCIATED COMPUTER PROGRAM PRODUCT - A digital circuit design method includes: before performing physical design: performing a logic synthesis according to a Register Transfer Level (RTL) design and a plurality of constraints to at least generate a netlist, a standard delay format file and a first constraint file; retrieving information of at least a specific node of circuit from the first constraint file to generate a second constraint file; generating an updated standard delay format file at least according to the standard delay format file and the second constraint file, wherein a delay of the specific node of the updated standard delay format file is less than a delay of the specific node of the standard delay format file; and using the netlist and the updated standard delay format file to perform a pre-post-layout simulation. | 03-17-2016 |
| 20160078162 | CONDITIONAL PHASE ALGEBRA FOR CLOCK ANALYSIS - A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of numerous waveforms without simulating the individual waveforms. The design tool can determine two or more input sequences of signal transition representations associated with an input net of an indicated component in an RTL circuit design, where the two or more input sequences of signal transition representations are associated with a mode element. Each signal transition representation represents a nondeterministic transition from a previous signal state to possible signal state(s). The mode element indicates a selection between two or more output sequences of signal transition representations. It is determined, based on the indicated component and the mode element, two or more output sequences of signal transition representations derived from the input sequence(s) of signal transition representations. | 03-17-2016 |
| 20160162619 | Cell Having Shifted Boundary and Boundary-Shift Scheme - An embodiment cell shift scheme includes abutting a first transistor cell against a second transistor cell and shifting a place and route boundary away from a polysilicon disposed between the first transistor cell and the second transistor cell. In an embodiment, the cell shift scheme includes shifting the place and route boundary to prevent a mismatch between a layout versus schematic (LVS) netlist and a post-simulation netlist. | 06-09-2016 |
| 20160171148 | VERIFICATION ENVIRONMENTS UTILZING HARDWARE DESCRIPTION LANGUAGES | 06-16-2016 |
| 20160180000 | NON-INVASIVE INSERTION OF LOGIC FUNCTIONS INTO A REGISTER-TRANSFER LEVEL ('RTL') DESIGN | 06-23-2016 |
| 20190147121 | Efficient Mechanism for Interactive Fault Analysis in Formal Verification Environment | 05-16-2019 |
