| Entries |
| Document | Title | Date |
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| 20100333046 | METHOD FOR PROCESSING OPTICAL PROXIMITY CORRECTION - A method for processing optical proximity correction is disclosed which eliminates a need for repeated implementation of experiments and result in a reducing the processing time as compared to trial and error. Furthermore, the method can realize an optimal insertion of the assist pattern by applying different conditions to specific layers. The method includes determining whether or not to insert an assist pattern around an outermost pattern. A shape of the assist pattern inserted around the outermost pattern is determined. The contrast of the outermost pattern is compared against a contrast of a cell array pattern. The contrast of the outermost pattern is repeated compared with the contrast of the cell array pattern under a defocus state. | 12-30-2010 |
| 20100333047 | METHOD AND SYSTEM FOR CONFIGURABLE CONTACTS FOR IMPLEMENTING DIFFERENT BIAS DESIGNS OF AN INTEGRATED CIRCUIT DEVICE - In a computer implemented synthesis system, a fabrication method for an integrated circuit device. The method includes receiving a circuit netlist representing a first form of an integrated circuit design to be realized in physical form. A plurality of contacts of the netlist are accessed. The plurality of contacts are configured to implement a second form of the integrated circuit design. | 12-30-2010 |
| 20110004854 | Method for Fabricating Assist Features in a Photomask - Disclosed is a method of fabricating an assist feature in a photomask, which includes: fabricating a design layout in which main patterns are arranged; setting a critical dimension (a) of assist features to be formed and a spacing (b) between the main pattern and the assist feature; setting a first expanded region extending from the main pattern by (a+b); setting a second expanded region extending from the main pattern by (b); and setting the assist features by removing the second expanded region from the first expanded region. | 01-06-2011 |
| 20110029936 | Method of generating layout of semiconductor device - A method of manufacturing a semiconductor device, and more particularly, a method of generating a layout of a semiconductor device. The method of preparing layout of a semiconductor device may include preparing a design layout including a main pattern; dividing the design layout into a plurality of first pieces of layout; preparing a plurality of second pieces of layout by providing a dummy pattern on each of the plurality of first pieces of layout; preparing a plurality of third pieces of layout by performing an optical proximity correction (OPC) process with respect to each of the plurality of second pieces of layout; and recombining the plurality of third pieces of layout. | 02-03-2011 |
| 20110035709 | Gradient-Based Search Mechanism for Optimizing Photolithograph Masks - A mechanism is provided for optimizing a photolithograph mask. A given target pattern is received. An initial fictitious mask is generated from the given target pattern and an initial value of α | 02-10-2011 |
| 20110061030 | PHOTOMASK DESIGN VERIFICATION - Solutions for verifying photomask designs are disclosed. In one embodiment, a method of verifying a photomask design includes: simulating an initial semiconductor manufacturing process using a plurality of mask shapes and variation models for the initial semiconductor manufacturing process, to generate a plurality of contours for the initial semiconductor manufacturing process; simulating a subsequent semiconductor manufacturing process using the contours for the initial semiconductor manufacturing process and variation models for the subsequent semiconductor manufacturing process, to generate a plurality of contours for the subsequent semiconductor manufacturing process; repeatedly simulating at least one further subsequent semiconductor manufacturing process using a plurality of contours for the subsequent semiconductor manufacturing process and variation models for the further subsequent semiconductor manufacturing process; and generating and storing a verification result for the photomask design on a computer readable storage medium. | 03-10-2011 |
| 20110093823 | SEMICONDUCTOR INTER-FIELD DOSE CORRECTION - A method and apparatus are provided for adapting a semiconductor inter-field dose correction map from a first photolithography mask to a second photolithography mask using the same manufacturing stack and reactive ion etching processes, the method including: obtaining a first dose correction map for the first photolithography mask as a function of first chip or die identities; determining a first transformation matrix from the first chip or die identities of the first photolithography mask into an orthogonal coordinate system; determining a second transformation matrix from second chip or die identities of the second photolithography mask into the orthogonal coordinate system; and transforming the first dose correction map for the first photolithography mask into a second dose correction map for the second photolithography mask in correspondence with each of the first and second transformation matrices. | 04-21-2011 |
| 20110107277 | RECORDING MEDIUM AND DETERMINATION METHOD - The present invention provides a computer-readable recording medium recording a program for causing a computer to execute a method of determining a pattern of a mask and an effective light source distribution with which the mask is illuminated, both of which are used for an exposure apparatus including an illumination optical system which illuminates a mask with light from a light source and a projection optical system which projects a pattern of the mask onto a substrate. | 05-05-2011 |
| 20110119642 | Simultaneous Photolithographic Mask and Target Optimization - A mechanism is provided for simultaneous photolithographic mask and target optimization (SMATO). A lithographic simulator generates an image of a mask shape on a wafer thereby forming one or more lithographic contours. A mask and target movement module analytically evaluates a direction for mask and target movement thereby forming a plurality of pairs of mask and target movements. The mask and target movement module identifies a best pair of mask and target movements from the plurality of mask and target movements that minimizes a weighted cost function. A shape adjustment module adjusts at least one of a target shape or the mask shape based on the best pair of mask and target movements. | 05-19-2011 |
| 20110131538 | METHOD FOR DESIGNING TWO-DIMENSIONAL ARRAY OVERLAY TARGETS AND METHOD AND SYSTEM FOR MEASURING OVERLAY ERRORS USING THE SAME - A method for designing a two-dimensional array overlay target comprises the steps of: selecting a plurality of two dimensional array overlay targets having different overlay errors; calculating a deviation of a simulated diffraction spectrum for each two-dimensional array overlay target; selecting an error-independent overlay target by taking the deviations of the simulated diffraction spectra into consideration; and designing a two dimensional array overlay target based on structural parameters of the error-independent overlay target. | 06-02-2011 |
| 20110138342 | Retargeting for Electrical Yield Enhancement - A mechanism is provided for electrical yield enhancement retargeting of photolithographic layouts. Optical proximity correction is performed on a set of target patterns in order to produce a set of optical proximity correction mask shapes. A set of lithographic contours is generated for each of the set of optical proximity correction mask shapes. A determination is made of electrical yield sensitivities for at least one shape in a set of shapes in the set of target patterns. A determination is also made as to an amount and a direction of retargeting for each of the at least one shape in the set of shapes based on the electrical yield sensitivity of the shape. A new set of target patterns with retargeted edges is generated for each shape in the at least one shape based on the amount and the direction of retargeting. | 06-09-2011 |
| 20110154271 | Optical Proximity Correction for Improved Electrical Characteristics - A method, computer program product, and data processing system for performing an improved optical proximity correction are disclosed, which better respect the electrical properties of the device being manufactured. A preferred embodiment of the present invention performs OPC by first dividing the perimeter of a mask region into a plurality of segments, then grouping the segments into at least two distinct groups, wherein segments in the first of these groups are adjusted in position so as to minimize edge placement error (EPE) when the photolithography using the mask is simulated. Segments in the second group are adjusted in position so as to minimize cumulative error in a dimension spanning the region, wherein the span of such dimension extends from segments in the first group to segments in the second group. Correction so obtained by this process more readily preserves the intended electrical behavior of the original device design. | 06-23-2011 |
| 20110154272 | METHOD FOR DESIGNING TWO-DIMENSIONAL ARRAY OVERLAY TARGET SETS AND METHOD AND SYSTEM FOR MEASURING OVERLAY ERRORS USING THE SAME - A method for designing a two-dimensional array overlay target set comprises the steps of: selecting a plurality of two-dimensional array overlay target sets having different overlay errors; calculating a deviation of a simulated diffraction spectra for each two-dimensional array overlay target set; selecting a sensitive overlay target set by taking the deviations of the simulated diffraction spectra into consideration; and designing a two-dimensional array overlay target set based on the structural parameters of the sensitive overlay target set. | 06-23-2011 |
| 20110179391 | LEAKAGE AWARE DESIGN POST-PROCESSING - The present invention provides a method and computer program product for designing an on-wafer target for use by a model-based design tool such as OPC or OPC verification. The on-wafer target is modified by modifying a critical dimension so as to improve or optimize an electrical characteristic, while also ensuring that one or more yield constraints are satisfied. The use of an electrically optimized target can result in cost-effective mask designs that better meet the designers' intent. | 07-21-2011 |
| 20110185322 | METHOD OF IN-PROCESS INTRALAYER YIELD DETECTION, INTERLAYER SHUNT DETECTION AND CORRECTION - A system and method for in-process yield evaluation and correction in an array type of device are provided. The system and method include measuring electrical resistance between individual GATE lines, DATA lines, a DATA bus I/O pad, and a GATE bus I/O pad; and analyzing the measured electrical resistance to identify at least one of the following: GATE line open defects, GATE line bridge defects, DATA line open defects, DATA line bridge defects, and interlayer shunt defects. | 07-28-2011 |
| 20110197168 | DECOMPOSING INTEGRATED CIRCUIT LAYOUT - Various embodiments of the invention provide techniques to ensure a layout for an integrated circuit is split-able. In a method embodiment, a layout is generated in a customer site having a layout library as inputs wherein the library provides exemplary layouts that have been verified to be spit-able and that can be used and layouts that can cause conflicts to avoid. A real-time odd cycle checker is also provided in which the checker identifies in real time conflict areas and odd cycles as they arise during layout generation. To reduce memory usage layouts of various devices may be separated so that each individual layout or a small number of layouts, rather than a large layout for the whole application circuit, can be checked against conflicts. Once the layout is ready at the customer site, it is sent to the foundry site to be decomposed into two masks and taped-out. Other embodiments are also disclosed. | 08-11-2011 |
| 20110219341 | METHOD, SYSTEM, AND PROGRAM PRODUCT FOR INTERACTIVE CHECKING FOR DOUBLE PATTERN LITHOGRAPHY VIOLATIONS - Disclosed are a method, apparatus, and computer program product for performing interactive layout editing to address double patterning approaches to implement lithography of electronic designs. A spatial query is performed around the shape(s) being created during editing with the distance of allowed spacing in a single mask. If a design error is encountered, corrective editing may occur to correct the error. Checking may occur to make sure that the error detection and corrective actions can be performed interactively. | 09-08-2011 |
| 20110231803 | Wavefront engineering of mask data for semiconductor device design - Optical wave data for a semiconductor device design is divided into regions. First wavefront engineering is performed on the wave data of each region, accounting for just the wave data of each region and not accounting for the wave data of neighboring regions of each region. The optical wave data of each region is normalized based on results of the first wavefront engineering. Second wavefront engineering is performed on the wave data of each region, based at least on the wave data of each region as has been normalized. The second wavefront engineering takes into account the wave data of each region and a guard band around each region that includes the wave data of the neighboring regions of each region. The second wavefront engineering can be sequentially performed by organizing the regions into groups, and sequentially performing the second wavefront engineering on the regions of each group in parallel. | 09-22-2011 |
| 20110239167 | Simplified Micro-Bridging and Roughness Analysis - The invention provides apparatus and methods for processing substrates using pooled statistically based variance data. The statistically based variance data can include Pooled Polymer De-protection Variance (PPDV) data that can be used to determine micro-bridging defect data, LER defect data, and LWR defect data. | 09-29-2011 |
| 20110271237 | METHOD TO COMPENSATE OPTICAL PROXIMITY CORRECTION - A method to compensate optical proximity correction adapted for a photolithography process is provided. An integrated circuit (IC) layout firstly is provided. The IC layout includes active regions and a shallow trench isolation (STI) region. The STI region is a region except the active regions. The IC layout further includes ion implant regions which are overlapped with a part of the STI region and at least a part of the active regions. Subsequently, at least a photoresist line width compensation region is acquired in a photoresist covering region outside the ion implant regions according to the IC layout. Each photoresist line width compensation region is disposed in the STI region. Afterwards, the IC layout is corrected according to a width of the photoresist line width compensation region, a length of a side of the active region facing a side of the photoresist line width compensation region and a distance from the side of the photoresist line width compensation region to the active region facing the side. Finally, the corrected IC layout is transferred to a photomask. | 11-03-2011 |
| 20120036486 | METHOD FOR RESIZING PATTERN TO BE WRITTEN BY LITHOGRAPHY TECHNIQUE, AND CHARGED PARTICLE BEAM WRITING METHOD - A method for resizing a pattern to be written by using lithography technique includes calculating a first dimension correction amount of a pattern for correcting a dimension error caused by a loading effect, for each small region made by virtually dividing a writing region of a target workpiece into meshes of a predetermined size, based on an area density of the each small region, calculating a second dimension correction amount in accordance with a line width dimension of the pattern to be written in the each small region, correcting the first dimension correction amount by using the second dimension correction amount, and resizing the line width dimension of the pattern by using a corrected first dimension correction amount, and outputting a result of the resizing. | 02-09-2012 |
| 20120167018 | Method for Decomposing a Designed Pattern Layout - A method for decomposing a designed pattern layout and a method for fabricating an exposure mask using the same. After the designed pattern layout is automatically decomposed to obtain a plurality of mask layouts, a problematic region is determined through simulation of the mask layout, and fed back to correct the designed pattern layout. As a result, problems can be detected in each process and corrected to reduce the process time. | 06-28-2012 |
| 20120180005 | LAYOUT METHOD FOR SOFT-ERROR HARD ELECTRONICS, AND RADIATION HARDENED LOGIC CELL - This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modem technologies (.ltoreq.90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors. | 07-12-2012 |
| 20130055171 | Method, Program Product and Apparatus for Performing Double Exposure Lithography - A method of generating complementary masks based on a target pattern having features to be imaged on a substrate for use in a multiple-exposure lithographic imaging process is disclosed. The method includes defining an initial H-mask and an initial V-mask corresponding to the target pattern; identifying horizontal critical features in the H-mask and vertical critical features in the V-mask; assigning a first phase shift and a first percentage transmission to the horizontal critical features, which are to be formed in the H-mask; and assigning a second phase shift and a second percentage transmission to the vertical critical features, which are to be formed in the V-mask. The method further includes the step of assigning chrome to all non-critical features in the H-mask and the V-mask. | 02-28-2013 |
| 20130086534 | METHOD FOR DETERMINING WIRE LENGTHS BETWEEN NODES USING A RECTILINEAR STEINER MINIMUM TREE (RSMT) WITH EXISTING PRE-ROUTES ALGORITHM - A method for the creation of rectilinear Steiner minimum trees includes determining a set of candidate connections from a terminal node to a different terminal node or to a graph edge. The length of each candidate connection may be used to determine the set of candidate connections that span the graph with a minimum total length. | 04-04-2013 |
| 20130198695 | Multi-Gate Field Effect Transistor with A Tapered Gate Profile - A multi-gate field effect transistor apparatus and method for making same. The apparatus includes a source terminal, a drain terminal, and a gate terminal which includes a tapered-gate profile. A method for designing a multi-gate field effect transistor includes arranging a source terminal, a drain terminal and a gate terminal with a tapered-gate profile to create a wider gate width on a bottom of a fin. | 08-01-2013 |
| 20130311957 | SEMICONDUCTOR DEVICE DESIGN SYSTEM AND METHOD OF USING THE SAME - A circuit design system includes a schematic design tool configured to generate schematic information and pre-coloring information for a circuit. The circuit design system also includes a netlist file configured to store the schematic information and the pre-coloring information on a non-transitory computer readable medium and an extraction tool configured to extract the pre-coloring information from the netlist file. A layout design tool, included in the circuit design system, is configured to design at least one mask based on the schematic information and the pre-coloring information. The circuit design system further includes a layout versus schematic comparison tool configured to compare the at least one mask to the schematic information and the pre-coloring information. | 11-21-2013 |
| 20140068527 | SYSTEM AND METHOD FOR MODIFYING A DATA SET OF A PHOTOMASK - The present invention provides a method for compensating infidelities of a process that transfers a pattern to a layer of an integrated circuit, by minimizing, with respect to a photomask pattern, a cost function that quantifies the deviation between designed and simulated values of circuit parameters of the pattern formed on a semiconductor wafer. | 03-06-2014 |
| 20140351771 | SCATTEROMETRY OVERLAY METROLOGY TARGETS AND METHODS - Scatterometry overlay (SCOL) targets as well as design, production and measurement methods thereof are provided. The SCOL targets have several periodic structures at different measurement directions which share some of their structural target elements or parts thereof. An array of common elements may have symmetry directions which are parallel to the measurement directions and thus enable compacting the targets or alternatively increasing the area use efficiency of the targets. Various configurations enable high flexibility in arranging the number of layers in the target and measurement directions, and carrying out respective overlay measurements among the layers. | 11-27-2014 |
