| Entries |
| Document | Title | Date |
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| 20100275177 | METHOD FOR TRANSFERRING SELF-ASSEMBLED DUMMY PATTERN TO SUBSTRATE - A semiconductor device fabrication method is disclosed. The method includes obtaining an inverse layout of an original circuit layout, reducing the inverse layout in size, thereby obtaining a reduced layout, obtaining a dummy pattern layout having an outline identical to an outline of the reduced layout and a given line width such that the dummy pattern layout is self-assembled to the circuit layout, and transferring the self-aligned or self-assembled dummy pattern layout and circuit layout to a semiconductor substrate. | 10-28-2010 |
| 20100287521 | MASK CREATION WITH HIERARCHY MANAGEMENT USING COVER CELLS - A method and apparatus for translating a hierarchical IC layout file into a format that can be used by a mask writer that accepts files having a limited hierarchy. Cover cells of the original IC layout file or a modified file are designated, and the hierarchical file is redefined to include only those designated cover cells. Non-designated cover cells and other geometric data are flattened into the designated cover cells. The hierarchy of the modified file is then redefined to be less than or equal to the hierarchy limit of the mask writing tool. | 11-11-2010 |
| 20100325592 | COMPUTER READABLE MEDIUM HAVING MULTIPLE INSTRUCTIONS STORED IN A COMPUTER READABLE DEVICE - A computer readable medium comprising multiple instructions stored in a computer readable device, upon executing these instructions, a computer performing the following steps: providing a first semiconductor layout and a second semiconductor layout predetermined to be fabricated on different material layers of a semiconductor device, the second semiconductor layout comprising a circuit pattern; setting a forbidden area of the circuit pattern on the first semiconductor layout according to a restriction condition; defining at least a virtual pattern arrangement area on a portion of the first semiconductor layout which does not correspond to the forbidden area; and selecting a positioning point at a boundary of the virtual pattern arrangement area and providing a virtual pattern array in the virtual pattern arrangement by taking the positioning point as an origin of a coordinate system of the virtual pattern array. | 12-23-2010 |
| 20100333049 | Model-Based Retargeting of Layout Patterns for Sub-Wavelength Photolithography - Mechanism are provided for model-based retargeting of photolithographic layouts. An optical proximity correction is performed on a set of target patterns for a predetermined number of iterations until a counter value exceeds a maximum predetermined number of iterations in order to produce a set of optical proximity correction mask shapes. A set of lithographic contours is generated for each of the set of optical proximity correction mask shapes in response to the counter value exceeding the maximum predetermined number of iterations. A normalized image log slope (NILS) extraction is performed on the set of target shapes and use the set of lithographic contours to produce NILS values. The set of target patterns is modified based on the NILS values in response to the NILS values failing to be within a predetermined limit. The steps are repeated until the NILS values are within the predetermined limit. | 12-30-2010 |
| 20110004856 | Inverse Mask Design and Correction for Electronic Design - Various implementations of the invention provide for the generation of “smooth” mask contours by inverse mask transmission derivation and by subsequently “smoothing” the derived mask contours by proximity correction. | 01-06-2011 |
| 20110010678 | Method and Apparatus for Reference Distribution Aerial Image Formation Using Non-Laser Radiation - A non-laser beam of electromagnetic radiation is divided into an illumination beam and a reference beam. A portion of the illumination beam is passed through, or reflected off of, a subject to create a subject distribution, and a portion of the reference beam is passed through a reference object, or reflected off a reference object reflector, to produce a reference distribution. An imaging system is used to form an aerial image of the subject distribution and the reference distribution. The resulting aerial image of the subject distribution exhibits improved resolution, depth of field and field size. | 01-13-2011 |
| 20110016438 | FLASH-BASED ANTI-ALIASING TECHNIQUES FOR HIGH-ACCURACY HIGH-EFFICIENCY MASK SYNTHESIS - Techniques and systems for converting a non-bandlimited pattern layout into a band-limited pattern image are described. During operation, the system receives the non-bandlimited pattern layout which comprises one or more polygons. The system further receives an anti-aliasing filter (AAF) kernel, wherein the AAF kernel is configured to convert a non-bandlimited pattern into a band-limited pattern. The system then constructs an AAF lookup table for the AAF kernel, wherein the AAF lookup table contains precomputed values for a set of convolution functions which are obtained by convolving a set of basis functions with the AAF kernel. Next, the system creates a sampled pattern layout by applying a grid map over the pattern layout. The system then obtains the band-limited pattern image by using the AAF lookup table to convolve the AAF kernel with each grid location in the sampled pattern layout. | 01-20-2011 |
| 20110022994 | Determining Source Patterns for Use in Photolithography - Embodiments of a computer system, a process, a computer-program product (i.e., software), and a data structure or a file for use with the computer system are described. These embodiments may be used to determine or generate source patterns that define illumination patterns on photo-masks during a photolithographic process. Moreover, a given source pattern may be determined concurrently with an associated mask pattern (to which a given photo-mask corresponds) or sequentially (i.e., either the given source pattern may be determined before the associated mask pattern or vice versa.). During the determining, the given source pattern may be represented using one or more level-set functions. Additionally, the source pattern may be determined using an Inverse Lithography (ILT) calculation. | 01-27-2011 |
| 20110029939 | METHOD FOR CORRECTING LAYOUT PATTERN - A method for correcting layout pattern is disclosed. The method includes the steps of: providing a layout pattern having at least one segment; forming a rule-checking rectangle from the segment, wherein the rule-checking rectangle comprises at least one square; verifying whether the square of the rule-checking rectangle overlaps other layout pattern; removing the portion of other layout pattern overlapped by the square to obtain a corrected layout pattern; and outputting the corrected layout pattern to a mask. | 02-03-2011 |
| 20110029940 | METHOD AND APPARATUS FOR MODELING THIN-FILM TOPOGRAPHY EFFECT ON A PHOTOLITHOGRAPHY PROCESS - One embodiment of the present invention provides a system that determines image intensity at a location in a photoresist (PR) layer on a wafer. During operation, the system receives a set of masks which were used to generate one or more patterned layers of a multilayer structure on the wafer, wherein a patterned layer includes a set of reflectors on a top surface of the patterned layer, which correspond to patterns in a patterned-layer mask in the set of masks, wherein a reflector reflects light from a light source during a photolithography process. The system then generates a first virtual mask based on the first mask and the patterned-layer mask, wherein the first virtual mask uses a clear area to model a reflector in the set of reflectors. Next, the system determines the image intensity value at the location on the PR layer based at least on the first mask and the first virtual mask. | 02-03-2011 |
| 20110078639 | FILLER CELLS FOR DESIGN OPTIMIZATION IN A PLACE-AND-ROUTE SYSTEM - A system and method are provided for laying out an integrated circuit design into a plurality of circuit layout cells having gaps therebetween, and inserting into each given one of at least a subset of the gaps, a corresponding filler cell selected from a predefined database in dependence upon a desired effect on a performance parameter of at least one circuit cell adjacent to the given gap. The circuit layout cells may be arranged in rows, and in some embodiments the selection of an appropriate filler cell for a given gap depends upon effects desired on a performance parameter of both circuit cells adjacent to the given gap. The predefined filler cells can include, for example, dummy diffusion regions, dummy poly lines, N-well boundary shifts and etch stop layer boundary shifts. In an embodiment, circuit layout cells can be moved in order to accommodate a selected filler cell. | 03-31-2011 |
| 20110113390 | SMART SELECTION AND/OR WEIGHTING OF PARAMETERS FOR LITHOGRAPHIC PROCESS SIMULATION - The present invention generally relates to simulating a lithographic process, and more particularly to methods for smart selection and smart weighting when selecting parameters and/or kernels used in aerial image computation. According to one aspect, advantages in simulation throughput and/or accuracy can be achieved by selecting TCC kernels more intelligently, allowing highly accurate aerial images to be simulated using a relatively fewer number of TCC kernels than in the state of the art. In other words, the present invention allows for aerial images to be simulated with the same or better accuracy using much less simulation throughput than required in the prior art, all else being equal. | 05-12-2011 |
| 20110113391 | LAYOUT DESIGN TOOL - Design time (TAT) is reduced in a layout design of a semiconductor integrated circuit having a well supplied with a potential different from a substrate potential. A layout design method of the present invention includes preparing a first cell pattern placed on a semiconductor substrate of a first conductive type, preparing a second cell pattern having a deep well of a second conductive type, placing the first cell pattern in a first circuit region, and placing the second cell pattern in a second region different from the first circuit region. This reduces TAT in chip design. | 05-12-2011 |
| 20110154274 | FREQUENCY DIVISION MULTIPLEXING (FDM) LITHOGRAPHY - Systems and methods for generating an image are provided. These systems and methods include generating multiple light beams from a light source by controlling at least one parameter of the light source to be different among each of the multiple light beams. The systems and methods further include forming multiple light patterns of circuit structures that are separated in frequency by directing each of the light beams at a mask of circuit features. The systems and methods, when used in lithography for example, further include directing each of the light patterns toward a silicon substrate. The silicon substrate includes a silicon wafer having a surface at least partially covered with at least one of a photoresist material and a reversible contrast enhancement material (R-CEM). | 06-23-2011 |
| 20110173578 | Method and Apparatus for Enhancing Signal Strength for Improved Generation and Placement of Model-Based Sub-Resolution Assist Features (MB-SRAF) - Model-Based Sub-Resolution Assist Feature (SRAF) generation process and apparatus are disclosed, in which an SRAF guidance map (SGM) is iteratively optimized to finally output an optimized set of SRAFs as a result of enhanced signal strength obtained by iterations involving SRAF polygons and SGM image. SRAFs generated in a prior round of iteration are incorporated in a mask layout to generate a subsequent set of SRAFs. The iterative process is terminated when a set of SRAF accommodates a desired process window or when a predefined process window criterion is satisfied. Various cost functions, representing various lithographic responses, may be predefined for the optimization process. | 07-14-2011 |
| 20110179393 | ETCH-AWARE OPC MODEL CALIBRATION BY USING AN ETCH BIAS FILTER - One embodiment of the present invention relates to a system that constructs and calibrates an etch-aware photolithography model. During operation, the system constructs an etch bias model which models a critical dimension (CD) difference between a measured CD value of a feature after the photolithography process and a measured CD value of the feature after the etch process. The system then fits the photolithography process model based at least on the post-lithography measured CD data and the etch bias model, thereby causing the photolithography process model to be aware of etch effects. The present techniques facilitate bridging the gap between the photolithography and the etch process in the OPC modeling flow. In particular, these techniques can be used to modify conventional staged OPC model or to construct a model based rule table for correcting a retarget model. | 07-21-2011 |
| 20110179394 | Method for Reducing Plasma Discharge Damage During Processing - A semiconductor process and apparatus to provide a way to reduce plasma-induced damage by applying a patterned layer of photoresist ( | 07-21-2011 |
| 20110185324 | METHOD AND APPARATUS FOR CALIBRATING A PHOTOLITHOGRAPHY PROCESS MODEL BY USING A PROCESS WINDOW PARAMETER - One embodiment of the present invention relates to a system that calibrates a photolithography process model. During operation, the system receives a process model which models a photolithography process. The system further receives measured critical dimension (CD) values for a first set of features that were printed by applying the photolithography process to a layout. The system then calibrates the process model using the measured CD values so that CD values predicted by the process model substantially match the measured CD values, and depth of focus (DOF) values predicted by the process model for a second set of features are substantially maximized. | 07-28-2011 |
| 20110191729 | Method and Apparatus for Interconnect Layout in an Integrated Circuit - An embodiment of the invention relates to a computer-implemented method of designing an integrated circuit (IC). In this embodiment, layout data describing conductive layers of the integrated circuit on a substrate is generated according to design specification data for the integrated circuit. The conductive layers include a topmost layer of bond pads. Metal structures in the layout data are modified to maximize metal density in a superimposed plane of the conductive layers within a threshold volume under each of the bond pads. A description of the layout data is generated on one or more masks for manufacturing the integrated circuit. By maximizing metal density in the superimposed plane, vertical channels through the dielectric material in the interconnect are reduced or eliminated. Thus, alpha particles cannot readily penetrate the interconnect and reach the underlying semiconductor substrate, reducing soft errors, such as single event upsets in memory cells. | 08-04-2011 |
| 20110209106 | METHOD FOR DESIGNING OPTICAL LITHOGRAPHY MASKS FOR DIRECTED SELF-ASSEMBLY - A method and a computer system for designing an optical photomask for forming a prepattern opening in a photoresist layer on a substrate wherein the photoresist layer and the prepattern opening are coated with a self-assembly material that undergoes directed self-assembly to form a directed self-assembly pattern. The methods includes: generating a mask design shape from a target design shape; generating a sub-resolution assist feature design shape based on the mask design shape; using a computer to generate a prepattern shape based on the sub-resolution assist feature design shape; and using a computer to evaluate if a directed self-assembly pattern of the self-assembly material based on the prepattern shape is within specified ranges of dimensional and positional targets of the target design shape on the substrate. | 08-25-2011 |
| 20110209107 | MASK-LAYOUT CREATING METHOD, APPARATUS THEREFOR, AND COMPUTER PROGRAM PRODUCT - According to one embodiment, a design layout highly likely to be a dangerous point in a lithography process is set, a coherence map kernel for generating the mask layout is set with respect to the set design layout, the coherence map is created based on the set coherence map kernel and the set design layout, the auxiliary pattern is extracted from the created coherence map and shaped to generate the mask layout, a cost function COST for evaluating an optimization degree of the mask layout is defined, the generated mask layout is evaluated using the cost function, and at least one of parameters of the coherence map kernel and parameters in extracting and shaping the auxiliary pattern from the coherence map are changed until the mask layout evaluated using the cost function is optimized. | 08-25-2011 |
| 20110225555 | Structural feature formation within an integrated circuit - An integrated circuit is formed using an lithographic process including a stage of forming a lithographic layer from a plurality of separately printed pattern layers. Within the integrated circuit there is formed a circuit including at least two devices that are matched devices such that the performance of the circuit is degraded if the match devices deviate from having matched performance characteristics. Dummy contacts | 09-15-2011 |
| 20110239169 | EMF CORRECTION MODEL CALIBRATION USING ASYMMETRY FACTOR DATA OBTAINED FROM AERIAL IMAGES OR A PATTERNED LAYER - A computer-implemented method is provided for generating an electromagnetic field (EMF) correction boundary layer (BL) model corresponding to a mask, which can include using a computer to perform a method, in which asymmetry factor data is determined from aerial image measurements of a plurality of different gratings representative of features provided on a mask, wherein the aerial image measurements having been made at a plurality of different focus settings. The method may also include determining boundary layer (BL) model parameters of an EMF correction BL model corresponding to the mask by fitting to the asymmetry factor measurements. Alternatively, the asymmetry factor data can be determined from measurements of line widths of photoresist patterns, wherein the photoresist patterns correspond to images cast by a plurality of gratings at a plurality of different defocus distances, and the gratings can be representative of features of a mask. | 09-29-2011 |
| 20110239170 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, METHOD FOR GENERATING MASK DATA, MASK AND COMPUTER READABLE RECORDING MEDIUM - A semiconductor device has first wiring layers | 09-29-2011 |
| 20110252387 | METHOD AND APPARATUS FOR REDUCING IMPLANT TOPOGRAPHY REFLECTION EFFECT - Embodiments of the present disclosure provide methods and apparatuses for integrated circuits. An exemplary integrated circuit (IC) method includes providing an IC design layout that includes a design feature; determining a dimensional difference between the design feature and a corresponding developed photoresist feature of a photoresist layer; modifying the CD of the design feature to compensate for the difference, thereby generating a modified IC design layout; and making a mask using the modified IC design layout. | 10-13-2011 |
| 20110271238 | DECOMPOSITION WITH MULTIPLE EXPOSURES IN A PROCESS WINDOW BASED OPC FLOW USING TOLERANCE BANDS - Setting final dimensions while protecting against the possibility of merging shapes is provided by performing a decomposition of tolerance bands onto a plurality of masks for use in a multi-exposure process. This allows the maximum process latitude between open and short failure mechanisms, while also providing a mechanism to enforce strict CD tolerances in critical regions of a circuit. The decomposition enables co-optimizing various types of shapes placed onto each mask along with the source used to print each mask. Once the tolerance bands are decomposed onto the two or more masks, standard tolerance-band-based data preparation methodologies can be employed to create the final mask shapes. | 11-03-2011 |
| 20110271239 | Lithography Performance Check Methods and Apparatus - The present disclosure provides for many different embodiments. A mask fabrication method and system is provided. The method and system identify critical areas of an integrated circuit (IC) design layout that has undergone optical proximity correction. The critical areas are areas of the OPCed IC design layout that are at risk for hot spots. A lithography process check is then performed on the critical areas of the OPCed IC design layout. | 11-03-2011 |
| 20110271240 | METHOD AND SYSTEM FOR COMPUTING FOURIER SERIES COEFFICIENTS FOR MASK LAYOUTS USING FFT - A method and system for computing Fourier coefficients for a Fourier representation of a mask transmission function for a lithography mask. The method includes: sampling a polygon of a mask pattern of the lithography mask to obtain an indicator function which defines the polygon, performing a Fourier Transform on the indicator function to obtain preliminary Fourier coefficients, and scaling the Fourier coefficients for the Fourier representation of the mask transmission function, where at least one of the steps is carried out using a computer device. | 11-03-2011 |
| 20110283244 | Test Pattern for Contour Calibration in OPC Model Build - A method of calibrating a lithographic process model is provided. The method includes providing a test pattern that includes a plurality of shapes; transferring the test pattern onto a photo-mask forming a resist image of the test pattern using the photo-mask; collecting model calibration data from the resist image; and calibrating the lithographic process model using the model calibration data, wherein the plurality of shapes of the test pattern have at least a first shape and a second shape, and distances from an edge of the first shape to an edge of the second shape over a range thereof, when being measured parallel to each other, differ from each other. | 11-17-2011 |
| 20110307845 | PATTERN DIMENSION CALCULATION METHOD AND COMPUTER PROGRAM PRODUCT - A pattern dimension calculation method according to one embodiment calculates a taper shape of a mask member used as a mask when a circuit pattern is processed in an upper layer of the circuit pattern formed on a substrate. The method calculates an opening angle facing the mask member from a shape prediction position on the circuit pattern on the basis of the taper shape. The method calculates a dimension of the circuit pattern according to the opening angle formed at the shape prediction position. | 12-15-2011 |
| 20110320988 | LAYOUT PATTERN GENERATING APPARATUS AND LAYOUT PATTERN GENERATING METHOD - An apparatus for generating a layout pattern of each element includes a storage, a basic figure generator, an additional figure generator, a display unit and an operation input unit; wherein the storage stores terminal figure relative position information, figure adjustment value information and additional figure relative position information; the basic figure generator generates an effective area figure and a terminal figure of a layout pattern generation target element on the basis of the terminal figure relative position information and the figure adjustment value information; the additional figure generator generates the additional figure of the layout pattern generation target element on the basis of the generated effective area figure and terminal figure and the additional figure relative position information; the display unit displays the generated effective area figure, terminal figure and additional figure; and the figure adjustment value information is changed depending on an input from the operation input unit. | 12-29-2011 |
| 20120005637 | SMART SELECTION AND/OR WEIGHTING OF PARAMETERS FOR LITHOGRAPHIC PROCESS SIMULATION - The present invention generally relates to simulating a lithographic process, and more particularly to methods for smart selection and smart weighting when selecting parameters and/or kernels used in aerial image computation. According to one aspect, advantages in simulation throughput and/or accuracy can be achieved by selecting TCC kernels more intelligently, allowing highly accurate aerial images to be simulated using a relatively fewer number of TCC kernels than in the state of the art. In other words, the present invention allows for aerial images to be simulated with the same or better accuracy using much less simulation throughput than required in the prior art, all else being equal. | 01-05-2012 |
| 20120017184 | SYSTEM FOR CREATING LAYOUT PATTERN FOR MANUFACTURING MASK ROM, MASK ROM MANUFACTURED USING THE SYSTEM, AND METHOD FOR CREATING MASK PATTERN - When generating a temporary ROM code file and a design information file, a host server generates a dedicated ROM compiler and an intermediate file associated with the dedicated ROM compiler. In a workstation, the dedicated ROM compiler is executed, whereby the contents of a design information file are changed to the contents corresponding to a correct ROM code. The dedicated ROM compiler is specifically designed to be capable of changing only a particular design parameter and the design information file associated with the temporary ROM code file. | 01-19-2012 |
| 20120042290 | Method of Selecting a Set of Illumination Conditions of a Lithographic Apparatus for Optimizing an Integrated Circuit Physical Layout - The invention relates to a method of selecting a set of illumination conditions of a lithographic apparatus, in a process for transferring an integrated circuit layout to a target substrate. The layout is comprised of a number of polygon patterns having a predetermined geometrical relation relative to each other. An initial set of illumination conditions is provided and a plurality of polygon patterns requiring illumination conditions critical for circuit functionality. For the initial set of illumination conditions a local cost number is calculated, defining a difference measure of at least one critical dimension, between the polygon pattern and a transferred polygon pattern as a function of illumination condition. For each polygon pattern the cost numbers are aggregated; and the illumination conditions are varied so as to select an optimal set of illumination conditions having an optimized aggregated cost number. Polygon patterns are identified as predefined complex circuit elements and wherein the cost numbers are expressed as circuit element cost number functions that are individually associated with said identified complex circuit elements, so as to express circuit design intent. The cost number functions can further have interdependencies in multiple critical dimensions of the polygon patterns so as to take the two dimensional nature into account. | 02-16-2012 |
| 20120042291 | Inverse Mask Design and Correction for Electronic Design - Various implementations of the invention provide for the generation of “smooth” mask contours by inverse mask transmission derivation and by subsequently “smoothing” the derived mask contours by proximity correction. | 02-16-2012 |
| 20120047475 | SEMICONDUCTOR DEVICE - A semiconductor device is provided having a physical pattern based on a designed pattern, the designed pattern including a target pattern and a correction pattern designed for a pattern to be formed on a wafer; the target pattern includes a first portion of an edge with a first distance, a second portion of the edge with a second distance, which is different from the first distance, and a third portion of the edge having a first region of the edge with the first distance and a second region of the edge with the second distance; and the correction pattern is added to at least one of the first portion, the second portion, and the third portion such that the first portion, the second portion, and the third portion are caused to differ from one another in dimensions of the designed pattern. | 02-23-2012 |
| 20120060131 | Method And Apparatus For Merging Multiple Geometrical Pixel Images And Generating A Single Modulator Pixel Image - The present invention relates to customizing individual workpieces, such as chip, flat panels or other electronic devices produced on substrates, by direct writing a custom pattern. Customization can be per device, per substrate, per batch or at some other small volume that makes it impractical to use a custom mask or mask set. In particular, it relates to customizing a latent image formed in a radiation sensitive layer over a substrate, merging standard and custom pattern data to form a custom pattern used to produce the customized latent image. A wide variety of substrates can benefit from the technology disclosed. | 03-08-2012 |
| 20120060132 | Non-Linear Rasterized Contour Filters - A system includes a conversion module that preserves the shape of a contour when converting an image to a different resolution. The conversion module receives a first image and divides the first image into regions of pixel values. For each region, a contribution of the region to the pixel values in the second image is determined. The contribution is selected from a set of pre-determined contributions that are a nonlinear function of the values in the region, and the selection is made based at least in part on the values in the region. The contributions are accumulated together to generate a second image. The conversion module may be, for example, part of a design flow for an integrated circuit that connects a mask simulation stage with an optical simulation stage. | 03-08-2012 |
| 20120066652 | Technique for Analyzing a Reflective Photo-Mask - During a calculation technique, contributions to reflected light from multiple discrete cells in a model of a multilayer stack in a reflective photo-mask may be determined based on angles of incidence of light in a light pattern to the multilayer stack, a polarization of the light in the light pattern, and a varying intensity of the light in the light pattern through the multilayer stack. Then, phase values of the contributions to the reflected light from the multiple discrete cells are adjusted, thereby specifying optical path differences between the multiple discrete cells in the multilayer stack that are associated with the defect. Moreover, the contributions to the reflected light from multiple discrete cells are combined to determine the reflected light from the multilayer stack. Next, k-space representations of the contributions to the reflected light from the multiple discrete cells are selectively shifted based on the angles of incidence. | 03-15-2012 |
| 20120066653 | DOSE-DATA GENERATING APPARATUS, DOSE-DATA GENERATING METHOD, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - According to one embodiment, generating virtual data by mirroring data based on a dimension measurement result in a measurement region on an inner side of a shot region to a non-shot region on an outer side of a shot edge, and calculating dose data of the measurement region and a non-measurement region based on data in the measurement region and the virtual data are included. | 03-15-2012 |
| 20120079436 | Fast photoresist model - A method of modeling an image intended to reside in a photoresist film on a substrate is provided. A simulated latent acid image of the image is produced, the simulated latent acid image is compressed in a predetermined direction, and developed to a pattern that enables (a) transfer of the pattern to the substrate or (b) further modeling of the pattern for transfer to the substrate. | 03-29-2012 |
| 20120084741 | STRUCTURE, DESIGN STRUCTURE AND PROCESS FOR INCREASING MAGNITUDE OF DEVICE THRESHOLD VOLTAGE FOR LOW POWER APPLICATIONS - A method of increasing an initial threshold voltage (Vt) of selected devices. The method includes designing devices with desired antenna effects and adjusting an increase in Vt of some devices to specific values. The desired antenna effects produce a desired threshold voltage of the devices. | 04-05-2012 |
| 20120102442 | SYSTEM AND METHOD FOR MODEL BASED MULTI-PATTERNING OPTIMIZATION - Some embodiments provide a method for optimally decomposing patterns within particular spatial regions of interest on a particular layer of a design layout for a multi-exposure photolithographic process. Specifically, some embodiments model the spatial region using a mathematical equation in terms of two or more intensities. Some embodiments then optimize the model across a set of feasible intensities. The optimization yields a set of intensities such that the union of the patterns created/printed from each exposure intensity most closely approximates the patterns within the particular regions. Based on the set of intensities, some embodiments then determine a decomposition solution for the patterns that satisfies design constraints of a multi-exposure photolithographic printing process. In this manner, some embodiments achieve an optimal photolithographic printing of the particular regions of interest without performing geometric rule based decomposition. | 04-26-2012 |
| 20120110524 | METHODS, PHOTOMASKS AND METHODS OF FABRICATING PHOTOMASKS FOR IMPROVING DAMASCENE WIRE UNIFORMITY WITHOUT REDUCING PERFORMANCE - A method of improving damascene wire uniformity without reducing performance. The method includes simultaneously forming a multiplicity of damascene wires and a multiplicity metal dummy shapes in a dielectric layer of a wiring level of an integrated circuit chip, the metal dummy shapes dispersed between damascene wires of the multiplicity of damascene wires; and removing or modifying those metal dummy shapes of the multiplicity of metal dummy shapes within exclusion regions around selected damascene wires of the multiplicity of damascene wires. Also a method of fabricating a photomask and a photomask for use in improving damascene wire uniformity without reducing performance. | 05-03-2012 |
| 20120117523 | INVERSE LITHOGRAPHY FOR HIGH TRANSMISSION ATTENUATED PHASE SHIFT MASK DESIGN AND CREATION - Various implementations of the invention provide for generation of a high transmission phase shift mask layout through inverse lithography techniques. In various implementations of the present invention, a set of mask data having a plurality of pixels is generated. The transmission value associated with each pixel may then be determined through an inverse lithography technique. With various implementations of the invention, the inverse lithography technique identifies an objective function, minimizes the objective function in relation to a simulation of the optical lithographic process, such that the transmission value, which is greater than 6%, may be determined. | 05-10-2012 |
| 20120124530 | MAKING A DISCRETE SPATIAL CORRELATION CONTINUOUS - A mechanism is provided for making a discrete spatial correlation on a 2D grid continuous. The region has given grid points and each of the grid points has its discrete stochastic variable. Additional grid points and associated stochastic variables are established on the boundary and corners of the region. All correlation coefficients are obtained among the given discrete stochastic variables and the additional discrete stochastic variables. For each of two given spatial points whose spatial correlation is needed, a quadrilateral containing it is identified by four grid points, and a stochastic variable for it is expressed as a weighted linear combination of four stochastic variables at four grid points, with four weights being a continuous function of the coordinate of the point. The resulting spatial correlation is a weighted linear combination of multiple discrete correlation coefficients each weight being a continuous function of the coordinates of the two given points. | 05-17-2012 |
| 20120124531 | I/O CELL ARCHITECTURE - A system includes a computer readable storage medium and a processor. The computer readable storage includes data representing an input/output (“I/O”) cell of a first type for modeling and/or fabricating a semiconductor device. The I/O cell of the first type includes circuitry for providing a first plurality of functions. The processor is in communication with the computer readable storage medium and is configured to select the I/O cell of the first type, arrange a plurality of the I/O cells of the first type on a model of an semiconductor device, and store the model of the semiconductor device including the plurality of the I/O cells of the first type in the computer readable storage medium. | 05-17-2012 |
| 20120131522 | METHOD FOR GENERATING ULTRA-SHORT-RUN-LENGTH DUMMY POLY FEATURES - A method and apparatus for designing a lithography mask set which provides polygon features of a desired size at advanced technology nodes, for example, using live features and dummy features. A dummy feature can be formed within a confined space by specifying an allowable dummy feature length even though the feature length may result in contact between the dummy feature and the live feature. After specifying the dummy feature length, a pattern generation (PG) extract can be performed to pull back the dummy feature away from the live feature by an allowable distance. The PG exact process can result in a shorter dummy feature which has a length which is shorter than can be specified directly by design rules, but which passes rule checking. | 05-24-2012 |
| 20120167021 | Cell Layout for Multiple Patterning Technology - A system and method for providing a cell layout for multiple patterning technology is provided. An area to be patterned is divided into alternating sites corresponding to the various masks. During a layout process, sites located along a boundary of a cell are limited to having patterns in the mask associated with the boundary site. When placed, the individual cells are arranged such that the adjoining cells alternate the sites allocated to the various masks. In this manner, the designer knows when designing each individual cell that the mask pattern for one cell will be too close to the mask pattern for an adjoining cell. | 06-28-2012 |
| 20120180007 | REPLACING SINGLE-CUT VIA INTO MULTI-CUT VIA IN SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN - According an aspect of the invention, there is provided a design support system of a semiconductor integrated circuit includes: a first unit configured to determine a wiring path by calculating wiring resource consuming information for carrying out a connection through a multi-cut via in case that the connection is carried out through the multi-cut via in a wiring region having a plurality of layers; and a second unit configured to replacing a single-cut via into the multi-cut via. | 07-12-2012 |
| 20120192125 | Correcting and Optimizing Contours for Optical Proximity Correction Modeling - A contour biasing method can include receiving contour input files, processing the contour input files, receiving contour measurements, receiving raw contour data, processing the raw contour data and outputting processed contour data based on the contour input files. | 07-26-2012 |
| 20120192126 | SYSTEMS AND METHODS PROVIDING ELECTRON BEAM PROXIMITY EFFECT CORRECTION - A method for writing a design to a material using an electron beam includes assigning a first dosage to a first polygonal shape. The first polygonal shape occupies a first virtual layer and includes a first set of pixels. The method also includes simulating a first write operation using the first polygonal shape to create the design, discerning an error in the simulated first write operation, and assigning a second dosage to a second polygonal shape to reduce the error. The second polygonal shape occupies a second virtual layer. The method further includes creating a data structure that includes the first and second polygonal shapes and saving the data structure to a non-transitory computer-readable medium. | 07-26-2012 |
| 20120192127 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A space area is extracted from a product area on which element patterns are laid out and a mark region is extracted from the space area in the product area under a predetermined condition. The product area is divided into multiple regions and a monitor pattern forming region is selected from the mark regions for each divided region under a predetermined condition. A monitor pattern is laid out within the selected monitor pattern forming region. | 07-26-2012 |
| 20120204136 | METHOD AND SYSTEM FOR FEATURE FUNCTION AWARE PRIORITY PRINTING - A method and system for photomask pattern generation is provided, and more specifically, a method and system for feature function aware priority printing is provided. The method of printing a photolithographic mask includes fracturing mask design data into write shapes that are multiples of a spot size and passing fractured mask design data to a write tool. Additionally, the method includes writing one or more non-critical shapes according to one or more time-saving rules. | 08-09-2012 |
| 20120216157 | ROUTING ANALYSIS WITH DOUBLE PATTERN LITHOGRAPHY - Graph analysis for double pattern lithography is described. Layout shapes are decomposed into rectangles and a vertex is provided for each rectangle. Double pattern spacing conflicts are determined and shown as edges for the graph analysis. Odd cycles are used to identify double pattern lithography violations. Cycles can be completed with the addition of edges between vertices where stitches have been included in the layout. Edges between touching shapes do not count toward the odd count in the cycles. Fixes are included by increasing space or by rerouting. A portion of the layout can be incrementally changed and a local update of the graph analysis performed. Correct by construction layout is implemented by avoiding certain odd cycle prone layout routings. | 08-23-2012 |
| 20120221985 | METHOD AND SYSTEM FOR DESIGN OF A SURFACE TO BE MANUFACTURED USING CHARGED PARTICLE BEAM LITHOGRAPHY - A method and system for fracturing or mask data preparation are disclosed which can reduce the critical dimension variation of patterns formed on a resist-coated surface using particle beam lithography by providing a higher peak dosage near the perimeter of the patterns than in the interiors of the patterns. | 08-30-2012 |
| 20120227018 | Method and Apparatus of Patterning Semiconductor Device - Provided is an apparatus for fabricating a semiconductor device. The apparatus includes a first photomask and a second photomask. The first photomask has a plurality of first features thereon, and the first photomask having a first global pattern density. The second photomask has a plurality of second features thereon, and the second photomask has a second global pattern density. The plurality of first and second features collectively define a layout image of a layer of the semiconductor device. The first and second global pattern densities have a predetermined ratio. | 09-06-2012 |
| 20120233575 | LAYOUT METHOD FOR INTEGRATED CIRCUIT INCLUDING VIAS - A layout method for an integrated circuit including vias connecting stacked metal layers through cuts in intermediate cut layers includes generating interconnection blockage and obstruction statements that define exclusion regions of the metal layers blocked by existing initial interconnections for routing additional interconnections. Shape, size and spacing data are generated for de-selection areas of the exclusion regions in the conductive layers. The de-selection areas are sufficiently far from the boundaries of the exclusion regions that cut spacing rules applied to the initial cuts within the de-selection areas do not block placement of additional cuts outside the exclusion regions of the conductive layers. Only those of the initial cuts within the exclusion regions that lie outside the de-selection areas are selected. Cut blockage and obstruction statements are generated for the selected cuts. A layout view is derived, including routing the additional interconnections in the electrically conductive layers and placing the additional cuts. | 09-13-2012 |
| 20120246603 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, METHOD FOR GENERATING MASK DATA, MASK AND COMPUTER READABLE RECORDING MEDIUM - A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines. | 09-27-2012 |
| 20120304134 | EXPOSURE DATA GENERATION METHOD - An exposure data generation method includes generating a first multi-layer wiring pattern including a plurality of wiring layers according to a netlist and a wiring rule; dividing a layer pattern of each layer included in the generated first multi-layer wiring pattern by a subfield; by referring to a pattern database in which a subfield pattern of a wiring layer, included in a second multi-layer wiring pattern generated in the subfield according to the wiring rule, and a pattern identifier corresponding to the subfield pattern are registered, extracting the pattern identifier of the subfield pattern corresponding to the divided layer pattern of the first multi-layer wiring pattern; and generating exposure data including the extracted pattern identifier and an exposure position of the subfield pattern corresponding to the extracted pattern identifier. | 11-29-2012 |
| 20120324407 | SIMULATION MODEL CREATING METHOD, COMPUTER PROGRAM PRODUCT, AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - According to a simulation model creating method of an embodiment, a resist pattern is formed by transferring a mask pattern on a first substrate with an exposing amount and a focus value being changed, and a line width of the resist pattern is measured. Next, measurement results which are not within an allowable change range due to an irregularity of the exposing amount, an irregularity of the focus value or pattern feature amount are removed. In addition, measurement results which are not with in an allowable change range due to an irregularity of the line width of the mask pattern are removed. Next, a simulation model is created by using measurement results which are not removed. | 12-20-2012 |
| 20130024825 | MASK DATA GENERATION METHOD, MASK GENERATION METHOD, AND RECORDING MEDIUM - According to one embodiment, there is provided a mask data generation method. The method repeatedly arranges hole patterns with a pitch Px in an x direction and a pitch Py in a y direction in each of a first block region and a second block region aligned in the y direction. The method specifies a pitch P between the hole pattern in the first block region closest to the second block region and the hole pattern in the second block region closest to the first block region. The method determines a position in which a subsidiary pattern is to be arranged in an inter-block region between the first block region and the second block region according to a relative size of the pitch P to the pitch Py and arranges the subsidiary pattern in the determined position. | 01-24-2013 |
| 20130042213 | Data Flow Branching in Mask Data Preparation - Branching of the data-flow in a mask data preparation processes is described herein. In various implementations, the output stream from a first mask data processing operation is branched. Subsequently, the branched output stream may be connected to the input stream of a first independent mask data preparation operation and a second independent mask data preparation operation. This provides that the first and the second independent mask data preparation operations may operate in parallel. Furthermore, this provides that the first and the second independent mask data preparation operations may operate upon discrete “portions” of the data processed by the first mask data preparation operation. | 02-14-2013 |
| 20130061185 | MASK ASSIGNMENT FOR MULTIPLE PATTERNING LITHOGRAPHY - A mechanism is provided for mask assignment for triple patterning lithography. The mechanism identifies tip-to-tip (TT), tip-to-side (TS), and side-to-side (SS) conflicting parts by design rule dependent projection. The mechanism finds stitch location for TT, TS, and SS conflicts separately. The mechanism colors TT, TS, and SS conflicting parts with mask0/mask1, mask0/mask2, mask1/mask2 coloring cycle with each type colored separately. The mechanism uses existing infrastructure of two-way coloring. As a first objective, the mechanism attempts to minimize conflicts. As a second objective, the mechanism attempts to minimize the number of stitches by assigning the two sides of stitches to the same mask. Once coloring of all conflicting parts is done, the mechanism colors non-conflicting parts to maximize minimum overlap of exposures and to use both colors if two sides are different colors and one color if both sides are the same color. | 03-07-2013 |
| 20130061186 | MULTI-PATTERNING METHOD - A method includes receiving data representing a layout of a DPT-layer of an integrated circuit generated by a place and route tool. The layout includes a plurality of polygons to be formed in the DPT-layer by a multi-patterning process. First and second ones of the plurality of polygons to be formed using first and second photomasks, respectively are identified. Any intervening polygons along a first path connecting the first polygon to the second polygon, and separator regions between adjacent polygons along the first path are identified. The separator regions have sizes less than a minimum threshold distance between polygons formed on the first photomask. The separator regions are counted. A multi-patterning conflict is identified, if the count of separator regions is even, prior to assigning all remaining ones of the plurality of polygons to the first or second masks. | 03-07-2013 |
| 20130061187 | STRIPING METHODOLOGY FOR MASKLESS LITHOGRAPHY - The present disclosure involves a method of performing a maskless lithography process. The method includes receiving a computer layout file for an integrated circuit (IC) device. The layout file contains a plurality of IC sections. The method includes separating the computer layout file into a plurality of sub-files. The method includes striping the plurality of sub-files concurrently using a plurality of computer processors, thereby generating a plurality of striped sub-files. The method includes transferring the plurality of striped sub-files to a maskless lithography system. | 03-07-2013 |
| 20130074018 | MULTI-PATTERNING METHOD - A method comprises (a) receiving data representing a layout of a DPT-layer of an integrated circuit generated by a place and route tool, the layout including a plurality of polygons to be formed in the DPT-layer by a multi-patterning process; (b) receiving at least one identification of a subset of the plurality of polygons that are to be formed in the DPT-layer using the same photomask as each other; (c) constructing a graph of the subset of the plurality of polygons and any intervening polygons of the plurality of polygons, where the subset of the plurality of polygons are represented in the graph by a single node, the graph including connections connecting adjacent ones of the polygons in the graph that are positioned within a threshold distance of each other; and (d) identifying a multi-patterning conflict if any subset of the connections form an odd loop. | 03-21-2013 |
| 20130086536 | METHOD OF GENERATING STANDARD CELL LIBRARY FOR DPL PROCESS AND METHODS OF PRODUCING A DPL MASK AND CIRCUIT PATTERN USING THE SAME - A method of constructing a standard cell library for double patterning lithography (DPL) includes dividing a standard cell into a first region determined not to have an interaction with an adjacent outer cell and a second region that is likely to have such an interaction, generating data representative of DPL patterns corresponding to the first and second regions, and generating a standard cell library made up of the data. The library is then accessed and used to form a DPL mask. The DPL mask can be used to form a pattern on a substrate made up of a layout of cells in which the pattern of the standard cell is duplicated at several locations in the layout. | 04-04-2013 |
| 20130091476 | METHOD AND SYSTEM FOR REPLACING A PATTERN IN A LAYOUT - A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output. | 04-11-2013 |
| 20130111421 | Method and Apparatus for Model Based Flexible MRC | 05-02-2013 |
| 20130132914 | Method and Apparatus for Placing Transistors In Proximity to Through-Silicon Vias - Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone. | 05-23-2013 |
| 20130174106 | STITCH AND TRIM METHODS FOR DOUBLE PATTERNING COMPLIANT STANDARD CELL DESIGN - A method for creating double patterning compliant integrated circuit layouts is disclosed. The method allows patterns to be assigned to different masks and stitched together during lithography. The method also allows portions of the pattern to be removed after the process. | 07-04-2013 |
| 20130179848 | SYSTEM AND METHOD OF CIRCUIT LAYOUT FOR MULTIPLE CELLS - A method and system check a double patterning layout in abutting cells and switch the pattern in one of the cells if the edge patterns in each cell are in the same mask. The method includes receiving layout data having patterns in abutting cells, changing a designated mask in one cell if the edge patterns are in the same mask, adjusting cell edge spacings at a shared edge according to a minimum spacing rule and a G1-rule, and outputting a presentation of the layout data. | 07-11-2013 |
| 20130191796 | INTEGRATED CIRCUIT LAYOUT MODIFICATION - Methods are disclosed of modifying an integrated circuit (IC) design that utilizes multiple patterning technology (MPT). The methods include configuring a first layout of an integrated circuit, having at least one layer with features to be formed utilizing fabrication by at least two masks. The at least one layer includes a plurality of active cells and a plurality of spare cells. A second layout is configured to re-route the spare cells and active cells, wherein the re-routing utilizes at least a portion of the plurality of spare cells. Fewer than all of the at least two masks are replaced to configure the second layout. | 07-25-2013 |
| 20130205266 | COLORING/GROUPING PATTERNS FOR MULTI-PATTERNING - A method comprises: accessing a persistent, machine readable storage medium containing data representing an integrated circuit (IC) design to be fabricated using multi-patterning; identifying at least one network of conductive patterns configured to transmit signals that substantially impact timing of at least one circuit in the IC; pre-grouping the at least one network of conductive patterns in a first group; and electronically providing data to an electronic design automation (EDA) tool to cause inclusion in a first single photomask of all portions of the patterns within the first group that are to be formed in a single layer of the IC, wherein the single layer is to be multi-patterned using at least two photomasks. | 08-08-2013 |
| 20130205267 | PATTERN DATA SYSTEM FOR HIGH-PERFORMANCE MASKLESS ELECTRON BEAM LITHOGRAPHY - One embodiment relates to a pattern data system for maskless electron beam lithography. The system includes a renderer that receives pre-exposure die image data, performs rendering of the pre-exposure die image data to generate raster data. The system further includes a plurality of data distributors communicatively coupled to the renderer. Each data distributor adapts the raster data to characteristics of an associated pattern writer. Other embodiments, aspects and feature are also disclosed. | 08-08-2013 |
| 20130212544 | SYSTEM AND METHOD OF ELECTROMIGRATION MITIGATION IN STACKED IC DESIGNS - A computer implemented method comprises accessing a 3D-IC model stored in a tangible, non-transitory machine readable medium, processing the model in a computer processor to generate a temperature map containing temperatures at a plurality of points of the 3D-IC under the operating condition; identifying an electromigration (EM) rating factor, and calculating and outputting from the processor data representing a temperature-dependent EM current constraint at each point. | 08-15-2013 |
| 20130219351 | METHOD OF DESIGNING A PHOTO MASK LAYOUT - A method of designing a photo mask layout may include selecting a target pattern from polygonal patterns in a layout, setting a reference point on the target pattern, obtaining a target raster at the reference point, and comparing the target raster with a hot-spot raster to determine whether the target pattern corresponds to a failure pattern. | 08-22-2013 |
| 20130227499 | LAYOUT METHOD FOR SOFT-ERROR HARD ELECTRONICS, AND RADIATION HARDENED LOGIC CELL - This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modem technologies (.ltoreq.90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors. | 08-29-2013 |
| 20130227500 | Calculation System For Inverse Masks - A system for calculating mask data to create a desired layout pattern on a wafer reads all or a portion of a desired layout pattern. Mask data having pixels with transmission values is defined along with corresponding optimal mask data pixel transmission values. An objective function is defined that compares image intensities as would be generated on a wafer with an optimal image intensity at a point corresponding to a pixel. The objective function is minimized to determine the transmission values of the mask pixels that will reproduce the desired layout pattern on a wafer. | 08-29-2013 |
| 20130239073 | METHOD AND SYSTEM FOR FEED-FORWARD ADVANCED PROCESS CONTROL - Embodiments of the present disclosure disclose a method of forming a new integrated circuit design on a semiconductor wafer using a photolithography tool. The method includes selecting a previously processed wafer having a past integrated circuit design different than the new integrated circuit design, selecting a plurality of critical dimension (CD) data points extracted from the previously processed wafer after the previously processed wafer was etched, and creating a field layout and associated baseline exposure dose map for the new integrated circuit design. The method also includes refining each field in the baseline exposure dose map based on a difference between an average CD for the previously processed wafer and an average CD for each field in the field layout and controlling the exposure of the photolithography tool according to the refined baseline exposure dose map to form the new integrated circuit design on the semiconductor wafer. | 09-12-2013 |
| 20130246983 | GATE CD CONTROL USING LOCAL DESIGN ON BOTH SIDES OF NEIGHBORING DUMMY GATE LEVEL FEATURES - A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W | 09-19-2013 |
| 20130263065 | PRE-COLORED METHODOLOGY OF MULTIPLE PATTERNING - Some embodiments relate to a method for pre-coloring data within an integrated chip layout to avoid overlay errors that result from mask misalignment during multiple patterning lithography. The method may be performed by generating a graphical IC layout file containing an integrated chip layout having a plurality of IC shapes. The IC shapes within the graphical IC layout file are assigned a color during decomposition. The IC shapes are further pre-colored in a manner that deliberately assigns the pre-colored data to a same mask. During mask building data associated with IC shapes that have been pre-colored is automatically sent to a same mask, regardless of the colors that are assigned to the shapes. Therefore, the pre-colored shapes are not assigned to a masked based upon a decomposition, but rather based upon the pre-coloring. By assigning IC shapes to a same mask through pre-coloring, overlay errors can be reduced. | 10-03-2013 |
| 20130263066 | Pre-Colored Methodology of Multiple Patterning - Some embodiments relate to a method of pre-coloring word lines and control lines within an SRAM integrated chip design to avoid timing delays that result from processing variations introduced through multiple patterning lithography processes. The method is performed by generating a graphical IC layout file having an SRAM circuit with a plurality of word lines and Y-control lines. The word lines and Y-control lines are assigned a color during decomposition. The word lines and Y-control lines are further pre-colored in a manner that deliberately assigns the pre-colored data to a same mask. Therefore, during mask building, data associated with pre-colored word and Y-control lines is sent to a same mask, regardless of the colors that are assigned to the data. By assigning word and Y-control lines to a same mask through pre-coloring, processing variations between the word and Y-control lines are minimized, thereby mitigating timing variations in an SRAM circuit. | 10-03-2013 |
| 20130290914 | Methods and Apparatus for Floorplanning and Routing Co-Design - Methods and apparatus of performing floorplanning and routing for function blocks within a die and among multiple die are disclosed. Multiple die together with function blocks within each die may be represented by a flexible hierarchical (FH) tree. An initial floorplan for multiple die may be generated and hot spots between die or among function blocks within a die may be identified. Spacer blocks may be inserted between die, and block inflation may be performed, to remove hot spots. More perturbation of the block positions can be performed on the FH tree to rearrange the blocks and die. After the multiple die floorplanning, a plurality of micro bumps may be mapped to a plurality of pins of blocks of the plurality of die, placement and routing may be performed for the plurality of blocks within each die and connections for the plurality of dies. | 10-31-2013 |
| 20130311960 | METHOD AND APPARATUS FOR ENHANCING SIGNAL STRENGTH FOR IMPROVED GENERATION AND PLACEMENT OF MODEL-BASED SUB-RESOLUTION ASSIST FEATURES (MB-SRAF) - Model-Based Sub-Resolution Assist Feature (SRAF) generation process and apparatus are disclosed, in which an SRAF guidance map (SGM) is iteratively optimized to finally output an optimized set of SRAFs as a result of enhanced signal strength obtained by iterations involving SRAF polygons and SGM image. SRAFs generated in a prior round of iteration are incorporated in a mask layout to generate a subsequent set of SRAFs. The iterative process is terminated when a set of SRAF accommodates a desired process window or when a predefined process window criterion is satisfied. Various cost functions, representing various lithographic responses, may be predefined for the optimization process. | 11-21-2013 |
| 20130318483 | STANDARDIZED TOPOGRAPHICAL ARRANGEMENTS FOR TEMPLATE REGIONS THAT ORIENT SELF-ASSEMBLY - This disclosure relates generally to systems and methods of providing standardized topographical configurations for template regions. In one embodiment, a set of array arrangements is selected. Arrays of template structures are then formed on at least one substrate. Each of the arrays is arranged in accordance with an array arrangement in the set of array arrangements such that the arrays correspond surjectively onto the set of array arrangements. After the arrays are formed, a self-assembly material is provided on the arrays. Self-assembly patterns formed by self-assembling material as a result of the arrays may be empirically observed and used to map a set of self-assembly pattern arrangements surjectively onto the set of array arrangements. Using this mapping, a combination of the self-assembly pattern arrangements that match a target pattern arrangement can be used to select a combination of array arrangements from the set of array arrangements for a template region. | 11-28-2013 |
| 20130326438 | LAYOUT MODIFICATION METHOD AND SYSTEM - A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer identifies a proper subset of a plurality of first devices in the IC layout, such that replacement of the proper subset of the first devices by second devices in a revised IC layout satisfies a second specification value different from the first specification value. At least one layout mask is generated and stored in at least one non-transitory machine readable storage medium, accessible by a tool for forming at least one additional photomask, such that the set of photomasks and the at least one additional photomask are usable to fabricate an IC according to the revised IC layout. | 12-05-2013 |
| 20130326439 | IMAGE PROCESSING DEVICE AND COMPUTER PROGRAM FOR PERFORMING IMAGE PROCESSING - It is an object of the present invention to provide an image processing device for allowing an actual-image-closer pattern to be formed based on the design data, or its simulation image. In order to accomplish the above-described object, the proposal is made concerning an image processing device which includes an image processing unit which sets the operation condition of a charged-particle beam device on the basis of the design data on a semiconductor element. Here, the image processing device accesses a library for storing device-condition information on the charged-particle beam device, pattern types, and a plurality of combinations of pattern information on each pattern-region basis. Moreover, the image processing device forms a composite image of each pattern region, using the pattern information on each pattern-region basis, and based on the device-condition information and the selection of a pattern type from the pattern types. | 12-05-2013 |
| 20130332893 | FILLER CELLS FOR DESIGN OPTIMIZATION IN A PLACE-AND-ROUTE SYSTEM - A system and method are provided for laying out an integrated circuit design into a plurality of circuit layout cells having gaps therebetween, and inserting into each given one of at least a subset of the gaps, a corresponding filler cell selected from a predefined database in dependence upon a desired effect on a performance parameter of at least one circuit cell adjacent to the given gap. The circuit layout cells may be arranged in rows, and in some embodiments the selection of an appropriate filler cell for a given gap depends upon effects desired on a performance parameter of both circuit cells adjacent to the given gap. The predefined filler cells can include, for example, dummy diffusion regions, dummy poly lines, N-well boundary shifts and etch stop layer boundary shifts. In an embodiment, circuit layout cells can be moved in order to accommodate a selected filler cell. | 12-12-2013 |
| 20130339911 | STITCH AND TRIM METHODS FOR DOUBLE PATTERNING COMPLIANT STANDARD CELL DESIGN - A method for creating double patterning compliant integrated circuit layouts is disclosed. The method allows patterns to be assigned to different masks and stitched together during lithography. The method also allows portions of the pattern to be removed after the process. | 12-19-2013 |
| 20140007026 | LAYOUT METHOD AND SYSTEM FOR MULTI-PATTERNING INTEGRATED CIRCUITS | 01-02-2014 |
| 20140013288 | METHOD AND DEVICE FOR INCREASING FIN DEVICE DENSITY FOR UNALIGNED FINS - A method of generating a layout for a device includes receiving a first layout including a plurality of active regions, each active region of the plurality of active regions having sides. The method further includes defining a plurality of elongate mandrels that each extend in a first direction and are spaced apart from one another in a second direction perpendicular to the first direction. The method further includes for each adjacent pair of partially-parallel active regions of the plurality of active regions having a minimum distance less than a specified minimum spacing, connecting at least a portion of nearest ends of pairs of elongate mandrels, each mandrel of a pair from a different active region. The method further includes generating a second layout including a plurality of elongate mandrels in the plurality of active regions, and connective elements between active regions of at least one adjacent pair of active regions. | 01-09-2014 |
| 20140033146 | SYSTEM FOR DESIGNING SUBSTRATES HAVING REFERENCE PLANE VOIDS WITH STRIP SEGMENTS - Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor. | 01-30-2014 |
| 20140040839 | METHOD AND SYSTEM FOR DERIVED LAYER CHECKING FOR SEMICONDUCTOR DEVICE DESIGN - A system and method are provided for enabling a systematic detection of issues arising during the course of mask generation for a semiconductor device. IC mask layer descriptions are analyzed and information is generated that identifies devices formed by active layers in the masks, along with a description of all layers in proximity to the found devices. The IC mask information is compared to a netlist file generated from the initial as-designed schematic. Determinations can then made, for example, as to whether all intended devices are present, any conflicting layers are in proximity to or interacting with the intended devices, and any unintended devices are present in the mask layers. Steps can then be taken to resolve the issues presented by the problematic devices. | 02-06-2014 |
| 20140047398 | MASKS FOR DOUBLE PATTERNING PHOTOLITHOGRAPHY - Improved masks for double patterning lithography are described. In one example, conflict spaces between features of a target design are identified. The conflict spaces are represented as nodes of a graph. Connections are inserted between nodes based on a local search. The connections are cut to determine double patterning mask assignment. The connections are extended to form a checkerboard that is then overlayed on the target mask design to split the features of the target mask design for double patterning. | 02-13-2014 |
| 20140059503 | METHOD FOR PREPARING A PATTERN TO BE PRINTED ON A PLATE OR MASK BY ELECTRON BEAM LITHOGRAPHY, CORRESPONDING PRINTED CIRCUIT DESIGN SYSTEM AND COMPUTER PROGRAM - A method for preparing a pattern to be printed on a plate or mask by electron beam lithography comprising the following steps: modelling of the pattern by breaking down this pattern into a set of elementary geometric shapes intended to be printed individually in order to reproduce said pattern and, for each elementary geometric shape of the model; determination of an electrical charge dose to be applied to the electron beam during the individual printing of the elementary shape, this dose being chosen from a discrete set of doses including several non-zero predetermined doses recorded in memory. The set of elementary geometric shapes is a bidimensional paving of identical elementary geometric shapes covering the pattern to be printed. In addition, when the doses to be applied to the elementary geometric shapes are determined, a discretisation error correction is made by dithering. | 02-27-2014 |
| 20140059504 | METHOD AND SYSTEM FOR REPLACING A PATTERN IN A LAYOUT - A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output. | 02-27-2014 |
| 20140068531 | PRE-COLORED METHODOLOGY OF MULTIPLE PATTERNING - Some embodiments relate to a method for pre-coloring data within an integrated chip layout to avoid overlay errors that result from mask misalignment during multiple patterning lithography. The method may be performed by generating a graphical IC layout file containing an integrated chip layout having a plurality of IC shapes. The IC shapes within the graphical IC layout file are assigned a color during decomposition. The IC shapes are further pre-colored in a manner that deliberately assigns the pre-colored data to a same mask. During mask building data associated with IC shapes that have been pre-colored is automatically sent to a same mask, regardless of the colors that are assigned to the shapes. Therefore, the pre-colored shapes are not assigned to a masked based upon a decomposition, but rather based upon the pre-coloring. By assigning IC shapes to a same mask through pre-coloring, overlay errors can be reduced. | 03-06-2014 |
| 20140082572 | METHOD OF GENERATING ASSISTANT FEATURE - A method of generating an assistant feature is provided. A plurality of main features is provided. A first main feature is selected from the main features. A plurality of rule-based features is disposed around the first main feature. A model-based feature is generated around the first main feature. An overlap Boolean feature is extracted from the rule-based features, wherein the overlap Boolean feature overlaps with the model-based feature in an overlap ratio up to a target value. The overlap Boolean feature serves as an assistant feature, and the assistant feature and the first main feature constitute a transfer feature. | 03-20-2014 |
| 20140109027 | ESD/ANTENNA DIODES FOR THROUGH-SILICON VIAS - Roughly described, an antenna diode is formed at least partially within the exclusion zone around a TSV, and is connected to the TSV by way of a metal 1 layer conductor at the same time that the TSV is connected to either the gate poly or a diffusion region of one or more transistors placed outside the exclusion zone. | 04-17-2014 |
| 20140115546 | Layout Design for Electron-Beam High Volume Manufacturing - The present disclosure relates to a method and apparatus to create a physical layout for electron-beam lithography, comprising defining a layout grid for a physical design, the layout grid further comprising vertical grid lines which coincide with stitching lines resulting from partitioning the physical design into a plurality of subfields. The physical design is assembled in accordance with design restrictions regarding interaction between design shapes and the layout grid. In some embodiments, the design restrictions are realized though layout restrictions. In some embodiments, the design restrictions are realized by shifting standard cells to minimize design shape interaction with the layout grid in a post-layout step. In some embodiments, the design restrictions are realized by exchanging positions between a plurality of standard cells for an exchange permutation which minimizes the number of interactions in a post-layout step. In some embodiments a routing grid is refined to rule out interactions between a subset of design constructs and the layout grid. Remaining design shape placement is then optimized along the routing grid relative to the stitching lines. | 04-24-2014 |
| 20140137055 | METHOD AND APPARATUS FOR MERGING MULTIPLE GEOMETRICAL PIXEL IMAGES AND GENERATING A SINGLE MODULATOR PIXEL IMAGE - The present invention relates to customizing individual workpieces, such as chip, flat panels or other electronic devices produced on substrates, by direct writing a custom pattern. Customization can be per device, per substrate, per batch or at some other small volume that makes it impractical to use a custom mask or mask set. In particular, it relates to customizing a latent image formed in a patterning sensitive layer over a substrate, merging standard and custom pattern data to form a custom pattern used to produce the customized latent image. A wide variety of substrates can benefit from the technology disclosed. | 05-15-2014 |
| 20140173534 | RESOLUTION ENHANCING TECHNOLOGY USING PHASE ASSIGNMENT BRIDGES - In one embodiment, a spacing is determined for each edge of a number of features in a photolithographic design. The edges have at least a partially predictable layout. Based on the spacing and the predictable layout, a bridge structure is generated. Each bridge of the bridge structure connects one of the edges to an edge of a neighboring feature. Then, the features and the bridge structure are provided for a phase assignment. The phase assignment assigns features at opposite ends of each bridge in the bridge structure to opposite phases. In another embodiment, a sub-resolution assist feature (SRAF) is introduced for an edge of a feature and a bridge is generated from the feature to the SRAF. Then, the feature and the SRAF are assigned to opposite phases based on the relationship defined by the bridge. | 06-19-2014 |
| 20140181763 | Methods Of Forming A Mask And Methods Of Correcting Intra-Field Variation Across A Mask Design Used In Photolithographic Processing - A method of forming a mask includes creating a difference map between a desired intra-field pattern that is to be formed on substrates and an intra-field signature pattern. The intra-field signature pattern represents a pattern formed on an example substrate by an exposure field using an example E-beam-written mask. Modifications are determined to formation of mask features to be made using an E-beam mask writer if forming a modified E-beam-written mask having mask features modified from that of the example E-beam-written mask that will improve substrate feature variation identified in the difference map. The E-beam mask writer is programmed using the determined modifications to improve the substrate feature variation identified in the difference map. It is used to form the modified E-beam-written mask having the modified mask features. One or more substrates are photolithographically processed using the modified E-beam-written mask. | 06-26-2014 |
| 20140189615 | SIGNAL PATH AND METHOD OF MANUFACTURING A MULTIPLE-PATTERNED SEMICONDUCTOR DEVICE - A multiple-patterned semiconductor device and a method of manufacture are provided. The semiconductor device includes one or more layers with signal tracks. The signal tracks have a quality characteristic. The semiconductor device also includes repeater banks to repower signals. The method of manufacture includes defining portions of layers with photomasks having signal track patterns, determining a quality characteristic of the signal track patterns, and selecting a photomask for etching vias. | 07-03-2014 |
| 20140189616 | INCREMENTAL CONCURRENT PROCESSING FOR EFFICIENT COMPUTATION OF HIGH-VOLUME LAYOUT DATA - Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, different data processing stages can partition the layout data differently, and portions of the layout data that are not required by a data processing stage can be either passed-through or passed-around the data processing stage. | 07-03-2014 |
| 20140195994 | DEFECTIVE ARTIFACT REMOVAL IN PHOTOLITHOGRAPHY MASKS CORRECTED FOR OPTICAL PROXIMITY - Defective artifact removal is described in photolithography masks corrected for optical proximity. In one example a method is described in which partitions are identified in a mask design for independent optimization. The partitions are grouped and ordering into stages. The first stage is processed. Geometries are extracted from the periphery of the first stage partitions. The extracted geometries are added to the peripheries of second stage partitions. Then the second stage partitions are processed. | 07-10-2014 |
| 20140201692 | PRE-COLORED METHODOLOGY OF MULTIPLE PATTERNING - Some embodiments relate to a system that pre-colors word lines and control lines within a memory cell to avoid timing delays that result from processing variations introduced through multiple patterning lithography processes. The system has a memory element that stores a graphical IC layout with a memory circuit having layout features including a plurality of word lines and a plurality of Y-control lines. A pre-coloring element pre-colors one or more of the plurality of word lines and Y-control lines, to indicate that pre-colored word lines and Y-control lines are to be formed on a same mask of a multiple mask set used for a multiple patterning lithography process. A decomposition element assigns different colors to uncolored layout features of the memory circuit, to indicate that different colored memory features are to be formed on different masks of the multiple mask set. | 07-17-2014 |
| 20140223396 | PATTERN-BASED REPLACEMENT FOR LAYOUT REGULARIZATION - Methods and systems for generating a regularized integrated circuit layout are disclosed. Pattern replacement of various portions of wiring within an integrated circuit layout with a common pattern is performed in order to generate a regularized layout. The regularized layout is then subjected to additional mask data preparation processing, such as optical proximity correction. | 08-07-2014 |
| 20140237436 | Layout Decomposition For Triple Patterning Lithography - Aspects of the invention relate to techniques of layout decomposition for triple patterning lithography. Data of a coloring graph are derived from layout data for a layout design. The coloring graph is simplified through graph reduction and graph partitioning processes. The graph partitioning process comprises separating biconnected components. The graph partitioning process may further comprise separating subgraphs connected by one or two edges. Based on the simplified coloring graph, the layout design is decomposed to generate decomposition information. The decomposition process may comprise applying a heuristic method for coloring if needed. The decomposition information may comprise information of one or more layout regions that cannot be decomposed. | 08-21-2014 |
| 20140245241 | GENERATION METHOD, STORAGE MEDIUM AND INFORMATION PROCESSING APPARATUS - The present invention provides a generation method of generating data of patterns of a plurality of masks used in an exposure apparatus for exposing a substrate, including a step of specifying, from a plurality of points on a grid having pattern elements to be formed on the substrate as intersections, an allowable point that allows a pattern to be transferred other than points of target pattern elements constituting a target pattern to be formed on the substrate, and a step of, for a pattern element group including a target pattern element whose distance to an adjacent target pattern element is shorter than a resolution limit of the exposure apparatus, grouping the adjacent target pattern elements on the grid a space between which is filled with the allowable point. | 08-28-2014 |
| 20140258946 | MASK SET FOR DOUBLE EXPOSURE PROCESS AND METHOD OF USING THE MASK SET - A mask set for double exposure process and method of using said mask set. The mask set is provided with a first mask pattern having a first base and a plurality of first teeth and protruding portions, and a second mask pattern having a second base and a plurality of second teeth, wherein the second base may at least partially overlap the first base such that each of the protruding portions at least partially overlaps one of the second teeth. | 09-11-2014 |
| 20140282304 | METHOD AND SYSTEM FOR FORMING A DIAGONAL PATTERN USING CHARGED PARTICLE BEAM LITHOGRAPHY - A method and system for fracturing or mask data preparation is disclosed in which the central core portion of a diagonal pattern is fractured using overlapping variable shaped beam (VSB) shots, and an outer portion of the diagonal pattern is fractured using non-overlapping VSB shots. A transition region is interposed between the central core and outer pattern portions, and transition region shots are generated so as to produce in the transferred pattern a smooth transition in pattern characteristics such as line edge roughness or period of waviness, from the central core portion of the pattern to the outer portion of the pattern. A pattern determined by the transition region shots is then compared to a reticle pattern created using conventional non-overlapping VSB shots. Methods for forming a semiconductor device layout pattern on a reticle or substrate are also disclosed. | 09-18-2014 |
| 20140282305 | COMMON TEMPLATE FOR ELECTRONIC ARTICLE - One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor. | 09-18-2014 |
| 20140282306 | Layout Optimization for Integrated Design - A method for laying out a target pattern includes assigning a keep-out zone to an end of a first feature within a target pattern, and positioning other features such that ends of the other features of the target pattern do not have an end within the keep-out zone. The target pattern is to be formed with a corresponding main feature and cut pattern. | 09-18-2014 |
| 20140304667 | MEMS Modeling System and Method - A system and method for modeling microelectromechanical devices is disclosed. An embodiment includes separating the microelectromechanical design into separate regions and modeling the separate regions separately. Parametric parameters or parametric equations may be utilized in the separate models. The separate models may be integrated into a MEMS device model. The MEMS device model may be tested and calibrated, and then may be used to model new designs for microelectromechanical devices. | 10-09-2014 |
| 20140331193 | METHOD AND DEVICE FOR INCREASING FIN DEVICE DENSITY FOR UNALIGNED FINS - A semiconductor manufacturing method of generating a layout for a device includes defining a first plurality of mandrels in a first active region of a first layout. Each mandrel of the first plurality of mandrels extends in a first direction and being spaced apart in a second direction perpendicular to the first direction. The method further includes defining a second plurality of mandrels in a second active region of the first layout. Each mandrel of the second plurality of mandrels extends in the first direction and being spaced apart in the second direction. An edge of the first active region is spaced from an edge of the second active region by a minimum distance less than a specified minimum spacing. The method further includes connecting, using a layout generator, at least one mandrel of the first plurality of mandrels to a corresponding mandrel of the second plurality of mandrels. | 11-06-2014 |
| 20140337809 | METHOD FOR FORMING SEMICONDUCTOR LAYOUT PATTERNS, SEMICONDUCTOR LAYOUT PATTERNS, AND SEMICONDUCTOR STRUCTURE - A method for forming semiconductor layout patterns providing a pair of first layout patterns being symmetrical along an axial line, each of the first layout patterns comprising a first side proximal to the axial line and a second side far from the axial line; shifting a portion of the first layout patterns toward a direction opposite to the axial line to form at least a first shifted portion in each first layout pattern, and outputting the first layout patterns and the first shifted portions on a first mask. | 11-13-2014 |
| 20140359544 | LAYOUT RE-DECOMPOSITION FOR MULTIPLE PATTERNING LAYOUTS - Among other things, one or more techniques and systems for layout re-decomposition of a new layout corresponding to a change order to an original layout associated with an integrated circuit are provided. The change order is applied to the original layout to create the new layout. The original layout comprises one or more original pattern portions assigned pattern colors that correspond to pattern masks. One or more new pattern portions within the new layout are assigned pattern colors such that the new layout has a relatively high color similarity with respect to the original layout. In this way, changes to the pattern masks are reduced, thus mitigating fabrication delay or costs that would otherwise result from significant changes to the pattern masks. | 12-04-2014 |
| 20140365985 | MASK PATTERN GENERATING METHOD, RECORDING MEDIUM, AND INFORMATION PROCESSING APPARATUS - A method for generating a pattern of a mask used for an exposure apparatus through a calculation by a processor includes applying, to a target main pattern, a reference map of a characteristic value of an image of a representative main pattern with respect to a position of a representative auxiliary pattern calculated for each of a plurality of positions while the position of the representative auxiliary pattern with respect to the representative main pattern is changed and calculating a map of the characteristic value of the image of the target main pattern with respect to a position of an auxiliary pattern, and determining the position of the auxiliary pattern by using data of the map of the characteristic value of the image of the target main pattern and generating a pattern of a mask including the target main pattern and the determined auxiliary pattern. | 12-11-2014 |
| 20140380256 | DOUBLE PATTERNING LAYOUT DESIGN METHOD - A double patterning layout design method comprises defining critical paths comprising a first path and a second path on a schematic circuit, and defining a double patterning layout divided into a first mask layout having a first color and a second mask layout having a second color, the double patterning layout corresponding to the schematic circuit. The defining of the double patterning layout comprises anchoring the critical paths on the schematic circuit. | 12-25-2014 |
| 20150012896 | METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING GENERATING PHOTOMASKS FOR DIRECTED SELF-ASSEMBLY - Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern on a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the photomask includes, using a computing system, inputting a DSA target pattern. Using the computing system, a DSA model, an OPC model, and a MPC model, cooperatively running a DSA PC algorithm, an OPC algorithm, and a MPC algorithm to produce an output MPCed pattern for a mask writer to write on the photomask. | 01-08-2015 |
| 20150012897 | METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING GENERATING PHOTOMASKS FOR DIRECTED SELF-ASSEMBLY - Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern on a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the photomask includes using a computing system, inputting a DSA target pattern and an initial pattern. An output mask writer pattern is produced from the initial pattern using the computing system, the DSA target pattern, a DSA model, an OPC model, and a MPC model. The output mask writer pattern is for a mask writer to write on the photomask. | 01-08-2015 |
| 20150040082 | LAYOUT DECOMPOSITION METHOD - A method of assigning layout patterns includes identifying a first set of layout patterns of a current layout design that is new or has been modified in comparison with a reference layout design. A second set of layout patterns of the current layout design is identified. A member of the second set of layout patterns that is not a member of the first set of layout patterns has a distance, less than a predetermined threshold distance, to at least another member of the second set of layout patterns. A third set of layout patterns is not modified in comparison with the reference layout design. The third set of layout patterns is assigned to a plurality of masks according to the reference pattern-assigning result. | 02-05-2015 |
| 20150040083 | SYSTEM AND METHOD FOR DECOMPOSITION OF A SINGLE PHOTORESIST MASK PATTERN INTO 3 PHOTORESIST MASK PATTERNS - A system and method of decomposing a single photoresist mask pattern to three photoresist mask patterns. The system and method assign nodes to polygon features on the single photoresist mask pattern, designate nodes as being adjacent nodes for those nodes that are less than a predetermined distance apart, iteratively remove nodes having 2 or less adjacent nodes until no nodes having 2 or less adjacent nodes remain, identify one or more internal nodes, map photoresist mask pattern designations (colors) to the internal nodes, and replace and map a color to each of the nodes removed by the temporarily removing nodes, such that each node does not have an adjacent node of the same color. | 02-05-2015 |
| 20150040084 | STRUCTURE, METHOD AND SYSTEM FOR COMPLEMENTARY STRAIN FILL FOR INTEGRATED CIRCUIT CHIPS - A structure, method and system for complementary strain fill for integrated circuit chips. The structure includes a first region of an integrated circuit having multiplicity of n-channel and p-channel field effect transistors (FETs); a first stressed layer over n-channel field effect transistors (NFETs) of the first region, the first stressed layer of a first stress type; a second stressed layer over p-channel field effect transistors (PFETs) of the first region, the second stressed layer of a second stress type, the second stress type opposite from the first stress type; and a second region of the integrated circuit, the second region not containing FETs, the second region containing first sub-regions of the first stressed layer and second sub-regions of the second stressed layer. | 02-05-2015 |
| 20150046888 | MASK DESIGN AND DECOMPOSITION FOR SIDEWALL IMAGE TRANSFER - A design level compatible with a sidewall image transfer process employs an alternating grid of mandrel-type line tracks and non-mandrel-type line tracks. Target structure design shapes are formed such that all vertices of the target structure design shapes are on the grid. The target structure design shapes are classified as mandrel-type design shapes and non-mandrel-type design shapes depending on the track type of the overlapping line tracks for lengthwise portions. All mandrel-type line tracks and straps of the mandrel-type design shapes less lateral strap regions of the non-mandrel-type design shapes collectively form mandrel design shapes, which can be employed to generate a first lithographic mask. Sidewall design shapes are generated from the mandrel design shapes. Blocking shapes for a second lithographic mask can be generated by selecting all areas that are not included in the target structure design shapes or the sidewall design shapes. | 02-12-2015 |
| 20150058817 | Semiconductor Overlay Production System and Method - Disclosed herein is a system and method for producing semiconductor devices using overlays, the method comprising associating one or more patterned overlays with respective ones of reserved regions in a layer template, receiving a layer design based on the layer template, identifying the reserved regions in the layer design, generating a production layer design based on the layer design, the production layer design describing at least one production overlay in one of the reserved regions, and fabricating one or more devices based on the production layer design. | 02-26-2015 |
| 20150095859 | PHOTOLITHOGRAPHY MASK SYNTHESIS FOR SPACER PATTERNING - Photolithography mask synthesis is disclosed for spacer patterning masks. In one example, backbone features are extracted from a target layout of a mask design. A connectivity graph is generated based on the target layout in which lines of the backbone features are represented as nodes on the connectivity graph. The nodes are connected based on spacer patterning process limitations and the connections are assigned to sets. A backbone mask layout is then generated based on one of the sets of nodes. | 04-02-2015 |
| 20150100927 | Chip Level Critical Point Analysis with Manufacturer Specific Data - A method and computer program are provided for analyzing a set of layers within an integrated circuit design to determine a set of critical points for each layer within the set of layers. The critical points are based at least in part on manufacturer specific process parameters. The method includes assigning a critical point value to each of the critical points within each set of critical points, analyzing a path through the integrated circuit design across multiple integrated circuit design layers, and determining a sum of critical point values of each critical point along the path. | 04-09-2015 |
| 20150121318 | AUTOMATED GENERATION OF MASK FILE FROM THREE DIMENSIONAL MODEL FOR USE IN GRAYSCALE LITHOGRAPHY - A method, apparatus and program product automatically generate a grayscale lithography mask file ( | 04-30-2015 |
| 20150128099 | MASK AND METHOD OF FORMING PATTERN BY USING THE SAME - A method of forming a pattern is disclosed. At first, a layout pattern is provided to a computer system. The layout pattern includes at least a first strip pattern and at least a second strip pattern, and a width of the second strip pattern is substantially larger than a width of the first strip pattern. Subsequently, the second strip pattern neighboring the first strip pattern is defined as a selected pattern. Then, an assist pattern is formed in the selected pattern, and the assist pattern does not overlap a center line of the selected pattern. The layout pattern and the assist pattern are further outputted through the computer system onto a mask. | 05-07-2015 |
| 20150143306 | METHODS FOR FABRICATING HIGH-DENSITY INTEGRATED CIRCUIT DEVICES - An integrated circuit device having a plurality of lines is described in which the widths of the lines, and the spacing between adjacent lines, vary within a small range which is independent of variations due to photolithographic processes, or other patterning processes, involved in manufacturing the device. A sequential sidewall spacer formation process is described for forming an etch mask for the lines, which results in first and second sets of sidewall spacers arranged in an alternating fashion. As a result of this sequential sidewall spacer process, the variation in the widths of the lines across the plurality of lines, and the spacing between adjacent lines, depends on the variations in the dimensions of the sidewall spacers. These variations are independent of, and can be controlled over a distribution much less than, the variation in the size of the intermediate mask element caused by the patterning process. | 05-21-2015 |
| 20150149971 | OPTIMIZING LITHOGRAPHY MASKS FOR VLSI CHIP DESIGN - In one embodiment, a computer-implemented method includes accessing mask input data. The mask input data includes a mathematical representation of a mask in a mask representation space, where the mask is configured to create an integrated circuit microprocessor. A set of values is obtained based on a derivative of the mask input data. The set of values is optimized, by a computer processor, in a derivative domain to obtain optimized mask data. The optimized mask data is transformed into the mask representation space to obtain printable mask output data. | 05-28-2015 |
| 20150302127 | Semiconductor Overlay Production System and Method - Disclosed herein is a system and method for producing semiconductor devices using overlays, the method comprising associating one or more patterned overlays with respective ones of reserved regions in a layer template, receiving a layer design based on the layer template, identifying the reserved regions in the layer design, generating a production layer design based on the layer design, the production layer design describing at least one production overlay in one of the reserved regions, and fabricating one or more devices based on the production layer design. | 10-22-2015 |
| 20150302129 | MASK ASSIGNMENT TECHNIQUE FOR M1 METAL LAYER IN TRIPLE-PATTERNING LITHOGRAPHY - In an embodiment, a method in the manufacture of triple-patterning lithography masks, each mask represented by one of three colors, where each cell layout has exactly one polygonal pattern at one-half the different-color spacing from its left boundary, and exactly one polygonal pattern at one-half the different-color spacing from its right boundary. During placement of the cell layouts into a row, the method includes switching assigned colors in a cell layout to ensure that no two polygonal patterns of the same color in the layout are at a distance from each other less than the same-color spacing. | 10-22-2015 |
| 20150339423 | RETICLE MARK ARRANGEMENT METHOD AND NONTRANSITORY COMPUTER READABLE MEDIUM STORING A RETICLE MARK ARRANGEMENT PROGRAM - Reticle marks are arranged at a plurality of places in a kerf region of a reticle, the area of a polygon with apexes at arrangement positions of the reticle marks is calculated, and the arrangement positions of the reticle marks are decided based on results of calculation of the area of the polygon. | 11-26-2015 |
| 20150356223 | Techniques for Generating Nanowire Pad Data from Pre-Existing Design Data - In one aspect, a CAD-based method for designing a lithographic mask for nanowire-based devices is provided which includes the steps of: create a design for the mask from existing (e.g., FINFET or planar CMOS) design data which includes, for each of the devices, one or more nanowire mask shapes (FINFET design data) or continuous shapes (planar CMOS design data); for FINFET design data, merging the nanowire mask shapes into continuous shapes; expanding the continuous shapes to join all of the continuous shapes in the design together forming a single polygon shape; removing the continuous shapes from the single polygon shape resulting in landing pad shapes for anchoring the nanowire mask shapes; for CMOS design data, dividing the continuous active shapes into one or more nanowire mask shapes; and merging the landing pad shapes with the nanowire mask shapes to form the lithographic mask. | 12-10-2015 |
| 20150356225 | MASKS FORMED BASED ON INTEGRATED CIRCUIT LAYOUT DESIGN HAVING CELL THAT INCLUDES EXTENDED ACTIVE REGION - A set of masks corresponds to an integrated circuit layout. The integrated circuit layout includes a first cell having a first transistor region and a second transistor region, and a second cell having a third transistor region and a fourth transistor region. The first cell and the second cell adjoin each other at side cell boundaries thereof, the first transistor region and the third transistor region are formed in a first continuous active region, and the second transistor region and the fourth transistor region are formed in a second continuous active region. The set of masks is formed based on the integrated circuit layout. | 12-10-2015 |
| 20150370945 | INTEGRATED CIRCUIT DESIGN SYSTEM WITH BALANCED COLOR ASSIGNMENT - A method comprises grouping sub-components based on an association between the sub-components and connections coupled to the sub-components. The method also comprises determining a total ratio area per group based on normalized ratio units of the sub-components. The method further comprises identifying a priority group based on a ranking of the groups, the ranking being based on the total area per group. The method also comprises assigning, by a priority assignment process, a first color scheme or a second color scheme to the sub-components included in the priority group. The method further comprises assigning, by an other assignment process, the first color scheme or the second color scheme to the remainder of the sub-components. At least the other assignment process is based on a balancing of a first total area of sub-components having the first color scheme with a second total area of sub-components having the second color scheme. | 12-24-2015 |
| 20160019331 | CHIP CROSS-SECTION IDENTIFICATION AND RENDERING ANALYSIS - A defective integrated circuit (IC) is analyzed to identify a portion of the integrated circuit possibly containing an electrical defect. A computer is used to process the design information of the integrated circuit and to navigate to the physical portion of the integrated circuit where the potential electrical defect might be found. The design information includes information on the layout and the technology used to fabricate the integrated circuit. A three-dimensional view of the portion of the design of the integrated circuit where the electrical defect might be found is rendered, based on the design information for the integrated circuit. | 01-21-2016 |
| 20160026743 | METHOD FOR GENERATING PATTERN, STORAGE MEDIUM, AND INFORMATION PROCESSING APPARATUS - A method for generating a pattern includes defining a footprint of a main pattern in each cell, arranging a first cell and a second cell which has an auxiliary pattern outside the footprint of the main pattern, side by side in such a manner that the auxiliary pattern outside the footprint of the second cell is present in the footprint of the main pattern of the first cell, and generating the pattern of the mask by removing a pattern element of the auxiliary pattern outside the footprint of the second cell in a portion where the pattern element of the auxiliary pattern outside the footprint of the second cell is close to or overlaps with the main pattern in the first cell of the first cell and the second cell arranged side by side. | 01-28-2016 |
| 20160042108 | METHOD OF GENERATING MODIFIED LAYOUT FOR RC EXTRACTION - A method of includes determining a first set of width bias values of an i-th set of layout patterns of an original layout according a first type width variation. The original layout has N sets of layout patterns corresponding to N masks, where the i-th set of layout patterns has an i-th mask assignment corresponding to an i-th mask of the N masks. The order index i is an integer from 1 to N, and N is an integer and greater than 1. A second set of width bias values of the i-th set of layout patterns of the original layout is determined according to a second type width variation. The modified layout is generated based on the first and second sets of width bias values of the i-th set of layout patterns. | 02-11-2016 |
| 20160078164 | METHOD OF FORMING LAYOUT DESIGN - A method of forming a layout design for fabricating an integrated circuit (IC) is disclosed. The method includes identifying one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design; and generating a set of layout patterns overlapping the identified one or more areas. The plurality of gate structure layout patterns has a predetermined pitch smaller than a spatial resolution of a predetermined lithographic technology. A first layout pattern of the set of layout patterns has a width less than twice the predetermined pitch. | 03-17-2016 |
| 20160085896 | METHOD FOR DESIGNING TOPOGRAPHIC PATTERNS FOR DIRECTING THE FORMATION OF SELF-ASSEMBLED DOMAINS AT SPECIFIED LOCATIONS ON SUBSTRATES - Methods and computer program products for designing topographic patterns for directing the formation of self-assembled domains at specified locations on substrates. The methods include generating mathematical models that operate on mathematical descriptions of the number and locations of cylindrical self-assembled domains in a mathematical description of a guiding pattern. | 03-24-2016 |
| 20160098509 | INTEGRATED CIRCUIT AND METHOD OF DESIGNING LAYOUT OF INTEGRATED CIRCUIT - A method of designing a layout of an integrated circuit (IC) includes placing a first cell in the layout, placing a second cell in the layout adjacent to the first cell at a first boundary between the first and second cells, and generating a plurality of commands executable by a processor to form a semiconductor device based on the layout. The first cell includes a first pattern and a second pattern. The first and second patterns are adjacent to the first boundary, the first and second patterns have different colors, and a first boundary space between the first pattern and the first boundary is different from a second boundary space between the second pattern and the first boundary. | 04-07-2016 |
| 20160098510 | Integrated Circuit Design Using Pre-Marked Circuit Element Object Library - This disclosure describes an approach to create a library of pre-marked circuit element objects and use the pre-marked circuit element object library to design and fabricate an integrated circuit. Each of the circuit element objects are “pre-marked” and include embedded voltage markers having independent pre-assigned voltage values for each terminal in the circuit element object. When a circuit designer inserts a pre-marked circuit element object in a schematic design, the design tool determines whether each of the circuit element object terminal's pre-assigned voltage values match their corresponding nets to which they are connected. When the circuit designer completes the schematic design that includes valid nets throughout the schematic design, the design tool generates a layout design from the schematic design. The design tool, in turn, generates mask layer data from the layout design when the layout design passes verification testing. | 04-07-2016 |
| 20160098513 | CONFLICT DETECTION FOR SELF-ALIGNED MULTIPLE PATTERNING COMPLIANCE - Among other things, one or more techniques and systems for performing design layout are provided. An initial design layout is associated with an electrical component, such as a standard cell. A conflict graph is generated based upon the initial design layout. The conflict graph comprises one or more nodes, representing polygons within the initial design layout, connected by one or more edges. A same-process edge specifies that two nodes are to be generated by the same pattern process, while a different-process edge specified that two nodes are to be generated by different pattern processes, such as a mandrel pattern process and a passive fill pattern process. The conflict graph is evaluated to identify a conflict, such as a self-aligned multiple pattering (SAMP) conflict, associated with the initial design layout. The conflict is visually displayed so that the initial design layout can be modified to resolve the conflict. | 04-07-2016 |
| 20160132626 | METHOD OF DECOMPOSING LAYOUT DESIGN FOR PREPARING PHOTOMASK SET PRINTED ONTO WAFER BY PHOTOLITHOGRAPHY, METHOD OF FORMING PHOTOMASK SET AND METHOD OF FABRICATING INTEGRATED CIRCUIT - A method of decomposing layout design for preparing a photomask set printed onto a wafer by photolithography includes the following steps. An integrated circuit layout design including several features is obtained. The overlay relation of these features is recognized to classify these features into a first group and a second group. These features printed onto different layers of the wafer are distinguished to decompose the first group into a first feature and a third feature, and the second group into a second feature and a fourth feature. The first feature is outputted to a first photomask, the second feature is outputted to a second photomask, a third feature is outputted to a third photomask and a fourth feature is outputted to a fourth photomask. A method of forming a photomask set and a method of fabricating an integrated circuit are also provided. | 05-12-2016 |
| 20160132629 | SEMICONDUCTOR DEVICE DESIGNING METHOD, DESIGNING APPARATUS, AND COMPUTER-READABLE STORAGE MEDIUM - A method designs a semiconductor device that includes first and second wirings provided in an uppermost of wiring layers, and a setting part coupled to the first and second wirings and including third and fourth wirings provided in each of the wiring layers, and vias that electrically connect wirings of different wiring layers, wherein each of the third and fourth wirings in each of the wiring layers extends in one of 2 mutually perpendicular directions, and the third and fourth wirings in the wiring layers are arranged and connected so as to turn around using the vias as turn-around points. The method modifies a direction in which the third and fourth wirings extend in one wiring layer specified by layer information, and modifying a connection of the first and second wirings with respect to the third and fourth wirings in a lowermost of the wiring layers. | 05-12-2016 |
| 20160140267 | PROCESS BASED METROLOGY TARGET DESIGN - Methods and systems for automatically generating robust metrology targets which can accommodate a variety of lithography processes and process perturbations. Individual steps of an overall lithography process are modeled into a single process sequence to simulate the physical substrate processing. That process sequence drives the creation of a three-dimensional device geometry as a whole, rather than “building” the device geometry element-by-element. | 05-19-2016 |
| 20160147929 | METHOD OF RESOLVING MULTI-PATTERNED COLOR CONFLICTS FOR MULTI-ROW LOGIC CELLS - According to one general aspect, a method may include dividing circuit cells into colorable sub-portions, wherein each circuit cell includes one or more colorable sub-portions. The method may include determining if a violating colorable sub-portion is to be re-colored. The method may include indicating that the violating colorable sub-portion is to be at least partially re-colored. | 05-26-2016 |
| 20160203252 | MASK CREATION WITH HIERARCHY MANAGEMENT USING COVER CELLS | 07-14-2016 |
| 20160252807 | FREE FORM FRACTURING METHOD FOR ELECTRONIC OR OPTICAL LITHOGRAPHY USING RESIST THRESHOLD CONTROL | 09-01-2016 |
| 20160253447 | METHOD AND APPARATUS FOR FACILITATING MANUFACTURING OF SEMICONDUCTOR DEVICE | 09-01-2016 |
| 20160253449 | THREE DIMENSIONAL (3D) VIRTUAL IMAGE MODELING METHOD FOR OBJECT PRODUCED THROUGH SEMICONDUCTOR MANUFACTURING PROCESS | 09-01-2016 |
| 20170235866 | METHOD WHEREIN TEST CELLS AND DUMMY CELLS ARE INCLUDED INTO A LAYOUT OF AN INTEGRATED CIRCUIT | 08-17-2017 |
| 20170235867 | METAL LINE LAYOUT BASED ON LINE SHIFTING | 08-17-2017 |
