| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 716056000 | Yield | 10 |
| 20100275178 | COMPUTATIONAL EFFICIENCY IN PHOTOLITHOGRAPHIC PROCESS - Photolithographic process simulation is described in which fast computation of resultant intensity for a large number of process variations and/or target depths (var,z | 10-28-2010 |
| 20110145769 | COMPUTATIONAL EFFICIENCY IN PHOTOLITHOGRAPHIC PROCESS SIMULATION - Photolithographic process simulation is described in which fast computation of resultant intensity for a large number of process variations and/or target depths (var,z | 06-16-2011 |
| 20110307846 | METHODS AND SYSTEM FOR ANALYSIS AND MANAGEMENT OF PARAMETRIC YIELD - Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design. | 12-15-2011 |
| 20120227019 | METHODS AND SYSTEM FOR ANALYSIS AND MANAGEMENT OF PARAMETRIC YIELD - Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design. | 09-06-2012 |
| 20130061188 | Hierarchical Wafer Yield Predicting Method and Hierarchical Lifetime Predicting Method - For improving wafer fabrication, yield and lifetime of wafers are predicted by determining coefficients of a yield/lifetime domain, an integral domain, an electric/layout domain, a metrology/defect domain, and a machine sensor domain in a hierarchical manner. With the aid of the hierarchically-determined coefficients, noises in prediction can be reduced so that precision of prediction results of the yields or the lifetimes of wafers can be raised. | 03-07-2013 |
| 20130290915 | COMPUTATIONAL EFFICIENCY IN PHOTOLITHOGRAPHIC PROCESS SIMULATION - Photolithographic process simulation is described in which fast computation of resultant intensity for a large number of process variations and/or target depths (var,z | 10-31-2013 |
| 20130332894 | SYSTEM AND METHOD FOR LITHOGRAPHY SIMULATION - In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. | 12-12-2013 |
| 20140089871 | Hierarchical Wafer Yield Prediction Method and Hierarchical Lifetime Prediction Method - For improving wafer fabrication, yield and lifetime of wafers are predicted by determining coefficients of a yield domain for wafer yield prediction and a lifetime domain for a wafer lifetime prediction, an integral domain, an electric/layout domain, a metrology/defect domain, and a machine sensor domain in a hierarchical manner. With the aid of the hierarchically-determined coefficients, noises in prediction can be reduced so that precision of prediction results of the yields or the lifetimes of wafers can be raised. | 03-27-2014 |
| 20140173535 | ANALYSIS OF CHIP-MEAN VARIATION AND INDEPENDENT INTRA-DIE VARIATION FOR CHIP YIELD DETERMINATION - Systems and methods for determining a chip yield are disclosed. One method includes obtaining a first probability distribution function modeling variations within a chip and a second probability distribution function modeling variations between dies. Further, a discontinuous first level integration is performed with the first probability distribution function and a continuous second level integration is performed by a hardware processor based on the second probability function to determine the chip yield. | 06-19-2014 |
| 20140282307 | METHOD AND APPARATUS FOR PROVIDING METRIC RELATING TWO OR MORE PROCESS PARAMETERS TO YIELD - A process and apparatus are provided for generating and evaluating one or more metrics for analyzing the design and manufacture of semiconductor devices. Embodiments include scanning a drawn semiconductor design layout to determine a difficult-to-manufacture pattern within the drawn semiconductor design layout based on a match with a pre-characterized difficult-to-manufacture pattern determining a corrected pattern based on a pre-determined correlation between the corrected pattern and the pre-characterized difficult-to-manufacture pattern, and replacing the difficult-to-manufacture pattern with the corrected pattern within the drawn semiconductor design layout. | 09-18-2014 |
