| Entries |
| Document | Title | Date |
|---|
| 20100264945 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a sense amplifier for sensing input data and a sense amplifier controller for blocking a signal path between the sense amplifier and a memory cell when a test mode signal is activated. | 10-21-2010 |
| 20100295568 | SELF TESTING FAULT CIRCUIT APPARATUS AND METHOD - A self testing fault circuit interrupter device comprising a fault circuit comprising at least one line monitoring circuit, at least one line interrupting circuit and at least one fault detector circuit which is configured to selectively operate said at least one line interrupting circuit when a fault is detected. This fault circuit also includes at least one test circuit configured to initiate a self test on the fault circuit and at least one timing circuit for controlling the time period for a self test being performed on said at least one self test circuit. The timing circuitry can be in the form of external circuitry which comprises a transistor which controls the discharge rate of a timing capacitor. The timing capacitor is present to prevent any false triggering of a fault circuit. A fault circuit test condition does not stop until the capacitor is fully discharged. By controlling the timing capacitor discharge rate, the triggering of an SCR is not delayed too much in the presence of an external fault because during the presence of this external fault the test cycle is considerably shortened in time based directly upon the size of the external fault. The testing circuit can include a microcontroller which can be programmed to perform a self test across at least two different half cycles of opposite polarity. The determination of the timing of the self test is based upon timing performed by the microcontroller in combination with zero crossing circuitry. | 11-25-2010 |
| 20100308852 | SHIELDED ANTENNA FOR SYSTEM TEST OF A NON-CONTACT VOLTAGE DETECTOR - A system and method of conducting a full system test on a non-contact voltage detector while simultaneously shielding the voltage detector's antenna from stray electric fields is disclosed. When a user runs the self-test, an alternating current generator capacitively couples to the antenna through an antenna shielding to detect any breaks in the antenna. The coupled signal is amplified and filtered by the voltage detector's electronics, and triggers an indicator if the voltage detector is fully operative. | 12-09-2010 |
| 20100321050 | ON-CHIP MEASUREMENT OF SIGNALS - A method, system, and computer usable program product for on-chip measurement of signals in an integrated circuit are provided in the illustrative embodiments. A signal to be measured is identified in the IC. The signal is provided as a first control voltage input to a first VCO in the IC. A first output frequency is generated from the first VCO, the first output frequency having a first frequency value corresponding to the signal. The signal is provided as a second control voltage input to a second VCO in the IC. A second output frequency is generated from the second VCO, the second output frequency having a second frequency value corresponding to the signal. The first and the second output frequency values are exported from the IC. A mean value and a standard deviation of the signal are computed using the output first and second frequency values. | 12-23-2010 |
| 20100321051 | SEMICONDUCTOR INTEGRATED CIRCUIT, DEBUG/TRACE CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT OPERATION OBSERVING METHOD - A main functional structure executes continuous predetermined operations to continuously generate events associated with the operations. A debug/trace circuit compares an event occurring at the main functional structure with detection condition indicating information of one entry in a control information list, and executes the operation designated by operation indicating information paired with the detection condition indicating information in accordance with the result of the comparison. The debug/trace circuit continuously performs this in accordance with the control information list to identify the event. | 12-23-2010 |
| 20100327892 | Parallel Array Architecture for Constant Current Electro-Migration Stress Testing - A parallel array architecture for constant current electro-migration stress testing is provided. The parallel array architecture comprises a device under test (DUT) array having a plurality of DUTs coupled in parallel and a plurality of localized heating elements associated with respective ones of the DUTs in the DUT array. The architecture further comprises DUT selection logic that isolates individual DUTs within the array. Moreover, the architecture comprises current source logic that provides a reference current and controls the current through the DUTs in the DUT array such that each DUT in the DUT array has substantially a same current density, and current source enable logic for selectively enabling portions for the current source logic. Electro-migration stress testing is performed on the DUTs of the DUT array using the heating elements, the DUT selection logic, current source logic, and current source enable logic. | 12-30-2010 |
| 20110001503 | INTEGRATED CIRCUIT HAVING ELECTRICALLY ISOLATABLE TEST CIRCUITRY - Special test circuitry in an IC for wafer level testing selectively connects the specialized test circuitry to the functional circuitry during wafer test. Following wafer test the special test circuitry is electrically isolated from the functional circuitry and power supplies such that it does not load functional circuit signals nor consume power. | 01-06-2011 |
| 20110006792 | METHOD OF ON-CHIP CURRENT MEASUREMENT AND SEMICONDUCTOR IC - A semiconductor integrated circuit is constituted to include a circuit block having a predetermined function, a power switch capable of supplying an operating power to the circuit block, and a current measuring circuit for obtaining a current flowing to the circuit block based on a voltage between terminals of the power switch in a state in which the power switch is turned on and an on-resistance of the power switch. The current flowing to the circuit block is obtained based on the voltage between terminals of the power switch in the state in which the power switch is turned on and the on-resistance of the power switch. Thus, it is possible to measure a current of the circuit block in a state in which a chip is normally operated. | 01-13-2011 |
| 20110057673 | TEST APPARATUS AND TEST METHOD - There is provided a test apparatus for testing a device under test, including: a plurality of test sections; and a first synchronization section and a second synchronization section that, for each of a plurality of domains that respectively include one or more of the plurality of test sections, synchronize the one or more test sections included in the domain, where each of the first synchronization section and the second synchronization section includes: a local collection section that collects, for each domain, synchronization requests from the test sections connected to the corresponding synchronization section; an exchange section that exchanges, for a discrete domain of that includes test sections connected to the first synchronization section and test sections connected to the second synchronization section, synchronization requests collected in the corresponding synchronization section with synchronization requests collected in the other synchronization section; a global collection section that collects, the synchronization requests collected in the corresponding synchronization section and the synchronization requests collected in the other synchronization section; and a distribution section that distributes the collected synchronization requests to each of the test sections connected to the corresponding synchronization section. | 03-10-2011 |
| 20110068814 | PARALLEL SCAN DISTRIBUTORS AND COLLECTORS AND PROCESS OF TESTING INTEGRATED CIRCUITS - An integrated circuit ( | 03-24-2011 |
| 20110074453 | SEMICONDUCTOR CHIP HAVING A CRACK TEST CIRCUIT AND METHOD OF TESTING A CRACK OF A SEMICONDUCTOR CHIP USING THE SAME - A semiconductor chip includes a line structure arranged along a peripheral region of the semiconductor chip region in order to inspect a crack, a first pad and second pad arranged on different end portions of the line structure, a second pad arranged on another end portion of the line structure, an inspection device activated during a crack test mode to electrically connect the first pad, the line structure and the second pad. The inspection device may include a first switching circuit connected between the first pad and the line structure, the first switching circuit being deactivated during a normal operation mode and being activated a crack test mode; and a second switching circuit connected between the second pad and the line structure, the second switching circuit being deactivated during the normal operation mode and being activated during the crack test mode. | 03-31-2011 |
| 20110080184 | METHOD FOR TESTING THROUGH-SILICON-VIA AND THE CIRCUIT THEREOF - The method and circuit for testing a TSV of the present invention exploit the electronic property of the TSV under test. The TSV under test is first reset to a first state, and is then sensed at only one end to determine whether the TSV under test follows the behavior of a normal TSV, wherein the reset and sense steps are performed at only one end of the TSV under test. If the TSV under test does not follow the behavior of a normal TSV, the TSV under test is determined faulty. | 04-07-2011 |
| 20110080185 | METHOD FOR TESTING THROUGH-SILICON-VIA AND THE CIRCUIT THEREOF - The method and circuit for testing a TSV of the present invention exploit the electronic property of the TSV under test. The TSV under test is first reset to a first state, and is then sensed at only one end to determine whether the TSV under test follows the behavior of a normal TSV, wherein the reset and sense steps are performed at only one end of the TSV under test. If the TSV under test does not follow the behavior of a normal TSV, the TSV under test is determined faulty. | 04-07-2011 |
| 20110102005 | On-Chip Accelerated Failure Indicator - An accelerated failure indicator embedded on a semiconductor chip includes an insulating region; a circuit located inside the insulating region; a heating element located inside the insulating region, the heating element configured to heat the circuit to a temperature higher than an operating temperature of the semiconductor chip; and a reliability monitor configured to monitor the circuit for degradation, and further configured to trigger an alarm in the event that the degradation of the circuit exceeds a predetermined threshold. A method of operating an accelerated failure indicator embedded on a semiconductor chip includes determining an operating temperature of the semiconductor chip; heating a circuit located inside an insulating region of the accelerated failure indicator to a temperature higher than the determined operating temperature; monitoring the circuit for degradation; and triggering an alarm in the event that the degradation of the circuit exceeds a predetermined threshold. | 05-05-2011 |
| 20110102006 | CIRCUIT AND METHOD FOR TESTING SEMICONDUCTOR APPARATUS - A circuit for testing a semiconductor apparatus includes a test voltage applying unit configured to apply a test voltage to a first end of a through-silicon via (TSV) in response to a test mode signal and a detecting unit configured to be connected to a second end of the TSV and detect a current outputted from the second end of the TSV. | 05-05-2011 |
| 20110115509 | Semiconductor Devices Including Design for Test Capabilities and Semiconductor Modules and Test Systems Including Such Devices - A semiconductor device includes a resistor terminal, a reference voltage generator and a detector. The resistor terminal is connected to an external resistor. The reference voltage generator generates at least one reference voltage. The detector generates a detection signal based at least in part on a resistor terminal voltage and the at least one reference voltage. The detection signal indicates a state of an electrical connection to the resistor terminal. The resistor terminal voltage is a voltage at the resistor terminal. | 05-19-2011 |
| 20110115511 | ELECTRICAL DEVICE WITH MISWIRE PROTECTION AND AUTOMATED TESTING - The present invention is directed to an electrical wiring device that includes an actuator assembly that is responsive to the fault detection signal. The actuator assembly includes a breaker coil configured to generate an actuation force in response to being energized. A circuit interrupter includes four sets of movable contacts configured to be driven into a reset state in response to a reset stimulus, the four sets of movable contacts being configured to be driven into a tripped state in response to the actuation force. A self-test circuit is coupled to the plurality of line terminals or the at least one sensor. The self-test circuit is configured to automatically generate a test signal from time to time during a predetermined portion of an AC power line cycle. The self-test circuit is configured such that the test signal is sensed by the at least one sensor when the at least one sensor is operational, the sensor output signal being a function of the test signal. A monitor circuit is configured to monitor the fault detection circuit or the actuator assembly; the mechanical actuation force is substantially inhibited when the fault detection circuit or at least a portion of the actuator assembly properly respond to the test signal. The monitor circuit generates an end-of-life response if the fault detection circuit or the actuator assembly do not respond to the test signal within a predetermined period of time. | 05-19-2011 |
| 20110128021 | PIN CONNECTOR AND CHIP TEST FIXTURE HAVING THE SAME - A chip test fixture for assisting in examining a test chip on a printed circuit board includes a switching module, a pin cord and a magnetic unit. The switching module includes a standard chip and a switch element configured to turn on either the standard chip or the test chip. The pin cord is connected with the switch module at one end and is formed with a contacting head at the other end. The contacting head has a set of contact pins corresponding to that of the test chip. The magnetic unit is configured to draw the contacting head of the pin cord and the test chip together in such a way that the contact pins of the contacting head are in contact with that of the test chip once the contacting head approaches the test chip. | 06-02-2011 |
| 20110128022 | Testing apparatus and method - A testing apparatus includes a test controller configured to output a plurality of chip selection signals for selecting chips to be tested from among a plurality of chips, a plurality of first control signals for controlling supply of a power supply voltage to the chips selected by the chip selection signals, and a plurality of second control signals for controlling receiving of test voltages output from the chips supplied with the power supply voltage, and a probe card including one or more test blocks each having a plurality of signal transmitters configured to respectively transfer the power supply voltage to the corresponding chips in response to the different first control signals and respectively apply the test voltages output from the corresponding chips to the test controller in response to the different second control signals. | 06-02-2011 |
| 20110140725 | OVER CURRENT PROTECTION TEST SYSTEM - A system includes a switching power supply, an electric load connected to the switching power supply, a voltage regulation circuit, and a detect device. The voltage regulation circuit is connected to the electric load and configured to output a Pulse Width Modulation (PWM) signal to regulate a voltage supplied to the electric load. The detect device is connected to the switching power supply for detecting whether the switching power supply is powered off when a current flowing to the electric load exceeds a preset tolerance value. | 06-16-2011 |
| 20110148445 | Testing Circuit and Method - A test interface circuit operates with different types of core circuits. As consistent with various embodiments, the test interface circuit includes a test input register (TIR) configured to select an operating mode and a plurality of test point registers (TPRs). Each TPR is configured to control signals passed from the input port to a mixed-signal core circuit, responsive to the received test input signals and the operating mode selected by a TIR. In a static mode, each TPR provides serial access to digital inputs and outputs of a mixed-signal core circuit. In a bypass mode, each TPR bypasses TPR slices to preserve test time in response to the TPR being chained to other ones of the TPRs during integration of at least two mixed-signal cores. | 06-23-2011 |
| 20110148446 | CAPACITIVE OPENS TESTING IN LOW SIGNAL ENVIRONMENTS - An improved system for capacitive testing electrical connections in a low signal environment. The system includes features that increase sensitivity of a capacitive probe. One feature is a spacer positioned to allow the probe to be partially inserted into the component without contacting the pins. The spacer may be a collar on the probe that contacts the housing of the component, contacts the substrate of the circuit assembly, or both. In some other embodiments, the spacer may be a riser extending beyond the surface of the sense plate that contacts the component, a riser portion of the component, or a combination of both. The spacer improves sensitivity by establishing a small gap between a sense plate of the probe and pins under test without risk of damage to the pins. A second feature is a guard plate of the probe with reduced capacitance to a sense plate of the probe. Reducing capacitance also increases the sensitivity of the probe. | 06-23-2011 |
| 20110156731 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a first bump pad and a second bump pad configured to perform at least one of a data input operation and a data output operation in a normal mode; a probe pad configured to perform at least one of a data input operation and a data output operation in a test mode; a data output unit configured to communicate a data to one of the first bump pad and the probe pad; a data input unit configured to communicate a data from one of the second bump pad and the probe pad; a first switching unit configured to connect the probe pad and the data output unit in response to a test mode signal; and a second switching unit configured to connect the probe pad and the data input unit in response to the test mode signal. | 06-30-2011 |
| 20110175634 | FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle. | 07-21-2011 |
| 20110181309 | TEST APPARATUS AND TEST MODULE - Provided is a test apparatus for testing at least one device under test, including: a test module that includes a plurality of test sections, the plurality of test sections testing the device under test by exchanging signals with the device under test; and a plurality of test control sections that control the plurality of test sections, where the test module includes the plurality of test sections; a setting storage section that stores setting as to which of the plurality of test control sections should be associated with each of the plurality of test sections; and an interface section that is connected to the plurality of test sections, provides an access request issued from one of the plurality of test control sections and directed to the test module, to a test section associated with the test control section, and is able to set, independently for each of the plurality of test sections, which of the plurality of test control sections should control the test section. | 07-28-2011 |
| 20110181310 | TEST APPARATUS AND TEST METHOD - Provided is a test apparatus for testing a device under test, including: a plurality of test modules that exchange signals with the device under test; a bus to which the plurality of test modules are connected; and a test control section that controls the plurality of test modules via the bus, where each of the plurality of test modules includes: a test section that exchanges signals with the device under test, and a module control section that controls the test section, and the module control section of each test module exchanges signals with the module control section of another test module, via the bus. | 07-28-2011 |
| 20110181311 | TEST APPARATUS AND TEST METHOD - Provided is a test apparatus and a test method related to the test apparatus for testing a device under test, including: a plurality of test modules that exchange a signal with the device under test; a test control section that outputs a group read instruction for collectively reading data stored in two or more of the test modules; and a control interface section that reads the data from the two or more test modules according to the group read instruction, and collectively sends the read data to the test control section. | 07-28-2011 |
| 20110181312 | Mixed signal integrated circuit, with built in self test and method - A mixed signal integrated circuit includes a signal source to inject a test signal into the signal path of the mixed signal integrated circuit, a feedback loop and a signal comparator for determining characteristics of a resulting signal. Conveniently, the test signal may be a digital signal injected upstream of a digital to analog converter (DAC). By connecting the output to the input, the entirety of the signal path and the majority of the integrated circuit may be tested. The signal may be condition or manipulated in the feedback loop. By incorporating test signal generation and measurement into the mixed signal integrated circuit, the cost of test equipment and the test duration for each device under test may be reduced. | 07-28-2011 |
| 20110187396 | QUIESCENT CURRENT (IDDQ) INDICATION AND TESTING APPARATUS AND METHODS - An embodiment of an electronic device includes a logic circuit, a switching element, and a quiescent current (IDDQ) evaluation circuit. The logic circuit is coupled to a first ground node. The switching element is coupled between the first ground node and a second ground node. The switching element is configurable in an electrically non-conductive state when the electronic device is in an IDDQ evaluation state, and in an electrically conductive state when the electronic device is not in the IDDQ evaluation state. When the electronic device is in the IDDQ evaluation state, the IDDQ evaluation circuit is configured to provide a first output signal when an IDDQ indicating voltage across the first and second ground nodes exceeds a reference voltage. Other embodiments include methods for producing an indication of IDDQ in an electronic device and methods for fabricating an electronic device with the capability of producing an IDDQ indication. | 08-04-2011 |
| 20110193580 | Fatal Failure Diagnostics Circuit and Methodology - A fault diagnostic circuit ( | 08-11-2011 |
| 20110204908 | SEMICONDUCTOR DEVICE - A semiconductor device is designed to facilitate analyzing a position and a cause of the failure of an integrated circuit adopting a polyphase clock. To this end, the semiconductor device is provided with an error detecting unit that detects that a problem of the operation occurs in the integrated circuit, a clock state holding unit that holds the information of phases in a predetermined term of a two- or more-phase clock and an output unit that outputs the information of the phases in the predetermined term of the two- or more-phase clock when the error detecting unit detects that the problem of the operation occurs in the integrated circuit. | 08-25-2011 |
| 20110221460 | Integrated Circuit Arrangement Having a Defect Sensor - The present disclosure relates to an integrated circuit arrangement. The circuit arrangement includes a semiconductor body having a first surface and defining a vertical direction running perpendicular to the first surface. At least one sensor line is at least partially arranged above the first surface, and includes a first and a second contact terminal and at least one vertical line section coupled between the first and second contact terminals and running in the vertical direction. An evaluation circuit is coupled to the first and second contact terminals and adapted to evaluate an impedance of the at least one sensor line. | 09-15-2011 |
| 20110273197 | SIGNAL GENERATOR FOR A BUILT-IN SELF TEST - An integrated circuit with Built-in Self Test (BiST) is described. The integrated circuit includes a signal generator used to perform a BiST on the integrated circuit. The integrated circuit also includes a local oscillator used by the signal generator to generate one or more test signals used to perform the BiST on the integrated circuit. | 11-10-2011 |
| 20110298484 | ELECTRONIC CIRCUIT AND ELECTRONIC DEVICE - An electronic circuit of at least one embodiment of the present invention includes: a plurality of electronic parts, of the plurality of electronic parts, at least one electronic part being at least one main part and the other electronic parts being auxiliary parts, the at least one main part being necessary for determination of whether or not the electronic circuit operates normally, the auxiliary parts being unnecessary for determination of whether or not the electronic circuit operates normally, the auxiliary parts being connected to a line which is connected to the at least one main part so as to supply a signal necessary for operation of the at least one main part or output a signal obtained by the operation of the at least one main part. This provides an electronic circuit which is capable of properly detecting a circuit wiring disconnection and easily detecting faulty wiring between elements without the need of providing the electronic circuit with more components for detecting a circuit wiring disconnection. | 12-08-2011 |
| 20110316569 | Digital Interface for Fast, Inline, Statistical Characterization of Process, MOS Device and Circuit Variations - A Circuit architecture and a method for rapid and accurate statistical characterization of the variations in the electrical characteristics of CMOS process structures, MOS devices and Circuit parameters is provided. The proposed circuit architecture and method enables a statistical characterization throughput of <1 ms/DC sweep at <2 mV or <1 nA resolution accuracy of variations in voltage or current of the device under test. Salient features of proposed circuit architecture include a programmable ramp voltage generator that stimulates the device under test, a dual input 9-11 bit cyclic ADC that captures input and output DC voltage/current signals to/from the device under test, a 2 Kb latch bank that captures 9-11 bit streams for each measurement point in a DC sweep of programmable granularity and a clocking and control scheme that enables continuous measurement and stream out of digital data blocks from which the analog characteristics of the devices under test are reconstructed post measurement. | 12-29-2011 |
| 20120007621 | CIRCUIT INTERRUPTER DEVICE WITH SELF-TEST FUNCTION - A ground fault circuit interrupter (GFCI) device with self-test function includes: hot and neutral conducting circuits; an fault detection circuit responsive to a fault in the hot and neutral conducting circuits to generate a fault detection signal; a signal driving circuit responsive to the fault detection signal to generate a drive signal; a disconnecting mechanism for disconnecting electrical connections in the hot and the neutral conducting circuits when the drive signal exceeds a predetermined level; a self-test circuit for generating a self-test signal according to a predetermined time period and when an alternating current of the power source passes zero points, generating an evaluation result based on the self-test signal and a feedback signal of a fault detection signal corresponding to the self-test signal, and generating error signals if the evaluation result indicates a circuit error; and a device-state indicator circuit for generating alarms based on the error signals. | 01-12-2012 |
| 20120007622 | IP CORE DESIGN SUPPORTING USER-ADDED SCAN REGISTER OPTION - An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port | 01-12-2012 |
| 20120013356 | Method And System For Performing Self-Tests In An Electronic System - A method and system for performing a self-test of power supply quality for an integrated circuit chip within an electronic system. The electronic system is subjected to a well-defined repetitive activity, such as by using an amplitude modulated system clock tree. With the repetitive activity causing current consumption within the chip, time-domain local power supply voltage (U(t)) is measured for a location on the chip. A set of time-domain measured voltage data (U(t)) is accumulated and transformed into the frequency domain to yield a local voltage profile (U(f)). The local voltage profile (U(f)) is compared with a reference voltage profile (U | 01-19-2012 |
| 20120019273 | NO PIN TEST MODE - This application provides apparatus and methods for initiating tests in an interface circuit without using inputs of the interface circuit dedicated to initiating the tests. In an example, a test mode interface circuit can include a voltage comparator configured compare a first voltage to a second voltage, a ripple counter configured to count pulses from a processor when the voltage comparator indicates that the first voltage is greater than the second voltage, and wherein the test mode interface circuit is configured to provide a test mode enable signal and an indication of the a desired test mode an interface circuit that includes the test mode interface circuit. | 01-26-2012 |
| 20120025855 | DISPLAY DEVICE HAVING REPAIR AND DETECT STRUCTURE - A display device having repair and detect structure includes a substrate, a pixel array, a first shorting bar and a first repair line. The pixel array disposed on the substrate includes a plurality of data lines and a plurality of gate lines. The first shorting bar disposed on the substrate is connected to the gate lines for testing the gate lines, and the first shorting bar includes a first shorting segment. The first repair line is disposed on the substrate for repairing at least one of the data lines. The first shorting segment of the first shorting bar is electrically connected to the first repair line. Furthermore, another repair and detect structure of a display device is disclosed, wherein the first shorting bar includes a first shorting segment, the first repair line includes a first repair segment, and the first shorting segment overlaps with the first repair segment. | 02-02-2012 |
| 20120038378 | METHOD AND DEVICE FOR SUPPLYING CLOCK - A clock supplying device for supplying a clock signal to be used in an operation of a communication apparatus, includes an oscillator for generating the clock signal; a measurement unit for acquiring a reference clock signal extracted from a transmission line connected to the communication apparatus, and measuring a frequency difference between the clock signal and the reference clock signal; and a determiner for determining whether a warm-up operation of the oscillator unit has been completed or not, in accordance with measurement results of the frequency difference and a status of power supplying. | 02-16-2012 |
| 20120043982 | CRITICAL PATH MONITOR HAVING SELECTABLE OPERATING MODES AND SINGLE EDGE DETECTION - A critical path monitor having selectable data output modes provides additional information about critical path delay variation. A pulse is propagated through a synthesized path representing a critical path in a functional logic circuit and a synthesized path delay is measured by a monitoring circuit that detects the arrival of an edge of the pulse at the output of the synthesized delay. The measured delay is provided as a real-time output and a processed result of the measured delay is processed according to a data output mode selected from multiple selectable output modes, thereby providing different information describing the real-time data about critical path delay, such as a range of edge positions corresponding to a variation of the critical path delay. | 02-23-2012 |
| 20120074972 | SENSOR SELF-DIAGNOSTICS USING MULTIPLE SIGNAL PATHS - Embodiments relate to systems and methods for sensor self-diagnostics using multiple signal paths. In an embodiment, the sensors are magnetic field sensors, and the systems and/or methods are configured to meet or exceed relevant safety or other industry standards, such as SIL standards. For example, a monolithic integrated circuit sensor system implemented on a single semiconductor ship can include a first sensor device having a first signal path for a first sensor signal on a semiconductor chip; and a second sensor device having a second signal path for a second sensor signal on the semiconductor chip, the second signal path distinct from the first signal path, wherein a comparison of the first signal path signal and the second signal path signal provides a sensor system self-test. | 03-29-2012 |
| 20120074973 | ON-DIE PARAMETRIC TEST MODULES FOR IN-LINE MONITORING OF CONTEXT DEPENDENT EFFECTS - An integrated circuit (IC) die has an on-die parametric test module. A semiconductor substrate has die area, and a functional IC formed on an IC portion of the die area including a plurality of circuit elements configured for performing a circuit function. The on-die parametric test module is formed on the semiconductor substrate in a portion of the die area different from the IC portion. The on-die parametric test module includes a reference layout that provides at least one active reference MOS transistor, wherein the active reference MOS transistor has a reference spacing value for each of a plurality of context dependent effect parameters. A plurality of different variant layouts are included on the on-die parametric test module. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing value for at least one of the context dependent effect parameters. | 03-29-2012 |
| 20120081138 | TESTING OF HIGH-SPEED INPUT-OUTPUT DEVICES - Embodiments of the invention are generally directed to testing of high-speed input-output devices. An embodiment of a high-speed input-output apparatus includes a transmitter and a receiver, and a loop-back connection from an output of the transmitter to an input of the receiver, the loop-back connection including a first connector and a second connector for transmission of differential signals. The apparatus further includes a first inductor having a first terminal and a second terminal and second inductor having a first terminal and a second terminal, the first terminal of the first inductor being connected to the first connector and the first terminal of the second inductor being connected to the second connector, the second terminal of the first inductor and the second terminal of the second inductor providing a test access port for direct current testing of the apparatus. | 04-05-2012 |
| 20120098557 | CAPACITIVE INPUT TEST METHOD - Method and system are provided for evaluating linearity of a capacitive-to-digital converter (CDC) of a capacitive sensor integrated circuit chip. The evaluating employs multiple test capacitors, which may be on-chip with the CDC, and includes: obtaining capacitance values for the multiple test capacitors and parasitic capacitances of a first input A and a second input B to the capacitive-to-digital converter; applying the multiple test capacitors in multiple permutations to the first input A and the second input B, and for each of at least some permutations, determining an error between an expected output of the CDC using the obtained capacitance values and an actual measured output of the CDC; and determining linearity error for the CDC using the determined errors for the permutations of applying the multiple test capacitors to the first input A and the second input B of the CDC. | 04-26-2012 |
| 20120119768 | Method and System of Improved Reliability Testing - A method and system of improved reliability testing includes providing a first substrate and a second substrate, each substrate comprising only a first metallization layer; processing regions on a first substrate by combinatorially varying at least one of materials, unit processes, and process sequences; performing a first reliability test on the processed regions on the first substrate to generate first results; processing regions on a second substrate in a combinatorial manner by varying at least one of materials, unit processes, and process sequences based on the first results of the first reliability test; performing a second reliability test on the processed regions on the second substrate to generate second results; and determining whether the first substrate and the second substrate meet a predetermined quality threshold based on the second results. | 05-17-2012 |
| 20120126840 | Semiconductor Device with Cross-shaped Bumps and Test Pads Alignment - A semiconductor device includes a semiconductor substrate; bumps disposed in a plurality of rows along a first axis direction of the semiconductor substrate; and test pads disposed in one or more columns along a second axis direction perpendicular to the first axis direction. The bumps and the test pads form a cross shape in the center portion of the semiconductor substrate. Disposing bumps in the central portion of the semiconductor substrate facilitates forming physical connections between stacked semiconductor devices of a semiconductor stack, regardless of the chip sizes. | 05-24-2012 |
| 20120139569 | CIRCUIT APPARATUS - A circuit apparatus includes an input end, an output end, an enable module, a first function module and a second function module. The enable module couples to the input end for receiving an input voltage and outputs an enable signal while the input voltage falls within a first voltage scope. The first function module couples to the enable module and the output end, and performs a test mode according to the enable signal so as to output a test result to the output end. The second function module couples to the input end for receiving the input voltage via the input end and performs a standard mode while the input voltage falls within a second voltage scope. | 06-07-2012 |
| 20120139570 | SEMICONDUCTOR DEVICE AND METHOD FOR TESTING SAME - According to an embodiment, a semiconductor device includes a switch circuit selecting a signal pathway between a common terminal and one of a plurality of terminals using a plurality of FETs provided in series between the common terminal and each of the terminals. The semiconductor device also includes a test switch including a plurality of FETs connected to the common terminal, an oscillation circuit connected to the common terminal via the test switch, and a detection circuit receiving an output of the oscillation circuit. | 06-07-2012 |
| 20120146672 | Performance monitor with memory ring oscillator - Disclosed is a monitoring system that includes at least one performance monitor integrated into a semiconductor die. The performance monitor comprises at least one ring oscillator that includes a plurality of stages. Each stage comprises at least one memory device. In one embodiment, the performance monitor may also include a setting circuit that has a burn-in input and an enable input. The setting circuit is capable of setting an input signal of the at least one ring oscillator to a reference voltage level. The performance monitor is configured to produce a ring delay that is characterized by a performance of the at least one memory device. The ring delay may be utilized to scale an operating voltage of the at least one memory device on the semiconductor die. | 06-14-2012 |
| 20120146673 | METHOD AND EQUIPMENT FOR TESTING SEMICONDUCTOR APPARATUSES SIMULTANEOUSLY AND CONTINUOUSLY - A method for testing a plurality of semiconductor apparatuses, the method including mounting a plurality of semiconductor apparatuses on a first test board, wherein the plurality of semiconductor apparatuses include test circuits, loading test software into the test circuits, performing, by using the test circuits, self-tests on the plurality of semiconductor apparatuses based on the test software, and removing the plurality of semiconductor apparatuses, which have completed the self-tests, from the first test board. Upon completion of the loading of the test software, the test software is loaded into test circuits of a plurality of semiconductor apparatuses on a second test board, while the self-tests are performed on the plurality of semiconductor apparatuses on the first test board. | 06-14-2012 |
| 20120146674 | DETERMINING LOCAL VOLTAGE IN AN ELECTRONIC SYSTEM - A system for measuring a test voltage level (V | 06-14-2012 |
| 20120169361 | BUILT IN SELF TEST FOR TRANSCEIVER - An integrated circuit (IC), comprises a receiver on an IC substrate. The receiver is configured to receive a stressed input signal. A built in self test (BIST) circuit is provided on the IC substrate for testing the receiver. The BIST circuit comprises an encoder configured for receiving an input signal and identifying whether a first condition is present, in which two or more consecutive input data bits have the same polarity as each other. An output driver circuit provides the stressed input signal corresponding to the two or more consecutive input data bits. The stressed input signal has an amplitude that is larger when the encoder identifies that the first condition is present and smaller when the encoder identifies that two or more consecutive input data bits have different polarity from each other. | 07-05-2012 |
| 20120169362 | MULTI-LAYER DISTRIBUTED NETWORK - Apparatuses and processes for distributing signals in an integrated circuit are disclosed. An embodiment to use a custom layer together with a base layer on an integrated circuit for testing the integrated circuit includes having a structured network on the base layer. The custom layer connects the network to logic elements on the integrated circuit. The network may be evenly distributed across the base layer of the integrated circuit. Even distribution of the network may reduce skew of the test signals. Buffers are also placed along the structured network. The buffers may be placed to ensure a deterministic test signals distribution. Unused buffers in the base layer may be tied off to reduce current leakage. | 07-05-2012 |
| 20120176149 | SUBSTRATE AND METHOD FOR MOUNTING SEMICONDUCTOR PACKAGE - A substrate includes a join-structure including a semiconductor package, first electrode pad, bump, second electrode pad, and circuit substrate joined in the order named. The substrate also includes a first wire and a second wire formed in a region bellow a corner of the semiconductor package. The first and second wires are configured to detect a change in electrical resistance value when the first wire or the second wire is disconnected. One of the first and second wires is connected to the first electrode pad or the second electrode pad. A break strength of each of the first wire and the second wire is lower than a break strength of the join-structure. | 07-12-2012 |
| 20120182032 | TEST MODE CONTROLLER AND ELECTRONIC APPARATUS WITH SELF-TESTING THEREOF - A test mode controller comprises an enable signal generator, a control signal generator, and a latch. The enable signal generator receives a power signal and a second control signal, and generates a first enable signal and a second enable signal respectively to the latch and the control signal generator. The control signal generator receives a power indicating voltage and a reference voltage, and generates the first control signal to the latch when the first enable signal is enabled. The latch receives the first control signal, and generates the second control signal according to the first control signal when the second enable signal is enabled. The second control signal controls a chip to operate in a test mode or a normal mode. Accordingly, the test mode controller may reduce the test time without a test pin, and may also reduce the chip area and the package cost. | 07-19-2012 |
| 20120182033 | DIE TESTING USING TOP SURFACE TEST PADS - Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size. | 07-19-2012 |
| 20120187969 | BUILT-IN TEST FOR AN OVERVOLTAGE PROTECTION CIRCUIT - An overvoltage protection circuit connected to protect electrical components from overvoltage conditions includes a blocking diode connected in series with a transient voltage suppression device (TVS) via a first node and includes a reference voltage for biasing the first node at a voltage sufficient to reverse bias the blocking diode during normal operations. A built-in test circuit associated with the overvoltage protection circuit includes a resistor connected to the first node and a switch connected in series with the resistor that is selectively turned On and Off. The built-in test circuit monitors voltage on a control line associated with the electrical components and at the first node while the switch is Off and while the switch is On, and detects fault conditions based on the monitored voltages. | 07-26-2012 |
| 20120212245 | CIRCUIT AND METHOD FOR TESTING INSULATING MATERIAL - An integrated circuit is disclosed. The integrated circuit includes an insulating material layer. The integrated circuit also includes a metal structure. Furthermore, the integrated circuit includes a via through the insulating material layer that is coupled to the metal structure for testing insulating material by applying dynamic voltage switching to two adjacent metal components of the metal structure. | 08-23-2012 |
| 20120229155 | SEMICONDUCTOR INTEGRATED CIRCUIT, FAILURE DIAGNOSIS SYSTEM AND FAILURE DIAGNOSIS METHOD - A semiconductor integrated circuit includes a memory containing multiple memory bits that store predetermined data placed in a first address direction and a second address direction. The semiconductor integrated circuit includes a BIST (Built-in Self-Test) circuit that diagnoses a failure of the memory. | 09-13-2012 |
| 20120249170 | Circuit Arrangement with a Plurality of On-Chip Monitor Circuits and a Control Circuit and Corresponding Methods - Implementations are presented herein that include a plurality of on-chip monitor circuits and a controller. Each of the plurality of on-chip monitor circuits is configured to measure a parameter of a semiconductor chip. The controller is coupled to the plurality of on-chip monitor circuits. The controller is configured to receive a measurement result from at least one of the plurality of on-chip monitor circuits and to control a calibration of another one of the plurality of on-chip monitor circuits in accordance with the measurement result. | 10-04-2012 |
| 20120262196 | SEMICONDUCTOR DEVICE INCLUDING PLURAL CORE CHIPS AND INTERFACE CHIP THAT CONTROLS THE CORE CHIPS AND CONTROL METHOD THEREOF - Disclosed herein is a device includes first and second core chips and a test circuit. The first core chip outputs an internal signal to a second node thereof in response to a core-chip test signal supplied to a first node thereof. The second core chip outputs an internal signal to a second node thereof in response to the core-chip test signal supplied to a first node thereof. The test circuit generates test result signals based on the internal signal of the first core chip being output from the second node of the first core chip, and the internal signal of the second core chip being output from the third node of the first core chip. | 10-18-2012 |
| 20120262197 | TEST STRUCTURE AND METHODOLOGY FOR THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURES - A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer. | 10-18-2012 |
| 20120313656 | ELECTRONIC CIRCUIT MODULE AND METHOD OF MAKING THE SAME - An electronic circuit module and a method of manufacturing the electronic circuit module are disclosed. In one embodiment, the electronic circuit module includes i) a substrate on which a circuit is formed, ii) a plurality of electrical devices electrically connected to the circuit and iii) a first molding unit coated on the substrate to cover at least the electrical devices. The module further includes i) a test terminal unit comprising a plurality of test wires and configured to inspect the circuit, wherein each of the test wires comprises a first end electrically connected to the circuit and a second end exposed from the first molding unit, and wherein the second ends of the test wires form an inspection unit and are adjacent to each other on the substrate and ii) a second molding unit coated on the substrate to cover the second ends of the test wires. | 12-13-2012 |
| 20120326739 | SELF-ISOLATING MIXED DESIGN-RULE INTEGRATED YIELD MONITOR - Assessing open circuit and short circuit defect levels in circuits implemented in state of the art ICs is difficult when using conventional test circuits, which are designed to assess continuity and isolation performance of simple structures based on individual design rules. Including circuit blocks from ICs in test circuits provides a more accurate assessment of defect levels expected in ICs using the circuit blocks. Open circuit defect levels may be assessed using continuity chains formed by serially linking continuity paths in the circuit blocks. Short circuit defect levels may be assessed by using parallel isolation test structures formed by linking isolated conductive elements in parallel to buses. Forming isolation connections on a high metal level enables location of shorted elements using voltage contrast on partially deprocessed or partially fabricated test circuits. | 12-27-2012 |
| 20130002276 | SEMICONDUCTOR APPARATUS AND TESTING METHOD THEREOF - A semiconductor apparatus includes a through via and a comparison unit. The through via is electrically connected with another chip. The comparison unit includes a reference capacitor, and compares a capacitance value of the through via and a capacitance value of the reference capacitor in response to a test start signal and a reset signal and generates a comparison result. | 01-03-2013 |
| 20130002277 | SEMICONDUCTOR MODULE, TEST SYSTEM AND METHOD EMPLOYING THE SAME - A semiconductor module includes a plurality of module pins and a semiconductor device. Module pins receive an identification pattern signal having M bits and outputs a test identification pattern, where M is a positive integer. The semiconductor device includes device pins, and outputs the identification pattern signal through the device pins in response to a connection identification control signal for identifying a configuration of pin connections between the module pins and the device pins. The semiconductor module effectively identifies a configuration of pin connections between the module pins and the device pins. | 01-03-2013 |
| 20130002278 | Methods and Devices for Determining Sensing Device Usability - Methods and devices for determining sensing device usability, e.g., for self-monitoring and point of care devices. In one embodiment, the invention is to a method of determining device usability, comprising the steps of providing a device comprising a first electrical pad; a second electrical pad; and a humidity-responsive polymer layer contacting at least a portion of the first and second electrical pads; applying a potential across the first and second electrical pads; measuring an electrical property associated with the humidity-responsive polymer layer; and determining whether the measured electrical property associated with the humidity-responsive polymer layer has exceeded a humidity threshold level associated with the device usability. | 01-03-2013 |
| 20130002279 | Methods and Devices for Determining Sensing Device Usability - Methods and devices for determining sensing device usability, e.g., for point of care immunoassay devices. In one embodiment, the invention is to a method of determining device usability, comprising the steps of providing a device comprising a first electrical pad; a second electrical pad; and a continuous polymer layer contacting at least a portion of the first and second electrical pads; applying a potential across the first and second electrical pads; measuring an electrical property associated with the continuous polymer layer; and determining whether the measured electrical property associated with the continuous polymer layer has exceeded a threshold level associated with the device usability. | 01-03-2013 |
| 20130021048 | IC, CIRCUITRY, AND RF BIST SYSTEM - An IC, a circuitry, and an RF BIST system are provided. The RF BIST system includes a test equipment, a module circuitry, and an IC. The IC is arranged to communicate with the module circuitry by an RF signal in response to a command signal from the test equipment, determine a test result by the RF signal, and report the test result to the test equipment, wherein the module circuitry is external to the IC and the test equipment. | 01-24-2013 |
| 20130038342 | MOTOR CONTROL APPARATUS - Provided is a motor control apparatus that can easily distinguish between a current sensor abnormality and a rotation-angle sensor abnormality, without making a current sensor a duplex system. An MGECU ( | 02-14-2013 |
| 20130049780 | BUILT-IN SELF-TEST FOR RADIO FREQUENCY SYSTEMS - Techniques for performing built-in self-test (BIST) of performance of an RF system are disclosed. The techniques may be used, for example, for measuring distortion generated by the RF system under test, detecting faults in the system, determining calibration of the system, and/or assisting in compensating analog circuitry that is sensitive to temperature, supply voltage, and/or process variations. Also, a BIST architecture for determining RF performance of an RF systems is disclosed. | 02-28-2013 |
| 20130057307 | CIRCUIT BREAKER AND METHOD FOR CHECKING A ROGOWSKI CONVERTER IN A CIRCUIT BREAKER - A circuit breaker is disclosed. A Rogowski converter is checked for wire breakage by applying the Rogowski converter with a voltage which is output by a digital/analog converter in response to a digital signal. The digital signal is dependent on the switch rated current of the circuit breaker. | 03-07-2013 |
| 20130063170 | TEST CIRCUIT ALLOWING PRECISION ANALYSIS OF DELTA PERFORMANCE DEGRADATION BETWEEN TWO LOGIC CHAINS - A test circuit for measuring a gate delay as a function of stress is disclosed. The test circuit includes an oscillator, a reference gate chain, a test gate chain, and a counter. The counter measures the difference in propagation delay between the test chain and the reference chain in calibrated oscillator cycles. Differences in test gate delay as a function of applied stress may be measured within the calibration accuracy of the oscillator frequency. The use of the reference gate chain allows a simpler unipolar counter. | 03-14-2013 |
| 20130069679 | Testing of Defibrillator Electrodes - A defibrillator ( | 03-21-2013 |
| 20130076383 | METHOD FOR TESTING AN INTEGRATED CIRCUIT - A method for testing an integrated circuit and an integrated circuit. The integrated circuit has an internal testing structure which may be accessed via an internal test access port and a control bus which is conducted to the outside via control ports, it being possible to switch over between a running mode and a test mode so that, in the test mode, the test access port is accessed via the control ports and the control bus, thus testing the integrated circuit. | 03-28-2013 |
| 20130082726 | TEST STRUCTURE ACTIVATED BY PROBE NEEDLE - A test structure ( | 04-04-2013 |
| 20130088249 | METHOD OF DETECTING A FAULT WITH THE MEANS FOR DE-ICING A PROBE FOR MEASURING A PHYSICAL PARAMETER - A method of detecting a fault in a de-icer probe for measuring a physical parameter on an airplane engine, the method including: prior to starting an engine, measuring a first value of the physical parameter with help of the probe; activating the probe de-icer; at an end of a determined duration from a start of de-icing, measuring a second value of the parameter with help of the probe; and comparing the first and second values and generating a fault signal if the difference between the first and second values is less than a determined threshold. | 04-11-2013 |
| 20130093445 | Voice-Activated Pulser - A voice-activated pulser can trigger an oscilloscope or a meter, upon a simple voice command, thereby enabling hands-free signal measurements. The pulser can also be used to control the circuit under test, activating it or changing parameters, all under voice control. The pulser includes numerous switch-selectable output modes that allow users to generate complex, tightly-controlled diagnostic sequences, all activated upon a voice command and hands-free. The invention includes a fast, robust command-interpretation protocol that completely eliminates the expense and complexity of word recognition. Visual indicators display the device status and various operating modes, and also confirm each output pulse. The device receives voice commands directly through an internal microphone, or through a detachable headset, and confirms each command with an acoustical signal in the headset. | 04-18-2013 |
| 20130106452 | REAL-TIME ON-CHIP EM PERFORMANCE MONITORING | 05-02-2013 |
| 20130120011 | SEMICONDUCTOR DEVICE AND METHOD OF DRIVING THE SAME - A semiconductor device including a plurality of sensor units and a plurality of storage units, the device comprising a controller which in a normal mode, sets first control information based on outputs from the plurality of sensor units, stores the first control information in the plurality of storage units, and accumulates charges in each of the plurality of sensor units up to a reference defined in the corresponding first control information, and in a test mode, stores second control information for tests determined in advance in the plurality of storage units, accumulates charges in each of the plurality of sensor units up to a reference defined in the corresponding second control information, and tests the plurality of sensor units based on the amounts of charges accumulated in the plurality of sensor units. | 05-16-2013 |
| 20130147501 | SEMICONDUCTOR INTEGRATED CIRCUIT - According to one embodiment, there is provided a semiconductor integrated circuit including an on-chip measurement circuit. The measurement circuit includes a buffer line, a ring oscillator, a first measurement unit measuring a duty cycle of a periodic pulse output from the buffer line, and a second measurement unit measuring a frequency of a periodic pulse output from the ring oscillator. The buffer line including a plurality of delay elements connected in series. Each of the plurality of delay elements includes a former-stage inverter unit including a PMOS transistor and an NMOS transistor and having a first delay amount, and a latter-stage inverter unit including a PMOS transistor and an NMOS transistor and having a second delay amount different from the first delay amount. | 06-13-2013 |
| 20130154677 | APPARATUS AND METHOD FOR TESTING PAD CAPACITANCE - A pad capacitance test circuit may be coupled to one or more pads of an electronic circuit, such as a processor. The pad capacitance test circuit may be located on a die including the electronic circuit. The pad capacitance test circuit may reset a pad voltage of one or more of the pads to zero, and then couple the pad to a supply voltage through a pullup resistor for a time period. The final pad voltage at or near the end of the period of time may be measured. The pad capacitance may be determined from the measured value of the final pad voltage and known values of the supply voltage, the time period, and resistance of the pullup resistor. | 06-20-2013 |
| 20130162275 | SEMICONDUCTOR DEVICE HAVING COMMAND MONITOR CIRCUIT - A semiconductor device includes a plurality of channels, a plurality of command monitor circuits provided corresponding to the plurality of channels, respectively, and a plurality of signal lines coupled in common to the plurality of command monitor circuits. Each of the plurality of command monitor circuits includes a selector configured to receive a plurality of input signals and selectively output a plurality of selected signals among the input signals, based on a first selection information, and an output circuit coupled between the selector and the plurality of signal lines, and configured to output the selected signals to the plurality of signal lines, respectively, based on a second selection information. One of the plurality of command monitor circuits is selected to output the selected signals to the plurality of signal lines while the remaining of the command monitor circuits is non selected, based on the second selection information. | 06-27-2013 |
| 20130176044 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a control chip including a first selection unit configured to output one of signals which are inputted through a first normal port and a shared test port, in response to a test mode signal; and a second selection unit configured to output one of signals which are inputted through a second normal port and the shared test port, in response to the test mode signal, wherein the control chip is configured to transmit an output of the first selection unit to a first chip and transmit an output of the second selection unit to a second chip. | 07-11-2013 |
| 20130200909 | SENSOR SELF-DIAGNOSTICS USING MULTIPLE SIGNAL PATHS - Embodiments relate to systems and methods for self-diagnostics and/or error detection using multiple signal paths in sensor and other systems. In an embodiment, a sensor system comprises at least two sensors, such as magnetic field sensors, and separate signal paths associated with each of the sensors. A first signal path can be coupled to a first sensor and a first digital signal processor (DSP), and a second signal path can be coupled to a second sensor and a second DSP. A signal from the first DSP can be compared with a signal from the second DSP, either on-chip or off, to detect faults, errors, or other information related to the operation of the sensor system. Embodiments of these systems and/or methods can be configured to meet or exceed relevant safety or other industry standards, such as safety integrity level (SIL) standards. | 08-08-2013 |
| 20130222001 | CURRENT SENSOR HAVING SELF-DIAGNOSIS FUNCTION AND SIGNAL PROCESSING CIRCUIT - There are provided a current sensor which has a self-diagnosis function and a signal processing circuit. The current sensor is provided with an offset component output circuit | 08-29-2013 |
| 20130241586 | INDUSTRIAL AUTOMATIC-DIAGNOSTIC DEVICE - An industrial automatic-diagnostic device connected to an FA system in which a plurality of FA devices are connected to each other, the industrial automatic-diagnostic device includes: an engineering tool; and a display unit. Based on interface connection information and device configuration information of a corresponding FA device held by each of the FA devices, the engineering tool creates overall configuration information of the FA system and displays an overall configuration of the FA system on the display unit based on the overall configuration information. When an abnormality occurs in the FA device, diagnosis information about an abnormal part self-diagnosed by the FA device and abnormality contents with respect to the abnormality occurred in a corresponding abnormal part is obtained. Based on the obtained diagnosis information, occurrence of an abnormality is displayed in an abnormal part in an overall configuration of the FA system displayed on the display unit. | 09-19-2013 |
| 20130249578 | SEMICONDUCTOR DEVICE HAVING PENETRATING ELECTRODES EACH PENETRATING THROUGH SUBSTRATE - Disclosed herein is a device that includes a semiconductor substrate, a check circuit and a through-substrate via. The check circuit includes a check line formed over the semiconductor substrate and including first and second parts each extending in a first direction and a third part extending in a second direction that crosses the first direction, the first and second parts being opposite to each other, the third part connecting one end of the first part with one end of the second part, a charge circuit coupled to a one end of the check line, and a comparator coupled to the other end of the check line at a first input node thereof. The through-substrate via penetrates through the semiconductor substrate and is located in an area that is between the first and second parts of the check line. | 09-26-2013 |
| 20130265068 | BUILT-IN SELF-TEST METHOD AND STRUCTURE - A method of testing a semiconductor wafer and a related structure. In various embodiments, a method includes: placing a probe on a first chip on the semiconductor wafer; testing a scribe line automatic built-in self-test (ABIST) for the first chip to search for a fault; progressively testing a subsequent scribe line ABIST for a subsequent chip on the semiconductor wafer in response to determining the ABIST for the first chip does not indicate the fault; moving the probe point to the subsequent chip and retesting the subsequent scribe line ABIST in response to determining the ABIST for the subsequent chip indicates a fault; and testing a further subsequent scribe line ABIST for a further subsequent chip on the semiconductor wafer in response to determining the retesting of the subsequent scribiline ABIST does not indicate a fault in the subsequent scribe line ABIST. | 10-10-2013 |
| 20130265069 | Liquid Crystal Panel, Liquid Crystal Module, and Method Of Determining Reason Behind Bad Display - The present invention discloses a liquid crystal panel, which, in shorting bar area, connects scan signal line to scan signal test point through a first switch, connects data signal line to data signal test point through a first unidirectional circuit or a second switch, and connects common electrode to common electrode test point through conductive wire. The present invention also discloses a liquid crystal module and a method of determining reason behind bad display for liquid crystal module. With the method, the liquid crystal panel of the present invention can realize to spare the cutting of test leads of shorting bar area and cutting facility used in cell process. | 10-10-2013 |
| 20130265070 | SELF TEST OF MEMS ACCELEROMETER WITH ASICS INTEGRATED CAPACITORS - An apparatus comprises a micro-electromechanical system (MEMS) sensor including a first capacitive element and a second capacitive element and an integrated circuit (IC). The IC includes a switch network circuit and a capacitance measurement circuit. The switch network circuit is configured to electrically decouple the first capacitive element of the MEMS sensor from a first input of the IC and electrically couple the second capacitive element to a second input of the IC. The capacitance measurement circuit can be configured to measure capacitance of the second capacitive element of the MEMS sensor during application of a first electrical signal to the decoupled first capacitive element. | 10-10-2013 |
| 20130271168 | WIRING STRUCTURE OF WIRING AREA ON LIQUID CRYSTAL DISPLAYING PANEL AND TESTING METHOD OF LIQUID CRYSTAL DISPLAYING PANEL - A wiring structure of a wiring area on a liquid crystal displaying panel includes a number of wiring lines connected to one end of a corresponding data line and corresponding scan line on the wiring area, at least one signal testing point, a number of first testing lines connected between the wiring lines and the signal testing point, a number of second testing lines connected between the signal testing point and the other end of the corresponding data line and the corresponding scan line, and a switch controlling circuit connected to the second testing lines. After the testing lines are disconnected from the wiring lines in the previous process, the testing signal still can be transmitted through the other end of the corresponding data line or the scan line, to implement the image test of the liquid crystal displaying panel. | 10-17-2013 |
| 20130278278 | SYSTEMS AND METHODS FOR VOLTAGE DETECTION - Embodiments disclosed herein include systems and methods for voltage detection. One embodiment of a method includes receiving, at a voltage detection device, a power command, implementing a power conditioning stage, where the power conditioning stage provides power to electrical components of the voltage detection device, and performing an internal battery charge state built in test (BIT) function. Some embodiments include providing device function, control, sensing, signal processing, and user output functions, sampling a state of charge of a power supply of the voltage detection device, and outputting test result information. Still some embodiments include receiving, via an antenna of the voltage detection device, an indication of an ambient voltage and outputting a warning signal that identifies presence of the ambient voltage. | 10-24-2013 |
| 20130285683 | INTERNAL LINE REPLACEABLE UNIT HIGH INTENSITY RADIATED FIELD DETECTOR - Various embodiments for detecting a high Intensity radiated field (HIRF) in a line replaceable unit are provided. In an embodiment, the internal detector comprises a receiving means for receiving HIRF and generating an AC signal proportional to the HIRF, an RF filter configured to sample the AC signal to create a DC signal; and a detecting section configured to compare the DC signal with a threshold and output a result of the comparison to a built-in test section. The internal detector may be used to test EMI filter pin connectors of a closed line replaceable unit. | 10-31-2013 |
| 20130285685 | SELF-CONTAINED, PATH-LEVEL AGING MONITOR APPARATUS AND METHOD - An aging monitor circuit that provides a more accurate estimate of aging and/or delay in a circuit and/or circuit path. The aging monitor circuit employs a separate aging path with driving and receiving flip flops (FFs) and a tunable replica circuit (TRC) to enable measurements of single-transition DC-stressed path delay that only propagates through stressed transistors or other circuit element(s). A finite state machine (FSM) in the aging monitor circuit is configured to adjust a frequency of a clock signal output by a digitally controlled oscillator (DCO) in response to an error signal output by the receiving FF. The error signal is generated in response to single transition DC-stressed path delay, and therefore enables the adjustment of the frequency of the clock signal to correspond to an amount or effect of the delay. | 10-31-2013 |
| 20130293250 | INTEGRATED CIRCUIT WITH STRESS GENERATOR FOR STRESSING TEST DEVICES - An integrated circuit device includes at least one test device and a stress generator coupled to the test device and operable to cycle the at least one test device to generate an AC stress. A method for testing an integrated circuit device including at least one test device and a stress generator coupled to the test device includes enabling the stress generator to cycle the at least one test device to generate an AC stress and measuring at least one parameter of the test device to determine an effect of the AC stress. | 11-07-2013 |
| 20130293251 | WIRE BREAK DETECTION IN REDUNDANT COMMUNICATIONS - A system and method for low-cost, fault tolerant, EMI robust data communications, particularly for an EV environment. | 11-07-2013 |
| 20130321013 | PHOTOVOLTAIC DEVICE FOR MEASURING IRRADIANCE AND TEMPERATURE - A solar array system includes a plurality of power-generator modules, each power-generator module having an identical form factor and comprising a plurality of photovoltaic cells wired for power generation. The system also includes at least one sensor module having a substantially identical appearance and form factor as the power-generator modules and comprising a like plurality of photovoltaic cells. The operational state of the system is monitored by an array performance monitor, which measures signals sent from the various modules. At least one photovoltaic cell in the sensor module delivers a short-circuit current signal to the array performance monitor and at least one photovoltaic cell in the sensor module delivers an open-circuit voltage signal to the array performance monitor. These signals are used to calculate a theoretical power output of the array system, which is compared to the actual power output. | 12-05-2013 |
| 20130328583 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR DESIGNING THE SAME - A power-on self-test circuit and a pattern generation circuit are provided. The power-on self-test circuit includes a selection circuit and a comparator circuit. The selection circuit selects, instead of an external pin group corresponding to a test access port, an output of the pattern generation circuit when a self-diagnosis execution signal is asserted and supplies a test pattern generated by the pattern generation circuit to a built-in self-test circuit. The comparator circuit compares a test result of a circuit-under-test with an expected value. By asserting the self-diagnosis execution signal in this manner, the semiconductor integrated circuit mounted on a user system executes BIST. | 12-12-2013 |
| 20130335107 | CONTINUITY TEST IN ELECTRONIC DEVICES WITH MULTIPLE-CONNECTION LEADS - An electronic device includes an electronic component having terminals including a set of first terminals and a set of second terminals, a protective package embedding the electronic component, leads exposed from the protective package including a set of first leads and a set of second leads, for each first lead a first electrical connection inside the protection package between the first lead and a corresponding one of the first terminals, and for each second lead electrical connections inside the protective package each one between the second lead and a corresponding one of the second terminals. For each second lead the electronic component includes test structures, each being coupled between a corresponding one of the second terminals connected to the second lead and a corresponding test one of the first terminals connected to a test one of the first leads. | 12-19-2013 |
| 20130342229 | LIQUID CRYSTAL DISPLAY AND DEAD PIXEL TEST CIRCUIT AND METHOD FOR LIQUID CRYSTAL DISPLAY - A liquid crystal display includes a liquid crystal display panel and a test circuit. The liquid crystal panel includes a number of scanning lines and a number of data lines cooperatively forming a pixel cell. The test circuit includes a control unit, a gate driving circuit, a data driving circuit and a detecting circuit. The gate driving circuit and the data driving circuit respectively provide a scan pulse and a test pulse to the pixel cells. The test pulse includes a first voltage. After a predefined period for providing the scan pulse and the test pulse to the pixel cells, the detecting circuit detects a voltage of the data lines, and determines the pixel cell is damaged if the voltage of the data lines is equal to the first voltage. A test circuit and a test method for detecting damaged pixel cells are also provided. | 12-26-2013 |
| 20140002120 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR MEASURING INTERNAL VOLTAGE THEREOF | 01-02-2014 |
| 20140002121 | SYSTEM AND METHOD FOR ELECTRONIC TESTING OF PARTIALLY PROCESSED DEVICES | 01-02-2014 |
| 20140021971 | BUILT-IN TEST INJECTION FOR CURRENT SENSING CIRCUIT - A current sense system includes a current transformer having a primary coil and a secondary coil, wherein the secondary coil has a first and second terminal; a burden resistor connected between the first terminal of the secondary coil and ground; a monitor circuit that measures current in the primary coil by monitoring voltage across the burden resistor; and a built-in test (BIT) circuit connected to the second terminal of the secondary coil. The BIT circuit provides a virtual ground during normal operation, and either a positive voltage or a negative voltage during test operations. | 01-23-2014 |
| 20140028336 | PRINTED CIRCUIT BOARD - Disclosed herein is a printed circuit board. In the printed circuit board provided with a router machining line to be partitioned into a unit region in which a plurality of unit substrates are formed and a dummy region enclosing the unit region, the unit region and the dummy region are formed in a plurality of layers and the printed circuit board includes detection coupons formed on each of the plurality of layers. | 01-30-2014 |
| 20140055153 | SLIP RING AND SLIP RING ELECTRICAL SYSTEM - A slip ring includes an exterior, a plurality of brushes, a plurality of rings, a brush fixing member that causes the plurality of brushes to contact the plurality of rings and supports the plurality of brushes, and a rotating shaft inserted into the plurality of rings and supports the plurality of rings. The slip ring also includes a reference signal generation unit configured to generate a reference signal, and a detection unit configured to detect a signal, wherein a circuit is formed by the reference signal generation unit, a first brush, which is at least one of the plurality of brushes, a first ring that contacts the first brush, and the detection unit, and wherein a state of contact of the first brush and the first ring is detected based on the signal detected by the detection unit. | 02-27-2014 |
| 20140062514 | SEMICONDUCTOR DEVICE WITH TEST MODE CIRCUIT - A semiconductor device includes a plurality of test entry selection units configured to selectively activate a plurality of test entry signals in response to a test entry code, and a plurality of test operation blocks, corresponding to the respective test entry signals, each configured to be reset in response to activation of the corresponding test entry signal to perform a set test operation corresponding to a test selection code. | 03-06-2014 |
| 20140070829 | DEVICE FOR DETECTING THE THINNING DOWN OF THE SUBSTRATE OF AN INTEGRATED CIRCUIT CHIP - A device for detecting the thinning down of the substrate of an integrated circuit chip, including, in the active area of the substrate, bar-shaped diffused resistors connected as a Wheatstone bridge, wherein: first opposite resistors of the bridge are oriented along a first direction; the second opposite resistors of the bridge are oriented along a second direction; and the first and second directions are such that a thinning down of the substrate causes a variation of the imbalance value of the bridge. | 03-13-2014 |
| 20140091819 | METHOD OF TESTING A SEMICONDUCTOR STRUCTURE - An integrated circuit (IC) comprises routing circuitry including a plurality of signal line segments in routing layers of the IC, and a plurality of micro-bump contacts coupled to the routing circuitry. The IC includes a plurality of test circuits coupled to respective subsets of the plurality of signal line segments. Each test circuit is configured to connect micro-bump contacts in the respective subset to form first and second sets of daisy chains. Each test circuit is configured to test the first and second sets of daisy chains for open circuits and test for short circuits between the first and second sets of daisy chains. Each test circuit is configured to determine the locations of detected open circuits and determine the locations of detected short circuits. | 04-03-2014 |
| 20140097861 | SEMICONDUCTOR DEVICE AND TEST METHOD - A semiconductor device includes a semiconductor substrate including an element region, an inner sealing and an outer sealing which are formed on the element region and have a first opening part and a second opening part, respectively, a multilayer interconnection structure which is formed on the substrate and stacks multiple inter-layer insulation films each including a wiring layer, a moisture resistant film formed between a first inter-layer insulation film and a second inter-layer insulation film which are included in the multilayer interconnection structure, a first portion which extended from a first side of the moisture resistant film and passes the first opening part, a second portion which extended from a second side of the moisture resistant film and passes through the second opening part, and a wiring pattern including a via plug which penetrates the moisture resistant film and connects the first portion and the second portion. | 04-10-2014 |
| 20140111234 | Die, Chip, Method for Driving a Die or a Chip and Method for Manufacturing a Die or a Chip - In various embodiments, a die is provided. The die may include a physical unclonable function circuit configured to provide an output signal, wherein the output signal is dependent on at least one physical characteristic specific to the die; and a self-test circuit integrated with the physical unclonable function circuit on the die, wherein the self-test circuit is configured to provide at least one test input signal to the physical unclonable function circuit and to determine as to whether the output signal provided in response to the at least one test input signal fulfills a predefined criterion. | 04-24-2014 |
| 20140132291 | SCALABLE BUILT-IN SELF TEST (BIST) ARCHITECTURE - A circuit with built-in self test (BIST) capability includes a master BIST controller, a plurality of slave BIST controllers, and a collector. The master BIS controller issues test instructions in response to a master resume input signal. The plurality of slave BIST controllers is coupled to the master BIST controller. Each slave BIST controller is adapted to perform a test on a functional circuit in response to a test instruction and to provide a resume signal at a conclusion of the test. The collector receives a corresponding resume signal from each of the multiple slave BIST controllers after the master BIST controller issues the test instruction, and subsequently provides the master resume signal in response to an activation of all of the corresponding resume signals. | 05-15-2014 |
| 20140132292 | TEST BOARD - A test board is disclosed. The test board serves as an interface for testing a conference phone. The test board includes a plurality of test channel selectors. Each of the test channel selectors receives a plurality of test voltages provided by the conference phone and a first and a second control signals. The test voltages are divided into a plurality test voltage pairs, and each of the test channel selectors selects one of the test voltages in each of the test voltage pairs for generating a plurality of selected voltages according to the first control signal. Each of the test channel selectors selects two of the selected voltages for generating a first and a second output voltages according to the second control signal, where the first and the second output voltages are transmitted to a test machine for testing the conference phone. | 05-15-2014 |
| 20140132293 | INTEGRATED CIRCUIT WITH DEGRADATION MONITORING - An integrated circuit including a degradation monitoring circuit. The degradation monitoring circuit includes a comparison circuit having a programmable delay element including an input coupled to a data node of a timing path and having an output to provide a delayed signal of a data signal of the data node that is delayed by a programmable amount. The comparison circuit includes a logic comparator that provides a logic comparison between a data signal of the data node and the output of the delay element. The monitoring circuit includes a sampling circuit that provides a sampled signal of the output of the logic comparator that is a sampled with respect to a clock signal of the clock signal line. The monitoring circuit includes a hold circuit that provides a signal indicative of a data signal of the data node transitioning within a predetermined time of an edge transition of a clock signal of the clock signal line. | 05-15-2014 |
| 20140132294 | APPARATUS AND METHOD FOR TESTING A CAPACITIVE TRANSDUCER AND/OR ASSOCIATED ELECTRONIC CIRCUITRY - A method of testing a capacitive transducer circuit, for example a MEMS capacitive transducer, by applying a test signal via one or more capacitors provided in the transducer circuit. | 05-15-2014 |
| 20140132295 | DRIVE FAILURE PROTECTION - The present techniques include methods and systems for detecting a failure in a capacitor bank of an electrical drive system. Embodiments include using discharge resistors to discharge capacitors in the capacitor bank, forming a neutral node of the capacitor bank. In different capacitor configurations, the neutral node is measured, and the voltage is analyzed to determine whether a capacitor bank unbalance has occurred. In some embodiments, the node is a neutral-to-neutral node between the discharged side of the discharge resistors and a neutral side of the capacitor bank, or between the discharged side of the discharge resistors and a discharged side of a second set of discharge resistors. In some embodiments, the node is a neutral-to-ground node between the discharged side of the discharge resistors and a ground potential. | 05-15-2014 |
| 20140145739 | DISPLAY PANEL AND METHOD FOR TESTING DISPLAY PANEL - A display panel including a display part including a plurality of sub-pixels configured to display a plurality of colors, and a plurality of data lines connected with the sub-pixels; a first test part configured to supply a test signal to (2K−1)th data lines (‘K’ is an integer above 0) by each color for the sub-pixels among the plurality of data lines; and a second test part configured to supply a test signal to 2Kth data lines by each color for the sub-pixels among the plurality of data lines when the first test part supplies the test signal. Further, a polarity of the test signal supplied by the second test part is opposite to a polarity of the test signal supplied by the first test part. | 05-29-2014 |
| 20140167796 | WIRING STRUCTURE AND DISPLAY DEVICE INCLUDING THE SAME - There is provided a wiring structure comprising a board, which includes a connection pattern, and a plurality of flexible printed circuit boards (FPCBs). Each of the flexible printed circuit boards includes test patterns connected to the connection pattern. The test patterns included in each of the FPCBs are connected to each other by the connection pattern. | 06-19-2014 |
| 20140167797 | CURRENT MONITORING CIRCUITS AND METHODS - Various automatic range scaling solutions for smart power switches are provided, to enable current monitoring across a wide dynamic range. In preferred examples, use is made of current sensing transistors. The circuits provide overload protection combined with wide range current measurement. | 06-19-2014 |
| 20140176167 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes: an output timing controller configured to delay an applied external read command by a predetermined time and generate a normal output enable flag signal, during a normal mode, a test output timing controller configured to generate a DLL clock signal from an external clock signal, delay the applied external read command in synchronization with the DLL clock signal, and output the delayed applied external read command as a test output enable flag signal, during a test mode, and a multiplexer (MUX) configured to output any one of the normal output enable flag signal or the test output enable flag signal as an output enable flag signal. | 06-26-2014 |
| 20140176168 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes: a receiver configured to receive a plurality of input signals through a plurality of pads; a signal processing unit configured to process the input signals received by the receiver and output the processed signals as a plurality of internal signals; a MUX unit configured to select the plurality of internal signals as a plurality of MUX output or select test input data and a plurality of latch signals as the plurality of MUX output signals in response to an input/output select signal; a latch unit configured to output the plurality of MUX output signals as the plurality of latch signals and a final output signal in response to a latch clock signal; and a clock selection unit configured to output any one of a test clock signal and an internal clock signal as the latch clock signal in response to a test mode signal. | 06-26-2014 |
| 20140176169 | ELECTRONIC DEVCIE WITH CHIP-ON-FILM PACKAGE - An electronic device with COF package is provided. The electronic device includes a flexible substrate, a core circuit unit, multiple output pads, multiple switching elements, and a common test pad. The flexible substrate includes a non-cutting-out area and a cutting-out area. The core circuit unit and output pads are disposed in the non-cutting-out area. First terminals of the switching elements are respectively and electrically connected to output pads of the core circuit unit, and second terminals of the switching elements are respectively and electrically connected to the output pads. The common test pad is disposed in the cutting-out area and electrically connected to the output pads. In a test stage, the switching elements are sequentially turned on such that one of multiple output signals of the core circuit unit is transmitted to the common test pad. | 06-26-2014 |
| 20140184254 | DEBUG CARD - A debug card includes a connector, a control chip, a pin switching unit, and a control module. The connector is used to connect to a debug signal output port of an electronic device. The connector includes a number of pins. The control chip includes a number of control pins. The pin switching unit is connected between the pins of the connector and the control pin of the control chip. The control module is connected to the pin switching unit, and controls the pin switching unit to establish a first connection relationship between the pins of the connector and the control pins of the control chip by a first connection mode or establish a second connection relationship between the pins of the connector and the control pins of the control chip by a second connection modes. | 07-03-2014 |
| 20140197856 | SELF TESTING FAULT CIRCUIT APPARATUS AND METHOD - A process for self testing a fault circuit includes disabling an actuator, performing a self test by creating a simulated fault signal across at least a portion of a half cycle of a first polarity and across at least a portion of a hall cycle of a second polarity, and determining whether the self test was successful. | 07-17-2014 |
| 20140210496 | CHIP-TO-CHIP SIGNAL TRANSMISSION SYSTEM AND CHIP-TO-CHIP CAPACITIVE COUPLING TRANSMISSION CIRCUIT - A chip-to-chip signal transmission system is provided, which includes a first chip, a second chip, and a dielectric layer. A signal transmission is performed between a transmitter of the first chip and a receiver of the second chip through a transmission-metal-pad unit and a receiving-metal-pad unit. The transmitter transmits a transmission-testing-coupling signal through the transmission-metal-pad unit according to a driving-testing signal when the transmitter receives the driving-testing signal. A first testing unit receives the transmission-testing-coupling signal and outputs a transmission-testing signal according to the transmission-testing-coupling signal. A second testing unit transmits a receiving-testing-coupling signal through the receiving-metal-pad unit according to the driving-testing signal when the second testing unit receives the driving-testing signal. The receiver receives the receiving-testing-coupling signal and outputs a receiving-testing signal according to the receiving-testing-coupling signal. | 07-31-2014 |
| 20140210497 | STACK INCLUDING INSPECTION CIRCUIT, INSPECTION METHOD AND INSPECTION APPARATUS - According to one embodiment, a stack includes first and second wiring structures and an inspection circuit. The inspection circuit includes a switching circuit having an input terminal, a drive terminal, and an output terminal electrically connected with a discharge mechanism. The inspection circuit is configured such that, in a state where a first electric connection is made in the first wiring structure and a second electric connection is made in the second wiring structure, at the time of applying charges to first and second electrodes, the charge applied to the second electrode flows to the drive terminal through the second wiring structure to bring the input terminal and the output terminal of the switching circuit into an electrically conducted state, and the charge applied to the first electrode flows to the discharge mechanism through the first wiring structure and the switching circuit. | 07-31-2014 |
| 20140218060 | DEGRADATION DIAGNOSING CIRCUIT AND DEGRADATION DIAGNOSING METHOD - In order to measure a state of degradation of a semiconductor integrated circuit more correctly by use of a simple configuration, a degradation diagnosing circuit includes: a test block including a first circuit which is an object of a degradation diagnosis; a reference block including a second circuit which has a configuration identical with a configuration of the first circuit; a judgment unit that judges whether a component of the test block is degraded or not by comparing a characteristic of a first signal outputted from the test block, and a characteristic of a second signal outputted from the reference block, in the case in which a signal indicating a measurement mode is inputted; and a control unit that outputs the signal which indicates the measurement mode to the judgment unit. | 08-07-2014 |
| 20140239987 | System and Method for Determining Operational Robustness of a System on a Chip - A system and method for determining operational robustness of a system on a chip (SoC) includes modifying one or more internal states of the SoC, during operation of the SoC, to mimic an effect which one or more disturbances have on the SoC, generating one or more signal traces that correspond to at least one internal state of the SoC after modifying the one or more internal states of the SoC, and determining if the operation of the SoC is stable based on the one or more generated signal traces. | 08-28-2014 |
| 20140239988 | SEMICONDUCTOR DEVICE WHICH CAN DETECT ABNORMALITY - A semiconductor device includes: a drive circuit; a standby circuit; and a detection circuit. The drive circuit turns on an output transistor connected to a load based on an active input signal. The standby circuit intermittently outputs an output signal based on a non-active input signal. The detection circuit measures voltage of a load side of the output transistor based on the output signal and output a measurement result. | 08-28-2014 |
| 20140239989 | SEMICONDUCTOR DEVICE HAVING CIRCUITRY FOR DETECTING ABNORMALITIES IN A POWER SUPPLY WIRING NETWORK - A semiconductor device is capable of detecting a power supply voltage abnormality without degrading the performance of internal circuits. The semiconductor device includes a plurality of power supply inspection circuits and a result storage register. The power supply inspection circuits detect a power supply voltage abnormality in each pad that couples an internal wiring disposed in the semiconductor device to another part disposed outside of the semiconductor device. The result storage register stores inspection results indicated by result signals output from the power supply inspection circuits. | 08-28-2014 |
| 20140266272 | GROUND FAULT CIRCUIT INTERRUPTER AND METHOD - A ground fault interrupter circuit and a method for operating a ground fault interrupter that includes configuring the ground fault interrupter to perform a plurality of self tests. The ground fault interrupter may be configured to perform a ground fault self test, a grounded-neutral self test, and a trip circuit self test. | 09-18-2014 |
| 20140300377 | PROCESSING CIRCUIT HAVING SELF-DIAGNOSIS FUNCTION - A processing circuit has an input terminal to which an input signal generated by an input signal generator is inputted via an input line. An external capacitor is connected to the input line in parallel with the processing circuit. The processing circuit includes a pulse circuit, at least one switch, a controller, a detector and a determiner. The pulse circuit generates a pulsed voltage having at least one pulse. The least one switch is provided between the pulse circuit and the input line. The controller controls the at least one switch so as to apply the pulsed voltage to the input line via a resistor. The detector detects a change in a voltage of the input line caused by application of the pulsed voltage to the input line. The determiner determines whether the processing circuit is in a normal or abnormal condition based on the change detected by the detector. | 10-09-2014 |
| 20140306727 | FACILITY AND A METHOD FOR TESTING SEMICONDUCTOR DEVICES - A test facility may be used to test semiconductor devices. The test facility may include a stacker part configured to communicate with a server, wherein the server includes test programs for testing semiconductor devices, and a plurality of test board parts disposed in the stacker part, at least one of the test board parts including semiconductor devices disposed thereon and configured to provide at least one of the test programs from the server to the semiconductor devices. The stacker part may include unit stackers which include shelves configured to hold the plurality of test board parts and a stacker controller configured to communicate with the test board parts in the unit stackers and the server. | 10-16-2014 |
| 20140320154 | FIELD DEVICE WITH SELF-TESTING OF A PIEZOELECTRIC TRANSDUCER - An industrial process field device having a piezoelectric transducer performs self-testing of the condition of the piezoelectric transducer during a self-test mode. A charging current is supplied to the piezoelectric transducer, and voltage on the piezoelectric transducer as a result of the charging current is monitored. A diagnostic test result indicating condition of the piezoelectric transducer is produced based on the magnitude of the voltage. | 10-30-2014 |
| 20140320155 | CRITICAL CAPACITOR BUILT IN TEST - An electronic circuit and method for carrying out built in test of a capacitor connected to, and arranged to suppress noise at, an input of an electrical circuit is disclosed. The electronic circuit causes current pulses at the input, and monitors the voltage at the input by comparing the voltage at the input with high and/or low reference voltages, outputting a fault signal if the voltage at the input is greater than a high reference voltage or lower than a low reference voltage. | 10-30-2014 |
| 20140354311 | INTEGRATED CIRCUIT CHIP AND MULTI-CHIP SYSTEM INCLUDING THE SAME - An integrated circuit chip includes a test circuit suitable for performing a test operation and generating a test result signal indicating whether there is an error or not in the integrated circuit chip, a transmitting unit suitable for transmitting the test result signal through an interlayer channel. The interlayer channel is precharged to a first level before the transmitting unit transmits the test result signal, and the interlayer channel is driven to a second level when there is an error. | 12-04-2014 |
| 20140368227 | IN-LINE MEASUREMENT OF TRANSISTOR DEVICE CUT-OFF FREQUENCY - A test circuit within a semiconductor wafer that measures a cut-off frequency for a transistor device under test may include a radio frequency source, located within a region of the wafer, that generates a radio frequency signal. A biasing circuit, also located within the region, may provide a current bias setting to the transistor device under test. The biasing circuit receives the radio frequency signal and applies a buffered radio frequency signal to the transistor device under test. The biasing circuit generates a buffered output signal based on the transistor device under test generating a first output signal in response to receiving the applied buffered radio frequency signal. An rf power detector, within the region, receives the first output signal and the radio frequency signal, and generates an output voltage signal, wherein the cut-off frequency of the transistor device under test is determined from the generated output voltage signal. | 12-18-2014 |
| 20140368228 | FLEXIBLE DISPLAY DEVICE - A flexible display device includes a display panel, at least one inspection part, and a detector. The display panel includes at least one bending portion and a display area. The inspection part is located on the bending portion and bends in a manner similar to the bending portion. The detector applies an inspection signal to the inspection part and receives an output signal from the inspection part. A crack in the inspection part is then determined based on a comparison of the inspection and output signals. | 12-18-2014 |
| 20140375344 | LIQUID CRYSTAL PANEL, AND TESTING CIRCUIT AND TESTING METHOD THEREOF - A liquid crystal panel, the testing circuit and the testing method thereof are disclosed. The testing circuit includes shorting bars, bonding pads, and switches. The switches are arranged between the shorting bars and the bonding pads. In the testing process, the switches are turn on upon receiving the testing signals so as to transmit the testing signals from the shorting bars to the bonding pads. When the testing process ends, the switches are turn off to prevent the liquid crystal panel from being affected by the signals of the bonding pads during the normal screen display of the liquid crystal panel. In this way, the manufacturing cost is reduced. | 12-25-2014 |
| 20150015284 | TRANSMIT/RECEIVE UNIT, AND METHODS AND APPARATUS FOR TRANSMITTING SIGNALS BETWEEN TRANSMIT/RECEIVE UNITS - In one embodiment, apparatus for transmitting and receiving data includes a transmission line network having at least three input/output terminals; at least three transmit/receive units, respectively coupled to the at least three input/output terminals; and a control system. The control system is configured to, depending on a desired direction of data flow over the transmission line network, i) dynamically place each of the transmit/receive units in a transmit mode or a receive mode, and ii) dynamically enable and disable an active termination of each transmit/receive unit. Methods for using this and other related apparatus to transmit and receive data over a transmission line network are also disclosed. | 01-15-2015 |
| 20150042369 | METHOD AND AN APPARATUS OF DETERMINING PERFORMANCE OF AN INTEGRATED CIRCUIT - The present invention discloses an efficient method to determine the performance of an integrated circuit or a chip by instantiating a plurality of HPM in the integrated circuit to generate the performance of the integrated circuit according to a performance function, wherein each term of the performance function is based on the values of the HPM(s) and the weighting of the term is determined through machine leaning, so that the performance of each chip can be determined by the performance function. | 02-12-2015 |
| 20150042370 | APPARATUS FOR DETECTING A FAILED TRANSISTOR - An electronic load system for testing power supplies, batteries, and fuel cells is characterized by its ability to automatically detect a transistor failure in the load circuit. The electronic load system includes a plurality of field effect transistor (FET) modules. Each FET module includes an FET and a differential amplifier. A processor module serves as an input to the amplifier and provides a drive signal. The FET module further includes a diode and a light emitting diode that are arranged such that the light emitting diode lights when the field effect transistor fails as an open circuit. | 02-12-2015 |
| 20150061709 | METHOD FOR FORMING A PACKAGED SEMICONDUCTOR DEVICE - A method of fabricating a packaged semiconductor device includes integrating a plurality of singulated semiconductor die in a die carrier, and forming one or more interconnect layers on the die carrier. The interconnect layers include at least one of conductive intra-layer structures and inter-layer structures coupled to contact pads on the plurality of singulated semiconductor die. A set of landing pads is formed coupled to a first subset of the contact pads via a first set of the conductive intra-layer structures and inter-layer structures. A set of probe pads is formed coupled to a second subset of the contact pads via a second set of the conductive intra-layer structures and inter-layer structures. The die carrier is singulated to form a plurality of packaged semiconductor devices. The set of probe pads is removed during the singulating the die carrier. | 03-05-2015 |
| 20150061710 | SEMICONDUCTOR APPARATUS AND TEST METHOD - A test driver selection unit configured to enable a plurality of test driver selection signals in response to a test pulse and a test clock, and a plurality of drivers configured to receive the plurality of test driver selection signals, wherein each of the plurality of drivers is configured to output an output signal to a data bump in response to a test driver selection signal, data, and an output enable signal, and to receive a first driving voltage and a second driving voltage. | 03-05-2015 |
| 20150077147 | Circuit And Method For Monolithic Stacked Integrated Circuit Testing - A monolithic stacked integrated circuit (IC) is provided with a known-good-layer (KGL) path delay test circuit and at least a portion of a critical path in one of its layers. The test circuit includes a plurality of inputs, outputs, a flip-flop coupled to the at least a portion of the critical path and a multiplexer coupled to the flip-flop and to a second layer of the IC. The test circuit further includes a control element such that path delay testing of the IC may be conducted on a layer-by-layer basis. | 03-19-2015 |
| 20150115986 | ALIGNMENT TESTING FOR TIERED SEMICONDUCTOR STRUCTURE - Among other things, one or more techniques or systems for evaluating a tiered semiconductor structure, such as a stacked CMOS structure, for misalignment are provided. In an embodiment, a connectivity test is performed on vias between a first layer and a second layer to determine a via diameter and a via offset that are used to evaluate misalignment. In an embodiment, a connectivity test for vias within a first layer is performed to determine an alignment rotation based upon which vias are connected through a conductive arc within a second layer or which vias are connected to a conductive pattern out of a set of conductive patterns. In this way, the via diameter, the via offset, or the alignment rotation are used to evaluate the tiered semiconductor structure, such as during a stacked CMOS process, for misalignment. | 04-30-2015 |
| 20150123684 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device which can generate a new test pattern even after design and have a reduced footprint of a circuit not used in normal operation. The semiconductor device includes a first integrated circuit and a second integrated circuit. The first integrated circuit includes a memory circuit that stores data and a plurality of circuits that make a signal for an operation test of the second integrated circuit. The signal is made when the continuity between the plurality of circuits is controlled by the memory circuit according to the data. In the second integrated circuit, the memory circuit is used as a buffer memory device after the operation test is conducted according to the signal. | 05-07-2015 |
| 20150137841 | BUILT-IN SELF TEST SYSTEM, SYSTEM ON A CHIP AND METHOD FOR CONTROLLING BUILT-IN SELF TESTS - A built-in self test system comprises an integrated circuit device comprising a plurality of functional units coupled to built-in self test circuitry; a low power control unit operable to switch the integrated circuit device into a low power mode and to generate a BIST wake-up signal during or before entering the low power mode; and a built-in self test control unit coupled to the built-in self test circuitry and the low power control unit and arranged to initiate a built-in self test when receiving the BIST wake-up signal. | 05-21-2015 |
| 20150137843 | SIGNAL TRANSMISSION CIRCUIT DEVICE, SEMICONDUCTOR DEVICE, METHOD AND APPARATUS FOR INSPECTING SEMICONDUCTOR DEVICE, SIGNAL TRANSMISSION DEVICE, AND MOTOR DRIVE APPARATUS USING SIGNAL TRANSMISSION DEVICE - Disclosed is a signal transmission circuit device ( | 05-21-2015 |
| 20150301105 | PIEZOELECTRIC OR ELECTRET SENSING DEVICE - A piezoelectric and/or electret sensing device ( | 10-22-2015 |
| 20150309117 | SCAN TESTING SYSTEM, METHOD AND APPARATUS - Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible. | 10-29-2015 |
| 20150325158 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel and a display device comprising a pixel area (A) and a peripheral wiring area, wherein detection switches are arranged between the pixel area (A) and the peripheral wiring area, the detection switches correspond to gate lines ( | 11-12-2015 |
| 20150331039 | Diagnostics And Control Circuit - A circuit for self-diagnosis and control comprising a plurality of processing devices each having a voltage supply, the processing devices being arranged to communicate with one another and being arranged to be electrically isolated from each processing device having a different voltage supply. | 11-19-2015 |
| 20150331040 | INTEGRATED CIRCUIT DEVICE, SAFETY CIRCUIT, SAFETY-CRITICAL SYSTEM AND METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT DEVICE - An integrated circuit device comprises a first integrated circuit and a second integrated circuit wherein the first and second integrated circuits are comprised on a single semiconductor die. The second integrated circuit is a safety circuit arranged to monitor the operation of the first integrated circuit, report any detected faults and drive the device into a failsafe state if a fault is detected. The first integrated circuit may be a power management module for a safety critical system. An isolation barrier in the form of a trench is formed between the two integrated circuits so that the safety circuit is protected from any high voltage or thermal stresses arising in the first integrated circuit. The device has particular application to automotive safety-critical systems such as electric power steering systems. | 11-19-2015 |
| 20150331041 | Interlock Detector with Self-Diagnosis Function for an Interlock Circuit, and Method for the Self-Diagnosis of the Interlock Detector - The interlock detector includes a first input, wherein a first output signal from an interlock generator is applied to the first input. The interlock detector further includes a second output which is configured to provide a microprocessor with a second output signal. The interlock detector further includes a differential amplifier that includes a second input, a third input, and a third output, wherein the second input and the third input are connected to the first input. The interlock detector further includes a comparator circuit that includes a fourth input and a fourth output, wherein the fourth input is connected to the third output, the fourth output is connected to the second output, and the fourth input is positioned between the comparator circuit and the differential amplifier. | 11-19-2015 |
| 20150346275 | METHOD OF COMPENSATING FOR EFFECTS OF MECHANICAL STRESSES IN A MICROCIRCUIT - A method for manufacturing an integrated circuit includes forming in a substrate a measuring circuit sensitive to mechanical stresses and configured to supply a measurement signal representative of mechanical stresses exerted on the measuring circuit. The measuring circuit is positioned such that the measurement signal is also representative of mechanical stresses exerted on a functional circuit of the integrated circuit. A method of using the integrated circuit includes determining from the measurement signal the value of a parameter of the functional circuit predicted to mitigate an impact of the variation in mechanical stresses on the operation of the functional circuit, and supplying the functional circuit with the determined value of the parameter. | 12-03-2015 |
| 20150346276 | CONVERTER CIRCUIT AND OPEN-CIRCUIT DETECTION METHOD OF THE SAME - A converter circuit is provided. The converter circuit includes a capacitor module, bridge arms, a voltage measuring module and an open-circuit detection module. Each bridge arm is connected to the capacitor module in parallel and includes an upper arm and a lower bridge arm connected at a middle point. The voltage measuring module measures voltage differences between each two bridge arms. The open-circuit detection module transmits test impulse signals to the bridge arms to activate at least one upper-conducted bridge arm and at least one lower-conducted bridge arm. The open-circuit detection module retrieves the voltage differences of each pair of the upper-conducted and lower-conducted bridge arms to make comparison with a reference value to determine an operation state thereof, and makes comparison of the operation state determined according to the different groups of test impulse signals to determine whether the upper and the lower bridge arms are actually open circuit. | 12-03-2015 |
| 20150355273 | RESIDUAL-CURRENT-OPERATED PROTECTIVE ARRANGEMENT, CHARGING APPARATUS AND METHOD FOR CHECKING A RESIDUAL-CURRENT-OPERATED PROTECTIVE DEVICE - A residual-current-operated protective arrangement includes a residual-current-operated protective device that has a core and an evaluation coil. A control device is provided that has a detection unit for detecting an electric current flowing through the evaluation coil. The residual-current-operated protective arrangement has a test winding that is inductively coupled to the evaluation coil via the core and the control device has a testing unit for impressing a predetermined test current into the test winding. | 12-10-2015 |
| 20150362547 | Step Drill Test Structure of Layer Depth Sensing on Printed Circuit Board - A step drill test structure for a PCB and method for using the same is disclosed. In one embodiment, a test structure includes a drill path and a connection via. The drill path may include sensing pads on selected ones of a plurality of layers of the PCB (e.g., the non-surface layers). The sensing pads of a given drill path may be electrically conductive, while the remaining portion of the drill path is non-conductive. The sensing pads of each drill path may be electrically coupled to the connection via. The depth of a given layer at a particular drill path may be determined by drilling, using an electrically conductive drill bit, into the drill path and determining when an electrical connection is made between the drill bit and the connection via. | 12-17-2015 |
| 20150362550 | Circuits and Techniques for Detecting an Open Pin Condition of an Integrated Circuit - As integrated circuit as open pin detector includes a current source coupled to the pin, a comparator having a first input coupled to the pin, a second input responsive to a threshold voltage, and an output at which a comparator output signal is provided. A controller is responsive to the comparator output signal to provide an enable signed, to the current source and an open pin signal indicative of an open pin condition at the pin. An open pin condition can be detected by comparing the pin voltage to a first threshold voltage level initiating open pin detection in response to the pin voltage falling below the first threshold voltage level, such as by providing a current to the pin, and indicating an open pin condition if the pin voltage rises to exceed a second threshold voltage level within a predetermined time interval. The pin voltage may be prevented from exceeding a predetermined voltage level during open pin detection. | 12-17-2015 |
| 20160003896 | WIRELESS REMOTE POWER EQUIPMENT TEST SYSTEM AND METHOD OF USING SAME - Methods, systems, and devices are disclosed for the wireless remote testing of power equipment and for recording and reporting the associated test results. | 01-07-2016 |
| 20160003908 | METHOD FOR TESTING COMPARATOR AND DEVICE THEREFOR - An integrated circuit facilitates a self test routine that verifies proper operation of an analog comparator. In response to entering the self test routine, the voltage provided to an input of a comparator is changed from being at an operating voltage supply to being at a self test voltage that is used to verify operation of the comparator. In response to the comparator operating properly, the self test voltage provided to the input of the comparator is replaced with the operating voltage supply, and normal operation resumes. The duration of the self test cycle is based upon the amount of time during which the self test voltage is provided to the comparator is asynchronous in nature, and therefore not a function of a clock signal. | 01-07-2016 |
| 20160011263 | SEMICONDUCTOR APPARATUS | 01-14-2016 |
| 20160025805 | WAFER TEST STRUCTURES AND METHODS OF PROVIDING WAFER TEST STRUCTURES - Wafer test structures and methods of providing wafer test structures are described. The methods include: fabricating multiple test devices and multiple fuse devices on the wafer, each test device having a respective fuse device associated therewith, which open circuits upon failure of the test device; and fabricating a selection circuit operative to selectively connect one test device to a sense contact pad, and the other test devices to a stress contact pad. The selection circuit facilitates sensing one or more electrical signals of the one test device by electrical contact with the sense contact pad, while stress testing the other test devices by electrical contact with the stress contact pad. In one embodiment, each test device has respective first and second switch devices, operative to selectively electrically connect the test device to the sense or stress contact pads. In another embodiment, the method includes wafer testing using the test structure. | 01-28-2016 |
| 20160041221 | System and Method for Testing a Radio Frequency Integrated Circuit - In an embodiment, a method of testing a radio frequency integrated circuit (RFIC) includes generating high-frequency test signals using the on-chip test circuit, measuring signal levels using on-chip power detectors, and controlling and monitoring the on-chip test circuit using low-frequency signals. The RFIC circuit is configured to operate at high frequencies, and an on-chip test circuit that includes frequency generation circuitry configured to operate during test modes. | 02-11-2016 |
| 20160041222 | BUILT-IN TESTING OF AN ARC FAULT/TRANSIENT DETECTOR - The present invention relates to built-in testing of detectors for the detection of electrical arc faults or transients, where the detector is integrated into or electrically coupled to an electrical power supply system. | 02-11-2016 |
| 20160054383 | SEMICONDUCTOR STRUCTURE HAVING TEST DEVICE - There is set forth herein a semiconductor structure including a plurality of test devices, the plurality of test devices including a first test device and a second test device. A semiconductor structure can also include a waveform generating circuit, the waveform generating circuit configured for application of a first stress signal waveform having a first duty cycle to the first test device, and a second stress signal waveform having a second duty cycle to the second test device. A semiconductor structure can include a selection circuit associated with each of the first test device and the second test device for switching between a stress cycle and a sensing cycle. | 02-25-2016 |
| 20160061887 | WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE - Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals. | 03-03-2016 |
| 20160061894 | SCHEME TO MEASURE INDIVIDUALLY RISE AND FALL DELAYS OF NON-INVERTING LOGIC CELLS - A test circuit measures both the rising edge delay and the falling edge delay associated with a logic cell. The test circuit includes a flip-flop type ring oscillator with two groups of logic cells connected in series in the oscillation path. A first multiplexor switches the ring oscillator between a rising edge and a falling edge mode. A second multiplexer causes the second group of logic cells to be included or excluded from the oscillation path. By measuring the oscillation period in the various modes, the rising edge and falling edge delays can be individually calculated. | 03-03-2016 |
| 20160077142 | POWER ELECTRONICS DEVICE - According to one embodiment, a power electronics device has an output connected to an output of a different power electronics device by a power line. The power electronics device includes a detector to detect, from the power line or a space around the power electronics device, an electric power that the different power electronics device superimposes onto an output power, or at least one of an electric power, a sound, and an electromagnetic wave, each having a frequency of a carrier wave that the different power electronics device uses for power conversion. The power electronics device includes a determiner to determine a state of the different power electronics device based on a detection signal obtained through detection performed by the detector. | 03-17-2016 |
| 20160077152 | 3D TAP & SCAN PORT ARCHITECTURES - This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure. | 03-17-2016 |
| 20160084903 | INTEGRATED CIRCUIT AND METHOD OF OPERATING AN INTEGRATED CIRCUIT - An integrated circuit comprises a first functional unit and one or more other functional units. The first functional unit has an input for receiving data and an output for providing data. The integrated circuit tests and operates the first functional unit. Testing comprises: connecting the input of the first functional unit to the output of the first functional unit, thereby generating a loopback path from the output of the first functional unit to the input of the first functional unit; loading a test pattern onto the first functional unit; feeding a test clock signal comprising one or more clock edges, thereby prompting the first functional unit to transform the test pattern; and reading the transformed test pattern. Operating the first functional unit comprises: connecting the input of the first functional unit to an output of the other functional units; and feeding a normal clock signal to the first functional unit. | 03-24-2016 |
| 20160091557 | PRINTED BOARD WITH WIRING PATTERN FOR DETECTING DETERIORATION, AND MANUFACTURING METHOD OF THE SAME - A printed board with a wiring pattern for detecting deterioration includes an insulating substrate, a wiring pattern group that is formed on the insulating substrate and includes a wiring pattern for detecting deterioration; and a solder resist covering the wiring pattern group, in which the board has a thin film section, and a thick film section in which a thickness of the solder resist is larger than the thin film section, and the wiring pattern for detecting deterioration is formed in the thin film section whose entire surrounding area or partial surrounding area is surrounded by the thick film section. | 03-31-2016 |
| 20160091560 | INTEGRATED CIRCUIT AND METHOD OF TESTING - An integrated circuit includes a first circuit and a test circuit. The test circuit is configured to test the timing of a first circuit. The first circuit includes a plurality of flip-flops and a plurality of data paths. Each data path of the plurality of data paths is connected to one or more of the plurality of flip-flops. The test circuit includes a plurality of loopback paths, a controller, a multiplexer connected to the plurality of loopback paths and a counter connected to the multiplexer. The controller is configured to select a path from the plurality of loopback paths and the plurality of data paths. The multiplexer is configured to selectively output a first signal including an oscillation frequency. The first signal is applied to the selected path and the counter is configured to measure the oscillation frequency of the first signal. | 03-31-2016 |
| 20160091561 | SECURE LOW VOLTAGE TESTING - An integrated circuit includes a normal voltage detector configured to detect a normal voltage at which the integrated circuit being fully functional. A first voltage detector detects a first voltage that is less than the normal voltage. A second voltage detector detects a second voltage that is less than the first voltage. A reset module is coupled to a supply voltage, the normal voltage detector, the first voltage detector, and the second voltage detector. The reset module includes test logic to, when the supply voltage rises to the first voltage from the second voltage, perform a pass/fail test when the integrated circuit is in a pass/fail test mode, and perform a power up reset when the integrated circuit in not in the pass/fail test mode. | 03-31-2016 |
| 20160097803 | BUILT IN TEST CIRCUIT FOR TRANSIENT VOLTAGE SUPPRESSOR DEVICES - A built-in test system includes a control circuit, a transient voltage suppressor circuit, and a test switch. The control circuit is configured to receive a signal, and the transient voltage suppressor circuit includes first and second transient voltage suppressors connected in series between the signal and ground. The test switch is connected to selectively conduct current between the signal and a node between the first and second transient voltage suppressors. The control circuit is configured to control the test switch to test the first and second transient voltage suppressors. | 04-07-2016 |
| 20160097806 | METHOD FOR TESTING A SIGNAL PATH - A method for testing a signal path of a first IC formed as a monolithically integrated circuit on a semiconductor body together with a magnetic field sensor and has a signal output and a power supply connection and a test mode state and a normal operating state. A power supply of the first IC is switched off, and a signal output is connected with a reference potential, and the power supply of the first IC is switched on and the signal output is disconnected from the reference potential. Subsequently in a test mode state, a self-test is performed in the first IC and a test pattern is configured at the signal output or at the power supply connection and the test pattern is evaluated by the control unit for testing of the signal path. | 04-07-2016 |
| 20160103173 | APPARATUS AND A METHOD FOR PROVIDING AN OUTPUT PARAMETER AND A SENSOR DEVICE - An apparatus for providing an output parameter includes an output parameter generator circuit configured to determine a value of an output parameter repeatedly. The output parameter generator circuit includes at least one circuit block mandatory for the determination of a value of the output parameter. Further, the apparatus includes an output interface circuit configured to transmit the output parameter repeatedly to a receiver and a test circuit configured to test a basic functionality of the at least one mandatory circuit block of the output parameter generator circuit repeatedly. The at least one mandatory circuit block of the output parameter generator circuit is unavailable for the determination of a value of the output parameter during the basic functionality test. | 04-14-2016 |
| 20160103174 | CAPACITIVE MICROELECTROMECHANICAL SENSOR WITH SELF-TEST CAPABILITY - A capacitive sensor that includes at least one capacitive element and a switched-capacitor readout circuit part for detecting at least one signal capacitance that results from motions of the capacitive element. The self-test bias voltage of the actuation circuit part is coupled to the capacitive element during a first period that is synchronized to the front end reset period and occurs when the self-test of the capacitive sensor is enabled by the self-test controller. | 04-14-2016 |
| 20160109511 | RF DEVICE AND SWITCHING CONTROL PERFORMED THEREIN - In an RF device, an RF circuit includes at least two RF transmitting/receiving elements; and an RF switch controlled to selectively electrically couple to one of the RF transmitting/receiving elements for transmitting/receiving an RF signal in response to a control signal. In addition, a testing circuit includes a first filter unit having a first external terminal electrically coupled to a testing signal and a second external terminal electrically coupled to the RF circuit, wherein the first filter unit is configured to allow the testing signal to enter the RF circuit while blocking an RF signal transmitted in the RF circuit from entering the testing circuit; and a testing-result informing unit having an external input electrically coupled to the first external terminal, and determining contents of the control signal according to an electric level at the external input. | 04-21-2016 |
| 20160112700 | CIRCUIT AND METHOD FOR ON-CHIP TESTING OF A PIXEL ARRAY - Testing of control wires of a pixel array of an image sensor is performed by applying a signal transition to a control wire and detecting, based on a voltage signal detected on the control wire, the duration of at least part of the signal transition on the control wire. An electrical fault in the control wire is indicated based on a comparison of the detected duration to a threshold. | 04-21-2016 |
| 20160116530 | INTERPOSER INSTRUMENTATION METHOD AND APPARATUS - The disclosure describes a novel method and apparatus for improving interposers to include embedded monitoring instruments for real time monitoring digital signals, analog signals, voltage signals and temperature sensors located in the interposer. An embedded monitor trigger unit controls the starting and stopping of the real time monitoring operations. The embedded monitoring instruments are accessible via an 1149.1 TAP interface on the interposer. | 04-28-2016 |
| 20160117964 | TESTING APPARATUS FOR ELECTRONIC DEVICE - A testing apparatus to establish a fault by a process of elimination includes an input unit, a signal converting unit, a switch unit, and a display unit. The input unit receives an input signal and outputs a switch signal. The signal converting unit receives the switch signal and outputs a control signal. The switch unit receives the control signal and outputs a test signal. The display unit receives the test signal and runs a built in self test (BIST) program to test the proper functioning of the display unit. The signal converting unit outputs a data signal and a clock signal to the display unit when the display unit works normally. The signal converting unit not output the data signal and the clock signal to the display unit when the input signal and resulting control signal are repeated. | 04-28-2016 |
| 20160131697 | BUILT-IN TEST CIRCUIT OF SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a clock buffer and a reference voltage generation unit. The clock buffer generates an internal clock signal, based on first and second clock signals, in a first operation mode, and generates the internal clock signal, based on the first clock signal and a reference voltage, when a normal operation test is performed in a second operation mode. The reference voltage generation unit generates the reference voltage when the normal operation test is performed in the second operation mode. | 05-12-2016 |
| 20160139199 | Magnetic Field Sensor with Shared Path Amplifier and Analog-To-Digital-Converter - Methods and apparatus for processing a signal comprise at least one circuit configured to generate a measured signal during a measured time period and a reference signal during a reference time period. Also included is at least one dual- or multi-path analog-to-digital converter comprising at least a first processing circuit configured to process the measured signal, at least a second processing circuit configured to process the reference signal, and a third processing circuit configured to process both the measured signal and the reference signal. | 05-19-2016 |
| 20160146880 | DISPLAY SUBSTRATE, ITS TESTING METHOD AND ITS MANUFACTURING METHOD - The present disclosure provides a display substrate, its testing method and its manufacturing method. A first testing terminal is connected to a gate electrode of a first TFT, a second testing terminal is connected to a source electrode of the first TFT and a drain electrode of a second TFT, a third testing terminal is connected to a gate electrode of the second TFT, and a fourth testing terminal is connected to a drain electrode of the first TFT and a source electrode of the second TFT. | 05-26-2016 |
| 20160154045 | SENSOR CIRCUIT, VEHICLE AND METHOD THEREFOR | 06-02-2016 |
| 20160178665 | FAULT DETECTION FOR A FLEXIBLE PROBE TIP | 06-23-2016 |
| 20160202310 | Method for Testing Embedded Systems | 07-14-2016 |
| 20160252570 | TSV TESTING METHOD AND APPARATUS | 09-01-2016 |
| 20170234923 | DIAGNOSTIC CIRCUITRY FOR POWERED SENSOR MULTIPLE UNIQUE FAULTS DIAGNOSTICS AND RESISTIVE FAULT TOLERANT INTERFACE TO MICROPROCESSOR | 08-17-2017 |
| 20190146028 | On-Die Aging Measurements for Dynamic Timing Modeling | 05-16-2019 |
