Entries |
Document | Title | Date |
20080201680 | DESIGNING APPARATUS, DESIGNING METHOD, AND PROGRAM - An apparatus, method, and program for designing a semiconductor device having a storage unit configured to a differential signal library for use in generation of a design data of a differential signal cell that receives or outputs differential signals. The apparatus includes a logic synthesis unit performing logic synthesis based on the differential signal library configured to the storage unit. The apparatus generates a netlist design data of the differential signal cell that receives or outputs the differential signals. | 08-21-2008 |
20080201681 | COMPUTER PROGRAM PRODUCTS FOR DETERMINING STOPPING POWERS OF DESIGN STRUCTURES WITH RESPECT TO A TRAVELING PARTICLE - A computer program product, comprising a computer usable medium having a computer readable program code embodied therein, said computer readable program code including an algorithm adapted to implement a method including the following steps. First, design information of the design structure is provided including a back-end-of-line layer of the integrated circuit which includes N interconnect layers, N being a positive integer. Next, each interconnect layer of the N interconnect layers is divided into multiple pixels. Next, a first path of a traveling particle in a first interconnect layer of the N interconnect layers is determined. Next, M path pixels of the multiple pixels of the first interconnect layer on the first path of the traveling particle are identified, M being a positive integer. Next, a first loss energy lost by the traveling particle due to its completely passing through a first pixel of the M path pixels is determined. | 08-21-2008 |
20080222590 | Method and System for Building Binary Decision Diagrams Optimally for Nodes in a Netlist Graph Using Don't-Caring - An improved method, system and computer-readable medium for constructing binary decision diagrams for a netlist graph is disclosed. The method comprises traversing a netlist graph in a depth-first manner. At least one binary decision diagram is built for one input of a node of the netlist graph using a binary decision diagram for the other input of that node as a don't-care condition. | 09-11-2008 |
20080222591 | SIGNAL CONNECTION PROGRAM, METHOD, AND DEVICE OF HIERARCHICAL LOGIC CIRCUIT - Information of a logic circuit including a hierarchical structure and connection target information up to a connection target including a pin or a net via hierarchies of the logic circuit are read, and a tree structure in which a hierarchy is taken as a node and a connection target is taken as a leaf is produced. The tree structure is referred from its root, and a node from which the tree branches is set to an uppermost node. A leaf the connection target of which is a net is searched from the tree structure, and a hierarchy port or a net in a lower hierarchy is added as a leaf to a lower hierarchy node connected with a net via a hierarchy port. Connection processing is performed to the tree structure from bottom up and the information on the logic circuit is rewritten, and the logic circuit information is outputted. | 09-11-2008 |
20080229268 | Trace optimization in flattened netlist by storing and retrieving intermediate results - A method of trace optimization in a flattened netlist of a circuit is disclosed. The method generally includes the steps of (A) generating a first total result by tracing a first path through the flattened netlist, (B) writing an intermediate result in a memory, the intermediate result characterizing a module having a plurality of instances in the circuit, (C) adding the intermediate result as read from the memory to the first total result upon crossing each of the instances of the module along the first path and (D) writing the first total result into the memory. | 09-18-2008 |
20080229269 | DESIGN STRUCTURE FOR INTEGRATING NONVOLATILE MEMORY CAPABILITY WITHIN SRAM DEVICES - A design structure embodied in a machine readable medium used in a design process includes a nonvolatile static random access memory (SRAM) device, including a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data; and a pair of magnetic spin transfer devices coupled to opposing sides of the storage cell; wherein the magnetic spin transfer devices are configured to retain the storage cell data therein following removal of power to the SRAM device, and are further configured to initialize the storage cell with the retained data upon application of power to the SRAM device. | 09-18-2008 |
20080229270 | Design Structure for a Duty Cycle Correction Circuit - A design structure for a Duty Cycle Correction (DCC) circuit is provide in which pairs of field effect transistors (FETs) in known DCC circuit topologies are replaced with linear resistors coupled to switches of the DCC circuit such that when the switch is open, the input signal is routed through the linear resistors. The linear resistors are more tolerant of process, voltage and temperature (PVT) fluctuations than FETs and thus, the resulting DCC circuit provides a relatively smaller change in DCC correction range with PVT fluctuations than the known DCC circuit topology that employs FETs. The linear resistors may be provided in parallel with the switches and in series with a pair of FETs having relatively large resistance values. The linear resistors provide resistance that pulls-up or pulls-down the pulse width of the input signal so as to provide correction to the duty cycle of the input signal. | 09-18-2008 |
20080244494 | MIGRATION OF INTEGRATED CIRCUIT LAYOUT FOR ALTERNATING PHASE SHIFT MASKS - Method, system and program product for migrating an integrated circuit (IC) layout for, for example, alternating aperture phase shift masks (AltPSM), are disclosed. In order to migrate a layout to phase compliance, jogs are identified on a first (AltPSM) layer and shifted to another second layer. Isolated or clustered jogs are shifted into an open channel portions on the second layer where possible. Remaining clustered jogs are shifted into as few new channels as possible on the second layer. The jog removal process leaves unidirectional wires that can be trivially phase colored. Standard technology migration techniques are then used to legalize the results on the layers. | 10-02-2008 |
20080244495 | METHOD OF DETERMINING WIRE PATTERN ON BOARD AND BOARD DESIGNED BY THE METHOD - A method of determining a wire pattern | 10-02-2008 |
20080263493 | Method and Apparatus for Tie Net Routing - A method of performing tie net routing within an integrated circuit chip is disclosed without using wiring. Due to repeated use of designs in modern chip, there are often unused portions of the design that need to be connected permanently to a local logical1 or logical 0. These connections, known as tie nets, are not timing critical signals that, when poorly implemented can get in the way of functional signals in an integrated circuit. The current method is to connect the pin to the nearest power connections of the correct polarity. This requires some amount of wiring resources that may be needed for other functions or pin access. Accordingly, the present invention avoids this situation by avoiding wiring. | 10-23-2008 |
20080263494 | Power supply wiring structure - Provided is a power supply wiring structure which comprises a first and a second power supply wirings, which are disposed on different planes to cross each other two-dimensionally. The first and second power supply wirings are interlayer-connected by a first via at a crossing area where those power supply wirings cross each other. An extension wiring which is formed by partially extending from the crossing area along a wiring extending direction of other power supply wiring is provided at least to either the first power supply wiring or the second power supply wiring. The extension wiring and either the first power supply wiring or the second power supply wiring, which are disposed on a different plane from the extension wiring to face the extension wiring, are interlayer-connected by a second via. Thereby, generation of electro migration can be suppressed. | 10-23-2008 |
20080263495 | Software product for semiconductor device design - A software product including codes for the method of determining parasitic resistance and capacitance from a layout of an LSI is executed by a computer. The method is achieved by providing a plurality of patterns of a wiring structure which contains a target interconnection; and by producing a library configured to store parameters indicating the parasitic resistance and the parasitic capacitance in relation to the target interconnection to each of the plurality of patterns. The producing is achieved by calculating the parameters to a plurality of conditions corresponding to deviation in manufacture of the wiring structure for each of the plurality of patterns. | 10-23-2008 |
20080270966 | METHOD AND SYSTEM FOR UNFOLDING/REPLICATING LOGIC PATHS TO FACILITATE MODELING OF METASTABLE VALUE PROPAGATION - A net of an integrated circuit design is analyzed by unfolding paths on the receive side of an asynchronous boundary to facilitate modeling of the propagation of a metastable value from a receive latch to sinks of the net. The paths are unfolded by replicating combinational logic and wiring along the coincident portions to form non-intersecting, separate paths from the receive latch to two or more sinks. Common data or control inputs are provided for the gates in the replicated combinational logic. Driver logic may additionally be inserted along each replicated path, upstream of the combinational logic, to independently drive each of the sinks. | 10-30-2008 |
20080270967 | Net list producing device producing a net list with an interconnection parasitic element by hierarchical processing - A memory cell information producing unit obtains physical terminal coordinates, physical terminal names and logical terminal names of a memory cell and layout data, and operates based on them to specify parasitic elements parasitic on interconnections of the memory cell, and to produce memory cell information including the physical terminal names and representing physical properties and a connection relationship of inner elements of the memory cell and the parasitic elements. Memory cell array information producing unit obtains connection information determining the connection relationship of physical terminals of the memory cell, assigns node names to the physical terminals of the memory cell based on the connection information, and produces memory cell array information representing the node names of all the memory cells. A memory cell array net list producing unit produces a net list of the memory cell array formed of the memory cell information and the memory cell array information. | 10-30-2008 |
20080295055 | Routing analysis method, logic synthesis method and circuit partitioning method for integrated circuit - The present invention relates to a routing analysis method for performing a routing analysis on an integrated circuit from a netlist which is information on a plurality of cells constituting the integrated circuit and routes connecting the cells, and the routing analysis method comprises a step (Step | 11-27-2008 |
20080301615 | Focused ion beam defining process enhancement - Embodiments employ a method to define points on selected nets in a netlist for a focused ion beam (FIB) to create open circuits. A selected net is partitioned into a set of sub-segments, and after considering all metal layers at and above that of the selected net, a subset of the set of sub-segments is formed as those sub-segments having minimum distances from the considered metal layers greater than some threshold. All contiguous sub-segments in the subset of the set of sub-segments are grouped into groups. The midpoints of such groups, and any isolated sub-segments, are possible candidate for FIB points. For some embodiments, the midpoint of the longest (or one of the longest) groups of sub-segments is chosen as the FIB point for the selected net. Other embodiments are described and claimed. | 12-04-2008 |
20080301616 | Layout Generator for Routing and Designing an LSI - According to the present invention an automated layout generator is provided for routing and designing an LSI (Large Scale Integrated Circuit). First, at least one generic of an instance of a book to be connected is located on the chip, wherein a generic of an instance is an area defined according to the measurements of said instance. Then, an initial route to said instance is generated by optimizing the route to the corresponding generic according to given design rules. Thereby, an optimized pin location is determined for said instance. Then, on the basis of said optimized pin location a layout for said instance is generated in place of the corresponding generic. Finally, the actually generated pin is connected with the corresponding end of the initial route. | 12-04-2008 |
20080301617 | COMPUTER READABLE RECORDING MEDIUM WITH A WIRING DESIGN PROGRAM STORED THEREON AND WIRING DESIGN DEVICE - An apex is extracted from a designed wiring layout. In start/end portion circular arc processing a circular arc is added to the apex-containing portion, and the layout data file is rewritten so that a portion, representing a region surrounded by circular arc and two lines, is added to the wiring line. In bend portion circular arc processing circular arcs are added to the respective apex-containing portions, and the layout data file is rewritten so that: a portion corresponding to a region surrounded by the circular arc and two lines is added to the apex-containing portion of the layout when the determined angle is less than 180 degrees; a portion corresponding to a region surrounded by the circular arc and two lines is removed from the apex-containing portion of the layout when the determined angle exceeds 180 degrees. | 12-04-2008 |
20080307382 | COMBINATION OF GROUND DEVICES IN WIRING HARNESS DESIGNS - A method can include allowing a user to place a first wiring harness design component within a wiring harness topology in a wiring harness design workspace, allowing the user to place a first plurality of ground devices within the first wiring harness design component placed in the wiring harness topology, allowing the user to request an automatic ground combination, and, in response to the user requesting an automatic ground combination, automatically applying at least one electronically stored ground combination rule to a first set of ground devices comprising a plurality of the first plurality of ground devices and automatically combining at least two of the first set of ground devices into a first combined ground device based at least in part on the applied at least one electronically stored ground combination rule. | 12-11-2008 |
20080320431 | POWER MESH FOR MULTIPLE FREQUENCY OPERATION OF SEMICONDUCTOR PRODUCTS - The design of integrated circuits, i.e., semiconductor products, is made easier with a semiconductor platform having versatile power mesh that is capable of supporting simultaneous operations having different frequencies on the semiconductor product; e.g., higher frequency operations may be embedded as diffused blocks within the lower layers or may be programmed from a configurable transistor fabric above the diffused layers. Preferably the power mesh is located above the layers having the operations requiring the different frequencies, and may be fixed in an application set given to a chip designer or may be configurable by the designer her/himself. For example, to support high speed communications adjacent an embedded high speed data transceiver, the transistor fabric may be programmed as a data link layer having higher performance requirements than the rest of the integrated circuit. The data link layer may be connected to one of the localized grids of the versatile power mesh which may have an increased density and/or wider strap width of a power/ground grid. Additional decoupling capacitance can be embedded in the lower layers of the semiconductor product and/or can be programmed from the configurable transistors fabric. | 12-25-2008 |
20090007047 | Design Structure for a Phase Locked Loop with Stabilized Dynamic Response - A design structure for a hybrid phase locked loop (PLL) circuit that obtains stabilized dynamic response and independent adjustment of damping factor and loop bandwidth is provided. The hybrid PLL circuit of the illustrative embodiments includes the resistance/capacitance (RC) filter elements of a conventional RC PLL and the feed-forward path from the output of the phase frequency detector to the voltage controlled oscillator (VCO). The hybrid PLL essentially enhances the performance of the conventional feed-forward PLL by providing the RC filter whose components can be weighted to provide a dynamic response that is significantly less sensitive to parameter variation and which allows loop bandwidth optimization without sacrificing damping. | 01-01-2009 |
20090007048 | DESIGN STRUCTURE FOR A COMPUTER MEMORY SYSTEM WITH A SHARED MEMORY MODULE JUNCTION CONNECTOR - A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a memory module system and DIMM connector is provided. A DIMM connector includes a plurality of DIMM sockets for receiving a corresponding plurality of DIMMs in a radially oriented, angularly spaced orientation. The DIMM sockets are connected in parallel at a memory module junction so that socket terminals of each DIMM socket are joined to the same relative terminal of all the other DIMM sockets along electronic pathways of substantially equal length. A memory controller selectively communicates with the DIMMs via the DIMM junction. By virtue of the improved topology, impedance within the DIMM connector may be better matched to minimize reflections and improve signal quality. | 01-01-2009 |
20090019415 | STAGE MITIGATION OF INTERCONNECT VARIABILITY - The present invention provides a method, system and program product for mitigating effects of interconnect variability during a design stage of a chip. Under the technique of the present invention, a global and detailed routing of interconnects of the chip are determined. Thereafter, a dummy fill estimation and a grid based metal density estimation are performed. Then, based on a CMP model, a variable map of metal thicknesses is obtained. Based on the variable map, wiring nets of the chip that are sensitive to metal variability (e.g., that fail to meet timing closure due to metal thickness loss/gain in the CMP process) are identified. These wiring nets are then re-routed for optimization of the chip. | 01-15-2009 |
20090031274 | Computer Readable Medium, System and Associated Method For Designing Integrated Circuits With Loop Insertions - A computer readable medium, system and associated method is provided for designing an integrated circuit with inserted loops. The method comprises the steps of inserting a loop with tagged wire segments and/or vias in a fully routed and DCR clean integrated circuit; performing a DRC; and fixing DRC violations by removing tagged wire segments and/or vias which contribute to a violation. | 01-29-2009 |
20090055791 | PROCESS AND APPARATUS FOR ADJUSTING TRACES - Traces routed through a computer depiction of a routing area of an electronics system comprise a plurality of connected nodes. Forces are assigned to the nodes, and the nodes are moved in accordance with the forces. The forces may be based on such things as the proximity of the nodes to each other and to obstacles in the routing area. This tends to smooth, straighten and/or shorten the traces, and may also tend to correct design rule violations. | 02-26-2009 |
20090064079 | Apparatus and method for circuit layout - An apparatus, includes a search unit which searches a critical signal path from a plurality of candidate signal paths connecting a first terminal and a second terminal, the critical signal path including the most strict delay limit in the plurality of candidate signal paths, and a display control unit which controls a display device for displaying an information regarding to a circuit element, the circuit element including the critical signal path. | 03-05-2009 |
20090070725 | Method and system for manufacturing a semiconductor device having plural wiring layers - A software product including codes for the method of determining parasitic resistance and capacitance from a layout of an LSI is executed by a computer. The method is achieved by providing a plurality of patterns of a wiring structure which contains a target interconnection; and by producing a library configured to store parameters indicating the parasitic resistance and the parasitic capacitance in relation to the target interconnection to each of the plurality of patterns. The producing is achieved by calculating the parameters to a plurality of conditions corresponding to deviation in manufacture of the wiring structure for each of the plurality of patterns. | 03-12-2009 |
20090077520 | Method and System for Representing Manufacturing and Lithography Information for IC Routing - A mechanism to compress manufacturing awareness into a small representation and to enable the router to consult the representation without performing, or understanding, detailed process analysis, is disclosed. | 03-19-2009 |
20090077521 | Method and System for Representing Manufacturing and Lithography Information for IC Routing - A mechanism to compress manufacturing awareness into a small representation and to enable the router to consult the representation without performing, or understanding, detailed process analysis, is disclosed. | 03-19-2009 |
20090077522 | METHOD AND APPARATUS FOR ROUTING WITH INDEPENDENT GOALS ON DIFFERENT LAYERS - Some embodiments of the invention provide a method of routing. The method selects a net with a set of routable elements in a multi-layer layout region. In some embodiments, the method identifies a route for the net based on different congestion goals on different layers. In other embodiments, the method identifies a route for the net based on different congestion goals between different layer pairs. In some embodiments, the method identifies a route for the net based on both the different congestion goals on different layers and between different layer pairs. | 03-19-2009 |
20090083689 | GRIDDED-ROUTER BASED WIRING ON A NON-GRIDDED LIBRARY - A computerized method for automatically generating a grid-based derivative of a non-gridded cell library of an integrated circuit design comprises the step of determining at least one valid position of at least one wiring element of a circuit of the first cell library, wherein the at least one valid position fulfills all technological design rules and wherein the at least one valid position fits into the second grid format. The method can also be used for automatically transforming a first cell library of an integrated circuit design having a first grid format into a second cell library having a second grid format or for automatically analyzing a grid-based cell library of an integrated circuit design in view of the circuit quality regarding technical design rules. | 03-26-2009 |
20090094570 | Configurable Asic-based Sensing Circuit - A sensing circuit based on an application-specific integrated circuit (ASIC) sensor which includes a sensor portion and a processor portion which are integrated on an ASIC. The sensor portion outputs raw output in response to a stimulus. The output of the sensor portion is processed by the processor portion. The sensor portion and the processor portion together form at least two blocks which are configurable together by interconnections in two or more ways to produce differentiated sensing products. | 04-09-2009 |
20090106726 | DESIGN STRUCTURES INCLUDING MEANS FOR LATERAL CURRENT CARRYING CAPABILITY IMPROVEMENT IN SEMICONDUCTOR DEVICES - A design structure including a semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface. | 04-23-2009 |
20090106727 | METHODS AND SYSTEMS FOR LAYOUT AND ROUTING USING ALTERNATING APERTURE PHASE SHIFT MASKS - A method of laying out features for alternating aperture phase shift masks. The method includes defining features on a grid of a uniform basic pitch, orienting the features such that those of the features defined, at least in part, by phase shifting shapes are oriented along a primary direction, and spacing two features terminating adjacent one another such that the two features have space between them sufficient to prevent phase conflicts if both of the two features are defined, at least in part, by phase shifting shapes. | 04-23-2009 |
20090106728 | ROUTING METHODS FOR INTEGRATED CIRCUIT DESIGNS - Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time. | 04-23-2009 |
20090113371 | ROUTING INTERCONNECT OF INTEGRATED CIRCUIT DESIGNS - Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time. | 04-30-2009 |
20090113372 | INTERCONNECT ROUTING METHODS OF INTEGRATED CIRCUIT DESIGNS - Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time. | 04-30-2009 |
20090132988 | POWER MESH ARRANGEMENT METHOD UTILIZED IN AN INTEGRATED CIRCUIT HAVING MULTIPLE POWER DOMAINS - The invention discloses a power mesh arrangement method utilized in an integrated circuit having multiple power domains. The arrangement method includes: forming a first partial local power mesh according to a position of a first power domain; forming a second partial local power mesh according to a position of a second power domain; forming a global power mesh, utilized for providing powers needed by the first and the second power domains; coupling the first partial local power mesh to the global power mesh and the first power domain; and coupling the second partial local power mesh to the global power mesh and the second power domain. | 05-21-2009 |
20090144688 | Systems and Methods for Probabilistic Interconnect Planning - Systems and methods for interconnect planning which utilize probabilistic methodologies. One embodiment comprises a method for planning interconnect models in an integrated circuit design. Nets and a set of interconnect models that can be used to connect the pins of each net are first defined. For each net, the probability that each interconnect model will be used to connect the pins of the net is evaluated. Tiles in the integrated circuit design are then assigned probabilities indicating the likelihood that each of the interconnect models will traverse the tiles. A map is then generated to indicate probabilistic routing characteristics (e.g., probabilities of wire congestion, interconnect component congestion, power densities, interconnect model usage) based on the probabilities assigned to each of the tiles in the integrated circuit design. The map may then be output (e.g., printed or otherwise displayed) to a user or stored for later use. | 06-04-2009 |
20090150848 | Topologies and Methodologies for AMS Integrated Circuit Design - A tool for analog and mixed signal circuits includes a unit enabling a user to identify one or more critical interconnect lines in a chip architecture and one or more selectable, predefined topologies for said critical interconnect lines. Each topology includes one or more signal wires and a current return path. A majority of the electric field lines are contained within the boundary of the topology. The invention also includes a method for designing analog and mixed signal (AMS) integrated circuits (IC), including defining a chip architecture and a floor plan, identifying one or more critical interconnect lines and selecting pre-designed transmission line topologies for the critical interconnect lines. | 06-11-2009 |
20090164963 | SYSTEM AND METHOD FOR ROUTING CONNECTIONS - A method for modeling a circuit includes receiving a netlist that defines a plurality of connections between a plurality of circuit elements and identifying a subset of the connections. The method also includes routing the identified connections with a first group of wires having a first wire width and routing at least a portion of the remaining connections with a second wire width. The second wire width is smaller than the first wire width. The method further includes replacing the first group of wires with a third group of wires having the second wire width. | 06-25-2009 |
20090187872 | INTEGRATED CIRCUIT DEVICES AND METHODS AND APPARATUSES FOR DESIGNING INTEGRATED CIRCUIT DEVICES - Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed. | 07-23-2009 |
20090193379 | INTEGRATED CIRCUIT DEVICES AND METHODS AND APPARATUSES FOR DESIGNING INTEGRATED CIRCUIT DEVICES - Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed. | 07-30-2009 |
20090193380 | INTEGRATED CIRCUIT DEVICES AND METHODS AND APPARATUSES FOR DESIGNING INTEGRATED CIRCUIT DEVICES - Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed. | 07-30-2009 |
20090193381 | POWER MESH MANAGEMENT METHOD - The invention discloses a power mesh management method utilized in an integrated IC. The integrated circuit includes a macro block including at least a macro block power supplying line growing along a first direction. The management method includes: defining a plurality of first power supplying lines located in a metal layer above the macro block, wherein each of the first supplying lines grows along the first direction; defining a plurality of second power supplying lines located in another metal layer above the macro block, wherein each of the second supplying lines grows along a second direction; defining a partial power supplying line from the plurality of first power supplying lines where the partial power supplying line overlaps the macro block power supplying line; and removing the partial power supplying line from the plurality of first power supplying lines. | 07-30-2009 |
20090210847 | SYNCHRONOUS TO ASYNCHRONOUS LOGIC CONVERSION - Apparatus, systems, and methods may operate to generate a synchronous netlist from a synchronous circuit design representation, automatically substitute asynchronous components taken from an asynchronous standard cell component library for corresponding standard cell synchronous components in the synchronous netlist to form an asynchronous core, and convert the synchronous netlist to an asynchronous circuit design representation. Additional apparatus, systems, and methods are disclosed. | 08-20-2009 |
20090210848 | LOGIC ARRAY DEVICES HAVING COMPLEX MACRO-CELL ARCHITECTURE AND METHODS FACILITATING USE OF SAME - Logic array devices having complex macro-cell architecture and methods facilitating use of same. A semiconductor device comprising an array of logic cells and programmable metal includes gate structures that are pre-wired, where, inputs and/or outputs are available for routing in programmable metal, possibly as part of a hybrid process. The device can also include selectable, in-line inverters, which can share the input/output tracks with logic inputs. A bubble-pushing algorithm can take advantage of the selectable in-line inverters to reduce the number of inverters in a design. In some embodiments, an embedded clock line is common to a plurality of logic cells. The clock line is terminated in a clock cell, which can include test logic, so that a clock group is formed. Flexibility to power down cells, or groups of cells can be provided by power traces with programmable connections. | 08-20-2009 |
20090217229 | Wire Structures Minimizing Hostile Neighbors and Coupling Affects - A method for minimizing coupling capacitance between wires in a bus that is shifting by way of rearranging the order of said wires in said bus so that, aside from said first and last wires in said arrangement, the coupling capacitance across said bus is uniform and minimized relative to the original arrangement. Alternatively, a method for minimizing coupling capacitance between wires in a bus that is shifting by way of rearranging the order of said wires in said bus so that, aside from said first and last wires in said arrangement, one of said wires incurs the smallest possible amount of coupling capacitance and then the coupling capacitance across the rest of said wires in said bus gets progressively worse relative to the original arrangement. | 08-27-2009 |
20090254875 | PROACTIVE ROUTING SYSTEM AND METHOD - There is provided a proactive routing system and method. In some embodiments, the method includes determining slack for a net in a netlist, applying a routing condition to the net, calculating an extra delay related to the routing condition, determining a criticality of the net considering the extra delay and the determined slack, and setting a soft constraint based at least partially on the criticality. | 10-08-2009 |
20090265677 | INTEGRATED TEST WAVEFORM GENERATOR (TWG) AND CUSTOMER WAVEFORM GENERATOR (CWG), DESIGN STRUCTURE AND METHOD - Disclosed are embodiments of a clock generation circuit, a design structure for the circuit and an associated method that provide deskewing functions and that further provide precise timing for both testing and functional operations. Specifically, the embodiments incorporate a deskewer circuit that is capable of receiving waveform signals from both an external waveform generator and an internal waveform generator. The external waveform generator can generate and supply to the deskewer circuit a pair of waveform signals for functional operations. The internal waveform generator can be uniquely configured with control logic and counter logic for generating and supplying a pair of waveform signals to the deskewer circuit for any one of built-in self-test (BIST) operations, macro-test operations, other test operations or functional operations. The deskewer circuit can selectively gate an input clock signal with the waveform signals from either the external or internal waveform generator in order to generate the required output clock signal. | 10-22-2009 |
20090276749 | GATE MODELING FOR SEMICONDUCTOR FABRICATION PROCESS EFFECTS - In one embodiment, a method for determining a contour simplification of an object for a simulation is provided. An object in a layout of a transistor design to be created with the photolithographic process is determined. The object includes a width and a length in the layout. A contour simulation is performed to determine a generated contour object. The contour simulation simulates parametric variation factors that may occur in the photolithographic process. An adjusted width and adjusted length of the object is then determined based on the generated contour object. The adjusted width and the adjusted length are usable to determine a parametric model for simulation of the object. For example, a layout versus schematic (LVS) tool may back-annotate the layout. Then, a SPICE simulation may use the output of the LVS tool to verify the electrical behavior of the transistor using the adjusted width and adjusted length. | 11-05-2009 |
20090288055 | Method and system for characterizing an integrated circuit design - A method and a system for characterizing an integrated circuit (IC) design are disclosed. The method includes receiving a description of leaf cells used in the IC design. The IC design is described in a high-level language by using the description of the leaf cells. The description of the IC design includes specifying placement of the leaf cells and specifying connectivity between them. Further, the method includes extracting a circuit netlist file based on the physical layout of the IC design. The instructions are defined in the high-level language to perform simulations on the extracted circuit netlist file. These simulations are performed on the circuit netlist file to determine the values of the design parameters. Furthermore, the method includes providing the values of the design parameters of the IC design in a pre-defined output format based on the simulations. | 11-19-2009 |
20090288056 | Method, system and computer program product for determining routing of data paths in interconnect circuitry - A system, method and computer program product are provided for determining routing of data paths in interconnect circuitry for an integrated circuit. The interconnect circuitry on a first side provides a narrow interface for connection to a first device, and on a second side provides a wide interface for connection to a distributed plurality of further devices. Each data path is associated with one of the further devices and provides a connection through the interconnect circuitry between that associated further device and the first device. The method comprises the steps of defining a plurality of cells to be provided along the wide interface, each of the further devices being associated with at least one of the cells, and defining the interconnect circuitry as an array of blocks formed in rows and columns, with each cell abutting one of the columns. Further, the method includes the steps of providing a predetermined set of tiles, each tile providing a predetermined wiring layout, and for each block, applying predetermined rules to determine one of the tiles to be used to implement that block. The predetermined rules take into account the location of the block in the array and the association between the plurality of further devices and the plurality of cells, ensuring that each data path provided by the interconnect circuitry has the same propagation delay. By such an approach, a structured routing method is provided that uses predetermined tiles enabling a layout design for the interconnect circuitry to be readily produced whilst ensuring that the propagation delays are matched for each of the data paths within the interconnect circuitry. | 11-19-2009 |
20090307648 | THROUGH-HOLE LAYOUT APPARATUS THAT REDUCES DIFFERENCES IN LAYOUT DENSITY OF THROUGH-HOLES - A through-hole layout apparatus includes: an extractor extracting an existing through-hole from design data for a semiconductor integrated circuit; a calculator calculating, for each through-hole extracted by the extractor, a layout density of through-holes in a predetermined region; a selector selecting a through-hole at the center of a predetermined region where the layout density is lower than a predetermined value as a target through-hole from among the through-holes extracted by the extractor; and a through-hole adder determining, for each target through-hole selected by the selector, a given position in a predetermined region centered on the target through-hole as a placement position at which a through-hole is to be added. | 12-10-2009 |
20090313596 | System and Method for Integrated Circuit Planar Netlist Interpretation - Systems and methods for integrated circuit planar netlist interpretation are disclosed. In one embodiment, higher abstraction level descriptions of an integrated circuit are generated from a planar netlist and layout data of the integrated circuit. Various embodiments may derive the higher abstraction levels through, for example, netlist compression and netlist partitioning. Other embodiments may derive the higher abstraction levels using, for example, device and module hypothesis search functions based on device properties and design constraints derived from netlist and layout data. | 12-17-2009 |
20090327989 | Statistical Interconnect Corner Extraction - Various implementations of the invention provide methods and apparatuses that consider various inter/intra-die variations. In various implementations, a statistical parameter dimension reduction using linear reduced rank regression (RRR) is applied to dramatically reduce the high-dimensional variation sources while accurately capturing their impact on the resultant performance corners. With various implementations of the invention, an application specific corner finding algorithm is employed, the algorithm comprising timing metrics and an iterative output clustering operation. | 12-31-2009 |
20090327990 | Integrated Circuit Routing and Compaction - An iterative technique is used to automatically route nets and alter spacing of an integrated circuit design to achieve a fully routed and compact result. After identifying cells rows and channel, which are gaps between the rows, the technique determines which nets should be routed in which areas. Spine routing is used for nets than span more than one row or channel. Alter the space between rows, larger or smaller, which will allow routing of the nets. | 12-31-2009 |
20100017773 | Method for Minimizing Impact of Design Changes For Integrated Circuit Designs - A method is provided for updating an existing netlist to reflect a design change. A design incorporating the design change and the existing netlist are provided to a synthesis tool. The design and the existing netlist are processed with the synthesis tool reusing logic structures from the existing netlist. A result is generated by the synthesis tool including the existing netlist and a new portion of a netlist reflecting the design change. | 01-21-2010 |
20100023912 | LEAD FRAME DESIGN SUPPORT APPARATUS AND LEAD FRAME DESIGN SUPPORT METHOD - A lead frame design support apparatus and method include measuring a signal waveform transition time, calculating a distributed parameter unit length based on the transition time measured, calculating a division number for a lead frame by dividing the lead frame by the distributed parameter unit length calculated, and determining a respective line width for each lead frame divided by the division number calculated, based on a signal waveform quality. | 01-28-2010 |
20100037197 | Method and apparatus for integrated circuit design - An integrated circuit design method includes: obtaining layout data of an integrated circuit; and updating the layout data to modify the layout of the integrated circuit. In updating the layout data, a first via placed on an interconnection is replaced with a plurality of second vias having a size smaller than that of the first via. The positions of the via origin points of the second vias on the interconnection is different from the position of the via origin point of the first via on the interconnection. | 02-11-2010 |
20100042964 | REUSE OF CIRCUIT LABELS IN SUBCIRCUIT RECOGNITION - Method, apparatus and system for finding instances of a pattern in a main netlist include reading in the main netlist and the pattern that is used for finding pattern matches in the main netlist. The main netlist and the pattern include a plurality of vertices. Each of the vertices is a device or a net. Labels for the vertices are computed in both the pattern and the main netlist up to a depth appropriate for the pattern. A vertex of the pattern is identified and used in matching with one or more vertices in the main netlist at the depth appropriate for the pattern using the computed labels. The computed labels for each of the vertices of the main netlist are stored for possible reuse in subsequent pattern matches. | 02-18-2010 |
20100050145 | Optimizing a Netlist Circuit Representation by Leveraging Binary Decision Diagrams to Perform Rewriting - Leveraging existing Binary Decision Diagrams (BDDs) to enhance circuit reductions in a system model representing a state machine as a netlist. The netlist is evaluated to determine the regions with the greatest potential reductions. BDD sweeping is performed to identify redundancies in the netlist. BDD rewriting implements the circuit reductions by replacing gates of the original netlist with more efficient equivalent logic. | 02-25-2010 |
20100050146 | METHOD AND SYSTEM FOR ROUTING - Disclosed is a method, system, and computer program product for routing, modeling routes, and measuring congestion. In some embodiments, Gcells are implemented with reduced number of nodes to facilitate route modeling and congestion measurement. Some embodiments are particularly suitable for direct congestion and routing analysis of diagonal routing paths. In this way, congestion analysis can be directly performed along diagonal boundaries for diagonal routes, without requiring association with Gcell boundaries on Manhattan routing layers. | 02-25-2010 |
20100058270 | Hierarchy Reassembler for 1xN VLSI Design - Embodiments that reassemble hierarchical representations in a closed-loop 1×N system are disclosed. Some embodiments comprise creating a flat netlist from a hierarchical representation of a 1×N building block, creating attributes for the flat netlist, and altering one or more elements of the flat netlist, such as by an operation of a logic design tool, a synthesis tool, a physical design tool, or a timing analysis tool. The embodiments further comprise generating a second hierarchical representation of the 1×N building block that reflects the altered element. Further embodiments comprise an apparatus having a 1×N compiler and a reassembler. The 1×N compiler may create attributes for a flat netlist of elements of a hierarchical representation of a 1×N building block. The reassembler may use the attributes to create a second hierarchical representation of the 1×N building block that reflects alteration of elements to the flat netlist. | 03-04-2010 |
20100058271 | Closed-Loop 1xN VLSI Design System - Embodiments that design integrated circuits using a closed loop 1xN methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1xN building blocks. The embodiments may alter elements of the 1xN building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a viewer and a 1xN compiler. The viewer may generate displays of behavioral representations of 1xN building blocks, with the behavioral representations comprising RTL definitions. The 1xN compiler may create physical design representations of the 1xN building block and create behavioral representations from the physical design representations, wherein the physical design representations have elements altered by one or more tools of a tool suite. | 03-04-2010 |
20100058272 | Compiler for Closed-Loop 1xN VLSI Design - Embodiments that design integrated circuits using a 1×N compiler in a closed-loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a first generator to generate a behavioral representation of a design for an integrated circuit, a second generator to generate a logical representation of the design, and a third generator to generate a physical design representation of the design, wherein the representation generators may create updated versions of the representations which reflect alterations made to 1×N building block elements. | 03-04-2010 |
20100058273 | Automatic Wiring Device, Automatic Wiring Method, and Automatic Wiring Program - An automatic wiring method includes calculating a metal area within an integrated circuit, and determining whether the metal area calculated at the calculating is smaller than a minimum metal area as a predetermined threshold value. | 03-04-2010 |
20100077372 | Apparatus, Method and Computer Program Product for Fast Stimulation of Manufacturing Effects During Integrated Circuit Design - Methods, apparatus and computer program products provide a fast and accurate model for simulating the effects of chemical mechanical polishing (CMP) steps during fabrication of an integrated circuit by generating a design of an integrated circuit; while generating the design of the integrated circuit, using a simplified model to predict at least one physical characteristic of the integrated circuit which results from a CMP processing step to be used during manufacture of the integrated circuit, wherein the simplified model is derived from simulations performed prior to the design generation activities using a comprehensive simulation program used to model the physical characteristic; predicting performance of the integrated circuit using the predicted physical characteristic; and adjusting the design of the integrated circuit in dependence on the performance prediction. | 03-25-2010 |
20100077373 | WIRING INFORMATION GENERATING APPARATUS, METHOD AND PROGRAM - A wiring information generating apparatus includes an input unit that inputs a wiring layer number indicating a wiring layer, a via layer number indicating a next via layer to connect the wiring layer, and spacing information based on wiring rules. A storage unit stores a terminal figure table providing terminal figures, a logic element device wire protected area table, and a wire protected area table. A wire protected area creation unit adds an area of a terminal figure and a logic element device wire protected area obtained by searching the terminal figure table and the logic element device wire protected area table based on the input wiring layer number and/or via layer number and acquires wire layer-via layer spacing information. A wiring information generating unit generates wiring information in the wiring layer based on connection information and arrangement information of the semiconductor logic circuit, and wire protected area information. | 03-25-2010 |
20100115487 | METHOD AND SYSTEM FOR SCHEMATIC-VISUALIZATION DRIVEN TOPOLOGICALLY-EQUIVALENT LAYOUT DESIGN IN RFSiP - An improved approach for automatically generating physical layout constraints and topology that are visually in-sync with the logic schematic created for simulation is described. The present approach is also directed to an automatic method for transferring topology from logic design to layout. | 05-06-2010 |
20100115488 | CIRCUIT DESIGN DEVICE, CIRCUIT DESIGN METHOD, AND CIRCUIT DESIGN PROGRAM - A circuit design device comprises a logic synthesis unit that generates a circuit with reference to a circuit design description, a statistical timing analysis unit that obtains a probability distribution of delay times of a path in a circuit, a relative delay restriction fulfillment rate calculation unit that obtains a fulfillment rate of the relative delay restriction according to the probability distribution of the delay time from the same starting point at each restricted path subjected to the relative delay restriction, a path delay probability distribution changing unit that changes the probability distribution of delay times of the restricted path to changed probability distribution when the fulfillment rate does not reach a predetermined rate, and a logic circuit structure changing unit that changes the structure of the circuit so as to follow the changed probability distribution. | 05-06-2010 |
20100122230 | Method to Automatically Add Power Line in Channel Between Macros - In a particular embodiment, a method is disclosed that includes automatically adding a first power line in a channel between at least two macros when less than two system power supply lines with opposite polarities are detected within the channel. | 05-13-2010 |
20100146471 | FAST ROUTING OF CUSTOM MACROS - A system for creating layout and wiring diagrams for an integrated circuit (IC) includes a placement engine configured to receive a hierarchical schematic and to create a placed layout. The system also includes a flat layout engine configured to receive the hierarchical schematic and to create a flat layout and a back annotation engine coupled to the placement engine and the flat layout engine, the back annotation engine configured to receive the hierarchical placed layout and the flat unplaced layout and to create a flat placed layout there from. | 06-10-2010 |
20100169858 | Method and apparatus for performing parallel routing using a multi-threaded routing procedure - A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box. | 07-01-2010 |
20100175038 | Techniques for Implementing an Engineering Change Order in an Integrated Circuit Design - A technique for implementing an engineering change order (ECO) includes comparing a first hardware description language (HDL) design with a second HDL design. In this case, the second HDL design corresponds to the first HDL design with at least one implemented ECO. The technique identifies differences in latch points, primary inputs, and primary outputs between the first and second HDL designs. The second HDL design is converted to a non-optimized netlist. Logical cones (cones of logic) that feed the latch points, the primary inputs, and the primary outputs are extracted from the non-optimized netlist. Based on the extracted logical cones and the non-optimized netlist, a physical implementation of the second HDL design is synthesized. | 07-08-2010 |
20100175039 | INTEGRATED CIRCUIT DESIGN APPARATUS, DESIGN METHOD, AND STORAGE MEDIA - An integrated circuit design apparatus includes: a layout information storing unit which stores layout information of an integrated circuit; a scan path connection information storing unit which stores scan path connection information that indicates connection order of scan path terminals; a macro signal terminal position determination unit which determines temporary arrangement positions of a scan-in terminal and a scan-out terminal of each of a plurality of macros, and updates the layout information; an initial scan path route determination unit which updates the scan path connection information such that one of the plurality of macros arranged in a closest distance is connected in turn starting with the scan-in external terminal; and a scan path re-routing unit which determines a scan path connection order such that a scan path total wiring length becomes shortest, and updates the scan path connection information updated by the initial scan path route determination unit. | 07-08-2010 |
20100180249 | Chip-Scale Package Conversion Technique for Dies - A method is described for converting an existing die, originally designed for a non-chip-scale package, to a chip-scale package die, where the die's bonding pads are located in positions within a defined grid of candidate positions. In the first step, the die's layout, comprising its outer boundaries and areas needed to be electrically connected to bonding pads, are shifted relative to a grid of candidate positions for the bonding pads until an optimal alignment is identified. Bonding pads positions on the die are then selected corresponding to optimum grid positions within the outer boundaries of the die. The die is then fabricated using the original masks to form at least the semiconductor regions and using a new set of masks for defining the new locations of the bonding pads for the chip-scale package. The chip-scale package is then bonded to a PCB using chip-scale package technology. | 07-15-2010 |
20100199252 | ROUTABILITY OF INTEGRATED CIRCUIT DESIGN WITHOUT IMPACTING THE AREA - Improving the routability of integrated circuit (IC) design without impacting the area. A local region of congestion of an IC design is determined according to a design parameter. A cell with a specified level of complexity is identified within the local region of congestion. An alternative cell is algorithmically created with a same logic function as the cell by adding an access point to the alternative cell. The cell is then replaced with the alternative cell within the local region of congestion. | 08-05-2010 |
20100235802 | Customizable H-Tree Synthesis Tool - A computer program for generating an H-tree for an integrated circuit design stored on a computer readable medium includes code to receive from a user a set of parameters to configure the H-tree. The parameters include a starting segment length and an ending segment length. The computer program also includes code to select a starting location in the integrated circuit design. The computer program further includes code to place an anchor H at the starting location. The computer program further includes code to recursively place child Hs on the H-tree based on the starting segment length and the ending segment length to create a fan-out with equal weight on each child H. The number of levels of the H-tree is calculated according to a rounded down integer equal to a binary logarithm of a quotient of the starting segment length divided by the ending length. | 09-16-2010 |
20100235803 | Method and Apparatus for Automatically Connecting Component Interfaces in a Model Description - The Component Interface Definition Language (CIDL) disclosed in this document, along with the associated CIDL compiler, provides advantageous automation and simplification of the process of interconnecting components within modeled systems. In particular, the CIDL compiler automatically determines the correct connections to be made between the components represented within a CIDL source file. These automatic connection capabilities relieve the user from the burden of having to explicate the signal port connections to be made between various ones of the component interfaces represented in the CIDL source code. | 09-16-2010 |
20100251199 | Method and system for automated convergence of ternary simulation by saturation of deep gates - A method, system and computer program product for X-Saturated ternary simulation based reduction. An X-Saturated ternary simulation (XSTS) utility, which executes on a computer system, receives design information, where the design information includes a netlist. The XSTS utility initializes one or more data structures and/or variables and simulates, in a ternary fashion, the netlist at a time value by applying logical X values to all RANDOM gates of the netlist and to registers marked X_SATURATED. For each register of the netlist XSTS utility: determines whether or not the register departs from its expected prefix behavior, and if the register departs from its expected prefix behavior, the register is marked as X_SATURATED and the current state is updated with an X value upon the register. XSTS utility can store the current state in a data structure and can use the information from the data structure to simplify the design. | 09-30-2010 |