| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 716014000 | Detailed routing (e.g., channel routing, switch box routing) | 20 |
| 20080201683 | Method of Generating Wiring Routes with Matching Delay in the Presence of Process Variation - A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse. | 08-21-2008 |
| 20080244497 | On-chip decoupling capacitance and power/ground network wire co-optimization to reduce dynamic noise - A semiconductor power network ( | 10-02-2008 |
| 20080288907 | CROSSLINKING OF NETLISTS - In one embodiment, a method for determining crosslinking between netlists is provided. The first netlist and second netlist may have nets that have different net names but may be the same net. It is also possible that the content of individual nets in one list may need to be split or combined to accurately match the other list. Complete results will not be obtained if only 1 to 1 content matches are considered. The method determines an exploded list of one of the netlists, such as the second netlist, where the netlist is reversed such that the pins of the netlist are used as keys to an associated net name. A pin in the first netlist is then determined. The pin may be associated with a first net name in the first netlist. The pin is looked up in the exploded list using it as a key to determine a second net name for the pin. The process continues using each pin in the first netlist to determine the net name associated with the pin in the second netlist. When this process is finished, crosslinks between net names that match across netlists are determined. | 11-20-2008 |
| 20090024976 | Method for Automatically Routing Multi-Voltage Multi-Pitch Metal Lines - A method for program routing a circuit with at least a first and second voltages in a single layer is disclosed, which comprises defining a first and second layer types corresponding to the first and second voltages, respectively, specifying at least one first attribute for the first layer type and at least one second attribute for the second layer type, specifying at least one first net with a first voltage and at least one second net with a second voltage, reading the voltage information associated with the first net and the second net by a computer program, routing at least one first polygon for the first net onto the first layer type with the first attribute by the computer program, and routing at least one second polygon for the second net onto the second layer type with the second attribute by the same computer program. | 01-22-2009 |
| 20090024977 | LOCAL PREFERRED DIRECTION ARCHITECTURE, TOOLS, AND APPARATUS - model for use with one or more EDA tools (such as placing, routing, etc). An LPD wiring model allows at least one wiring layer to have a set of regions that each have a different preferred direction than the particular wiring layer. In addition, each region has a local preferred direction that differs from the local preferred direction of at least one other region in the set. Furthermore, at least two regions have two different polygonal shapes and no region in the set encompasses another region in the set. Some embodiments also provide a Graphical User Interface (GUI) that facilitates a visual presentation of an LPD design layout and provides tools to create and manipulate LPD regions in a design layout. | 01-22-2009 |
| 20090055793 | METHOD OF MAKING AN INTEGRATED CIRCUIT HAVING FILL STRUCTURES - A method for configuring an integrated circuit including configuring a plurality cells to form a cell library, wherein configuring each cell includes routing a intracell wiring in at least one layer positioned above a substrate, with the conductors being spaced apart from one another so as to have gaps there between, and configuring and positioning a plurality of fill structures in the gaps. The method further includes arranging selected logic cells from the cell library to form a desired layout of the integrated circuit, routing interconnect wiring between the selected logic cells in the at least one layer, and removing fill structures at positions that conflict with the routing of the interconnect wiring. | 02-26-2009 |
| 20090064081 | Process for Managing Complex Pre-Wired Net Segments in a VLSI Design - A method for pre-wiring through multiple levels of metal using flues includes steps of: receiving information comprising flue geometries and flue properties; producing multiple routing patterns of a design for the flues; identifying macro instance terminals to be pre-wired in the design; selecting at least one of the routing patterns for the macro instance terminals in the design to avoid blockage; and instantiating the design such that the flues can be manipulated as vias. | 03-05-2009 |
| 20090077523 | VERTICALLY TAPERED TRANSMISSION LINE FOR OPTIMAL SIGNAL TRANSITION IN HIGH-SPEED MULTI-LAYER BALL GRID ARRAY PACKAGES - Broadly speaking, the embodiments of the present invention fill the need for methods of designing vertical transmission lines for optimal signal transition in multi-layer BGA packages. By controlling the impedance and geometry continuity of micro vias in each micro via layer in the package to follow smooth impedance and geometry curves from layer to layer, the return loss and insertion loss of the transmission line can be reduced or controlled to within acceptable ranges. | 03-19-2009 |
| 20090113374 | Method for designing semiconductor device layout and layout design supporting apparatus - In a layout design method for a semiconductor device having a hard macro, a netlist data of the semiconductor device and a hard macro data are read out from a storage section. An arrangement position of the hard macro is determined from the netlist data and the hard macro data, and an extension direction of an interconnection pattern in a specified area of a chip for the semiconductor device is determined based on arrangement restriction data. The interconnection pattern is arranged to extend in the determined extension direction in the specified area. | 04-30-2009 |
| 20090132990 | Integrated Circuit Devices and Methods and Apparatuses for Designing Integrated Circuit Devices - Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed. | 05-21-2009 |
| 20090164964 | DESIGN STRUCTURES INCLUDING INTEGRATED CIRCUITS FOR REDUCING ELECTROMIGRATION EFFECT - A design structure including an integrated circuit for reducing the electromigration effect. The IC includes a substrate and a power transistor which has first and second source/drain regions. The IC further includes first, second, and third electrically conductive line segments being (i) directly above the first source/drain region and (ii) electrically coupled to the first source/drain region through first contact regions and second contact regions, respectively. The first and second electrically conductive line segments (i) reside in a first interconnect layer of the integrated circuit and (ii) run in the reference direction. The IC further includes an electrically conductive line being (i) directly above the first source/drain region, (ii) electrically coupled to the first and second electrically conductive line segments through a first via and a second via, respectively, (iii) resides in a second interconnect layer of the integrated circuit, and (iv) runs in the reference direction. | 06-25-2009 |
| 20090204934 | METHOD FOR COMPENSATING LENGTH OF DIFFERENTIAL PAIR AND METHOD FOR CALCULATING COMPENSATION LENGTH THEREOF AND COMPUTER ACCESSIBLE STORAGE MEDIA - A method for compensating length of differential pair and a method for calculating compensation length of the zigzagging type delay line thereof are provided. The method for calculating compensation length of the zigzagging type delay line includes following steps. The quantity A of hypotenuse and the quantity B of bends of the zigzagging type delay line are counted. The width W of the zigzagging type delay line is measured. The height S | 08-13-2009 |
| 20100031220 | VIA STRUCTURE TO IMPROVE ROUTING OF WIRES WITHIN AN INTEGRATED CIRCUIT - In consideration for the fact that a connection on the upper layers of an integrated circuit needs to access a lower layer to connect to, e.g., a transistor, at least one via on each layer is required below the top layer used by a connection for each pin. The vias (i.e., the connection structures between wiring planes within an integrated circuit) are arranged such that the number of wiring resources blocked on the lower layers is reduced. Various rules govern which vias are chosen. The main characteristic is to elect only a certain number of wiring channels appropriate for the vias on a single layer and then apply an optimization within the restricted elected wiring channels on that layer to select the most appropriate vias. | 02-04-2010 |
| 20100031221 | VIA DENSITY CHANGE TO IMPROVE WAFER SURFACE PLANARITY - Changing a via density for viafill vias to improve wafer surface planarity for later photolithography is provided, in one embodiment, by obtaining a circuit design including a plurality of viafill vias having differing via density across the circuit design, each viafill via interconnecting non-functional metal fill shapes in different layers of the circuit design; selecting a region of the circuit design to evaluate using an evaluation window; determining a via density within the evaluation window; and changing a number of viafill vias within the region in the circuit design in response to the via density being different than a threshold via density that is selected such that a coating deposited over the plurality of vias presents a substantially planar surface. | 02-04-2010 |
| 20100100863 | ROUTING DESIGN METHOD, ROUTING DESIGN APPARATUS AND RECORDING MEDIUM STORING ROUTING DESIGN PROGRAM - In a routing design method for designing routing of a SiP having first and second routing portions that are connected to each other via bonding wires, whether a DRC error of the first or second routing portion is present or not is determined and the DRC error is selected when the DRC error is present. A plurality of nets associated with the selected DRC error are specified and the routes of the specified nets are removed. Then, bonding wire allocations of the specified nets are changed. Further, the specified nets are rerouted so as not to cause a DRC error and whether the rerouting result is accepted or not is determined. | 04-22-2010 |
| 20100138803 | APPARATUS AND METHOD OF SUPPORTING DESIGN OF SEMICONDUCTOR INTEGRATED CIRCUIT - A method of supporting design of a semiconductor integrated circuit, is achieved by generating a data indicating a basic cell and a data indicating a cell group different in logic from the basic cell; and by storing the basic cell indicating data and the cell group indicating data in a library of a storage unit. An outer shape and a position of a wiring pattern of the cell group are same as those of the basic cell. The wiring pattern of the basic cell and the wiring pattern of the cell group contain a wiring obstruction section indicating an area in which a passage wiring is inhibited. When a design change is carried out, the basic cell is replaced by a change cell of the cell group corresponding to the design change. | 06-03-2010 |
| 20100180250 | METHOD AND APPARATUS FOR GENERATING LAYOUT REGIONS WITH LOCAL PREFERRED DIRECTIONS - Some embodiments of the invention provide a method for defining wiring directions in a design layout having several wiring layers. The method decomposes a first wiring layer into several non-overlapping regions. It assigns at least two different local preferred wiring directions to at least two of the regions. In some embodiments, the method decomposing the first wiring layer by using the vertices of items in the layout to decompose the layout. In some of these embodiments, the items include macro blocks. The method of some embodiments also identifies several power via arrays on the first wiring layer, and identifies a local preferred wiring direction based on the arrangement of the power via arrays on the first wiring layer. | 07-15-2010 |
| 20100223589 | COMBINATION OF GROUND DEVICES IN WIRING HARNESS DESIGNS - A method can include allowing a user to place a first wiring harness design component within a wiring harness topology in a wiring harness design workspace, allowing the user to place a first plurality of ground devices within the first wiring harness design component placed in the wiring harness topology, allowing the user to request an automatic ground combination, and, in response to the user requesting an automatic ground combination, automatically applying at least one electronically stored ground combination rule to a first set of ground devices comprising a plurality of the first plurality of ground devices and automatically combining at least two of the first set of ground devices into a first combined ground device based at least in part on the applied at least one electronically stored ground combination rule. | 09-02-2010 |
| 20100287520 | Dummy rule generating apparatus - A dummy rule generating apparatus includes a critical pattern estimating unit that determines a wiring pattern whose total perimeter length of wirings is smaller than an appropriate range based on constraints on the wirings for a circuit layout as a critical pattern. The dummy rule generating apparatus also includes a rule generating unit that generates dummy fill rules of a shape and a layout of dummy metals that increase number of dummy metals inserted in the critical pattern and decrease the number of dummy metals inserted in a wiring pattern whose total perimeter length of wirings is within an appropriate range. | 11-11-2010 |
| 20100293515 | METHOD OF LAYOUT OF PATTERN - A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The first area includes a second area. The second area is bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out. The first dummy pattern has at least a first distance from the first wiring. A second dummy pattern in the second area is laid out. The second dummy pattern has at least the first distance from the first wiring. The second dummy pattern has at least a third distance from the first dummy pattern. | 11-18-2010 |
