| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 716013000 | Global routing (e.g., shortest path, dead space, or duplicate trace elimination) | 52 |
| 20080201682 | Method of designing wiring structure of semiconductor device and wiring structure designed accordingly - A method of designing a wiring structure of an LSI is capable of reducing a capacitance variation ratio ΔC/C or a resistance-by-capacitance variation ratio Δ(RC)/(RC) of the wiring structure. The method sets a process-originated variation ratio (∈ | 08-21-2008 |
| 20080209383 | Reverse routing methods for integrated circuits having a hierarchical interconnect architecture - The present invention relates to methods for the global and detail routing of integrated circuits with hierarchical interconnect routing architecture. The methods includes the steps of: mapping routing resources of said integrated circuit to the nodes and edges of a graph theoretic tree, mapping each target to a target node; mapping each driver to a driver node; and routing each driver and its targets as a function of the minimum spanning tree spanning each driver node and its target nodes by traversing from the target nodes of a driver backwards toward its driver node in said tree. The methods of this invention are straightforward to implement, of polynomial time complexity, and can optimize routing resource usage. | 08-28-2008 |
| 20080209384 | Method of searching for wiring route in integrated circuit, automatic wiring device for integrated circuit, and program therefor - A wiring design device for an integrated circuit has been disclosed, which is capable of easily changing a via to a redundant via in a route for which search has been completed but which has been found to be changed after the design has advanced and of easily obtaining an optimum solution of a route even if the via is changed to the redundant via. The wiring design device for an integrated circuit comprises an evaluation value calculation circuit that calculates an evaluation value for each of a plurality of wiring routes from a start node to an end node, a determination circuit that determines a wiring route from the start node to the end node based on the calculated evaluation value, and a via type selection circuit that selects a via type to be used according to a difference between line widths of wires, wherein the evaluation value calculation circuit calculates, as to a wiring route in which a via is provided, the evaluation value after the via is provided by calculating a plurality of the evaluation values when different via types are used. | 08-28-2008 |
| 20080222592 | SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN SUPPORT DEVICE, AND SEMICONDUCTOR INTEGRATED CIRCUIT MANUFACTURING METHOD - A semiconductor integrated circuit including a user logic circuit is disclosed in which circuit parts for shifting data are composed of registers other than scan cells except for the circuit part right after a combinational circuit, and the parts configured of the registers other than the scan cells are used as a scan path. | 09-11-2008 |
| 20080244496 | LAYOUT DESIGN DEVICE AND LAYOUT METHOD - A layout design device according to an exemplary aspect of the present invention is a layout design device for designing layout of an integrated circuit, including a routing section for adjacently wiring a signal line having a high activity rate and a signal line having a low activity rate based on an activity rate of the signal line of each circuit element. | 10-02-2008 |
| 20080250376 | Integrating a boolean SAT solver into a router - One embodiment of the present invention provides a system that routes a set of pairs of points during the design of an integrated circuit (IC) chip. The system comprises a routing engine which is configured to search for a path to connect a current pair of points in the set of pairs of points, wherein the path comprises a set of rectangles and vertices. The routing engine uses a routing database, which keeps track of previously routed nets that can obstruct the routing of the current pair of points. The system further comprises a satisfiability (SAT) solver which is capable of solving a set of constraints, wherein the set of constraints are associated with the routability of the set of pairs of points. The SAT solver additionally comprises a SAT database which maintains the set of constraints and a current partial solution to the set of constraints. The SAT database is used to update the routing database if the current partial solution changes. | 10-09-2008 |
| 20080256502 | SYSTEM AND METHOD FOR GLOBAL CIRCUIT ROUTING INCORPORATING ESTIMATION OF CRITICAL AREA ESTIMATE METRICS - An electronic circuit layout refinement method and system. A grid of equally sized tiles is defined on a circuit layout area. Each tile of the grid has a respective critical area estimate metric associated with critical area estimates for a circuit to be placed on the circuit layout area. A global circuit routing for a circuit to be placed within a plurality of tiles of the grid is performed. An estimation of critical area estimate metrics that are assigned to respective tiles of the grid is performed prior to performing a detailed circuit routing for the circuit. The global circuit routing is adjusted, after estimating the critical area estimate metrics, in order to improve a respective critical area estimate metric assigned to at least one tile of the grid. The adjusted global circuit routing is then produced. | 10-16-2008 |
| 20080256503 | POWER MANAGEMENT ARCHITECTURE AND METHOD OF MODULATING OSCILLATOR FREQUENCY BASED ON VOLTAGE SUPPLY - A method and system for modulating logic clock oscillator frequency based on voltage supply. The system comprises a logic unit having a logic operation and a device to produce self-adjusting clocks to match the logic operation. The device is configured to use supply voltage as an independent variable to optimize device parameters for voltage variations. The invention is also directed to a design structure on which a circuit resides. | 10-16-2008 |
| 20080263496 | Enhanced routing grid system and method - Routing systems and methods are provided having various strategies for optimizing and evaluating possible routes for netlist connections. In one embodiment, a data structure or matrix provides cost related data weighted to evaluate the impact proposed a connection or segment will have upon an attribute of interest such as, for example, speed, manufacturability or noise tolerance. This cost information can be related to terrain costs as well as shape costs to provide multidimensional cost information for connections. Processing such higher information cost data is made more efficient with an additive process that is less demanding than a computationally intensive iterative multiplication process. Various methods are also disclosed for shifting and adjusting routing grids to improve use of available space or reduce run time in routing. In another embodiment, a parallel processing scheme is used to process multiple regions on multiple processors simultaneously without creating conflicts, that could arise, for example, when two processors try to route a trace on the same gridpoint. | 10-23-2008 |
| 20080263497 | Enhanced Routing Grid System and Method - Routing systems and methods are provided having various strategies for optimizing and evaluating possible routes for netlist connections. In one embodiment, a data structure or matrix provides cost related data weighted to evaluate the impact proposed a connection or segment will have upon an attribute of interest such as, for example, speed, manufacturability or noise tolerance. This cost information can be related to terrain costs as well as shape costs to provide multidimensional cost information for connections. Processing such higher information cost data is made more efficient with an additive process that is less demanding than a computationally intensive iterative multiplication process. Various methods are also disclosed for shifting and adjusting routing grids to improve use of available space or reduce run time in routing. In another embodiment, a parallel processing scheme is used to process multiple regions on multiple processors simultaneously without creating conflicts, that could arise, for example, when two processors try to route a trace on the same gridpoint. | 10-23-2008 |
| 20080263498 | Enhanced Routing Grid System and Method - Routing systems and methods are provided having various strategies for optimizing and evaluating possible routes for netlist connections. In one embodiment, a data structure or matrix provides cost related data weighted to evaluate the impact proposed a connection or segment will have upon an attribute of interest such as, for example, speed, manufacturability or noise tolerance. This cost information can be related to terrain costs as well as shape costs to provide multidimensional cost information for connections. Processing such higher information cost data is made more efficient with an additive process that is less demanding than a computationally intensive iterative multiplication process. Various methods are also disclosed for shifting and adjusting routing grids to improve use of available space or reduce run time in routing. In another embodiment, a parallel processing scheme is used to process multiple regions on multiple processors simultaneously without creating conflicts, that could arise, for example, when two processors try to route a trace on the same gridpoint. | 10-23-2008 |
| 20080276213 | Method of shield line placement for semiconductor integrated circuit, design apparatus for semiconductor integrated circuit, and design program for semiconductor integrated circuit - A semiconductor integrated circuit design apparatus includes: an association information creating unit which creates association information for associating wiring information of a signal line with wiring information of a shield line placed for the signal line; an association information storage unit which stores the thus created association information; and a shield wiring unit which, when the placement of the signal line is changed, changes in interlinking fashion with the changed placement the placement of the shield line that is associated with the signal line by the association information. | 11-06-2008 |
| 20080282213 | METHOD TO REDUCE THE WIRELENGTH OF ANALYTICAL PLACEMENT TECHNIQUES BY MODULATION OF SPREADING FORCES VECTORS - A method of force directed placement programming is presented. The method includes: assigning a plurality of objects from a cell netlist to bins; shifting the objects based on the bins; computing a magnitude of a spreading force for each object of the plurality of objects based on the shifting; sorting the objects based on the magnitude of the spreading force of the objects; selecting a subset of the sorted objects based on a threshold value indicating at least one of a top percentage, a threshold force, and a threshold value that is based on a placement congestion; adjusting the spreading force of the selected objects to be equal to a predetermined value indicating a minimum spreading force; and determining a placement of the objects based on adjusted spreading force of the selected objects. | 11-13-2008 |
| 20080301618 | Method and System for Routing of Integrated Circuit Design - The invention relates to a method and a system for routing electric circuits in integrated circuit chip design. Specifically, the invention encompasses the steps of performing a congestion analysis ( | 12-04-2008 |
| 20080307383 | ITERATIVE SYNTHESIS OF AN INTEGRATED CIRCUIT DESIGN FOR ATTAINING POWER CLOSURE WHILE MAINTAINING EXISTING DESIGN CONSTRAINTS - An approach that iteratively synthesizes an integrated circuit design to attain power closure is described. In one embodiment, the integrated circuit design is initially synthesized to satisfy timing and power constraints. Results from the initial synthesis are fed back into the synthesis process where specific nodes in the circuit design are targeted to satisfy the timing and power constraints. Selected nodes in the circuit design are worked on in an iterative manner until it has been determined that all of selected nodes have undergone evaluation for satisfying timing and power constraints. Once all of the selected nodes have undergone evaluation for satisfying timing and power constraints, then a final netlist representing the circuit design is generated. | 12-11-2008 |
| 20080320432 | Disabling unused IO resources in platform-based integrated circuits - The present invention is directed to methods for disabling unused IO resources in a platform-based integrated circuit. A slice is received from a vendor. The slice includes an IO circuit unused by a customer. The IO circuit is disabled. For example, when the IO circuit is desired to be tied to a power source, a primary input/output pin of the IO circuit is shorted to a power bus of the IO circuit. When the IO circuit is desired to be tied to a ground source, a primary input/output pin of the IO circuit is shorted to a ground bus of the IO circuit. When the IO circuit is desired to be left floated, a primary input/output pin of the IO circuit is not connected to any bonding pad cell of the slice. Next, the IO circuit is removed from the customer's logic design netlist. The IO circuit is inserted in the vendor's physical design database. | 12-25-2008 |
| 20090013299 | BUFFER INSERTION TO REDUCE WIRELENGTH IN VLSI CIRCUITS - Wirelength in a net of an integrated circuit design is reduced by forming clusters of sinks to be interconnected, inserting a buffer at each cluster, and providing branch connections between clusters by connecting a sink of one cluster to a buffer of another cluster, to create a buffer tree spanning all sinks. The buffers are inserted at a point on a respective bounding box of a cluster that is closest to a source for the net. A sink that provides a branch connection to the buffer of another cluster is the closest sink to that buffer (except for those sinks in the cluster). Clusters may be formed by examining different pairs of the sinks with different bounding boxes, and identifying one of the pairs whose bounding box has a lowest half-perimeter as the best pair for clustering. | 01-08-2009 |
| 20090013300 | SYNTHESIS STRATEGIES BASED ON THE APPROPRIATE USE OF INDUCTANCE EFFECTS - A method of optimizing the signal propagation speed on a wiring layout is provided. In general, the method accounts for and uses inductance effects caused by the propagation of a high-speed signal on a signal wire surrounded by parallel ground wires. In particular, one of the physical parameters defining the wiring layout may be adjusted to create an rlc relationship in the wiring layout that maximizes the signal propagation speed. The physical parameter that is adjusted may be, for example, the wire separation between the signal wire and the ground wires or the width of the ground wires. The disclosed method may also be applied to a wiring layout having multiple branches, such as a clock tree. In this context, a first branch may be optimized using the disclosed method. Downstream branches may then be adjusted so that the impedances at the junction between the branches are substantially equal. | 01-08-2009 |
| 20090031275 | Method and System for Performing Global Routing on an Integrated Circuit Design - A method for performing global routing on an integrated circuit design is disclosed. The integrated circuit design is initially divided into multiple G-cells. The G-cells are interconnected by a set of nets. The set of nets is then decomposed into corresponding wires. The wires are prerouted to interconnect the G-cells. BoxRouting is performed on the wires until all the wires are routed. Finally, postrouting is performed on the wires. | 01-29-2009 |
| 20090037865 | ROUTER - Configuration of reconfigurable multidimensional fields are described. Information is provided for handling feedback, among other things. | 02-05-2009 |
| 20090055792 | Method and system for designing semiconductor integrated circuit providing dummy pattern in divided layout region - A method of designing a semiconductor integrated circuit, includes dividing a layout area in which a wiring pattern is disposed, into a plurality of division areas, determining a dummy pattern disposition area provided in each of the plurality of division areas, adding a dummy pattern to the dummy pattern disposition area of each of the plurality of division areas, and combining division areas to which the dummy pattern is added. The dummy pattern disposition area is arranged away from at least one of boundaries between a corresponding division area of the plurality of division areas and adjacent division areas. | 02-26-2009 |
| 20090064080 | BUFFER INSERTION TO REDUCE WIRELENGTH IN VLSI CIRCUITS - Wirelength in a net of an integrated circuit design is reduced by forming clusters of sinks to be interconnected, inserting a buffer at each cluster, and providing branch connections between clusters by connecting a sink of one cluster to a buffer of another cluster, to create a buffer tree spanning all sinks. The buffers are inserted at a point on a respective bounding box of a cluster that is closest to a source for the net. A sink that provides a branch connection to the buffer of another cluster is the closest sink to that buffer (except for those sinks in the cluster). Clusters may be formed by examining different pairs of the sinks with different bounding boxes, and identifying one of the pairs whose bounding box has a lowest half-perimeter as the best pair for clustering. | 03-05-2009 |
| 20090070726 | Enhanced Routing Grid System and Method - Routing systems and methods are provided having various strategies for optimizing and evaluating possible routes for netlist connections. In one embodiment, a data structure or matrix provides cost related data weighted to evaluate the impact proposed a connection or segment will have upon an attribute of interest such as, for example, speed, manufacturability or noise tolerance. This cost information can be related to terrain costs as well as shape costs to provide multidimensional cost information for connections. Processing such higher information cost data is made more efficient with an additive process that is less demanding than a computationally intensive iterative multiplication process. Various methods are also disclosed for shifting and adjusting routing grids to improve use of available space or reduce run time in routing. In another embodiment, a parallel processing scheme is used to process multiple regions on multiple processors simultaneously without creating conflicts, that could arise, for example, when two processors try to route a trace on the same gridpoint. | 03-12-2009 |
| 20090089735 | METHOD AND APPARATUS FOR ROUTING - Some embodiments of the invention provide a routing method. The routing method receives a set of nets to route in a region of an integrated circuit (“IC”) layout. The routing method defines routes for the nets in a manner that ensures that each segment of each route is not less than a minimum length that is required for the segment. | 04-02-2009 |
| 20090113373 | Layout design apparatus, layout design method, and computer product - A layout design apparatus that limits the maximum wiring density and the maximum edge length of partial regions when determining wiring layout. After determining the wiring layout, the layout design apparatus inserts a dummy into a partial region having a low wiring density and thereby, the minimum wiring density and the minimum edge length of the partial regions are limited. Thus, the respective wiring densities and respective edge lengths of the partial regions are constrained within a constant range and irregularities in the substrate surface after polishing can be suppressed. | 04-30-2009 |
| 20090132989 | Method of Determining Minimum Cost Path - A network is represented using a graph. The graph comprises a plurality of vertices and a plurality of edges. The vertices comprise a source vertex, a destination vertex and a vertex u. The edges link corresponding adjacent pairs of the vertices. A minimum cost path in the graph is determined from the source vertex to the destination vertex, wherein the vertex u is in the minimum cost path. An edge from the vertex u in the minimum cost path introduces an additional capital expenditure cost that is dependent on how the minimum cost path traverses from the source vertex to the vertex u. | 05-21-2009 |
| 20090158232 | CIRCUIT ARRANGEMENTS AND ASSOCIATED APPARATUS AND METHODS - There is provided a method comprising: examining the location of one or more feature(s) of the one or more component(s) of a circuit arrangement to determine the displacement of the location of said one or more associated communication contact(s) with respect to a designed location for the communication contact(s), and providing corrective communication path layout data of said circuit arrangement based upon the said displacement(s). | 06-18-2009 |
| 20090158233 | Automatic design method and computer program thereof - An automatic design method according to the present invention comprises the steps of: grouping rats and tentatively disposed vias by bonding pad groups to be connected, corresponding to the pads that are grouped by four sides of a substrate surface; setting boundary lines to define regions each of which contains any one of the pads and the tentatively disposed vias; checking whether there exist(s) the tentatively disposed via(s) surrounded by bonding pad group(s) that is/are different from the one to which the via(s) in question belong(s) or not; and in a predetermined case, moving and redisposing the tentatively disposed via(s) on respective position(s) each of which is located on a rat to which it is connected and on the boundary line that defines a plurality of adjacent regions containing other vias in the bonding pad group to which the via in question belongs. | 06-18-2009 |
| 20090172628 | Method and System for Utilizing Hard and Preferred Rules for C-Routing of Electronic Designs - An improved approach for implementing C-routing is described. Cost-based analysis is performed to balance the different rule requirements, to optimize the assignment of objects and nets during C-routing. | 07-02-2009 |
| 20090172629 | Validating continuous signal phase matching in high-speed nets routed as differential pairs - Methods and apparatus to validate continuous signal phase matching in high-speed nets routed as differential pairs are described. In one embodiment, a primary net of a differential pair may be traversed to determine whether a design rule violation has occurred based on comparison of calculated trace lengths of the primary net and a secondary net against a threshold value. Other embodiments are also described. | 07-02-2009 |
| 20090187873 | SIGNAL DELAY SKEW REDUCTION SYSTEM - A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method further includes identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding skew-influencing features in a second connection path in the initial netlist. The method also includes generating a skew-corrected netlist wherein the second connection path includes one or more added skew-influencing features corresponding to those of the first connection path. The method further includes outputting the skew-corrected netlist. | 07-23-2009 |
| 20090193382 | METHOD OF MAKING AN INTEGRATED CIRCUIT INCLUDING SIMPLIFYING METAL SHAPES - A method for simplifying metal shapes in an integrated circuit including receiving an incoming wire layout for at least one metal layer of an integrated circuit, the incoming wire layout for the at least one layer including a plurality of wires running in a preferred direction and a plurality of vias connected thereto. The method further includes segmenting each of the wires into a plurality of bricks according to a set of equally spaced parallel grid lines extending in direction which is perpendicular to the preferred direction such that each wire comprises a series of consecutive bricks with brick boundaries between consecutive bricks occurring at a grid line, defining each brick as a regular or complex brick based on at least one brick criteria, and defining brick groups based on one or more grouping criteria, wherein each group contains one or more consecutive bricks of a same wire and each brick belongs to only one group so that each wire comprises a series of one or more consecutive groups, and wherein groups containing at least one complex brick are defined as complex groups. | 07-30-2009 |
| 20090193383 | Auto-Router Performing Simultaneous Placement of Signal and Return Paths - An auto routing method and system provides optimized circuit routing while maintaining proper reference return paths for critical signals. Critical signal paths are auto-routed simultaneously with corresponding reference return paths, and the reference return paths can be merged into reference planes if they are adjacent to regions connected to the same reference net. The reference return paths may be in a plane adjacent to the signal path plane in the same channel, or the reference returns may be routed in adjacent channels in the same plane as the signal path. A check may be performed on endpoints of each critical signal path to determine whether a reference return via is present within a proximity tolerance of the signal path endpoints, and a reference return via placed if not. | 07-30-2009 |
| 20090210849 | Accurate Parasitics Estimation for Hierarchical Customized VLSI Design - Disclosed is a method of estimating interconnect wire parasitics in integrated circuits which includes obtaining a circuit layout having circuit components placed thereon including source input/output (I/O) pins and sink I/O pins, the circuit layout having a circuit hierarchy, bubbling up of the I/O pins until all I/O pins are on a same level of the circuit hierarchy, and then estimating interconnect segments to be employed in interconnecting at least some circuit components of the placed circuit components of the circuit layout. Also disclosed is a circuit design system and program storage device. | 08-20-2009 |
| 20090210850 | Method for Simplifying Tie Net Modeling for Router Performance - A method for preprocessing tie net routing data organizes the data into a plurality of tie nets each based on an optimal connection path between a pin or set of pins and the power grid. The router then routs the data embodying the thusly-simplified plurality of tie nets. Once the routing is complete, post processor takes the routed design and returns it to it's original net list state while keeping the routing solution. | 08-20-2009 |
| 20090217230 | AUTOMATIC BUS ROUTING - Particular embodiments generally relate to automatic routing of a bus in an integrated circuit design. In one embodiment, a method includes receiving a description of a circuit design. Buses are automatically detected based on pin adjacency in terms of distance between pins and routing layer of the pins. A bus routing area is determined by the bounding box of first group of source pins and a second group of destination pins. Bus routing guidance is then generated by an automatically search engine in the bus routing area. The bus routing guidance models a bus as a skinny wire with large spacing, and it does not violate design rules. Real bus wires are generated based on the bus guidance. A bus is then automatically routed between a first group of source pins and a second group of destination pins based on the bus routing guidance. | 08-27-2009 |
| 20090235221 | ROUTING CHANNEL DISPLAYING METHOD AND COMPUTER-ACCESSIBLE STORAGE MEDIUM THEREOF - A routing channel displaying method and a computer-accessible storage medium are provided. In the method, a circuit board is divided into m×n blocks which form a matrix with size m×n, and m, n are positive integers. Then, a processing direction is determined by a relative position of a first and a second component of the circuit board. After dividing the blocks into at least one set of processing blocks according to the processing direction, an analysis of the used space rate is sequentially performed on each set of the processing blocks. Finally, all blocks in each set of the processing blocks are labeled according to the result of the analysis of the used space rate so as to display at least one routing channel between the first component and the second component. Thereby, the probability of rerouting is reduced, and the routing efficiency of the circuit board is improved. | 09-17-2009 |
| 20090259982 | NETLIST CELL IDENTIFICATION AND CLASSIFICIATION TO REDUCE POWER CONSUMPTION - In an integrated circuit device, a power circuit for maintaining asserted values on an input output pin of the device when a functional block of the device is placed in a sleep mode. The device includes a power circuit disposed along the periphery of the device, the power circuit configured to maintain power when the device is placed in a low-power mode. A plurality of input output blocks are included in the device and are for receiving external inputs for the integrated circuit device and for providing outputs from the integrated circuit device. The power circuit is coupled to provide power to at least one of the input output blocks to maintain state when the integrated circuit device is in the low-power mode. | 10-15-2009 |
| 20090259983 | METHODS FOR DESIGNING A PRODUCT CHIP A PRIORI FOR DESIGN SUBSETTING, FEATURE ANALYSIS, AND YIELD LEARNING - A method for designing a chip a priori for design subsetting, feature analysis, and yield learning. The method includes identifying a plurality of signal paths within a chip design that can be readily identified from chip fail data and removing a fraction of the plurality of signal paths that have physical design constraints to generate a subset of the plurality of signal paths. The method further includes constructing a physical implementation of each of the signal paths in the subset, identifying one or more signal paths in the subset that are not constructed consistently with the respective physical implementation, and removing those signal paths from the subset. | 10-15-2009 |
| 20090271754 | METHOD AND APPARATUS FOR COMPUTING A DETAILED ROUTABILITY ESTIMATION - One embodiment of the present invention provides a system that computes a routability estimation across a collection of local routing regions associated with a circuit layout. This system first selects a first local routing region associated with a route overflow, wherein a respective local routing region is associated with an estimation of a number of route overflows for routing layers in a region of the circuit layout. Furthermore, a respective routing layer is associated with a preferred direction variable D. Next, the system transfers an overflow value k in direction d away from an overflowing routing layer for the first local routing region to a second local routing region, which has the capacity to handle an overflow of k or more routes in a direction d. Finally, the system computes a global routability estimation as a function of a global overflow cost and an adjacent overflow cost. | 10-29-2009 |
| 20090271755 | Unified Layer Stack Architecture - A method for producing a family of digital integrated circuit designs, where the family has a highest level design and at least one lower level design. The highest level design is first produced. Then, in a programmed computing system without user intervention, the highest level design is automatically processed to selectively remove at least one predetermined metal layer. A closest remaining overlying layer to the at least one removed metal layer is automatically mapped to a closest remaining underlying layer to the at least one removed metal layer, thereby producing the at least one lower level design. | 10-29-2009 |
| 20090282382 | SYSTEM AND METHOD FOR ROUTING CONNECTIONS WITH IMPROVED INTERCONNECT THICKNESS - A method for modeling a circuit includes generating a circuit model based on a netlist that defines a plurality of connections between a plurality of circuit elements. The circuit model includes a model of one or more of the circuit elements. The method further includes determining a wire width associated with at least a selected connection based, at least in part, on design rules associated with the netlist. Additionally, the method includes determining a wire thickness associated with the selected connection based, at least in part, on a signal delay associated with the wire thickness. Furthermore, the method also includes routing the selected connection in the circuit model using a wire having a width substantially equal to the wire width calculated for the connection and a thickness equal to the wire thickness calculated for the connection and storing the circuit model in an electronic storage media. | 11-12-2009 |
| 20090319977 | Interconnect-Driven Physical Synthesis Using Persistent Virtual Routing - A persistence-driven optimization technique is provided in which nets can be ranked based on unpredictability and likely quality of result impact. The top nets in that ranking can be routed and their parasitics extracted. A timing graph can be back-annotated with route-based delays and parasitics for the selected nets. At this point, synthesis can be run using actual route-based delays and parasitics for the selected nets, with their routes being updated incrementally as needed. In one embodiment, the nets can be re-ranked after synthesis. Finally, these routes can be preserved across the subsequent global routing of the remaining nets. | 12-24-2009 |
| 20100023913 | METHOD FOR IC WIRING YIELD OPTIMIZATION, INCLUDING WIRE WIDENING DURING AND AFTER ROUTING - Disclosed are embodiments of a method, service, and computer program product for performing yield-aware IC routing for a design. The method performs an initial global routing which satisfies wiring congestion constraints. Next, the method performs wire spreading and wire widening on the global route, layer by layer, based on, for example, a quadratic congestion optimization. Following this, timing closure is performed on the global route using results of the wire spreading and wire widening. Post-routing wiring width and wire spreading adjustments are made using the critical area yield model. In addition, the method allows for the optimization of already-routed data. | 01-28-2010 |
| 20100095263 | Post-routing power supply modification for an integrated circuit - A technique for generating the layout of an integrated circuit | 04-15-2010 |
| 20100100862 | WIRING DESIGN METHOD - A wiring design method and apparatus are provided. The wiring design method includes dividing a wiring region represented by wiring region data to generate a plurality of first division regions based on a first wiring rule and generating, when a second wiring rule different from the first wiring rule may be set in the first division region, second division regions with the second wiring rule in the first division region. | 04-22-2010 |
| 20100146472 | ROUTING SYSTEM - A routing system is improved by performing three steps sequentially to complete an execution process. The first step estimates a normalized criticality score for each design net. The second step arranges the scores for each design net in descending order. Third step rips up and reroutes the design so as to make it more feasible. | 06-10-2010 |
| 20100146473 | ROUTING SYSTEM - A process for shortest path routing in computer-aided designs (CAD) is performed using an incremental graph traversal technique. This technique searches the shortest path routing trees in a graph by path exploration limited only to an incremented search region thereby reducing run time complexity. Graph traversal begins in the incremented search region, and propagates successive changes thereafter. | 06-10-2010 |
| 20100199253 | Routing Method for Double Patterning Design - A method of designing a double patterning mask set includes dividing a chip into a grid comprising grid cells; and laying out a metal layer of the chip. In substantially each of the grid cells, all left-boundary patterns of the metal layer are assigned with a first one of a first indicator and a second indicator, and all right-boundary patterns of the metal layer are assigned with a second one of the first indicator and the second indicator. Starting from one of the grid cells in a row, indicator changes are propagated throughout the row. All patterns in the grid cells are transferred to the double patterning mask set, with all patterns assigned with the first indicator transferred to a first mask of the double patterning mask set, and all patterns assigned with the second indicator transferred to a second mask of the double patterning mask set. | 08-05-2010 |
| 20100218157 | TIMING-OPTIMAL PLACEMENT, PIN ASSIGNMENT, AND ROUTING FOR INTEGRATED CIRCUITS - Techniques for timing-optimal placement, pin assignment, and routing for integrated circuits are described herein. According to one embodiment, a list of paths providing implementation possibilities is constructed. A means is provided for removing paths from the list as well as a means for committing paths to the implementation if such paths are required for making the circuit implementation valid. Paths with worst case attributes are iteratively removed from the list until all paths in the list are committed to the implementation. Other methods and apparatuses are also described. | 08-26-2010 |
| 20100223588 | REDUCING COUPLING BETWEEN WIRES OF AN ELECTRONIC CIRCUIT - A routing method for reducing coupling between wires of an electronic circuit is proposed, wherein sets of nets are classified according to their coupling characteristics, and spacing between wires assigned to the sets of nets is chosen according to the coupling characteristics. | 09-02-2010 |
| 20100262945 | REPEATER DRIVEN ROUTING METHODOLOGY - A method for routing a chip, involving forming a plurality of nets configured to connect components of the chip, wherein each of the plurality of nets is included in a netlist, assigning at least one repeater to each of the plurality of nets in the netlist, wherein the repeaters are assigned prior to performing physical routing of the plurality of nets, inserting the at least one repeater in a corresponding net, wherein the insertion of the at least one repeater divides the corresponding net into at least two subnets, and performing the physical routing of the plurality of nets by connecting each of the subnets. | 10-14-2010 |
