| Entries |
| Document | Title | Date |
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| 20080209368 | Layout design method, layout design apparatus, and computer product - An apparatus for designing the layout of a circuit includes an acquiring unit, a determining unit, a specifying unit, an arranging unit, a modifying unit, and a routing unit. Based on net information acquired by the acquiring unit, the determining unit determines a wiring block of signal paths connecting cells connected through adjacent. The arranging unit arranges a wiring area between the cells that extends along user-specified reference points or user-specified reference segments received by the specifying unit. The modifying unit modifies the arranged wiring area and the routing unit routes the signal paths of the wiring block in the modified wiring area. | 08-28-2008 |
| 20080209369 | DEVICE, METHOD, AND STORAGE FOR VERIFICATION SCENARIO GENERATION, AND VERIFICATION DEVICE - A verification scenario generation device including a first input unit which accepts input of a device list showing devices connected with a circuit to be verified, parameter setting information for the devices, and a test bench combination list corresponding to the devices, a test bench library which holds the test bench, and a test bench generation unit to generate a test bench for verification, a scenario template generation unit which generates a scenario template. The device further includes a data combination list generation unit which generates a combination list of data kinds, a verification item generation unit which generates verification items based on a combination list of the data kind and a combination list of the test bench input, and a verification scenario generation unit which generates a verification scenario based on the scenario template, and the verification items. | 08-28-2008 |
| 20080209370 | FORMALLY PROVING THE FUNCTIONAL EQUIVALENCE OF PIPELINED DESIGNS CONTAINING MEMORIES - One embodiment of the present invention provides a system that formally proves the functional equivalence of pipelined designs. First, the system receives a specification for a first pipelined design, which includes a first memory system, and a specification for a second pipelined design, which includes a second memory system. Next, the system determines a correspondence between operations on the first memory system and corresponding operations on the second memory system. This correspondence enables memory operations to be represented in a combinational form based on design inputs, thereby allowing both memory systems to be logically abstracted out of their respective designs. After the memory systems have been abstracted out, the system compares the combinational outputs of the first pipelined design and the combinational outputs of the second pipelined design to verify that the designs are functionally equivalent. | 08-28-2008 |
| 20080209371 | Logic cell configuration processing method and program - A logic cell configuration processing method for a CMOS semiconductor is configured in which leak current per unit width equal for P-channel and N-channel MOS transistors, by calculating a probable average leak current, which is an expected value of leak current of the P-channel MOS transistor and the N-channel MOS transistor in the logic cell based on an input signal to be input to the logic cell; comparing a contribution of the P-channel MOS transistor with a contribution of the N-channel MOS transistor to the calculated probable average leak current; deciding the P-channel MOS transistor or the N-channel MOS transistor, whichever has a greater contribution, to be a low leak type MOS transistor; and adjusting ON current of the low leak type MOS transistor to be equal to ON current of the other MOS transistor. | 08-28-2008 |
| 20080216028 | FAST EVALUATION OF AVERAGE CRITICAL AREA FOR IC - Method and apparatus for approximating the average critical area of a layout or layout region, involving summing, over all the object segments of interest, respective critical area contribution values that are dependent upon particular layout parameters of the objects, each of the contribution values being representative of a plurality of defect sizes, and being defined such that for each defect size in the plurality of defect sizes, and for a particular defect type, the contribution values collectively count all critical areas arising due to the object segments of interest only once. | 09-04-2008 |
| 20080216029 | METHOD AND SYSTEM FOR PERFORMING TARGET ENLARGEMENT IN THE PRESENCE OF CONSTRAINTS - A method for performing verification is disclosed. The method includes receiving a design, including one or one or more targets, one or more constraints, one or more registers and one or more inputs. A first function of one of the one or more targets over the one or more registers and the one or more inputs is computed. A second function of one or more of the one or more constraints over the one or more registers and the one or more inputs is computed. The inputs of the first function and the second function are existentially quantified. A bounded analysis is performed to determine if the one of the one or more targets may be hit while adhering to the constraints. A preimage of the inputs of the first function and a preimage of the inputs of the second function is existentially quantified to create a synthesizable preimage. The synthesizable preimage is simplified and synthesized to create an enlarged target. Verification of the enlarged target is performed. | 09-04-2008 |
| 20080216030 | System for Performing Verification of Logic Circuits - The present invention relates to a system for verifying the proper operation of a digital logic circuit and program product therefor. In order to add a useful alternative in the field of functional, exhaustive simulation and of symbolic simulation, it is proposed to perform the steps of: | 09-04-2008 |
| 20080216031 | DESIGN STRUCTURES FOR SEMICONDUCTOR STRUCTURES WITH ERROR DETECTION AND CORRECTION - A design structure including design data describing a semiconductor structure. The semiconductor structure includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip is on top of and bonded to the second semiconductor chip. The first and second semiconductor chips include a first and a second electric nodes. The second semiconductor chip further includes a first comparing circuit. The semiconductor structure further includes a first coupling via electrically connecting the first electric node of the first semiconductor chip to the first comparing circuit of the second semiconductor chip. The first comparing circuit is capable of (i) receiving an input signal from the second electric node directly, (ii) receiving an input signal from the first electric node indirectly through the first coupling via, and (iii) asserting a first mismatch signal in response to the input signals from the first and second electric nodes being different. | 09-04-2008 |
| 20080216032 | METHODS AND APPARATUSES FOR AUTOMATED CIRCUIT OPTIMIZATION AND VERIFICATION - Methods and apparatuses to automatically determine conditions at hierarchical boundaries of a hierarchical circuit design and to use the determined conditions in hierarchical optimization and verification. In one embodiment, a hierarchical block is optimized and transformed during design synthesis using one or more lemmas at the boundary of the hierarchical block. For example, the lemmas are automatically generated to specify range information for input boundary nodes. The lemmas are also used for the equivalence checker to perform hierarchical equivalence checking. Equivalence of hierarchical blocks is individually checked, in view of the lemmas. Thus, based on the lemmas, optimizations across hierarchical boundaries can be performed, while the hierarchical structure of the design is preserved so that equivalence checking of hierarchical circuit designs can still be based on the equivalence of individual hierarchical blocks. | 09-04-2008 |
| 20080222583 | METHOD AND SYSTEM FOR LOGIC VERIFICATION USING MIRROR INTERFACE - Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost and delay. The present invention provides an efficient and economical alternative. A mirror interface, or copy of the external interface undergoing verification, is used with a standardized control mechanism to verify the external interface. Because all interface I/O connections can thereby be utilized, a cost-effective and highly reusable way of verifying such interfaces is provided. | 09-11-2008 |
| 20080222584 | Method in a Computer-aided Design System for Generating a Functional Design Model of a Test Structure - A method in a computer-aided design system for generating a functional design model of a test structure. The test structure is used for performing device-specific testing and acquiring parametric data on integrated circuits, such that each chip generated from the functional design model is tested individually without excessive test time requirements, additional silicon, or special test equipment. The method includes a functional representation of a device test structure integrated into an IC design which tests a set of dummy devices that are identical or nearly identical to a selected set of functional representations of devices contained in the IC. The test structures are integrated from a device under test (DUT) library according to customer requirements and design requirements. The selected test structures are further prioritized and assigned to design elements within the design in order of priority. Placement algorithms use design, layout, and manufacturing requirements to place the selected test structures into the final layout of the design. | 09-11-2008 |
| 20080222585 | INTERLEAVED VOLTAGE CONTROLLED OSCILLATOR - A design structure embodied in a machine readable medium used in a design process includes an interleaved voltage-controlled oscillator, including a ring circuit of main logic inverter gates; a plurality of delay elements connected in parallel with a selected sequence of the main logic inverter gates; wherein each delay element comprises a feedforward section, comprising controls for regulating signal transmission through feedforward elements responsive to one or more control voltages; and a proportional section for regulating signal transmission through at least one logic inverter gate; at least one temperature compensation circuit responsive to a compensating voltage input that is proportional to temperature; an electronic circuit in communication with the temperature compensation circuit and configured to provide a voltage signal responsive to temperature; an amplifier in connection with the electronic circuit to amplify the voltage signal; and a DC offset generator configured to adjust the voltage of the amplified voltage signal. | 09-11-2008 |
| 20080229261 | DESIGN RULE SYSTEM FOR VERIFYING AND ENFORCING DESIGN RULES IN SOFTWARE - A software design rule system is provided. The software design rule system can employ a rule language that enables software developers to model valid interactions between multiple, inter-related objects; provide a rule verifier component that determines whether design rules achieve their intended purpose; and provide a rule enforcer component that determines whether the software complies with the specified rules. Software designers can provide design specifications using the rule language that the software design rule system employs. The rule language can specify a program that identifies “auxiliary states” associated with objects in the software that is being developed, transitions between the auxiliary states, and object invariants. | 09-18-2008 |
| 20080229262 | DESIGN RULE MANAGEMENT METHOD, DESIGN RULE MANAGEMENT PROGRAM, RULE MANAGEMENT APPARATUS AND RULE VERIFICATION APPARATUS - Disclosed is a rule management apparatus which acquires a design rule for regulating a part shape from systems such as a CAD system 401, converts the acquired deign rule into data having a hierarchical node format, calculates relationship strength which indicates strength of a relationship between the design rule converted into data having a hierarchical node format and another node, sets to the relationship strength between design rules which are substantially the same but described in different systems to be a maximum value, and stores in an integrating rule DB 300 the relationship strength and the design rules in association with one another. | 09-18-2008 |
| 20080229263 | PERFORMING UTILIZATION OF TRACES FOR INCREMENTAL REFINEMENT IN COUPLING A STRUCTURAL OVERAPPROXIMATION ALGORITHM AND A SATISFIABILITY SOLVER - A method, system and computer program product for performing verification are disclosed. The method includes creating and designating as a current abstraction a first abstraction of an initial design netlist containing a first target and unfolding the current abstraction by a selectable depth. A composite target is verified, using a satisfiability solver and, in response to determining that the verifying step has hit the composite target, a counterexample is examined to identify one or more reasons for the first target to be asserted. One or more refinement pairs are built by examining the counterexample and a second abstraction is built by composing the refinement pairs. A new target is built over one or more cutpoints in the first abstraction that is asserted when the one or more cutpoints assume values in the counterexample, and the new target is verified with the satisfiability solver. | 09-18-2008 |
| 20080235640 | Method and apparatus for performing static analysis optimization in a design verification system - Method and apparatus for performing static analysis optimization in a design verification system is described. In one example, a description of a verification environment having constrained objects is obtained. The constrained objects are analyzed incrementally to create a data structure of nodes. Each node includes a description of variables transitively connected by constraints. At least one of the nodes reuses a description from at least one other node. The data structure is then used during logic design verification. | 09-25-2008 |
| 20080235641 | CRITICAL AREA COMPUTATION OF COMPOSITE FAULT MECHANISMS USING VORONOI DIAGRAMS - Disclosed is a method that determines critical areas associated with different types of fault mechanisms in an integrated circuit design. The invention does this by constructing individual Voronoi diagrams for critical areas of individual fault mechanisms and a composite Voronoi diagram based on the individual Voronoi diagrams. The invention computes the critical area for composite fault mechanisms of the integrated circuit design based on the composite Voronoi diagram. | 09-25-2008 |
| 20080244481 | METHOD FOR DESIGNING AND MANUFACTURING SEMICONDUCTOR DEVICE AND SOFTWARE THEREFOR - A method for designing a semiconductor device including a semiconductor substrate and an interconnect on the semiconductor substrate, with X-direction being one direction parallel to the semiconductor substrate, Y-direction being a direction parallel to the semiconductor substrate and perpendicular to the X-direction, and Z-direction being perpendicular to the semiconductor substrate, the method includes: determining a cross-sectional configuration in the X-Z direction; three-dimensionalizing the cross-sectional configuration with a range in the Y-direction being specified; and using the three-dimensionalized configuration as a model. | 10-02-2008 |
| 20080244482 | INTEGRATED CIRCUIT DESIGN USAGE AND SANITY VERIFICATION - An automated system and method for sanity checking an integrated circuit cell layout. The method generally includes searching the cell layout for a sub-area containing a predefined identifier, determining a reference cell layout corresponding to the predefined identifier, verifying the cell layout by comparing the cell layout to the reference cell layout to determine if a cell is of concern, and reporting the cell of concern to a user. | 10-02-2008 |
| 20080244483 | INTEGRATED CIRCUIT DESIGN USAGE AND SANITY VERIFICATION - A method and system for verifying an integrated circuit design are provided. The method includes identifying cell tags embedded in a proposed integrated circuit design file, comparing cells identified as having a tag embedded therein to a cell library containing verified cell data to determine differences between the identified tagged cells and corresponding verified cell data from the cell library, and revising the proposed integrated circuit design to correct differences between the proposed integrated circuit design file and the verified cell data. | 10-02-2008 |
| 20080244484 | CIRCUIT DESIGN VERIFICATION SYSTEM, METHOD AND MEDIUM - A common-signal-terminal extracting section extracts common signal terminals from a netlist of the semiconductor device. An information converting section replaces the information of circuit components connected to the extracted common signal terminals by electric property information with reference a circuit-component library. A conformity detecting section determines whether or not the electric property information meets an electrical constraint rule with reference to an electrical constraint rule of the common signal terminals. An unverified-netlist creating section creates an unverified netlist from the netlist after excluding information of the common signal terminals. A simulation executing section executes logical simulation based on the created unverified netlist. | 10-02-2008 |
| 20080244485 | CAPACITANCE MODELING - A method of modeling capacitance for a structure comprising a pair of long conductors surrounded by a dielectric material and supported by a substrate. In particular, the structure may be on-clip coplanar transmission lines over a conductive substrate operated at very high frequencies, such that the substrate behaves as a perfect dielectric. It is assumed that the surrounding dielectric material is a first dielectric with a first permittivity (∈ | 10-02-2008 |
| 20080250363 | Design Support Apparatus for Semiconductor Devices - A design support apparatus supports wiring design for bond wires that connect a semiconductor chip and an interposer. The design support apparatus includes a creating unit that creates simulated design data simulating occurrence of fluctuation in an arrangement position of a semiconductor chip on an interposer and occurrence of fluctuation in bond wire connection terminal positions of the interposer, and an analyzing unit that analyzes, based on the simulated design data, deficiencies in manufacturing of semiconductor devices due to the fluctuation in the arrangement position of the semiconductor chip on the interposer and the fluctuation in the bond wire connection terminal positions of the interposer. | 10-09-2008 |
| 20080250364 | METHOD AND SYSTEM FOR VERIFICATION OF MULTI-VOLTAGE CIRCUIT DESIGN - Multi-voltage circuit design verification segregates design elements into iso-voltage-rail blocks. Information on cross-over connections between the iso-voltage-rail blocks is obtained. Voltage effects are simulated in the circuit design, and, based on the cross-over information, the simulation results are modified. This yields more accurate results of simulations for multi-voltage circuit designs. | 10-09-2008 |
| 20080250365 | Circuit State Scan-Chain, Data Collection System and Emulation and Verification Method - The present invention provides a circuit state scan-chain for emulating and verifying integrated circuit design, a data collection system and an emulation and verification method using the scan-chain. The said integrated circuit includes a number of registers and the corresponding input terminal combinational logics and output terminal combinational logics. The construction of the said scan-chain includes the first multiplex module and the second multiplex module arranged with regard to each register, changing the operation mode of the said integrated circuit by controlling the first multiplex module and the second multiplex module, enabling the said integrated circuit to switch among the normal mode, holding mode and snapshot mode, and enabling the registers to form a scan-chain loop in the snapshot mode. | 10-09-2008 |
| 20080250366 | NOISE CHECKING METHOD AND APPARATUS, AND COMPUTER-READABLE RECORDING MEDIUM IN WHICH NOISE CHECKING PROGRAM IS STORED - There is provided a technique in which internal wires of a large cell are spuriously patterned and treated as object of a noise check. Internal wires of a large cell are spuriously determined based on terminal information and wiring forbidden information of the large cell and are added to chip wires to be checked, from which an object wire to be checked and at least one affecting wire are selected, a noise value representing a degree at which the at least one affecting wire induces noise onto the signal of the object wire is calculated and the noise check is performed on the basis of the calculated noise check. | 10-09-2008 |
| 20080256500 | INTEGRATED OPC VERIFICATION TOOL - An integrated verification and manufacturability tool provides more efficient verification of integrated device designs than verification using several different verification components. The integrated verification and manufacturability includes a hierarchical database to store shared design data accessed by multiple verification components (e.g., layout versus schematic, design rule check, optical process correction, phase shift mask assignment and OPC verification and machine language conversion). The hierarchical database includes representations of one or more additional, or intermediate layer structures that are created and used by the verification components for operations performed on the design being verified. Use of a single hierarchical database having shared data for access and use by multiple verification components streamlines the verification process, which provides an improved verification tool. | 10-16-2008 |
| 20080263482 | Method and Apparatus for Small Die Low Power System-on-Chip Design with Intelligent Power Supply Chip - A method and system of system-on-chip design that provides the benefits of reduced design time, a smaller die size, lower power consumption, and reduced costs in chip design and production. The process seeks to remove the worst performance and worst power case scenarios from the design and application phases. This is accomplished by planning the power supply voltage in the design phase along with its tolerance with process corner and temperature combinations. The established plan is then applied with communications between power supply integrated circuits and load system-on-chip. | 10-23-2008 |
| 20080263483 | OPTICAL PROXIMITY CORRECTION METHOD, OPTICAL PROXIMITY CORRECTION APPARATUS, AND OPTICAL PROXIMITY CORRECTION PROGRAM, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, DESIGN RULE FORMULATING METHOD, AND OPTICAL PROXIMITY CORRECTION CONDITION CALCULATING METHOD - In the present invention, there is provided an optical proximity correction method including steps of: extracting a gate length distribution of a gate from a pattern shape of the gate of a transistor to be formed on a wafer; calculating electric characteristics of the gate; determining a gate length of a rectangular gate having electric characteristics equivalent to the calculated electric characteristics; calculating a corrective coefficient for describing an associated relationship between a statistical value of the extracted gate length distribution and the determined gate length; extracting a gate length distribution of a gate of a transistor by printing the design pattern, and calculating a gate length distribution representative value from the statistical value of the gate length distribution using the calculated corrective coefficient; and correcting the design pattern so that the calculated gate length distribution representative value will be a specification value. | 10-23-2008 |
| 20080263484 | Layout verification program, layout data and cell data - A layout verification program recorded on a computer-readable medium causes a computer to perform verification processing of a layout data of a semiconductor integrated circuit in which a plurality of cells are placed. The layout data includes a first identification layer in which predetermined patterns are placed. The predetermined patterns include: a first pattern placed on one corner of each cell; and a second pattern placed parallel to one side of each cell. The verification processing includes: (A) reading the layout data and a design rule from a memory device; (B) identifying an orientation of each cell by reference to the first pattern; (C) identifying a direction of each cell by reference to the second pattern; and (D) verifying whether or not the identified orientation and direction meet the design rule. | 10-23-2008 |
| 20080263485 | Verification support method and apparatus, and computer product - A verification support apparatus that verifies operation of a circuit includes a receiving unit, a detecting unit, and a determining unit. The receiving unit receives implementation description data of the circuit. Based on the implementation description data, the detecting unit detects a functional block that is in the circuit and includes an external input terminal that receives an external input signal. Based on a detection result of the detecting unit, the determining unit determines the functional block to verify an abnormal-event operation. The abnormal-event operation is an operation that differs from an operation implementing a function of the circuit. | 10-23-2008 |
| 20080263486 | VARIOUS METHODS AND APPARATUSES FOR CYCLE ACCURATE C-MODELS OF COMPONENTS - Various methods and apparatuses are described for generating a model of hardware components making up an interconnect that facilitates communications between Intellectual Property blocks in an integrated circuit coded in a software programming language at a high level of abstraction that is cycle accurate to a corresponding lower level of abstraction description of the hardware components making up the interconnect. The sub-components of the model at the high level of abstraction are tested in a simulation environment in parallel with the same sub-components of a model coded in a hardware description language at the low level of abstraction in order to verify the functional accuracy and cycle timing between the two models. After the sub-components are tested, the sub-components of the model at the high level of abstraction may be aggregated into a single model at the high level of abstraction that is functionally accurate and cycle accurate to the model at the low level of abstraction. | 10-23-2008 |
| 20080263487 | Multi-Format Consistency Checking Tool - A method and system for performing consistency checking of one or more design representations having different design types. A translator for each design type obtains information from each design needed to evaluate rules that are design type-neutral. The described examples also allow a user to add rules using predefined rule terms. In addition, certain examples allow the user to add terms to the rule set and to make new rules with the added terms. Each new term added to a rule set has a corresponding abstraction function in a translator for each design type. Thus, the abstraction functions are not design type-neutral. | 10-23-2008 |
| 20080270954 | System for and Method of Integrating Test Structures into an Integrated Circuit - A system and method for performing device-specific testing and acquiring parametric data on integrated circuits, for example ASICs, such that each chip is tested individually without excessive test time requirements, additional silicon, or special test equipment. The testing system includes a device test structure integrated into unused backfill space in an IC design which tests a set of dummy devices that are identical to a selected set of devices contained in the IC. The device test structures are selected from a library according to customer requirements and design requirements. The selected test structures are further prioritized and assigned to design elements within the design in order of priority. Placement algorithms use design, layout, and manufacturing requirements to place the selected test structures into the final layout of the design to be manufactured. | 10-30-2008 |
| 20080270955 | METHOD AND APPARATUS FOR MODIFYING EXISTING CIRCUIT DESIGN - The illustrative embodiments provide a computer implemented method and apparatus for modifying an existing circuit design. For a modification in a design of a circuit, the circuit design tool receives a code describing the modification, and a design of the circuit. The design of the circuit includes a first design, which includes a design for a number of metallic layers in the circuit. The design of the circuit further includes a second design, which includes and a design for a number of non-metallic layers in the circuit. The circuit design tool identifies a set of hooks, a set of disconnected components, and a set of filler cells in the design of the circuit. The circuit design tool produces a modification design, which is implemented in a revision of the first design, using the code, and one or more of the hooks, the disconnected components, and the filler cells. | 10-30-2008 |
| 20080270956 | SEMICONDUCTOR INTEGRATED CIRCUIT DESIGNING METHOD, SEMICONDUCTOR INTEGRATED CIRCUIT DESIGNING APPARATUS, AND RECORDING MEDIUM STORING SEMICONDUCTOR INTEGRATED CIRCUIT DESIGNING SOFTWARE - According to the present invention, there is provided a method for designing a circuit, having, generating electrical filter graphic data indicating a candidate portion where a dimensional value of a layout pattern is permitted to deviate from a design value by taking account of an electrical characteristic, and electrical filter data indicating the permissible dimensional value in the candidate portion of the layout pattern by taking account of the electrical characteristic, by using circuit diagram data, a static timing analytical result, and a result of a circuit simulation, and store them in the storage unit, generating design data by using the electrical filter graphic data, and form a layout pattern by using the design data, detecting a lithography error by performing a lithography simulation on the layout pattern, determining by using the electrical filter database whether the error requires correction by taking account of the electrical characteristic, correcting the layout if the error is found to require the correction, and outputting a result of the correction of the layout. | 10-30-2008 |
| 20080270957 | SEMICONDUCTOR INTEGRATED CIRCUIT DESIGNING APPARATUS, SEMICONDUCTOR INTEGRATED CIRCUIT DESIGNING METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of logical elements and a plurality of wiring lines. The plurality of wiring lines have a wiring line which connects the logical elements to each other, and a wiring line which is disconnected on one end from one of the logical elements and connected on the other end to another one of the logical elements. | 10-30-2008 |
| 20080270958 | METHOD AND SYSTEM FOR DEBUG AND TEST USING REPLICATED LOGIC - A method and system for debug and test using replicated logic is described. A representation of a circuit is compiled. The circuit includes a replicated portion and delay logic to delay inputs into the replicated portion. The circuit may also include trigger logic and clock control logic to enable execution of the replicated portion of the circuit to be paused when a trigger condition occurs. The compiled representation of the circuit may be programmed into a hardware device. A debugger may then be invoked. One or more triggering signals are selected. For each selected triggering signal, one or more states are selected to setup a trigger condition. The hardware device may then be run. The replicated portion of the circuit will be paused when the trigger condition occurs. The states of registers in the replicated portion of the circuit and the sequence of inputs that led to the trigger condition are recorded. This recorded data may then used to generate a test to be run on a software simulator when the circuit is modified. | 10-30-2008 |
| 20080276207 | Modeling the skin effect using efficient conduction mode techniques - Described herein are embodiments of methods for extracting various high frequency parameters for a circuit design. In one exemplary embodiment, circuit design information indicating at least a geometric layout of conductors in the circuit design and a desired frequency of operation for the circuit design is received. Conduction modes representing distribution functions for currents in the conductors at the desired frequency of operation are defined. A conduction mode matrix including matrix elements based on the defined conduction modes is generated. Values for one or more matrix elements are computed by decomposing integrands for calculating the matrix elements into simplified terms that are less computationally intensive than the integrands and computing the values of the simplified terms. The values for the one or more matrix elements can be stored (e.g., on one or more computer-readable media). | 11-06-2008 |
| 20080282209 | System for and Method of Verifying IC Authenticity - A verification system disclosed herein uses the unique signatures of an IC to perform authentication of the IC after the IC is shipped to a customer. The verification system records the fingerprint and associated IC identifier with the fingerprint into a data structure. The data structure is supplied to the customer for use in the customer's own security systems. When an IC interfaces with the customer's system, the verification system requests the IC's identifier and selects a data structure corresponding to that IC identifier. The verification system then performs a test on the IC (e.g. remotely operates the IC at 1V), records the resulting data and compares the test results with the corresponding data in the data structure. If a predetermined condition is satisfied then the IC is verified to be authentic. If not, the verification system responds, for example, by flagging the customer's security system. | 11-13-2008 |
| 20080282210 | System And Method For Product Yield Prediction - A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process. These yield predictions are then used to determine which areas in the fabrication process require the most improvement. | 11-13-2008 |
| 20080288901 | Formally deriving a minimal clock-gating scheme - The present invention provides a fully automatic method for obtaining a circuit having minimized power consumption due to clock-gating. A circuit design to be optimized is modified to a reduced power modified design and associated with a clock gating scheme. Verification tools compare the modified design with the original design to a predetermined trigger-events to determine if the modified design can be used. Further modifications may be made iteratively until an optimal design is achieved. | 11-20-2008 |
| 20080288902 | CIRCUIT DESIGN VERIFICATION METHOD AND APPARATUS AND COMPUTER READABLE MEDIUM - There is provided with a circuit design verification method including: accepting input of a circuit description which describes a circuit by using a plurality of conditional statements each including one or more conditional elements; extracting each conditional statement included in the circuit description and each conditional element included in the conditional statements; executing the circuit description by using test data for the circuit; and generating a table including verification information for each conditional statement, the verification information representing (A1) whether each conditional element has been always true, (A2) whether each conditional element has been always false, or (A3) whether each conditional element has been both true and false when the conditional statement is satisfied. | 11-20-2008 |
| 20080288903 | Generating testcases based on numbers of testcases previously generated - An apparatus, computer system, and storage medium that, in an embodiment, receive elements and a goal for each of the elements. In various embodiments, the elements may represent commands or parameter values for a device to be tested. Testcases are generated based on the elements. If the numbers of testcases for the elements are equally distant from their goals, then a new testcase is generated based on an element chosen at random. But, if the numbers of testcases are not equally distant from their goals, then the new testcase is generated based on the element whose number of testcases if furthest from its respective goal. The number of testcases associated with the chosen element is then incremented, and the process is repeated. In this way, the generated testcases are based on the numbers of previously generated testcases, which, in an embodiment, results in more complete coverage of testcases for the device under test. | 11-20-2008 |
| 20080295049 | PATTERN DESIGNING METHOD, PATTERN DESIGNING PROGRAM AND PATTERN DESIGNING APPARATUS - An embodiment of the invention provides a pattern designing method, including the steps of carrying out transfer simulation calculation and step simulation calculation by using physical layout data produced from circuit design data, and comparing a result of the transfer simulation calculation and the step simulation calculation with a preset standard; and carrying out calculation for electrical characteristics by using parameters obtained from the physical layout when as a result of the comparison, the preset standard is fulfilled, and carrying out calculation for the electrical characteristics by reflecting the result of the transfer simulation calculation and the step simulation calculation in the parameters when as the result of the comparison, the preset standard is not fulfilled, thereby extracting the parameters. | 11-27-2008 |
| 20080301597 | Method to Determine the Root Causes of Failure Patterns by Using Spatial Correlation of Tester Data - A method for determining the root causes of fail patterns in integrated circuit chips is provide wherein a known integrated circuit chip layout is used to identify a plurality of potential defects and a plurality of potential fail patterns in the integrated circuit chip. Correlations between the potential defects and the potential fail patterns that result from those defects are identified. Based on this identification, the potential fail patterns are grouped by common potential defect. An actual integrated circuit chip that is manufactured in accordance with the test layout is tested for failure patterns. These failure patterns are then compared to the groupings of potential fail patterns. When a match is found, that is when a given group of fail patterns is found in the actual integrated circuit chip, then the potential defect associated with the potential fail patterns to which the actual fail patterns are matched is identified. This defect is the root cause of the failure pattern in the actual chip. | 12-04-2008 |
| 20080301598 | METHOD FOR CHECKING CONSTRAINTS EQUIVALENCE OF AN INTEGRATED CIRCUIT DESIGN - The equivalence of two or more constraint files of an integrated circuit (IC) design are checked. The comparison is performed between files at the same stage of design, files that correspond to different stages of the design flow, or between top-level and block-level constraint files. | 12-04-2008 |
| 20080301599 | METHOD FOR RAPID ESTIMATION OF LAYOUT-DEPENDENT THRESHOLD VOLTAGE VARIATION IN A MOSFET ARRAY - An automated method for estimating layout-induced variations in threshold voltage in an integrated circuit layout. The method begins with the steps of selecting a diffusion area within the layout for analysis. Then, the system identifies Si/STI edges on the selected area as well as channel areas and their associated gate/Si edges. Next, the threshold voltage variations in each identified channel area are identified, which requires further steps of calculating threshold voltage variations due to effects in a longitudinal direction; calculating threshold voltage variations due to effects in a transverse direction; and combining the longitudinal and transverse variations to provide an overall variation. Finally, a total variation is determined by combining variations from individual channel variations. | 12-04-2008 |
| 20080301600 | CAD apparatus and check support apparatus - In a computer aided design (CAD) apparatus, an association-data acquiring unit acquires association data that defines an association between pins of a first connector and those of a second connector to be connected to the first connector, and an assignment of signals to the pins. A part-information acquiring unit acquires information including a symbol of the first connector. A layout-condition acquiring unit acquires a layout condition to lay out the symbol of the first connector on a circuit diagram. A circuit diagram creating/updating unit lays out the symbol of the first connector on the circuit diagram based on the layout condition, and adds a net name indicating a signal assigned to each of the pins to the symbol. | 12-04-2008 |
| 20080301601 | TECHNIQUES FOR USE WITH AUTOMATED CIRCUIT DESIGN AND SIMULATIONS - Various techniques for use in connection with automated circuit design and simulations are disclosed. In some embodiments, a method includes receiving initial condition signals from circuitry in a chip, and correlating values of at least some of the initial condition signals with objects in a hardware description language (HDL) used in simulation, wherein the HDL was used in describing at least some of the circuitry in the chip. Still other embodiments involve memory substitutions. Replicated circuitry may be in the same chip(s) are the design circuitry or a different chip(s). Still other embodiments are described. | 12-04-2008 |
| 20080301602 | METHOD AND APPARATUS FOR PERFORMING FORMAL VERIFICATION USING DATA-FLOW GRAPHS - An equivalency testing system, for formally comparing an RTLM and HLM, is presented. RTLM and HLM are first converted into DFGs RTLM | 12-04-2008 |
| 20080301603 | CLOCK-GATED MODEL TRANSFORMATION FOR ASYNCHRONOUS TESTING OF LOGIC TARGETED FOR FREE-RUNNING, DATA-GATED LOGIC - Asynchronous behavior of a circuit is modeled by modifying latches in a netlist to add an extra port to the latches, e.g., a single-port latch is transformed into a dual-port latch. Each input port has an enable line and a data input. The data input in the added port is a feedback line from the latch output, and the enable line in the added port is the logical NOR of all of the original enable lines. By adding this extra latch port in the higher-level model, it becomes possible to introduce assertion logic to ensure that one and only one latch port for a given latch is ever active during the same simulation cycle. The model can then be tested earlier in the design methodology prior to the availability of the post-synthesis netlist. The model can also be used in both simulation and formal or semi-formal verification. | 12-04-2008 |
| 20080313584 | Logic verification method - A logic verification method is disclosed to a computer to conduct a logic verification process by using a state machine based on a verification property, including the steps of (a) displaying at lease one waveform generated based on a logic verification result of the logic verification process, (b) displaying the verification property, and controlling the step (a) and the step (b) in response to an operation input. The step (c) controls the step (b) to display a first respective portion of a description of the verification property corresponding to a first desired portion of the at least one waveform selected by the operation input by correlating to the first desired portion, by a different display method from other portions in response to the operation input onto the at least one waveform being displayed in the step (a). | 12-18-2008 |
| 20080313585 | Method of verifying semiconductor integrated circuit and design program - A method of verifying a semiconductor integrated circuit is provided. A controlling cell and a controlled cell controlled by a control signal output from the controlling cell are placed in an IO region of the semiconductor integrated circuit. The method includes: (A) providing a library that includes requirement information specifying the controlling cell required by the controlled cell; (B) obtaining a region information indicating a region within the IO region in which a signal interconnection through which the control signal is transmitted is provided; and (C) verifying whether or not the specified controlling cell is placed within the region, in a case where the controlled cell is placed within the region. | 12-18-2008 |
| 20080313586 | Resistance net generating apparatus for circuit simulation - In an aspect of the present invention, a resistance net generating apparatus includes a dividing section configured to acquire a data of a wiring pattern which contains connection position with vias and to divide the wiring pattern into rectangular patterns; a division pattern processing section configured to set nodes and resistances base on the rectangular patterns; and an output section configured to output positions of the nodes and the resistances as a resistance net specifying data. The wiring pattern is represented by sidelines extending into an X direction and a Y direction orthogonal to the X direction. The dividing section divides the wiring pattern into the rectangular patterns by extension lines extending from the sidelines into an inside of the wiring pattern. | 12-18-2008 |
| 20080313587 | Apparatus and method for performing a sequence of verification tests to verify a design of a data processing system - An apparatus and method are provided for performing a sequence of verification tests to verify the design of a data processing system. The apparatus comprises a system under verification representing the design of the data processing system, the system under verification including a component model representing at least one hardware component of the data processing system. The component model includes an interface module through which the component model interacts with other portions of the system under verification during performance of the verification tests. An alternative model is provided for representing the hardware component for selected verification tests, and the interface module comprises a verification interface module which is responsive to switch criteria specified by the alternative model to switch in the alternative model in place of the component model. Accordingly, by such an approach, the alternative model can take the place of the component model during performance of the selected verification tests. This maintains system integrity of the system under verification, whilst providing a simple and effective mechanism for enabling the alternative model to take the place of the component model for certain specific verification tests, for example when testing corner cases in the design. | 12-18-2008 |
| 20080320422 | Design Rule Checking System - In a design rule checking system for checking whether or not an integrated circuit design complies with design rules specifying limit values for respective geometric parameters, non-binary functions are used to model the way in which systematic yield loss varies with the value of the geometric parameters. This enables a value to be assigned to systematic yield loss in cases where the geometric parameter is compliant with the design rule but takes a value close to the design rule limit. | 12-25-2008 |
| 20080320423 | SYSTEM AND METHOD TO PROTECT COMPUTING SYSTEMS - A system and method for protecting computing systems, and more particularly a system and method which a dedicated hardware component configured to communicate with a protection program. A computer hardware subsystem includes a memory comprising content. The content is at least a list of files which have been modified within a predetermined period of time. The list of files is a subset of files of a hard drive. A dedicated hardware component is configured to track the files which have been modified and provide a location of the files to the memory. A communication link between the dedicated hardware component and a protection program provides the protection program with the subset of files of the hard drive as referenced by the memory content. The invention is also directed to a design structure on which a circuit resides. | 12-25-2008 |
| 20080320424 | VALIDATION OF ELECTRICAL PERFORMANCE OF AN ELECTRONIC PACKAGE PRIOR TO FABRICATION - An electrical resistance determination method. Input to the method includes a description of at least one electrical network within a substrate. The description includes specification of a plurality of first ports on a first side of the substrate, and a plurality of second ports on a second side of the substrate, for each electrical network. All of the first ports are electrically isolated from one another. All of the second ports are electrically connected to a common voltage. A computer readable program code, which is executed by a processor of a computer system computes for a first electrical network of the at least one electrical network an electrical resistance between each first port and a port of the second ports. The computer code may also display a perspective plot of the computed electrical resistances as a bar oriented about normal to each first port. | 12-25-2008 |
| 20090007034 | Device, System, and Method for Correction of Integrated Circuit Design - Device, system and method of correcting an integrated circuit design. For example, a method includes receiving a list of one or more root points for an active netlist that requires logic correction, wherein the root points correlate between elements of the active netlist and elements of a re-synthesized netlist that is based on a high-level correction for the integrated circuit design; automatically identifying in the active netlist a driving logic cone for at least one of the root points; and automatically identifying in the re-synthesized netlist a driving logic cone for the respectively correlated root point, including one or more corrected logic elements that correspond to the one or more identified flawed logic elements. | 01-01-2009 |
| 20090007035 | Accurate Parasitic Capacitance Extraction for Ultra Large Scale Integrated Circuits - A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC. | 01-01-2009 |
| 20090007036 | Integrated Fin-Local Interconnect Structure - Embodiments of the invention generally relate to methods, systems and design structures for semiconductor devices, and more specifically to interconnecting semiconductor devices. A silicide layer may be formed on selective areas of a fin structure connecting one or more semiconductor devices or semiconductor device components. By providing silicided fin structures to locally interconnect semiconductor devices, the use of metal contacts and metal layers may be obviated, thereby allowing formation of smaller, less complex circuits. | 01-01-2009 |
| 20090007037 | Hybrid Fully-Silicided (FUSI)/Partially-Silicided (PASI) Structures - Embodiments of the invention generally relate to methods, systems and design structures for semiconductor devices and more specifically to forming partially silicided and fully silicided structures. Fabricating the partially silicided and fully silicided structures may involve creating one or more gate stacks. A polysilicon layer of a first gate stack may be exposed and a first metal layer may be deposited thereon to create a partially silicided structure. Thereafter, a polysilicon layer of a second gate stack may be exposed and a second metal layer may be deposited thereon to form a fully silicided structure. In some embodiments, the polysilicon layers of one or more gate stacks may not be exposed, and resistors may be formed with the unsilicided polysilicon layers. | 01-01-2009 |
| 20090007038 | HYBRID COUNTEREXAMPLE GUIDED ABSTRACTION REFINEMENT - Systems and methods are disclosed for performing counterexample guided abstraction refinement by transforming a design into a functionally equivalent Control and Data Flow Graph (CDFG); performing a hybrid abstraction of the design; generating a hybrid abstract model; and checking the hybrid abstract model. | 01-01-2009 |
| 20090007039 | HIERARCHICAL FEATURE EXTRACTION FOR ELECTRICAL INTERACTION CALCULATIONS - A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions. | 01-01-2009 |
| 20090013291 | Generating A Base Curve Database To Reduce Storage Cost - An enhanced library accessible by an EDA tool can include a base curve database and a plurality of curve data sets. Each curve data set refers to a standard cell having certain timing characteristics. To determine those timing characteristics, each curve data set identifies at least one base curve (in the base curve database) as well as a starting current, a peak current, a peak voltage, and a peak time. In one embodiment, each base curve can be normalized. The base curve(s), the starting current, peak current, peak voltage, and peak time can accurately model the functioning of the IC device, e.g. represented by an I(V) curve. | 01-08-2009 |
| 20090019405 | INTEGRATED CIRCUIT DEVICE EVALUATION DEVICE, EVALUATION METHOD, AND EVALUATION PROGRAM - Time-axis data that include the peak waveform and the clock frequency of the power supply current when the LSI is switched are inputted to the LSI information input unit, and the LSI equivalent circuit creation unit creates an equivalent circuit of the LSI on the basis of the time-axis data. The time-axis/frequency-axis conversion unit converts the time-axis data to frequency-axis data. The equivalent circuit synthesis unit synthesizes the equivalent circuits of the printed wiring substrate, the power supply regulator, and the LSI to create a single equivalent circuit; the frequency-axis circuit analysis unit performs frequency-axis analysis of the single equivalent circuit; and the frequency-axis/time-axis conversion unit converts the results to time-axis data. The amount of fluctuation of the power supply voltage of an integrated circuit device can thereby be evaluated in a short time. | 01-15-2009 |
| 20090019406 | VERIFICATION APPARATUS AND VERIFICATION METHOD - A variable is allocated to a statement that designates an event associated with a function call in an assertion. Generation of the event at an arbitrary time on a continuous time series is detected, and a value corresponding to a meaning of the statement is assigned to the variable. Whether or not a condition corresponding to the meaning of the statement is satisfied is determined based on the value of the variable at each time on a discrete time series. | 01-15-2009 |
| 20090019407 | CLOCK SUPPLY CIRCUIT AND METHOD OF DESIGNING THE SAME - A clock supply circuit according to the present invention has a clock tree structure, supplies a clock signal to operating elements, includes driving elements arranged in levels in the clock tree structure and includes connection lines which connect output terminals of the driving elements either to input terminals of driving elements arranged in levels immediately succeeding the levels of the respective driving elements with which the respective connection lines start or to input terminals of the operating elements with which last ones of the connection lines end, and in the clock supply circuit, the connection lines include first lines formed in a standard wiring layer and at least one second line formed above a circuit block which uses the standard wiring layer, and at least one second line formed above the circuit block is in a predetermined wiring layer higher than the standard wiring layer. | 01-15-2009 |
| 20090019408 | Production method, design method and design system for semiconductor integrated circuit - A production method for a semiconductor integrated circuit includes: creating a model parameter of an element constituting a cell, wherein the model parameter is defined by a design value and a distribution function of variability from the design value; performing a circuit simulation using the model parameter to create a response function that expresses response of cell characteristic to the model parameter; and creating a statistical cell library by using the response function. The statistical cell library used for circuit design and verification gives an expected value and statistical variation of the cell characteristic. The statistical variation is expressed by a product of the distribution function and sensitivity. The sensitivity is calculated based on the response function. When the model parameter is updated, the statistical cell library is updated by using the post-update model parameter and the response function without performing a circuit simulation. | 01-15-2009 |
| 20090024969 | SEMICONDUCTOR CHIP DESIGN HAVING THERMAL AWARENESS ACROSS MULTIPLE SUB-SYSTEM DOMAINS - A thermally aware design automation suite integrates system-level thermal awareness into the design of semiconductor chips. A thermal analysis engine performs fine-grain thermal simulations of the semiconductor chip based on thermal models and boundary conditions for all thermally significant structures in the chip and the adjacent system that impact the temperature of the semiconductor chip. The thermally aware design automation suite uses the simulations of the thermal analysis engine to repair or otherwise modify the thermally significant structures to equalize temperature variations across the chip, impose specified design assertions on selected portions of the chip, and verify overall chip performance and reliability over designated operating ranges and manufacturing variations. The thermally significant structures are introduced or modified via one or more of: change in number, change in location, and change in material properties. | 01-22-2009 |
| 20090024970 | Floor plan evaluating method, floor plan correcting method, program, floor plan evaluating device, and floor plan creating device - A floor plan evaluation method by which a floor plan can be quantitatively evaluated. The floor plan evaluation method includes first extracting a plurality of specified elements, which are specified in advance from data on a floor plan which is made automatically by, e.g., a floor planner, second obtaining an individual evaluation value on each of a plurality of individual evaluation items on the basis of the plurality of specified elements extracted in the first step, and third calculating an integrated evaluation value on the floor plan on the basis of a plurality of individual evaluation values obtained in the second step. Then, a plurality of integrated evaluation values obtained by executing the first to third operations for a plurality of floor plans are compared with one another to relatively evaluate the plurality of floor plans. | 01-22-2009 |
| 20090024971 | CURSOR PATH VECTOR ANALYSIS FOR DETECTING CLICK FRAUD - A system and method for detecting click fraud where data is received corresponding to a tracking of movement of a cursor on a web page. The movement of the cursor is associated with at least one vector. The at least one vector represents at least a portion of the cursor movement. A confidence level useable in the determination of click fraud is determined. The confidence level is responsive to analysis of the at least one vector representing at least a portion of the cursor movement. | 01-22-2009 |
| 20090024972 | STRUCTURES OF POWERING ON INTEGRATED CIRCUIT - Design structures, method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating element therefor; a processing unit including: a comparator for comparing the temperature against a predetermined temperature value, a controller, which in the case that the temperature is below the predetermined temperature value, delays functional operation of the IC and controls heating of the region of the IC, and a monitor for monitoring the temperature in the region; and wherein the controller, in the case that the temperature rises above the predetermined temperature value, ceases the heating and initiates functional operation of the IC. | 01-22-2009 |
| 20090031263 | METHOD AND SYSTEM FOR ANALYZING AN INTEGRATED CIRCUIT BASED ON SAMPLE WINDOWS SELECTED USING AN OPEN DETERMINISTIC SEQUENCING TECHNIQUE - Disclosed herein are embodiments of a system and an associated method for analyzing an integrated circuit to determine the value of a particular attribute (i.e., a physical or electrical property) in that integrated circuit. In the embodiments, an open deterministic sequencing technique is used to select a sequence of points representing centers of sample windows in an integrated circuit layout. Then, the value of the particular attribute is determined for each sample window and the results are accumulated in order to infer an overall value for that particular attribute for the entire integrated circuit layout. This sequencing technique has the advantage of allowing additional sample windows to be added and/or the sizes and shapes of the windows to be varied without hindering the quality of the sample. | 01-29-2009 |
| 20090031264 | System and method for finding electromigration, self heat and voltage drop violations of an integrated circuit when its design and electrical characterization are incomplete - A system and method for finding electromigration (EM), self heat (SH) and voltage drop/droop violations of an integrated circuit, when its design and electrical characterization are not complete, are disclosed. The method includes analyzing polygons for average, root-mean-square (RMS) and Ipeak current densities and voltages of a mask layout block and obtaining one or more electromigration, self heat and/or voltage drop/droop rules associated with the polygon from a technology and an external constraints file. The system reads the available design simulation data to calculate the average, RMS and Ipeak current densities and voltages, and estimates the current densities and voltages when no data available. The method also includes topological analysis of the mask layout and analysis of the electrical circuit elements of the design. The method finds the polygons where the current densities are higher than electromigration and self heat rules as taken from technology or external constraints file. The method also finds the polygons where the current densities are higher than in other polygons, by the defined threshold. The method also finds the nodes where the voltage drop/droop is larger than the rule. The method also finds the polygons where the voltage drop/droop is larger than in other polygons by the defined threshold. The method and system work on GDSII, GDSIII format files and on industry standards layout editors' database. | 01-29-2009 |
| 20090031265 | IC DESIGN MODELING ALLOWING DIMENSION-DEPENDENT RULE CHECKING - A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core portion of Voronoi diagrams to partition edges of a shape into intervals and assigns at least one dimension to each interval such as a local width and spacing. Dimension assignment can be made as any desirable definition set for width and spacing, e.g., numerical values or continuous dimension-dependent design rules. Design rule checking for dimension-dependent spacing rules given in any arbitrary functional form of width and spacing is possible. Application of the invention can be made anywhere the width and spacing of VLSI shapes play a role, e.g., relative to a single edge, neighboring edges, neighboring shapes, and/or for edges in more than one layer of the IC design. | 01-29-2009 |
| 20090031266 | IC DESIGN MODELING ALLOWING DIMENSION-DEPENDENT RULE CHECKING - A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core portion of Voronoi diagrams to partition edges of a shape into intervals and assigns at least one dimension to each interval such as a local width and spacing. Dimension assignment can be made as any desirable definition set for width and spacing, e.g., numerical values or continuous dimension-dependent design rules. Design rule checking for dimension-dependent spacing rules given in any arbitrary functional form of width and spacing is possible. Application of the invention can be made anywhere the width and spacing of VLSI shapes play a role, e.g., relative to a single edge, neighboring edges, neighboring shapes, and/or for edges in more than one layer of the IC design. | 01-29-2009 |
| 20090031267 | Layout correcting method for semiconductor integrated circuit and layout correcting device for semiconductor integrated circuit - A layout correction method, which minimize influence of changing a dummy metal on timings when signal wirings are corrected after completion of arrangement design of wirings including dummy metals, includes the steps of correcting, on a layout of a semiconductor integrated circuit in which at least signal wirings and a dummy metal are arranged, the signal wirings by ignoring the dummy metal, checking a wiring error between the dummy metal and the signal wirings corrected by ignoring the dummy metal, removing the dummy metal that causes the wiring error if the wiring error is found, and embedding another dummy metal after the dummy metal is removed. | 01-29-2009 |
| 20090037857 | METHODS FOR DESIGN RULE CHECKING WITH ABSTRACTED VIA OBSTRUCTIONS - Methods of treating via obstructions during design rule checking. The method comprises examining the size of the via obstruction with respect to a minimum size and a minimum spacing constraint of a design rule. Based upon the comparison, a neighboring via count for a number of via shapes neighboring the via obstruction may be initialized to equal a positive integer. Based upon the comparison, the via obstruction may be represented with a plurality of smaller via shapes during design rule checking. | 02-05-2009 |
| 20090037858 | Method For Automatic Maximization of Coverage in Constrained Stimulus Driven Simulation - A computer increases coverage in simulation of a design of a circuit by processing goals for coverage differently depending on whether or not the goals are on input signals of the circuit. Specifically, goals on input signals are used to automatically formulate constraints (“directly-derived constraints”) on values of input signals in test vectors. Goals on non-input signals (e.g. internal/output signals) are used with correlations to automatically formulate more additional constraints (“correlation-derived constraints”), by use of goals on non-input signals. The correlations indicate which non-input signals are associated with which input signals. The correlations are received from, for example, a human designer of the circuit. Depending on the embodiment, one or more of the automatically derived constraints are used with human-supplied constraints, to generate test vectors e.g. using a constraints solver, such as a satisfiability (SAT) engine. The test vectors are supplied to a simulator for functional verification. | 02-05-2009 |
| 20090037859 | METHOD FOR AUTOMATICALLY EXTRACTING A FUNCTIONAL COVERAGE MODEL FROM A CONSTRAINT SPECIFICATION - A computer is programmed to automatically generate in memory, goals for functional verification of a design of a circuit by use of constraints that are specified in the normal manner. Specifically, a predetermined set of rules are automatically applied to the constraints, on random values for signals to be input to the circuit during simulation of the design. Application of the rules identifies one or more templates of goal(s) to be met. The computer is programmed to automatically use constraint(s) and template(s) to instantiate goal(s) in memory. Each goal identifies a signal to be input to the circuit, and defines a counter for a value of the signal. The goals are used in the normal manner, i.e. used to measure coverage of functional verification during simulation of the design of the circuit. | 02-05-2009 |
| 20090044158 | METHOD, AND EXTENSIONS, TO COUPLE SUBSTRATE EFFECTS AND COMPACT MODEL CIRCUIT SIMULATION FOR EFFICIENT SIMULATION OF SEMICONDUCTOR DEVICES AND CIRCUIT - This invention comprises a new method to couple simulation of electronics circuits (using compact models) with simulation of physical effects which require a PDE (partial differential equation) based simulation, for semiconductor MOSFET based devices and circuits. In particular the method can be used to capture high injection substrate effects such as single event transients (SET), latch-up, ESD, or thermal effects. Bipolar substrate effects are handled correctly and completely with this algorithm. The method extends the applicability of technology CAD (TCAD) to multiple devices. | 02-12-2009 |
| 20090049416 | Computer Program Product for Extending Incremental Verification of Circuit Design to Encompass Verification Restraints - An incremental verification method includes eliminating verification constraints from a first netlist and using the resulting netlist to create a constraint-free composite netlist suitable for determining equivalence between the first netlist and a second netlist of a design. Eliminating a constraint from a netlist may include adding a modified constraint net where the modified constraint net is FALSE for all cycles after any cycle in which the original constraint is FALSE. The method may include, instead of eliminating constraints, determining that the verification result is a target-not-asserted result and that the second netlist constraints are a superset of the first netlist constraints or that the verification result is a target-asserted result and that the first netlist constraints are a superset of the second netlist constraints. In either case, the method may include creating the composite netlist by importing all of the original constraints into the composite netlist. | 02-19-2009 |
| 20090049417 | METHOD OF DESIGNING A CIRCUIT FOR OPTIMIZING OUTPUT BIT LENGTH AND INTEGRATED CIRCUIT THEREFOR - In a circuit designing method for arithmetic elements to be employed in digital signal processing, a program is produced so that a directive is added to a target arithmetic operation which provides an overflow determination about desired digital signal processing. On the basis of this program, behavioral synthesis is performed. By adding an overflow detector to the target arithmetic operation, an RTL-description circuit is produced. The operation verification of the RTL-description circuit is performed to obtain the detection results of the overflow detector. When the RTL-description circuit is again produced on the basis of the operation verification results, the output bit length of the target arithmetic operation is optimized on the basis of the overflow detection results so that overflow is suppressed, whereby an optimized RTL-description circuit can be produced. | 02-19-2009 |
| 20090055784 | METHOD FOR VERIFYING SAFETY APPARATUS AND SAFETY APPARATUS VERIFIED BY THE SAME - A verification method is provided for verifying a safety apparatus including a programmable logic device having a plurality of functional elements. The verification method includes the steps of exhaustively verifying the plurality of functional elements on actual hardware, generating a functional element that is the same as one of the functional elements verified on the actual apparatus using a predetermined hardware description language, independently logic-synthesizing each generated functional element into a plurality of first net lists, generating a connection function between the functional elements using the predetermined hardware description language, logic-synthesizing the generated connection function into a second net list corresponding to the connection function, synthesizing the first net lists with the second net list to generate a third net list, writing a logic circuit into the programmable logic device on the basis of the third net list, and verifying the actual programmable logic device. | 02-26-2009 |
| 20090064064 | Device, System and Method for Formal Verification - Device, system and method of efficient automata-based implementation of liveness properties for formal verification. A system according to embodiments of the invention includes a property transformation module to receive an assume verification directive on a liveness property in a property specification language, and to translate the property a fairness statement that uses a deterministic automaton. The deterministic automaton is exponential in the size of the input property. The assume verification directive may be transformed into a strong suffix implication in the property specification language. | 03-05-2009 |
| 20090064065 | Method of verifying circuit and computer-readable storage medium for storing computer program - A method of verifying a circuit for use in an apparatus for verifying a circuit operation indicated by circuit information, the circuit including a plurality of logic circuits and at least one connection line between the logic circuits, the method includes: obtaining information of a plurality of pieces of asynchronous circuits from the circuit information; determining information of asynchronous circuits of a first type and a second type stored in a library; extracting information of an asynchronous circuit of a third type including the asynchronous circuits of the first type and the second type; and extracting verification information associated with the information of the asynchronous circuit of the third type, for verifying the circuit. | 03-05-2009 |
| 20090064066 | METHOD AND APPARATUS FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT - A method, apparatus, and recording medium including computer instructions for estimating the size of a core section of a semiconductor integrated circuit are provided. The method includes calculating a total net length of wires of nets and usable channel length of the core section by referring to circuit information and a layout parameter that are used to design the semiconductor integrated circuit. The method includes determining a size of the core section that satisfies conditions based on total net length and usable channel length. | 03-05-2009 |
| 20090070718 | METHODOLOGY FOR PLACEMENT BASED ON CIRCUIT FUNCTION AND LATCHUP SENSITIVITY - A structure, apparatus and method for circuits to minimize sensitivity to latch. The method includes, for example, identifying element density of at least one functional circuit block and element attributes of elements associated with the at least one functional circuit block. An element density function parameterized from the element attributes is formed. The placement of the at least one functional circuit block is modified relative to other functional circuit blocks based on the element density function to substantially eliminate latching effects in a circuit. | 03-12-2009 |
| 20090077510 | RULES AND DIRECTIVES FOR VALIDATING CORRECT DATA USED IN THE DESIGN OF SEMICONDUCTOR PRODUCTS - A method to validate data used in a design of a semiconductor product currently in a partially fabricated state is disclosed. The partially fabricated state having a plurality of layers up to and including a first conductive layer. The method generally includes the steps of (A) adding a second conductive layer from a user specification to an application set, the application set having a plurality of resources that define the semiconductor product, (B) validating a new resource in the user specification against the resources in the application set, (C) adding the new resource to the application set upon passing the validating and (D) propagating the new resource throughout a description of the semiconductor product, the description being stored in a computer-readable medium. | 03-19-2009 |
| 20090077511 | Generating Constraints in a Class Model - A method of generating code from a class model for a modeled system. The class model specifies a plurality of elements of a modeling language and dependencies between elements of a plurality of elements. In operations the method analyzes the class model to identify a first possible source of under-specification with respect to the modeled system in the class model by using pattern recognition to find an occurrence of a first problem pattern of a plurality of problem patterns in the class model, the plurality of problem patterns are then stored in a repository. The method also includes identifying a set of constraint patterns where the at least first constraint pattern is linked in the repository to the first problem pattern. A user may then select a constraint pattern which is utilized in instantiating constraints and generating code based on the class model and the instantiated constraints. | 03-19-2009 |
| 20090077512 | MATCHING DEVICE - A matching device includes a first storing unit, a second storing unit, and a semiconductor device. The semiconductor device includes a control unit and a circuit unit. In the circuit unit, a first circuit including distance calculating circuits that calculate distances between unknown characters and dictionary characters and a selecting circuit that selects P distances having smallest values and character codes corresponding to the distances is configured, and then a second circuit including a permutation circuit that outputs distances in order from one having a smallest value and outputs character codes corresponding to the distances is configured. | 03-19-2009 |
| 20090077513 | GENERALIZED CONSTRAINT COLLECTION MANAGEMENT METHOD - Techniques are provided to allow users of Electronic Design Automation (EDA) tools to define constraint template types for efficiently associating constraints with design objects to specify design intent. Processes for creating and validating the constraints are provided by user-defined plug-ins, thereby allowing users to annotate circuit designs with constraints for proprietary layout and fabrication processes without exposing the constraints to tool vendors or competitors. The constraints are re-created from the template types whenever the circuit design is loaded into the EDA tool, so that the constraints are based upon the latest version of the template type. The constraints are also re-created when validation fails. Constraint groups are reusable in different designs, technology nodes, and processes because they automatically expand to provide the specific constraints to achieve a goal. The specific constraints in a template type can be modified as technology changes, and the modification will automatically be applied to the design objects. | 03-19-2009 |
| 20090083682 | SIMULATION APPARATUS AND CONTROL METHOD OF SIMULATION - A simulation apparatus, including a first simulator assigning an operating cycle number, a second simulator assigning an operating cycle number, and a control portion for synchronously controlling the first simulator and the second simulator, the control portion causing communication between the first simulator and the second simulator so as to control control-information and synchronous-information of the first simulator and the second simulator, the control-information controlling operations of the first simulator and the second simulator, wherein the control portion sets up the operating cycle numbers of the first simulator and the second simulator at a first cycle value when a synchronous condition of the synchronous-information is established, the control portion sets up at least one of the operating cycle numbers of the first simulator and the second simulator at a second cycle value being larger than the first cycle value when the synchronous condition of the synchronous-information is not established. | 03-26-2009 |
| 20090083683 | Method and Apparatus for Implementing Communication Between a Software Side and a Hardware Side of a Test Bench in a Transaction-Based Acceleration Verification System - Method and apparatus for implementing communication between a software side and a hardware side of a test bench in a transaction-based acceleration verification system are described. In one example, transactors and communication channels are identified in a hierarchy of the test bench. Software side endpoints of the communication channels are automatically bound to hardware side endpoints of the communication channels during verification based on naming attributes of the transactors and communication channels with respect to the software side and the hardware side of the test bench. | 03-26-2009 |
| 20090089724 | Detection Method for Identifying Unintentionally Forward-Biased Diode Devices in an Integrated Circuit Device Design - A detection method for identifying unintentionally forward-biased diode devices identifies one or more forward-biased diodes directly from a graphical representation of an integrated circuit (IC) device design. The graphical representation describing one or more IC components as a plurality of geometric shapes that correspond to a set of patterns in at least one semiconductor layer. A detection method may work in conjunction with one or more checks (e.g., electrical rule check (ERC)) to analyze the graphical representation and ensure its manufacturability by reducing the likelihood the forward-biased diodes will be present in the manufactured IC device. | 04-02-2009 |
| 20090089725 | SYNTHESIS OF ASSERTIONS FROM STATEMENTS OF POWER INTENT - A low power integrated circuit design verification method and tool for automatically synthesizing a set of low power assertions from statements of low power intent. The low power intent statements provide low power constraint information for an integrated circuit design. The low power assertions are automatically synthesized from the low power intent statements and may be used to monitor, check and verify power controller signals. The low power assertions may also be used to collect low power functional coverage data. | 04-02-2009 |
| 20090089726 | Layout Quality Gauge for Integrated Circuit Design - A method for layout design includes steps or acts of: receiving a layout for design of an integrated circuit chip; designing mask shapes for the layout; transmitting the mask shapes to a litho simulator for generating wafer shapes; receiving the wafer shapes; calculating electrically equivalent gate lengths for the wafer shapes; analyzing the gate lengths to check for conformity against a threshold value, wherein the threshold value represents a desired value of electrically equivalent gate lengths; placing markers on the layout at those locations where the gate length violates the threshold value; and generating a histogram of gate lengths for comparing layouts for electrically equivalent gate lengths for layout quality. | 04-02-2009 |
| 20090089727 | METHOD FOR DIMENSION CONVERSION DIFFERENCE PREDICTION, METHOD FOR MANUFACTURING PHOTOMASK, METHOD FOR MANUFACTURING ELECTRONIC COMPONENT, AND PROGRAM FOR DIMENSION CONVERSION DIFFERENCE PREDICTION - A method for dimension conversion difference prediction includes: determining an opening angle at a conversion difference prediction point on basis of a design pattern data; and predicting a dimension conversion difference on basis of correlation between the opening angle and an actual measurement value of the dimension conversion difference, or a method for dimension conversion difference prediction includes: determining an incident amount of incident objects at a conversion difference prediction point on basis of a design data; and predicting a dimension conversion difference on basis of correlation between the incident amount and an actual measurement value of the dimension conversion difference. | 04-02-2009 |
| 20090089728 | SYSTEMS FOR USING RELATIVE POSITIONING IN STRUCTURES WITH DYNAMIC RANGES - Systems for using relative positioning of items or components in a structure with dynamic ranges, such as an elastic I/O bus design for an Integrated Circuit (IC), are disclosed. Embodiments may include a user-defined type module having user-defined types representing relative instance positions within a structure. Embodiments may also include a translation helper module to receive information associated with a hierarchy and to return location information associated with the hierarchy and a translation module to translate between a specific location and a relative position of the instance based on one or more user-defined types and location information returned from the translation helper module to generate a list of translated results. Further embodiments of the translation module may include a relative position determiner to translate specific locations to relative positions and may also include a specific location determiner to translate relative positions to specific locations. | 04-02-2009 |
| 20090094568 | Validation Of An Integrated Circuit For Electro Static Discharge Compliance - An aspect of the present invention validates ESD compliance by examining netlist data generated from a schematic level design of an integrated circuit. Routing and placement may be performed only after confirming that whether each protected circuit (having exposure to ESD current, without the protection circuit) is protected by an appropriate protection circuit. As a result, the design cycle time may be reduced. According to another aspect of the present invention, layout guidelines for each protection circuit is also considered in performing the routing and placement. As a result, the number of iterations in a design cycle may be reduced. | 04-09-2009 |
| 20090094569 | TEST PATTERN EVALUATION METHOD AND TEST PATTERN EVALUATION DEVICE - Provided are an evaluation method and device of a test pattern which enable an appropriate evaluation in a reliability test with a simulation time reduced and high accuracy. It is assumed that each possible internal state of a cell determined at least by a logic value or a voltage value of an input terminal is a cell state, and each possible state of a transistor determined by a voltage between terminals of the transistor is a transistor state. The method comprises steps of: verifying operation of a semiconductor integrated circuit at a gate level or higher; acquiring an appearance cell state continuously appearing for a predetermined time or more in the operation verification; acquiring an appearance transistor state using the corresponding appearance cell state in the operation verification for each transistor; and calculating a test activity ratio of the transistor using the corresponding appearance transistor state for each transistor. | 04-09-2009 |
| 20090100388 | DEEP TRENCH CAPACITOR AND METHOD OF MAKING SAME - A trench capacitor, method of forming a trench capacitor and a design structure for a trench capacitor. The trench capacitor including: a trench in a single-crystal silicon substrate, a conformal dielectric liner on the sidewalls and the bottom of the trench; an electrically conductive polysilicon inner plate filling regions of the trench not filled by the liner; an electrically conductive doped outer plate in the substrate surrounding the sidewalls and the bottom of the trench; a doped silicon region in the substrate; a first electrically conductive metal silicide layer on a surface region of the doped silicon region exposed at the top surface of the substrate; a second electrically conductive metal silicide layer on a surface region of the inner plate exposed at the top surface of the substrate; and an insulating ring on the top surface of the substrate between the first and second metal silicide layers. | 04-16-2009 |
| 20090100389 | Shape-based photolithographic model calibration - A method and apparatus for determining how well a photolithographic model simulates a photolithographic printing process. A test pattern of features is printed on a wafer and the shape of the printed features is compared with the shape of simulated features produced by the model. A cost function is calculated from the comparison that quantifies how well the model simulates the photolithographic printing process. | 04-16-2009 |
| 20090100390 | Low Depth Circuit Design - A method of designing a logic circuit based on one of the functions of the form f | 04-16-2009 |
| 20090100391 | Overlay Measurement on Double Patterning Substrate - A method of measuring overlay between a first structure and a second structure on a substrate is provided. The structures include equidistant elements, such as parallel lines, wherein the equidistant elements of the first and second structure alternate. A design width CD | 04-16-2009 |
| 20090100392 | Securing Authenticity of Integrated Circuit Chip - A system and method are provided for securely manufacturing a device at a foundry. For example, an integrated circuit chip may be securely fabricated at an untrusted foundry by later verifying authenticity of the integrated circuit chip based on a valid usage of an original source code file associated with a semiconductor manufacturing process of the integrated circuit chip. The integrated circuit chip may be authenticated by matching a first set of unique daughter codes generated during fabrication with a second set of unique daughter codes generated independently by some entity other than the foundry. In this way, a trusted electronics integrator may compare the first and second unique daughter codes to nondestructively determine whether the integrated circuit chip is a trusted device or a tampered device. | 04-16-2009 |
| 20090106714 | METHODS AND SYSTEM FOR ANALYSIS AND MANAGEMENT OF PARAMETRIC YIELD - Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design. | 04-23-2009 |
| 20090106715 | Programmable Design Rule Checking - An analog design-rule-check tool analyzes a microdevice design, such as an integrated circuit design, to identify occurrences of geometric elements that share a specified relationship. When the tool identifies such an occurrence of these geometric elements, it will associate or “cluster” these geometric elements together into an identifiable unit. For specified “clusters” of geometric elements, the analog design-rule-check tool will then determine the value of a measurement or measurements required by a user. Once the analog design-rule-check tool has determined the necessary measurement values, it will use those values to evaluate the function describing a model. | 04-23-2009 |
| 20090106716 | VARIOUS METHODS AND APPARATUSES FOR MEMORY MODELING USING A STRUCTURAL PRIMITIVE VERIFICATION FOR MEMORY COMPILERS - A structural primitive verification tool for memory compilers is described. A first set of memory structural primitives are supplied by a designer by filling in fields of a presented user interface. The first set of structural primitives describe certain physical layout features of a proposed memory array in an integrated circuit. A first model of a memory instance derived from the first set of memory structural primitives supplied by the designer is compared to a second model of a memory instance derived from a memory layout file from a memory compiler under-test. The first model is verified against the second model to verify to an integrity of the first set of memory structural primitives supplied by the designer compared to the memory layout file derived from a second set of memory structural primitives configuring that memory instance from the memory compiler. | 04-23-2009 |
| 20090113361 | Design Structure for an Automated Real-Time Frequency Band Selection Circuit for use with a Voltage Controlled Oscillator - A design structure for an integrated circuit including a phase-locked loop (PLL) circuit responsive to a voltage controlled oscillator (VCO) frequency band selection circuit that provides automatic frequency band selection in real time to account for run-time variations, such as power supply and temperature variations over time. The PLL includes a charge pump and an LC tank circuit that provides the automatic frequency band selection based on a VCO control voltage signal supplied by the charge pump. | 04-30-2009 |
| 20090113362 | METHOD FOR DESIGNING A MASK FOR AN INTEGRATED CIRCUIT HAVING SEPARATE TESTING OF DESIGN RULES FOR DIFFERENT REGIONS OF A MASK PLANE - The invention relates to a method for designing integrated circuits, in particular a description and verification of design rules, wherein in one and the same process layer different design rules ( | 04-30-2009 |
| 20090113363 | METHOD AND SYSTEM FOR CREATING A BOOLEAN MODEL OF MULTI-PATH AND MULTI-STRENGTH SIGNALS FOR VERIFICATION - A system, method, computer program product for verification and equivalence checking. In one approach, the system, method, and computer program product analyzes the switching paths in a manner consistent with circuit functionality to provide a complete application which can verify the complex characteristics in the circuits to the accurate RTL model function, including FPGA, ROM Arrays, RAM circuits, and other custom integrated circuit designs. | 04-30-2009 |
| 20090113364 | APPARATUS AND COMPUTER PROGRAM PRODUCT FOR SEMICONDUCTOR YIELD ESTIMATION - A method, apparatus, system, and computer program product that performs yield estimates using critical area analysis on integrated circuits having redundant and non-redundant elements. The non-redundant elements are ignored or removed from the critical area analysis performed for undesired opens. | 04-30-2009 |
| 20090119624 | APPARATUS AND METHOD FOR ANALYZING SOURCE CODE USING PATH ANALYSIS AND BOOLEAN SATISFIABILITY - A computer readable storage medium includes executable instructions to identify a path in target source code. Constraints associated with the path are extracted. The constraints are converted to a Boolean expression. The Boolean expression is processed with a Boolean satisfiability engine to identify either a feasible path or an infeasible path. A feasible path is statically analyzed, while an infeasible path is not statically analyzed. | 05-07-2009 |
| 20090119625 | Structure for System Architectures for and Methods of Scheduling On-Chip and Across-Chip Noise Events in an Integrated Circuit - A design structure integrated circuit (IC) system architectures that allow for the reduction of on-chip or across-chip transient noise budgets by providing a means to avoid simultaneous high current demand events from at least two functional logic blocks, i.e., noise contributors, are disclosed. Embodiments of the IC system architectures include at least one noise event arbiter and at least two noise contributor blocks. A method of scheduling on-chip noise events to avoid simultaneous active transient noise events may include, but is not limited to: the noise event arbiter receiving simultaneously multiple requests-to-operate from multiple noise contributors; the noise event arbiter determining when each noise contributor may execute operations based on a pre-established dI/dt budget; and the noise event arbiter notifying each noise contributor as to when permission is granted to execute its operations. | 05-07-2009 |
| 20090119626 | DESIGN STRUCTURE INCLUDING TRANSISTOR HAVING GATE AND BODY IN DIRECT SELF-ALIGNED CONTACT - A design structure including a transistor having a directly contacting gate and body is disclosed. In one embodiment, the transistor includes a gate; a body; and a dielectric layer extending over the body to insulate the gate from the body along an entire surface of the body except along a portion of at least a sidewall of the body, wherein the gate is in direct contact with the body at the portion. | 05-07-2009 |
| 20090119627 | PATTERN DATA GENERATION METHOD, DESIGN LAYOUT GENERATING METHOD, AND PATTERN DATA VERIFYING PROGRAM - A pattern data generation method according to an example of the present invention includes based on design pattern data of a circuit including a plurality of MIS transistors having the same gate size, identifying types of the plurality of MIS transistors, setting size specs for gate patterns of the plurality of MIS transistors, the size specs being different for different types of the MIS transistors, and verifying whether gate patterns of the MIS transistors predicted by simulation using mask pattern data for forming the MIS transistors satisfy the size specs. | 05-07-2009 |
| 20090119628 | METHODS, SYSTEMS AND USER INTERFACE FOR EVALUATING PRODUCT DESIGNS IN LIGHT OF PROMULGATED STANDARDS - Systems, methods, and interfaces for evaluating proposed product designs having interconnected devices in light of promulgated industry standards via a graphical interface. | 05-07-2009 |
| 20090125855 | Forming Separation Directives Using A Printing Feasibility Analysis - Separation directives for integrated circuit layout design data are formed based upon one or more printing feasibility analyses performed on the layout design data. At least one printing feasibility analysis is performed on layout design data to identify portions of the design that may not be correctly formed or “printed” during a photolithographic process. The geometric element edges involved in a potential printing defect are then identified as edges to be formed using separate masks. Further, separation directives may be created to specifically designate the identified edges as edges to be formed using separate masks in a photolithographic manufacturing process. | 05-14-2009 |
| 20090125856 | METHODS AND APPARATUS FOR BOOLEAN EQUIVALENCY CHECKING IN THE PRESENCE OF VOTING LOGIC - In a first aspect, a first method of designing a circuit is provided. The first method includes the steps of (1) providing a model of an original circuit design including a latch; (2) providing a model of a modified version of the original circuit design, wherein the modified version of the original circuit design includes a set of latches associated with the latch of the original circuit design and voting logic having inputs coupled to respective outputs of latches in the latch set; and (3) during Boolean equivalency checking (BEC), injecting an error on at most a largest minority of the inputs of the voting logic to test the voting logic function. | 05-14-2009 |
| 20090132975 | Circuit Splitting in Analysis of Circuits at Transistor Level - Operating splitting methods for splitting a circuit into two sub circuits and analyzing the two sub circuits with improved computation efficiency and processing speed. | 05-21-2009 |
| 20090132976 | METHOD FOR TESTING AN INTEGRATED CIRCUIT AND ANALYZING TEST DATA - A method for testing an integrated circuit and analyzing test data. The method includes: defining a set of signal path selection criteria; selecting a subset of signal paths of an integrated circuit design, the selecting signal paths meeting the selection criteria; identifying pattern observation points for each signal path of the subset of signal paths; selecting a set of features associated with the integrated circuit design; applying a set of test patterns to one or more integrated circuit chips; determining failing signal paths of the subset of signal paths for each integrated circuit chip; mapping failing signal paths of the subset of signal paths to the set of features to generate a correspondence between the failing signal paths and the features; and analyzing the correspondence and identifying suspect features of the set of features based on the analyzing. | 05-21-2009 |
| 20090132977 | METHOD OF ESTABLISHING COUPON BAR - A method of establishing a coupon bar is applied to circuit layout of a multi-layer printed circuit board (PCB). A coupon bar library storing a great number of coupon bars and sets of setting parameters each corresponding to a coupon bar is connected. A set of parameters including a layer number value, a board thickness value, a line width value, and a distance value is input. The set of inputted layout parameters is compared with the setting parameters stored in the coupon bar library, so as to obtain a set of setting parameters and the corresponding coupon bar matching with each other. The obtained coupon bar is laid on one layer of the multi-layer PCB. | 05-21-2009 |
| 20090132978 | Method for automatically modifying frame of circuit diagram - A method for automatically modifying a frame of a circuit diagram is applicable for a computer-executable circuit layout software, which determines intersection or discontinuity of line segments generated after a diagram is converted through using a program, and automatically corrects the diagram to output a complete circuit diagram, so as to enhance the convenience of reading and determining the circuit diagram, and to simplify manual inspection procedures, and thus the working process is accelerated. | 05-21-2009 |
| 20090132979 | DYNAMIC POINTER DEREFERENCING AND CONVERSION TO STATIC HARDWARE - Disclosed herein are embodiments of methods and apparatus for handling dynamic pointers during algorithmic synthesis. In one disclosed embodiment, a high-level description of a circuit design (e.g., C++ description or a parsed C++ description) is received. In this embodiment, the high-level description comprises one or more dynamic pointer dereferencing operations. The high-level description of the circuit is converted into an RTL description or a gate-level netlist. In this embodiment, the RTL description or the gate-level netlist describes hardware capable of implementing the dynamic pointer dereferencing operations. The hardware can comprise, for instance, one or more multiplexers and/or one or more demultiplexers. | 05-21-2009 |
| 20090132980 | RANGE PATTERN DEFINITION OF SUSCEPTIBILITY OF LAYOUT REGIONS TO FABRICATION ISSUES - A memory is encoded with a data structure that represents a pattern having a range for one or more dimensions and/or positions of line segments therein. The data structure identifies two or more line segments that are located at a boundary of the pattern. The data structure also includes at least one set of values that identify a maximum limit and a minimum limit (i.e. the range) between which relative location and/or dimension of an additional line segment of the pattern in a portion of a layout of an integrated circuit (IC) chip, represents a defect in the IC chip when fabricated. In most embodiments, multiple ranges are specified in such a range defining pattern for example a width range is specified for the width of a trace of material in the layout and a spacing range is specified for the separation distance between two adjacent traces in the layout. | 05-21-2009 |
| 20090138836 | AUTOMATIC VERIFICATION OF ADEQUATE CONDUCTIVE RETURN-CURRENT PATHS - After finding the shortest conductive signal return-current path for each signal, the invention assesses whether each conductive return-current path is adequate. The method analyzes each shortest conductive signal return-current path and determines if a significant portion of the signal return current flows as displacement current rather than following the conductive current path. A significant displacement current flows when the length of the conductive return-current path that diverges from a signal net is more than a previously defined limit based on the signal transition time. Further, a significant displacement current flows when the overall length of the signal differs from the overall length of the conductive return-current path by more than a previously defined limit based on the signal transition time. | 05-28-2009 |
| 20090144676 | DESIGN VERIFICATION TECHNIQUE - A method includes determining whether or not a statement in a design has any functionality. The functionality includes impact on the operation of the design. Also included in the invention is an impact checker to determine the impact of portions of the design on the operation of the design. | 06-04-2009 |
| 20090144677 | Design Structure for a Circuit and Method to Measure Threshold Voltage Distributions in SRAM Devices - A design structure for a circuit for inline testing of memory devices which provides information on the variation of the threshold voltage. The design structure for the circuit includes an array of ring oscillators with a series of inverters, which already exist in the memory device. A control logic systematically steps through all of the ring oscillators by enabling each inverter and toggling the input. The mean frequency and its distribution is measured and recorded in an output circuit. The threshold voltage variation in the memory device is deduced from the ring oscillators. The circuit additionally includes two inverters place external of the memory device. Each ring oscillator is coupled to an inverter. The inverter preconditions the elements of the ring oscillator to prevent a resistive divider between the two transistors. | 06-04-2009 |
| 20090144678 | METHOD AND ON-CHIP CONTROL APPARATUS FOR ENHANCING PROCESS RELIABILITY AND PROCESS VARIABILITY THROUGH 3D INTEGRATION - A method and on-chip controller for enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging. Also provided is an on-chip reliability/variability controller arrangement for implementing the inventive method. | 06-04-2009 |
| 20090144679 | Staged Scenario Generation - A method of verifying integrated circuit designs, by constructing a series of atomic generators in a staged, hierarchical order, applying a lowest of the hierarchical generator stages to device level test cases of the verification process, applying a highest of the hierarchical generator stages to system level test cases of the verification process, reusing code written for and used in the lowest hierarchical generator stage in a next higher generator stage, creating a constraint scenario in the highest hierarchical generator stage, and injecting the constraint scenario into a next lower generator stage. | 06-04-2009 |
| 20090144680 | AUTOMATED DEBUGGING METHOD AND SYSTEM FOR OVER-CONSTRAINED CIRCUIT VERIFICATION ENVIRONMENT - An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described. | 06-04-2009 |
| 20090144681 | AUTOMATED DEBUGGING METHOD AND SYSTEM FOR OVER-CONSTRAINED CIRCUIT VERIFICATION ENVIRONMENT - An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described. | 06-04-2009 |
| 20090150837 | CHECKING A CIRCUIT LAYOUT FOR A SEMICONDUCTOR APPARATUS - Method for checking a circuit layout for a semiconductor apparatus, including:
| 06-11-2009 |
| 20090150838 | METHOD OF PROGRESSIVELY PROTOTYPING AND VALIDATING A CUSTOMER'S ELECTRONIC SYSTEM DESIGN - A method for prototyping and validating a customer's electronic system design (ESD) with design data is proposed. The design data is partitioned into hierarchical design elements (HDEs) plus their respective test benches. The ESD couples with customer's customer peripheral devices CPDs via their peripheral interface terminals PITs thus forming interconnected hierarchical system elements (HSEs) interacting with one another according to a functional validation specification. The HSEs form numerous system hierarchy levels (SHLs). The method includes:
| 06-11-2009 |
| 20090150839 | INTEGRATED PROTOTYPING SYSTEM FOR VALIDATING AN ELECTRONIC SYSTEM DESIGN - An integrated prototyping system (IPS) is proposed for verifying and validating an electronic system design (ESD) with hierarchical design elements (HDEs). The IPS has: a) A reprogrammable logic device (RPLD) having an emulation timing base and an RPLD-interface for programming and simulating HDEs under validation while transacting exchanging vectors. The RPLD is also switchably coupled to numerous external peripheral electronic devices (PED), b) An EDA simulator for simulating then verifying selected HDEs while transacting exchanging vectors. The EDA simulator also has a simulator interface; and c) An IPS controller bridging the RPLD and the EDA simulator. The IPS controller has an IPS executive for progressively verifying and validating the ESD. The IPS executive further includes a co-emulation software for jointly and simultaneously running the RPLD and the EDA simulator with an event-based synchronization scheme for interchanging exchanging vectors on demand between the RPLD and the EDA simulator. | 06-11-2009 |
| 20090150840 | METHOD FOR ACQUIRING BASIC CHARACTERISTIC OF SIMULTANEOUS SWITCHING NOISE IN METHOD FOR ESTIMATING SIMULTANEOUS SWITCHING NOISE ON SEMICONDUCTOR DEVICE - In an initial stage of device design, a circuit analysis control unit of an evaluation board stores SSO noise basic characteristic data actually measured by the evaluation board in an SSO noise basic characteristic data storage unit, and an SSO noise calculation unit calculates a rough amount of SSO noise on the basis of the SSO noise basic characteristic data. After a noise check is OR, the design proceeds, and a PCB parameter is determined, a circuit analysis control unit acquires the SSO noise basic characteristic data according to actual device PCB design information, and corrects the SSO noise basic characteristic data in the SSO noise basic characteristic data storage unit. Then, the SSO noise calculation unit performs a detailed analysis of an amount of SSO noise using the corrected SSO noise basic characteristic data. | 06-11-2009 |
| 20090150841 | SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN SUPPORTING METHOD, SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN SUPPORTING SYSTEM, AND COMPUTER READABLE MEDIUM - A semiconductor integrated circuit design supporting system has a memory unit which stores cell information containing the number of power supply pads formed at a chip as well as names and the number of a plurality of IO cells, and a drive factor definition file defining a drive factor of each of the plurality of IO cells, a pad laying out section which tentatively lays out the power supply pads and input-output pads corresponding to the IO cells, using the cell information, a package virtual designing section which prepares a package drawing based on coordinates of the power supply pads and the input-output pads, which have been tentatively laid out, an electric characteristics data calculating section which calculates inductance of the power supply pads, using the package drawing, and a noise risk calculating section which calculates noise risk of each of the input-output pads, using the inductance and the drive factor definition file. | 06-11-2009 |
| 20090150842 | IDENTIFYING PARASITIC DIODE(S) IN AN INTEGRATED CIRCUIT PHYSICAL DESIGN - A method comprises tracing a first and second terminal of a junction through a circuit layout to associated power supplies to determine their respective defined bias values. The method further comprises comparing the defined bias values of each terminal in order to determine, based on the comparison, whether the junction is forward biased. | 06-11-2009 |
| 20090158225 | METHOD AND SYSTEM FOR AUTOMATICALLY ACCESSING INTERNAL SIGNALS OR PORTS IN A DESIGN HIERARCHY - A method is disclosed that employs a hierarchical path database generator for accessing internal signal or port names in a design hierarchy of an integrated circuit design. The method comprises the steps of inputting design files into the hierarchical path database generator; and said hierarchical path database generator determining ports and signals in said design files, and storing the names of said ports and signals in a hierarchical database in a logical hierarchical order. The method comprises the further steps of providing a testcase to verify a defined aspect of the integrated circuit design; parsing the testcase to identify all signal and port names therein; and for each of the signal and port names identified in the testcase, inputting said each name into the hierarchical path database generator, and obtaining from that generator a hierarchical path associated with said each signal and port name. | 06-18-2009 |
| 20090158226 | HIGH-DENSITY, TRENCH-BASED NON-VOLATILE RANDOM ACCESS SONOS MEMORY CELLS FOR SOC APPLICATIONS - The present invention provides two-transistor silicon-oxide-nitride-oxide-semiconductor (2-Tr SONOS) non-volatile memory cells with randomly accessible storage locations as well as a design structure including the semiconductor memory devices embodied in a machine readable medium. In one embodiment, a 2-Tr SONOS cell is provided in which the select transistor is located with a trench structure having trench depth from 1 to 2 μm and the memory transistor is located on a surface of a semiconductor substrate adjoining the trench structure. In another embodiment, a 2-Tr SONOS memory cell is provided in which both the select transistor and the memory transistor are located within a trench structure having the depth mentioned above. | 06-18-2009 |
| 20090158227 | METHOD AND SYSTEM FOR CALCULATING HIGH FREQUENCY LIMIT CAPACITANCE AND INDUCTANCE FOR COPLANAR ON-CHIP STRUCTURE - Capacitance and inductance expressions used for modeling critical on-chip metal interconnects. A method for calculating high frequency limit capacitances C | 06-18-2009 |
| 20090164955 | METHOD FOR VERIFYING SAFETY APPARATUS AND SAFETY APPARATUS VERIFIED BY THE SAME - A verification method is provided for verifying a safety apparatus including a programmable logic device having a plurality of functional elements. The verification method includes the steps of exhaustively verifying the plurality of functional elements on actual hardware, generating a functional element that is the same as one of the functional elements verified on the actual apparatus using a predetermined hardware description language, independently logic-synthesizing each generated functional element into a plurality of first net lists, generating a connection function between the functional elements using the predetermined hardware description language, logic-synthesizing the generated connection function into a second net list corresponding to the connection function, synthesizing the first net lists with the second net list to generate a third net list, writing a logic circuit into the programmable logic device on the basis of the third net list, and verifying the actual programmable logic device. | 06-25-2009 |
| 20090172614 | AVOIDING DEVICE STRESSING - A system for protecting a weak device operating in micro-electronic circuit and a design structure including the system embodied in a machine readable medium are disclosed. The system includes a high voltage power supply from high voltage overstressing prevents the weak device from failing during power-up, power-down, and when a low voltage power supply in a multiple power supply system is absent. The system further includes a low voltage power supply detection circuit configured to detect circuit power-up, circuit power-down, and when the low voltage power supply is absent, and generate a control signal upon detection. The system further includes a controlled current mirror device configured to provide a trickle current to maintain a conduction channel in the weak device in response to the control signal received from the low voltage power supply detection circuit during circuit power-up, circuit power-down, and when the low voltage power supply is absent. | 07-02-2009 |
| 20090172615 | METHOD AND APPARATUS FOR ON-THE-FLY MINIMUM POWER STATE TRANSITION - The invention includes a design structure embodied in a computer readable medium for performing a method for inserting a scan chain into a VLSI circuit design. The scan chain structure, or structures, are included in the design structure for the VLSI circuit design. The scan chain structure includes a first flip-flop (L | 07-02-2009 |
| 20090172616 | Method, System, and Computer Program Product for Implementing a Direct Measurement Model for an Electronic Circuit Design - Various embodiments of the present invention are generally directed to a method, system, and computer program product for implementing direct measurement model with simulation and calibration of manufacturing process model in the manufacturing of precision devices such as electronic integrated circuits. The method and the system determine the measured measurement result and the direct measurement information and compare the direct measurement information against the other to determine whether to adjust the process models and the empirical parameters thereof. | 07-02-2009 |
| 20090172617 | Advisory System for Verifying Sensitive Circuits in Chip-Design - A verification system for verifying an integrated circuit design is provided. The verification system includes a functional block finding module configured to identify potential sensitive circuits in the integrated circuit design; and a search module. The search module is configured to find sensitive circuits from the potential sensitive circuits; and verify the sensitive circuits. | 07-02-2009 |
| 20090172618 | TECHNIQUE FOR CREATING ANALYSIS MODEL AND TECHNIQUE FOR CREATING CIRCUIT BOARD MODEL - According to a circuit board creation program presented herein, a simulation assuming a case in which an addition of a bypass capacitor near a another bypass capacitor provided between a pin and via of an LSI part can be performed, simply by adding a bypass capacitor property model and changing the value of a coefficient parameter by which the property value of an element of a line part is to be multiplied or divided. | 07-02-2009 |
| 20090178016 | METHOD FOR QUANTIFYING THE MANUFACTORING COMPLEXITY OF ELECTRICAL DESIGNS - A method and system for quantifying manufacturing complexity of electrical designs randomly places simulated defects on image data representing electrical wiring design. The number of distinct features in the image data without the simulated defects and the number of distinct features in the image data with the simulated defects are determined and the differences between the two obtained. The difference number is used as an indication of shorting potential or probability that shorts in the wiring may occur in the electrical wiring design. The simulating of the defects in the image data may be repeated and the difference value from each simulation or run may be used to obtain a statistical average or representative shorting potential or probability for the design. | 07-09-2009 |
| 20090193372 | Design Structure for Improvement of Matching FET Currents Using a Digital to Analog Converter - A design structure comprising apparatus to equalize currents on a matching pair of FETs having sources connected together on a silicon on insulator semiconductor chip, or other chip wherein FET bodies can be individually biased. During a determination period, functional inputs coupled to the gates of the matching pair of FETs are short circuited, and a DAC adjusts a first body voltage of a first FET in the matching pair of FETs relative to a second body voltage of a second FET in the matching pair of FETs until a currents in the first FET and the second FET are equal, within resolution of the DAC's voltage granularity. A proper DAC control value is stored and applied to the DAC following the determination period when the short circuit is removed from the functional inputs. | 07-30-2009 |
| 20090199140 | METHOD AND APPARATUS FOR THERMAL ANALYSIS - Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) layout that includes numerous circuit modules. In some embodiments, the method initially defines several power dissipation equations that express the temperature dependence of the power dissipation for several circuit modules. In some embodiments, the power dissipation equations express a non-linear relationship between power dissipation and temperature. The method defines a heat flow equation based on the specified power dissipation equations. The method then solves the heat flow equation to identify a temperature distribution for the design layout. | 08-06-2009 |
| 20090199141 | SYSTEMS AND METHODS FOR PROTOTYPING AND TESTING ELECTRICAL CIRCUITS IN NEAR REAL-TIME - A system for fabricating, testing, and modifying a prototype of an electrical circuit comprises a materials printer including a holder for positioning a substrate. The materials printer is adapted to receive information describing the prototype and is further adapted to fabricate the prototype on the substrate based on the information. An electrical measuring instrument associated with the holder is adapted to be placed in electrical communication with the prototype when the prototype is received by the holder. A display device receives a plurality of measurements of the prototype from the electrical measuring instrument. | 08-06-2009 |
| 20090199142 | Method and Apparatus for Automatic Orientation Optimization - Methods and apparatuses are disclosed for automatic orientation optimization in the course of generating a placed, routed, and optimized circuit design. Also disclosed are a circuit design and circuit created with the technology. Also disclosed are a circuit design and circuit created with the technology. | 08-06-2009 |
| 20090204931 | Method And Apparatus For Processing Assertions In Assertion-Based Verification of A Logic Design - Method and apparatus for processing assertions in assertion-based verification of a logic design are described. One example relates to processing an assertion during verification of a logic design. An evaluation engine is generated that encodes, using a non-deterministic finite automata (NFA) model, temporal behavior of the logic design required by the assertion for a single attempt to evaluate the assertion. The evaluation engine is implemented in first reconfigurable hardware. The logic design is simulated over a plurality of clock events. Attempts to evaluate the assertion by the evaluation engine are preformed sequentially based on input stimuli obtained from the logic design during simulation thereof. Each of the attempts results in one of the assertion passing, the assertion failing, or the assertion requiring further evaluation. | 08-13-2009 |
| 20090204932 | EQUIVALENCE VERIFICATION BETWEEN TRANSACTION LEVEL MODELS AND RTL AT THE EXAMPLE TO PROCESSORS - A method for formally verifying the equivalence of an architecture description with an implementation description. The method comprises the steps of reading an implementation description, reading an architecture description, demonstrating that during execution of a same program with same initial values an architecture sequence of data transfers described by the architecture description is mappable to an implementation sequence of data transfers implemented by the implementation description, such that the mapping is bijective and ensures that the temporal order of the architecture sequence of data transfers corresponds to the temporal order of the implementation sequence of data transfers, and outputting a result of the verification of the equivalence of the architecture description with the implementation description. | 08-13-2009 |
| 20090210833 | Semiconductor Structure and Method of Designing Semiconductor Structure to Avoid High Voltage Initiated Latch-up in Low Voltage Sectors - Method and semiconductor structure to avoid latch-up. Method includes identifying at least one high voltage device on a semiconductor chip, identifying a circuit on the semiconductor chip separated from the identified at least one high voltage device by a guard ring, evaluating the circuit for a latch-up condition, and when the latch-up condition occurs, adjusting the contact-circuit spacing in the circuit. | 08-20-2009 |
| 20090210834 | IC CHIP DESIGN MODELING USING PERIMETER DENSITY TO ELECTRICAL CHARACTERISTIC CORRELATION - IC chip design modeling using perimeter density to an electrical characteristic correlation is disclosed. In one embodiment, a method may include determining a perimeter density of conductive structure within each region of a plurality of regions of an integrated circuit (IC) chip design; correlating a measured electrical characteristic within a respective region of an IC chip that is based on the IC chip design to the perimeter density; and modeling the IC chip design based on the correlation. | 08-20-2009 |
| 20090210835 | Method and Apparatus for Efficient Power Region Checking of Multi-Supply Voltage Microprocessors - A improved method for very-early validation of voltage region physical power distribution networks uses initial floor plan and early power grid data to identify physical power connection problems associated with voltage regions defined in multi-supply voltage microprocessor chip designs. Since all checking algorithms are floor plan-based and do not require complete circuit data, they are executable very early in the design phase. As a result, power region-related problems can be resolved much sooner than by using conventional full-chip physical design checking and power grid analysis methods. | 08-20-2009 |
| 20090210836 | Automated Method and Apparatus for Very Early Validation of Chip Power Distribution Networks in Semiconductor Chip Designs - Validation of full-chip power distribution networks can be performed very early, and continuously throughout the design cycle, to detect real physical power connection problems and enable early correction of power grid designs using early floor plan and power grid design data. Common power connection and distribution errors are automatically addressed as an integral part of the early chip floor planning and chip power build processes providing efficient solutions requiring no extra wiring resource to be implemented and reducing the runtime of required final full-chip physical design checks, and the overall design cycle. | 08-20-2009 |
| 20090210837 | VERIFYING NON-DETERMINISTIC BEHAVIOR OF A DESIGN UNDER TEST - The invention generally relates to design verification, and more particularly to verification of non-deterministic behavior of a design under test. A method includes predicting a plurality of behaviors of a design under test (DUT), and forking respective verification tasks for each one of the plurality of behaviors. The method further includes verifying an actual behavior of the DUT with each of the verification tasks, and terminating a respective one of the verification tasks when the actual behavior of the DUT does not conform to the respective one of the verification tasks. | 08-20-2009 |
| 20090210838 | INTERPOLATION DISTANCE FOR LAYOUT DESING DATA CORRECTION MODEL - Various implementations of the present invention provide a method of determining is a optical proximity correction process model sufficiently covered the layout design. More particularly, various implementations of the invention provide a method for interpolating between test pattern features relative to layout design features under test. | 08-20-2009 |
| 20090217223 | Layout design method of semiconductor integrated circuit - A layout design method of a semiconductor integrated circuit includes degenerating a layout netlist extracted from layout data, comparing the layout netlist after the reduction with a circuit diagram netlist, and creating a layout circuit association table of a layout cell after the reduction and a circuit element. The method includes creating a before and after reduction association table based on the layout netlist before and after the reduction, counting the number of layout elements in a layout cell area before the reduction, comparing the counted number of layout elements and the number of degenerated elements, and creating mapping information associating the layout cell with the circuit element. | 08-27-2009 |
| 20090217224 | METHOD AND SYSTEM FOR MASK DESIGN FOR DOUBLE PATTERNING - A method and system for setting up multiple patterning lithographic processing of a pattern in a single layer is disclosed. The multiple patterning lithographic processing comprises a first and second patterning step. In one aspect, a method includes, for at least one process condition, obtaining values for a metric expressing a splitting correlated process quality as function of design parameters of a pattern and/or split parameters for the multiple patterning lithographic processing. The method also includes evaluating the values of the metric and selecting based thereon design and split parameters considering the process condition. The method may further include deriving design and/or split guidelines for splitting patterns to be processed using multiple patterning lithographic processing based on the evaluation. | 08-27-2009 |
| 20090222774 | Method for evaluating the quality of a computer program - The invention relates to a method for rating the quality of a computer program whose execution involves an integrated circuit's input data and output data being influenced, comprising
| 09-03-2009 |
| 20090222775 | Characterising circuit cell performance variability in response to pertibations in manufacturing process parameters - A technique for characterising variation in a performance parameter(s) of circuit cells within a circuit cell library with perturbations in manufacturing process parameters uses a statistical approach whereby the statistical distribution of performance parameter(s) resulting from a joint distribution across manufacturing process parameter space is determined. The perturbation in manufacturing process parameter which results in a characteristic amount of variation is then identified and common sets of such perturbations used to group families of circuit cells together. Families of circuit cells have a correlation in their response to manufacturing process parameter perturbation and this is represented by a correlation matrix. Variation characterising data generated in accordance with the above technique is used to drive electronic design automation tools in integrated circuit design and manufacture. | 09-03-2009 |
| 20090222776 | Device for and a Method of Designing a Sensor Arrangement for a Safe Automated System, an Automated System, a Program Element and a Computer-Readable Medium - A device for designing a sensor arrangement for an automated system, the device comprising a first input unit for receiving a specification of a plurality of sensor measurements to be carried out by the sensor arrangement, a second input unit for receiving a specification of a confidence region together with an associated confidence level for each of the specified sensor measurements, a third input unit for receiving a specification of a target confidence level for the automated system, and a configuration unit for configuring the plurality of sensor measurements and for configuring the combination of the sensor measurements in a manner to guarantee the target confidence level for the automated system. | 09-03-2009 |
| 20090222777 | Links and Chains Verification and Validation Methodology for Digital Devices - The links and chains (LNC) of this invention is an applications verification and validation (AVV) methodology. LNC is a hierarchical and systematic approach emphasizing conservation and reuse of effort expended. LNC creates objective metrics for validation. This invention ensures that the device will work in a system environment. LNC is an independent and complementary validation of the design before committing release to tape-out. The chip support library (CSL) and diagnostics used by LNC are natural outputs of the validation and are thus gating items to tape-out release. This ensures a fully tested device. | 09-03-2009 |
| 20090222778 | PROPERTY GENERATING APPARATUS, PROPERTY GENERATING METHOD AND PROGRAM - Disclosed is a property generating apparatus which generates a property representing a specification of an integrated circuit and verifying design information on the integrated circuit described in RTL (Register Transfer Level). The property generating apparatus includes: a storage unit, which stores a register name to identify a register; an address expanding unit, which expands property abbreviated description information on a group of registers including the register, and generates a group of addresses; an RTL analysis unit, which selects a group of register names from the register name stored in the storage unit; and a property generation unit, which generates the property by correlating the group of addresses with the group of register names. | 09-03-2009 |
| 20090235214 | Variable Performance Ranking and Modification in Design for Manufacturability of Circuits - A method, computer system and program product introduce adding a variable performance ranking parameter to a diagram of a circuit to drive implementation of modifications that are yield improving, performance boosting, or performance-neutral. The information is paired to accomplish a more complete design for manufacturability modification in the design of circuits implemented on chips. In this matter, both yield and chip performance are improved. | 09-17-2009 |
| 20090235215 | GRIDDED GLYPH GEOMETRIC OBJECTS (L3GO) DESIGN METHOD - A method of gridded glyph geometric objects (L3GO) integrated circuit (IC) design, wherein at least one inter-level connect in a L3GO circuit design is represented as a point matrix glyph (PMG) on a L3GO grid. Each PMG connects a pair of conductors on the next adjacent (above and below) layer and includes an array (one or two dimensional) of point glyphs contained within a cage. The point glyphs may have uniform size and may be on minimum pitch. Each PMG may also include a flange on the above and below layer. A default flange insures adequate coverage of cut shapes represented by the point glyphs. | 09-17-2009 |
| 20090235216 | Combinational Equivalence Checking for Threshold Logic Circuits - Aspects of a method and system for combinational equivalence checking for threshold logic circuits are provided. In this regard, one or more inputs may be received at a threshold logic gate. The threshold function of the threshold logic gate may be recursively decomposed into a first function and a second function using cofactors of the threshold function. A Boolean function representation of the threshold logic gate may be generated based on the recursive decomposition of the threshold function. The generated Boolean function representation of the threshold logic gate may be a maximally factored form representation of a minimal sum of products (SOP) for the threshold logic gate. A logical equivalence of the threshold logic gate may be verified with one or more other logic circuits based on the generated Boolean function representation of the threshold logic gate. | 09-17-2009 |
| 20090241076 | Test-Cases for Functional Verification of System-Level Interconnect - Generation of test cases for functional verification of a complex system-under-test is achieved by the use of a probability matrix. The probability matrix represents a non-uniform distribution function of resource combinations used in the transactions, and can be created randomly, or by application of various types of testing knowledge. The matrix is used by a test generator for selecting resources that participate in a transaction involving an interconnect between different types of system components. Applying the inventive principles increases the quality of design verification by stimulation of both the system's resources and its internal interconnects, with almost no knowledge of the structure of the system. | 09-24-2009 |
| 20090241077 | Site Selective Optical Proximity Correction - Techniques for performing optical proximity correction on a layout design or portion thereof are provided with various implementations of the invention. With various implementations of the invention, movement and simulation of selected edge fragments is disabled during the optical proximity correction process. The operations of the optical proximity correction process, such as for example simulation and displacement of edge segments, is then performed for the edge fragments that remain enabled. With further implementations of the invention, a simulation site is defined for ones of the edge fragments. The operations of the optical proximity correction process, such as for example simulation and displacement of edge segments, is performed for each simulation site. Additionally, during the optical proximity correction process, the simulations sites may be moved and or removed individually based on various conditions. | 09-24-2009 |
| 20090249267 | CONSTRAINED RANDOM SIMULATION COVERAGE CLOSURE GUIDED BY A COVER PROPERTY - One embodiment of the present invention provides a system which verifies a circuit design by biasing input stimuli for the circuit design to satisfy one or more temporal coverage properties to be verified for the circuit design. This system performs a simulation in which random input stimuli are applied to the circuit design. The system performs the simulation by using a finite state automaton (FSA) instance for a temporal coverage property to observe inputs and outputs of the circuit, and by using soft constraints associated with the FSA instance to bias the input stimuli for the circuit design so that the simulation is likely to progress through a sequence of states which satisfy the temporal coverage property. | 10-01-2009 |
| 20090249268 | WARNING DEVICE AND WARNING METHOD - A warning device checks for errors in design object data and issues a warning for detected errors by storing allowance information, which allows issuance of warning prevention, cancel information, which cancels relevant allowance information to permit issuance of warning for each error identification, and instruction identification, which identifies an edit command for editing generated design object data for error identification. When said edit command is accepted, the error identification for the instruction identification of edit command is acquired. Cancel information can be registered for error identification. Respective errors corresponding to error identifications are checked, when an operation for checking the design object data is accepted, and when a type of an error is identified, whether to issue a warning based on the allowance information and cancel information for relevant error identification is determined. | 10-01-2009 |
| 20090249269 | PROPERTY CHECKING SYSTEM, PROPERTY CHECKING METHOD, AND COMPUTER-READABLE STORAGE MEDIUM - Checking efficiency of property checking is improved. The operation synthesis tool synthesizes an RTL circuit description from a behavioral level circuit description. In addition, the property generating unit generates a behavioral level property from the behavioral level circuit description. Subsequently, the property converting unit converts the generated behavioral level property into an RTL property. The model checking unit then checks the RTL circuit description by model checking technique using the RTL property. | 10-01-2009 |
| 20090254873 | CIRCUIT BOARD ANALYZER AND ANALYSIS METHOD - A circuit board analyzer includes a storage unit for storing mesh position information on an analyzed mesh-division model and extracted circuit constants in relation to each other; a division-model configuration unit for dividing the layout of a circuit board into meshes to configure a new mesh-division model; an identical-mesh determination unit for making a comparison between mesh position information on the new mesh-division model and mesh position information on the analyzed mesh-division model to determine identical meshes that have identical mesh position information; and a circuit-constant extraction unit for performing analytical processing based on the new mesh-division model to extract new circuit constants and reusing, as a new circuit constant associated with the identical meshes, an extracted circuit constant that is related to the mesh position information on the identical meshes. | 10-08-2009 |
| 20090259977 | Assessing Resources Required to Complete a VLSI Design - A system, method and program product are described in which schematics in a library that a user has tagged are read as ready for layout. The difficulty of each layout is assessed based on statistics indicative of the complexity of the schematic. The statistics may regard the number of connections, pins, devices, and other schematic information. The information is used to calculate the total amount of effort required to complete the design and generate a report. | 10-15-2009 |
| 20090259978 | ARRANGEMENT VERIFICATION APPARATUS - An arrangement verification apparatus that makes it possible to shorten a time it takes to complete a failure/no-failure test on the arrangement of control circuits that control block circuits is provided. The arrangement verification apparatus arranges block circuits to be controlled comprising a semiconductor device and control circuits that control the block circuits over a predetermined floor and conducts a failure/no-failure test on the arrangement of the control circuits. The arrangement verification apparatus includes: a floor plan generation unit that arranges block circuits over a floor based on circuit specifications; a grouping generation unit that hierarchically groups the block circuits arranged over the floor and control circuits described in the circuit specifications based on a predetermined requirement to generate a group tree; a control circuit arrangement unit that arranges the control circuits over the floor according to a predetermined condition and the group tree generated at the grouping generation unit; and a failure/no-failure test unit that conducts a failure/no-failure test on the arrangement of the control circuits by the control circuit arrangement unit. | 10-15-2009 |
| 20090265672 | METHOD AND SYSTEM FOR ENTRY AND VERIFICATION OF PARASITIC DESIGN CONSTRAINTS FOR ANALOG INTEGRATED CIRCUITS - A method of designing an analog integrated circuit (IC), a parasitic constraint analyzer and a method of determining a layout of an analog IC complies with parasitic constraints. In one embodiment, the method of designing an analog IC includes: (1) creating a schematic of an analog integrated circuit based on a set of specifications, (2) attaching parasitic constraints to the schematic, (3) creating a layout of the analog integrated circuit based on the schematic including the parasitic constraints, (4) extracting parasitic values from parasitic elements of the layout and (5) comparing the extracted parasitic values with the parasitic constraints to verify compliance therewith. | 10-22-2009 |
| 20090265673 | INTERSECT AREA BASED GROUND RULE FOR SEMICONDUCTOR DESIGN - A design rule that determines a degree of overlap between two design elements in two adjoining levels by estimating a physical overlap area, or an “intersect area,” of corresponding structures in a semiconductor chip is provided. The estimation of the physical intersect area may factor in line edge biasing, critical dimension tolerance, overlay tolerance, and corner rounding to provide an accurate estimate of a physical area for each of the structures corresponding to the two design elements. The intersect area is employed as a metric to determine compliance with a ground rule, i.e., the ground rule is specified in terms of the intersect region. Other derived quantities such as electrical resistance, electromigration resistance, expected yield may be calculated from the intersect area, and may be advantageously employed to optimize the design data. | 10-22-2009 |
| 20090271749 | PATTERN-CLIP-BASED HOTSPOT DATABASE SYSTEM FOR LAYOUT VERIFICATION - One embodiment of the present invention provides a system that generates a pattern-clip-based hotspot database for performing automatic pattern-clip-based layout verification. During operation, the system receives a list of pattern clips which specify manufacturing hotspots to be avoided in a layout, wherein each pattern clip comprises a set of geometries in proximity to each other. Next, for each pattern clip, the system perturbs the pattern clip to determine a first range of variations for the constituent set of geometries wherein the perturbed pattern clip no longer causes a manufacturing hotspot. The system then extracts a set of correction guidance descriptions from the first range of variations for correcting the pattern clip. Subsequently, the system stores the pattern clip and the set of correction guidance descriptions in the pattern-clip-based hotspot database. | 10-29-2009 |
| 20090276738 | METHOD AND APPARATUS FOR EXECUTING A HARDWARE SIMULATION AND VERIFICATION SOLUTION - One embodiment of the present invention provides systems and techniques to execute a hardware simulation and verification solution on a multiprocessor system. The hardware simulation and verification solution can be partitioned into different modules which can include a simulation kernel to simulate changes in signal values, a value change dump module to store the changes in the signal values on a computer-readable storage medium, a functional coverage module to check functionality, a toggle coverage module to check signal toggling, an assertion engine to check complex behaviors, and a testbench module to generate test scenarios. Embodiments of the present invention can execute different modules on different processors, thereby improving performance. | 11-05-2009 |
| 20090276739 | IC CHIP AND DESIGN STRUCTURE INCLUDING STITCHED CIRCUITRY REGION BOUNDARY IDENTIFICATION - Stitched circuitry region boundary identification for a stitched IC chip layout is presented along with a related IC chip and design structure. One method includes obtaining a circuit design for an integrated circuit (IC) chip layout that exceeds a size of a photolithography tool field, wherein the IC chip layout includes a stitched circuitry region; and modifying the IC chip layout to include a boundary identification identifying a boundary of the stitched circuitry region at which stitching occurs, wherein the boundary identification takes the form of a negative space in the IC chip layout. One IC chip may include a plurality of stitched circuitry regions; and a boundary identification identifying a boundary between a pair of the stitched circuitry regions, wherein the boundary identification takes the form of a negative space in a layer of the IC chip. | 11-05-2009 |
| 20090276740 | VERIFICATION SUPPORTING APPARATUS, VERIFICATION SUPPORTING METHOD, AND COMPUTER PRODUCT - In a verification supporting apparatus, a recording unit records a DIRW matrix in which a state transition possibly occurring in a register of a circuit to be verified and information concerning validity of a path corresponding to the state transition are set and an acquiring unit acquires a control data flow graph that includes a control flow graph having a data flow graph written therein. When a register is designated for verification, a data flow graph having described therein the designated register is extracted from the control data flow graph. From the data flow graph extracted, a path indicating the flow of data concerning the register is extracted. The state transition of the path extracted is identified and if the state transition is determined to be is set in the DIRW matrix, information concerning the validity set in the DIRW matrix and the path are correlated, and output. | 11-05-2009 |
| 20090276741 | VERIFICATION SUPPORT APPARATUS, VERIFICATION SUPPORT METHOD, AND COMPUTER PRODUCT - In a verification support apparatus, an implementation description of a verification target is acquired and based on the implementation description, a combination of input gates is identified. A pair of output cones including gates to which input signals from the input gates reach, and a common output cone including gates common to the pair of output cones, are detected. Based on the common output cone, a degree of relation between the input gates is calculated and according to the calculation, the strength of relation is determined for the combination of input gates. The strength of relation for a combination of the input gates is set, the combination being based on a specification of the verification target and corresponding to the combination identified from the implementation description. Whether the strength of relation set and that determined for the identified combination coincide is judged and a result of the judgment is output. | 11-05-2009 |
| 20090276742 | AUTOMATING POWER DOMAINS IN ELECTRONIC DESIGN AUTOMATION - One or more portions of the design (e.g., components, channels, or portions thereof) can be assigned instances of one or more component power domains (CPDs). Assigning an instance of a CPD to a design element (or to a portion thereof) can indicate, for example, whether the element can be switched on and off, or whether the element can operate over a range of voltages. The CPD instances can, in turn, be assigned to one or more design power domains (DPDs). Assignments of a CPD to a DPD can be evaluated according to a set of compatibility rules. Two or more electronic design elements can be connected by one or more signal paths. Organizing the CPD instances into DPDs can aid in finding signal paths that cross from a first DPD to a second DPD. To improve the reliability of signal paths traversing a DPD boundary, one or more power domain interface (PDI) components can be created to handle the signal paths at the boundary. | 11-05-2009 |
| 20090282375 | Circuit And Method Using Distributed Phase Change Elements For Across-Chip Temperature Profiling - Disclosed is an across-chip temperature sensing circuit and an associated method that can be used to profile the across-chip temperature gradient. The embodiments incorporate a plurality of phase change elements distributed approximately evenly across the semiconductor chip. These phase change elements are programmed to have essentially the same amorphous resistance. Temperature-dependent behavior exhibited by each of the phase change elements individually is compared to a reference (e.g., generated by a discrete reference phase change element, generated by another one of the phase change elements, or generated by an external reference) in order to profile the temperature gradient across the semiconductor chip. Once profiled, this temperature gradient can be used to redesign and/or relocate functional cores, to set stress limits for qualification of functional cores and/or to adjust operating specifications of functional cores. | 11-12-2009 |
| 20090293026 | VERIFICATION DEVICE OF SEMICONDUCTOR INTEGRATED CIRCUIT, VERIFICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT, AND COMPUTER READABLE MEDIUM STORING VERIFICATION PROGRAM OF SEMICONDUCTOR INTEGRATED CIRCUIT - It is a verification device of semiconductor integrated circuit configured to verify the equivalence of circuit description and assertion description. The device includes an assertion based verification unit configured to perform assertion based verification of the circuit description on the basis of the assertion description, and generating pass information when the operation of the signal described in the assertion description conforming to a preliminary condition is observed in the circuit description, or generating failure information when the operation of the signal is not observed in the circuit description, a logic generating unit configured to extract a signal corresponding to the failure information from the assertion description, and generating an input/output logic of the circuit description from the extracted signal, a signal restriction generating unit configured to generate a signal restriction on the basis of the input/output logic generated by the logic generating unit, and an estimating unit configured to evaluate the validity of the signal restriction generated by the signal restriction generating unit. | 11-26-2009 |
| 20090293027 | Connection consistency check processing method, cable selection processing method, design confirmation processing device and recording medium that records design confirmation processing program - A device is provided with a unit that stores shape and state characteristics of connectors, their electric characteristics, a judging equation to judge whether their connections are good or not, and information defined in script; and a unit that stores information defined in script of transfer functions to transfer the electric characteristics and the judging equation along a cable, wherein the connection consistency of the cable to connect connectors of the components is checked by analyzing characteristics of each connector, and scripts of the judging equation and the transfer functions; and a suitable cable candidate is selected and a processing is achieved by making use of scripts and an algorism unified for connectors and cables with various characters. | 11-26-2009 |
| 20090293028 | TRANSFORMATION OF IC DESIGNS FOR FORMAL VERIFICATION - A memory is encoded with data that represents a reference IC design, a retimed IC design, and logical relationships, wherein at least one logical relationship describes combinational logic without reference to structural information, such as actual cells that have been instantiated in the IC designs. The logical relationships are used to instantiate logic described therein, and to define one or more black boxes as being functionally inverse of the logic. Each instantiated logic and its functionally inverse black box are thereafter added to the reference IC design to obtain a transformed reference IC design. A transformed retimed IC design is also obtained by addition of the instantiated logic(s) and functionally inverse black box(es) to the retimed IC design. These two transformed IC designs are then supplied to an equivalence checker, for formal verification. | 11-26-2009 |
| 20090300559 | Incremental Speculative Merging - An incremental speculative merge structure which enables the elimination of invalid merge candidates without requiring the discarding of the speculative merge structure and all verification results obtained upon that structure. Targets are provided for validating the equivalence of gates g | 12-03-2009 |
| 20090300560 | METHOD AND SYSTEM FOR FORMAL VERIFICATION OF AN ELECTRONIC CIRCUIT DESIGN - A new and convenient methodology for proving the correctness of multiplier and multiply-accumulate circuit designs in a full custom design flow. Such an approach utilizes a basic description of the implemented algorithm, which is created in early phases of the design flow and requires only little extra work for the designer who spends most of the time in full-custom optimizations. Such an approach also defines arithmetic circuit at the arithmetic bit level and allows for the generation of a gate level netlist. Given a structural similarity between the specification and design under verification, a large amount of structural similarity between the generated netlists is obtained so that a standard equivalence checker can be utilized to verify the design against the specification. | 12-03-2009 |
| 20090300561 | METHOD AND SYSTEM FOR POST-ROUTING LITHOGRAPHY-HOTSPOT CORRECTION OF A LAYOUT - One embodiment of the present invention provides a system that verifies an integrated circuit (IC) chip layout. During operation, the system receives a layout of an IC chip after the layout has gone through a place-and-route operation. Next, the system performs a lithography compliance checking (LCC) operation on the layout to detect lithography hotspots within the layout, wherein each lithography hotspot is associated with a local routing pattern around the lithography hotspot. Next, for each detected lithography hotspot, the system compares the associated local routing pattern against a hotspot database to determine if the local routing pattern matches an entry in the hotspot database, which stores a set of known hotspot configurations. If so, the system corrects the lithography hotspot using correction guidance information associated with the hotspot configuration stored in the hotspot database. Otherwise, the system corrects the lithography hotspot by performing a local rip-up and reroute on the local routing pattern, iteratively, until achieving convergence or given number of iterations. | 12-03-2009 |
| 20090300562 | Design structure for out of band signaling enhancement for high speed serial driver - A design structure is provided for a microelectronic serial driver. The serial driver is operable to transmit a differential pattern signal during a burst interval and a predetermined common mode voltage level during a second interval between adjacent burst intervals, the serial driver including at least one pre-driver and a driver coupled to an output of the pre-driver for transmitting the differential communication signal. A switching circuit is operable to switch the serial driver between a first power supply voltage level for the burst interval and the predetermined common mode voltage level, wherein the predetermined common mode voltage level is independent of variations in power supply voltage conditions and temperature conditions. | 12-03-2009 |
| 20090300563 | METHOD AND SYSTEM FOR PERFORMING SEQUENTIAL EQUIVALENCE CHECKING ON INTEGRATED CIRCUIT (IC) DESIGNS - One embodiment of the present invention provides a system that performs sequential equivalence checking between integrated circuit (IC) designs. During operation, the system receives a first IC design and a second IC design. Each of the first and second IC designs includes a top design level and a bottom design level, and the bottom design levels include one or more sub-blocks within the corresponding top design levels. The system then verifies if each of the sub-blocks in the bottom design level of the first design is conditionally equivalent to a corresponding sub-block in the second design. Note that two designs are conditionally equivalent if the two designs can become sequentially equivalent by adding registers on the input and output ports of the two designs. The system additionally verifies if the top design level of the first design is conditionally equivalent to the top design level of the second design and if the first design is temporally equivalent to the second design. | 12-03-2009 |
| 20090300564 | CIRCUIT OPERATION VERIFICATION METHOD AND APPARATUS - In order to confirm a propagation range of a signal whose signal value is fixed by a control signal to restrain switchings is within a predetermined range, it is judged by results of the logic simulation whether or not a switching restraining mode is enabled. If it is enabled, a switching probability restraint information list including the detected time and an ID of the net whose signal value is fixed is set to the net whose signal value is fixed, and then is propagated to the next net according to the results of the logic simulation. If the circuit changes are appropriated conducted, the results of the logic simulation do not satisfy the propagation condition of the switching probability restraint information list. Accordingly, the switching probability restraint information list is not propagated over the predetermined range, and no problem is detected. | 12-03-2009 |
| 20090307642 | METHOD AND SYSTEM FOR MODEL-BASED DESIGN AND LAYOUT OF AN INTEGRATED CIRCUIT - A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers. | 12-10-2009 |
| 20090307643 | VECTOR SEQUENCE SIMPLIFICATION FOR CIRCUIT VERIFICATION - One set of illegal vector sequences is manually generated for a circuit design and a symbolic simulator is used to automatically generate another set of illegal vector sequences for the circuit design. For verification purposes, the relationship between the manually generated set and the automatically generated set is determined. Prior to determining this relationship, one or both of the sets are simplified. One simplification technique includes replacing pairs of illegal vector sequences that are the same except at one bit position with a more general illegal vector sequence representative of both illegal vector sequences of the pair. Another simplification technique includes sorting the illegal vector sequences in a list having a sort order from most general to most specific and then identifying illegal vector sequences that are redundant in view of one or more other illegal vector sequences prior in the sort order based on a binary decision diagram (BDD)-based analysis that sequences through the sorted list in its sort order. | 12-10-2009 |
| 20090307644 | FAST EVALUATION OF AVERAGE CRITICAL AREA FOR IC LAYOUTS - Method and apparatus for approximating the average critical area of a layout or layout region, involving summing, over all the object segments of interest, respective critical area contribution values that are dependent upon particular layout parameters of the objects, each of the contribution values being representative of a plurality of defect sizes, and being defined such that for each defect size in the plurality of defect sizes, and for a particular defect type, the contribution values collectively count all critical areas arising due to the object segments of interest only once. | 12-10-2009 |
| 20090313590 | HIGHLY SPECIALIZED SCENARIOS IN RANDOM TEST GENERATION - A computer software product is provided. The product includes a computer-readable medium in which computer program instructions are stored, which instructions, when read by a computer, cause the computer to perform a method for functional verification of a design, having an operational space comprising the steps of accepting as an input a test template that specifies test parameters directed to a function of the design, the template comprising constraints and variables covering a working space within the operational space, associating an exemption mode of operation with at least one of the constraints or at least one of the variables, wherein a domain of the at least one of the variables is modified or the at least one of the constraints is disabled in the exemption mode of operation, producing a test case that lies in the operational space of the design by enabling the exemption mode of operation, the test case comprising a series of transactions originating from the template, wherein the transactions exercise the function of the design, wherein the working space is modified in the exemption mode of operation and submitting the test case for execution by the design, wherein the exemption mode of operation is associated with only a portion of the template. | 12-17-2009 |
| 20090313591 | METHOD FOR GENERATING A DEEP N-WELL PATTERN FOR AN INTEGRATED CIRCUIT DESIGN - A method for the design and layout for a patterned deep N-well. A tile is specified as a fundamental building block for the deep N-well pattern. The tile comprises a first element on a first layer and may comprise a second element on a second layer. A two dimensional region is covered with an array of contiguous tiles, with the elements on each layer connecting with elements of adjacent tiles to form extended shapes. The array may be converted to a collection of sub-arrays through the removal of tiles. The array or collection of sub-arrays may be merged to produce a first layer pattern and second layer pattern. Design rule checks may be applied to verify the pattern. The first layer shapes and second layer shapes may be edited. The first layer shapes and the second layer shapes may then be combined to produce a deep N-well pattern. | 12-17-2009 |
| 20090319968 | DESIGN AND VERIFICATION OF 3D INTEGRATED CIRCUITS - A method of designing a 3D integrated circuit (3D IC) including providing a first layout corresponding to a first device of a 3D IC and a second layout corresponding to a second device of a 3D IC is provided. A verification, such as LVS or DRC, may be performed not only on each device separately, but may also be performed to ensure proper connectivity between devices. The verification may be performed on a single layout file (e.g., GDS II file) including the interface layer of the first and second die. Dummy feature pattern may be determined for the 3D IC using a layout including the interface layers of the first and second devices. | 12-24-2009 |
| 20090319969 | METHOD AND SYSTEM FOR PERFORMING STATISTICAL LEAKAGE CHARACTERIZATION, ANALYSIS, AND MODELING - A method, system, and computer program product are disclosed for performing statistical leakage power characterization to estimate yield of a circuit in terms of leakage power. According to some approaches, this is performed with consideration of state correlation. | 12-24-2009 |
| 20090319970 | Method for Correcting Layout with Pitch Change Section - A method for correcting a layout with a pitch change section may include disposing a pattern layout with the pitch change section having a first pattern and a second pattern at a pitch relatively larger than that of the first pattern, measuring the pitch change from the pattern layout, a step of measuring an aerial image intensity by performing a simulation operation on the area with the pitch change section; modifying the pitch of the layout in the pitch change section based on a threshold intensity value at which the pattern is formed; and processing the layout correction to cause the pitch to exist within the threshold range by comparing the image intensity of the modified layout with the image intensity of the reference area. | 12-24-2009 |
| 20090319971 | METHOD OF VERIFYING LAYOUT OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - An exemplary aspect of an embodiment of the present Invention is a method of verifying a layout for a semiconductor integrated circuit device including: segmenting a layout of a semiconductor integrated circuit device into a plurality of local regions; calculating a ratio for each local region, the ratio being the area of a region in which an element isolation layer is exposed on a semiconductor wafer surface forming the semiconductor integrated circuit device to the area of the local region; and verifying the layout of the semiconductor integrated circuit device based on the ratio. | 12-24-2009 |
| 20090327982 | Method of verifying layout data for semiconductor device - A data verification method executed by a data verification device that verifies hierarchical structure layout data for a semiconductor device. The method includes retrieving a verification condition that is set in accordance with a data processing system which processes the layout data generated by and provided from a designing device, extracting shaped item existing range information and possessive layout information from the layout data to generate a hierarchical expansion table, cumulating the possessive layout information associated with each cell from an uppermost layer cell of a layout path to a target cell, calculating a cumulative value of the possessive layout information for the layout path, determining whether or not the possessive layout information satisfies the verification condition based on the cumulative value, the verification condition, and the possessive layout information, and determining whether or not the shaped item existing range information satisfies the verification condition. | 12-31-2009 |
| 20090327983 | Predictive Modeling of Interconnect Modules for Advanced On-Chip Interconnect Technology - A computer program product estimates performance of an interconnect structure of a semiconductor integrated circuit (IC). The program product includes code executing on a computer to calculate at least one electrical characteristic of the interconnect structure based on input data accounting for multiple layers of the interconnect structure. The electrical characteristics can be capacitance, resistance, and/or inductance. The capacitance may be based upon multiple components, including a fringe capacitance component, a terminal capacitance component, and a coupling capacitance component. | 12-31-2009 |
| 20090327984 | Method For Determining The Quality Of A Quantity Of Properties, To Be Employed For Verifying And Specifying Circuits - A method is specified for determining the quality of a quantity of properties describing a machine, including a step for determining the existence of at least one sub-quantity of interrelated properties (P | 12-31-2009 |
| 20100005433 | CIRCUIT DESIGN APPARATUS AND CIRCUIT DESIGN METHOD - A circuit design apparatus for designing an LSI including a memory circuit for storing data and an error protection circuit for performing an error protection over the data stored in the memory circuit on the basis of design information, the circuit design apparatus includes: an extracting unit for extracting information of configuration of the memory circuit with error protection circuit from the design information; and a circuit arrangement controller for determining whether to insert a check circuit for supplying a check signal into the memory circuit to verify the error protection circuit on the configuration information. | 01-07-2010 |
| 20100005434 | VERIFYING AN IC LAYOUT IN INDIVIDUAL REGIONS AND COMBINING RESULTS - When performing rule checking locally within any given region of a layout of an integrated circuit, certain data is generated to be checked globally, regardless of boundaries (hereinafter “to-be-globally-checked” data). The to-be-globally-checked data, resulting from execution of a given rule in each region of the IC layout, is merged across all regions, and the same rule (i.e. the given rule) is executed globally on the merged data. When an entire runset has been executed in all regions individually, and also executed globally on the merged data, the results thereof are all merged together to yield a final result of a complete execution of the entire runset over the entire IC layout. In some embodiments, certain additional data that could not be rule checked due to the presence of boundaries of adjacent regions is propagated between successive rules in each region. | 01-07-2010 |
| 20100011325 | METHOD AND APPARATUS FOR DETERMINING THE EFFECT OF PROCESS VARIATIONS - Embodiments of the present invention provide systems and techniques for determining the effect of process variations. During operation, the system can receive a layout which includes multiple instances of a pattern. Next, the system can correct the pattern instances using different photolithography process models which model the photolithography process at different exposure and focus conditions. Next, the corrected layout can be printed on a wafer. The system can then perform electrical tests on the wafer, or it can measure the critical dimensions of the features on the wafer. The yield loss or the exposure-focus matrix can then be generated by using the test data or the measurement data. | 01-14-2010 |
| 20100017764 | FUNCTIONAL VERIFICATION OF POWER GATED DESIGNS BY COMPOSITIONAL REASONING - A novel and useful method of functional verification of power gated designs by compositional reasoning. The method of the present invention performs a sequential equivalence check between the power gated design and a version of itself in which power gating is disabled. A compositional approach is first used to look for conditional equivalence of each functional block of the circuit (and its corresponding functional block with power gating disabled) under a suitable set of assumptions, guaranteed by the neighboring functional blocks. Circular reasoning rules are then employed to compose the conditional equivalences proved on the individual functional blocks back into total equivalence on the whole circuit. | 01-21-2010 |
| 20100017765 | MONITOR POSITION DETERMINING APPARATUS AND MONITOR POSITION DETERMINING METHOD - A monitor position determining apparatus includes an acquiring unit that acquires design data concerning circuit elements arranged in a layout of a semiconductor device and for each of the circuit elements, yield sensitivity data indicative of a percentage of change with respect to a yield ratio of the semiconductor device; a selecting unit that selects, based on the yield sensitivity data, a circuit element from a circuit element group arranged in the layout; a determining unit that determines an arrangement position in the layout to be an installation position of a monitor that measures a physical amount in the semiconductor device in a measurement region, the arrangement position being of the circuit element that is specified from the design data acquired by the acquiring unit and selected by the selecting unit; and an output unit that outputs the installation position determined by the determining unit. | 01-21-2010 |
| 20100023903 | METHOD AND APPARATUS FOR MULTI-DIE THERMAL ANALYSIS - Some embodiments of the invention provide a method for performing thermal analysis of a multi-die integrated circuit (IC) design layout. The thermal analysis produces a temperature distribution for analyzing internal properties of each die within the multi-die design and for analyzing thermal interactions between two or more dies of the design based on an internal configuration of the two or more dies. Therefore, in some embodiments, the temperature distribution shows a temperature distribution for each die and the individual temperature distribution show varying temperature across each of the dies. Some embodiments reduce the number of iteration required to perform the thermal analysis by constructing a high quality preconditioner based on thermal conducting segments introduced to model thermal effects at the boundaries between two dies. | 01-28-2010 |
| 20100031208 | METHOD OF DESIGNING SEMICONDUCTOR DEVICE - A method of designing a semiconductor device includes density verification of layout data of the semiconductor device at a macro level. The method includes disposing virtual patterns each including a predetermined step width on a circumference of a verification frame; and moving the verification frame outside which the virtual patterns are disposed sequentially by the predetermined step width and performing the density verification of the layout data of the semiconductor device. | 02-04-2010 |
| 20100037190 | METHODS AND SYSTEMS FOR ON-THE-FLY CHIP VERIFICATION - Methods and systems for on-the-fly chip verification method for tracking non-contiguous events. A method includes comparing a first search marker associated with a first check vector to search key associated with an output vector of a design under test (DUT). The method also includes performing either: verifying a validity of the output vector when the first search marker equals the search key, or comparing a second search marker associated with a second check vector to the search key when the first search marker does not equal the search key. | 02-11-2010 |
| 20100037191 | Method of generating reliability verification library for electromigration - A cell layout library is generated to store data on a cell. The cell includes multiple metal interconnection elements. The multiple metal interconnection elements include a first metal interconnection element group and a second metal interconnection element group. In the first metal interconnection element group, the metal interconnection elements are provided in a first direction, and an electric current flows, as a one-way electric current, in any one of the first direction and a direction opposite to the first direction. In the second metal interconnection element group, the metal interconnection elements are provided in a second direction, and an electric current flows, as a two-way current, in both of the second direction and a direction opposite to the second direction. By referring to the cell layout library, a net list is generated to associate data on the first and second metal interconnection element groups with corresponding resistance values of the first and second metal interconnection element groups, and corresponding identifiers representing the one-way and two-way electric currents. | 02-11-2010 |
| 20100042960 | Structure for Couple Noise Characterization Using a Single Oscillator - A design structure for a computer-aided design system for generating a functional design model of an integrated circuit design (having nets comprising wires) determines critical parameters for coupling noise between the wires of the nets and acceptable limits for the critical parameters. Further, methods herein include designing a ring oscillator to have stages, each of the stages measuring only one of the critical parameters. This ring oscillator is then included within an integrated circuit design and associated design structure. The embodiments herein produce an integrated circuit according to this integrated circuit design and operate the ring oscillator within the integrated circuit to measure the critical parameters of the integrated circuit and produce test results. These test results are output to determine whether the test results are within the acceptable limits. | 02-18-2010 |
| 20100042961 | IDENTIFICATION OF VOLTAGE REFERENCE ERRORS IN PCB DESIGNS - Disclosed is a computer implemented method for determining a voltage reference error in a PCB design comprising receiving information about said PCB design, identifying a signal associated with said design, receiving one or more user defined voltage references for said signal, and comparing the user defined voltage reference to the voltages of the power planes adjacent to said signal. | 02-18-2010 |
| 20100050138 | SYSTEM AND METHODOLOGY FOR DETERMINING LAYOUT-DEPENDENT EFFECTS IN ULSI SIMULATION - A layout of a semiconductor circuit is analyzed to calculate layout-dependant parameters that can include a mobility shift and a threshold voltage shift. Layout-dependant effects that affect the layout dependant parameters may include stress effects, rapid thermal anneal (RTA) effects, and lithographic effects. Intrinsic functions that do not reflect the layout-dependant effects are calculated, followed by calculation of scaling modifiers based on the layout-dependant parameters. A model output function that reflects the layout-dependant effects is obtained by multiplication of each of the intrinsic functions with a corresponding scaling parameter. | 02-25-2010 |
| 20100050139 | DATA PROCESSING DEVICE DESIGN TOOL AND METHODS - A method of designing a data processing device design includes determining thermal profile information to indicate a predicted operating temperature for a device instance in the design. The device instance is associated with a first library cell having a relatively high threshold voltage characteristic. A cost function value is determined for the device instance based on the thermal profile information and based on timing information for data paths associated with the device instance. Based on the cost function value, the library cell associated with the device instance can be changed to a cell having a higher threshold voltage characteristic. | 02-25-2010 |
| 20100058259 | OPTIMIZATION OF VERIFICATION OF CHIP DESIGN - Embodiments of methods and apparatus for optimization of verification of a chip design are disclosed. In various embodiments, a method for reducing a number of points to be verified during a verification process is disclosed, the method comprising selecting a first and a second verification point of a model of an integrated circuit design, determining whether the first and second verification points are isomorphic, and outputting the result of the determining to enable the first and second verification points being verified by verifying only a selected one of the first and second verification points in case the first and the second verification points are isomorphic. Additional variants and embodiments may also be disclosed and claimed. | 03-04-2010 |
| 20100058260 | Integrated Design for Manufacturing for 1xN VLSI Design - Embodiments that make DFM alterations to cells of 1×N building blocks via a closed-loop 1×N compiler are disclosed. Some embodiments comprise using a 1×N compiler to detect a relationship between two adjacent cells of a 1×N building block. Based on the relationship, the embodiments select a DFM alteration and apply the alteration to a physical design representation. The embodiments may apply various types of DFM alterations depending on the relationship, such as adding polysilicon, adding metal to create redundant connections, and merging diffusion areas to increase capacitance on supply nodes. Further embodiments comprise an apparatus having a cell examiner to examine two adjacent cells of a 1×N building block and determine a relationship of the two cells. The apparatus also comprises a DFM selector to select a DFM alteration based on the relationship and a DFM applicator to apply the selected DFM alteration to one of the cells. | 03-04-2010 |
| 20100058261 | TEMPORALLY-ASSISTED RESOURCE SHARING IN ELECTRONIC SYSTEMS - Methods and apparatuses to optimize integrated circuits by identifying functional modules in the circuit having similar functionality that can share circuit resources and producing a modified description of the circuit where the similar functional modules are folded onto common circuit resources and time-multiplexed using an original system clock or a fast clock. | 03-04-2010 |
| 20100058262 | VERIFICATION ASSISTING PROGRAM, VERIFICATION ASSISTING APPARATUS, AND VERIFICATION ASSISTING METHOD - A verification assisting apparatus for assisting a matching check between a specification and implementation of an object includes: an obtaining unit that obtains a specification description including elements executed to realize functions of the object and restricting conditions of the elements to realize the functions, and an implementation description concerning the functions; a creating unit that creates a graph structure including, as nodes, the elements and the restricting conditions, based on the implementation description; a first correlating unit that correlates nodes in the graph structure with the implementation description; a second correlating unit that correlates a node in the graph structure with the specification description, by detecting the node in the structure using a description concerning the element or the restricting condition in the specification description; and an outputting unit that outputs the correlation results. | 03-04-2010 |
| 20100058263 | Scanner Based Optical Proximity Correction System and Method of Use - A modeling technique is provided. The modeling technique includes inputting tool parameters into a model and inputting basic model parameters into the model. The technique further includes generating a simulated, corrected reticle design using the tool parameters and the basic model parameters. An image of test patterns is compared against the simulated, corrected reticle design. A determination is made as to whether δ | 03-04-2010 |
| 20100058264 | LOGIC CIRCUIT VERIFYING METHOD AND LOGIC CIRCUIT VERIFYING APPARATUS - A logic verification apparatus for verifying a logic circuit includes a line recognition unit that recognizes signal lines in the circuit based on design information regarding the circuit as a starting point; a decoder recognition unit that recognizes an area including an AND gate that outputs a certain logical value and an inverter as a decoder circuit area based on the design information, and determines a logical value of an input signal inputted to the recognized decoder circuit area when a logical value of the starting point has a specific logical value; and a determination unit that determines whether a logical configuration of the recognized decoder circuit area is correct based on the number of input signals and a combination of logical values of input signals between the recognized decoder circuit areas. | 03-04-2010 |
| 20100064269 | METHOD AND SYSTEM FOR DESIGN RULE CHECKING ENHANCED WITH PATTERN MATCHING - According to various embodiments of the invention, systems and methods for design rule checking enhanced with pattern matching is provided, wherein the design rule checker ignores certain patterns of the layout that violate design rules during validation. One embodiment of the invention includes receiving a first layout pattern that containing the original layout of an integrated circuit pattern. The pattern matcher processes the layout pattern and designates certain patterns of the integrated circuit pattern that meet a design waiver. The pattern matcher generates a second layout pattern with the waived patterns marked. The design rule checker subsequently processes the marked layout pattern and validates all but the marked patterns of the second layout pattern against a set of specified design rules. The design rule checker generates a third layout pattern with only the unmarked patterns of the layout being validated against the set of specified design rules. | 03-11-2010 |
| 20100064270 | Cost-Benefit Optimization for an Airgapped Integrated Circuit - A computer implemented method, apparatus and program product provide automated processes for determining the most cost-effective use of airgaps in a microchip. The performance gains realized by using airgaps for a given net or layer may be calculated. These improvements may be paired to a monetary cost associated with implementing the applicable airgaps at that net/layer. The paired benefit and cost of the airgap scenario may be compared to other possible airgap uses at other layers/nets to determine which airgaps provide the best improvement for the lowest cost. | 03-11-2010 |
| 20100064271 | METHOD AND SYSTEM FOR SIMULATING STATE RETENTION OF AN RTL DESIGN - Method and system for simulating state retention of an RTL design are disclosed. The method includes receiving a netlist description of the circuit represented in a register-transfer-level (RTL) design environment, receiving power information specifications of the circuit, identifying one or more power domains of the circuit using the netlist description and the power information specifications, associating the one or more power domains and the power information specifications in the RTL design environment, where the one or more power domains are controlled by a set of power control signals through a power manager logic, and simulating state retention behavior in response to variations in power applied to the power domain. | 03-11-2010 |
| 20100070939 | NANOTUBE CIRCUIT ANALYSIS SYSTEM AND METHOD - Carbon nanotube template arrays may be edited to form connections between proximate nanotubes and/or to delete undesired nanotubes or nanotube junctions. | 03-18-2010 |
| 20100070940 | Method and Apparatus for Merging EDA Coverage Logs of Coverage Data - An electronic design automation technology merges coverage logs. The coverage logs are generated by verification of a hardware description language circuit design. The coverage logs are merged as the coverage logs are generated, without waiting for all pending coverage logs. | 03-18-2010 |
| 20100077365 | GRAPHIC RENDERING OF CIRCUIT POSITIONING - A method may include receiving circuit information from a backend circuit test system and grouping components in the circuit information into collections by types, the types including segments, equipment, ports, and connections. The method may further include positioning, based on the grouping by types, the components from the circuit information for presentation of a circuit design on a display, and performing path rendering for the circuit design based on the positioning of the components. The method may also include sending an output file with the path rendering to a web browser. | 03-25-2010 |
| 20100077366 | METHOD AND APPARATUS FOR WORD-LEVEL NETLIST REDUCTION AND VERIFICATION USING SAME - A computer implemented representation of a circuit design is reduced by representing the circuit design as a data structure defining a netlist. A first set of nodes is identified in the netlist that includes datapath nodes, preferably nodes that do not intermingle data and control. The first set of nodes is segmented into segment widths that correspond to uniformly treated segments of the corresponding words. A second set of nodes, including nodes that intermingle data and control, are converted into bit-level nodes. The segmented nodes are analyzed to define reduced safe sizes by applying a computer implemented function. An updated data structure representing the circuit design is then generated using the reduced safe sizes of the segmented nodes. | 03-25-2010 |
| 20100077367 | LAYOUT EVALUATION APPARATUS AND METHOD - An apparatus that evaluates a layout of a semiconductor integrated circuit by estimating a result of planarization in manufacturing the circuit includes a unit that divides the layout into partial areas, a unit that calculates, for each partial area, at least one of a wiring density in the partial area, a total perimeter length of wirings in the partial area, and a maximum value of differences of wiring densities in adjacent partial areas adjacent to the partial area from the wiring density in the partial area as partial area data, a unit that sets ranges of the wiring density, the total perimeter length, and the maximum value from which a height variation larger than an upper limit value is expected as critical regions based on an equation corresponding to a type of the layout, and a unit that plots the critical regions and the partial area data on a same map. | 03-25-2010 |
| 20100083200 | METHODS, SYSTEM, AND COMPUTER PROGRAM PRODCUT FOR IMPLEMENTING COMPACT MANUFACTURING MODEL IN ELECTRONIC DESIGN AUTOMATION - Disclosed are a method, a system, and a computer program product for implementing compact manufacturing model during various stages of electronic circuit designs. In some embodiments, the method or the system receives or identifies physics based data. In some embodiments, the method or the system receives or identifies the physics based data for the corresponding manufacturing process by using the golden manufacturing process model. In some embodiments, the method or the system uses the physics based data to fine tune, modify, or adjust the golden manufacturing process model. In some embodiments, the method or the system invokes the just-right module. In some embodiments, the method or the system implements the compact manufacturing model and the correct-by-design module and provides guidelines for the various stages of the electronic circuit design. | 04-01-2010 |
| 20100083201 | Verification Technique Including Deriving Invariants From Constraints - A method of performing formal verification on a design for an integrated circuit can include accessing a set of constraints for the design. These constraints can be partitioned based on their variables, wherein any overlapping variables can result in the conjoining of their corresponding constraints. Binary decision diagrams (BDDs) can be generated based on such conjoining. Notably, invariants can be derived from the BDDs. These invariants can include constant, symmetric/implication, one-hot/zero-hot, and ternary invariants. Deriving the invariants can include cofactoring and counting of minterms of the BDDs. Using the invariants while performing formal verification on the design can advantageously optimize system performance. | 04-01-2010 |
| 20100088658 | METHOD AND APPARATUS FOR EFFICIENT INCREMENTAL STATISTICAL TIMING ANALYSIS AND OPTIMIZATION - In one embodiment, the invention is a method and apparatus for efficient incremental statistical timing analysis and optimization. One embodiment of a method for determining an incremental extrema of n random variables, given a change to at least one of the n random variables, includes obtaining the n random variables, obtaining a first extrema for the n random variables, where the first extrema is an extrema computed prior to the change to the at least one of the n random variables, removing the at least one of the n random variables to form an (n−1) subset, computing a second extrema for the (n−1) subset in accordance with the first extrema and the at least one of the n random variables, and outputting a new extrema of the n random variables incrementally based on the extrema of the (n−1) subset and the at least one of the n random variables that changed. | 04-08-2010 |
| 20100088659 | Compensating for non-uniform boundary conditions in standard cells - A method of design of a standard cell and a standard cell is disclosed. The method design comprising the steps of: identifying a non-uniformity in a boundary condition of said standard cell that would affect a characteristic of a neighbouring standard cell; introducing a further non-uniformity into said cell to mitigate the effect of said identified non-uniform boundary condition on said characteristic of said neighbouring standard cell. | 04-08-2010 |
| 20100088660 | Method for acquiring overshoot voltage and analyzing degradation of a gate insulation using the same - A method of acquiring an overshoot voltage applied to a transistor includes determining a first extraction value, the first extraction value including a product of acceleration factors determined in a test of the transistor, determining an applied time, the applied time corresponding to a length of time a voltage deviates from a predetermined level of an input voltage in a circuit employing the transistor, determining a second extraction value by dividing the first extraction value by the applied time, and determining the overshoot voltage by multiplying the second extraction value by the input voltage. | 04-08-2010 |
| 20100095255 | SYSTEM AND METHOD FOR VERIFYING RACE-DRIVEN REGISTERS - Embodiments include a system and method for generating RTL description of an electronic device provided for a design test and a test bench environment to drive stimulus into the electronic device, identifying at least one register to be verified during the design test, authoring a property list including a plurality of properties, wherein each property includes a cause and an effect, creating a new property instance upon receiving an enqueue cause, transitioning a property instance from a waiting state to a pending state based on a dequeue cause, advancing property instances from the pending state to an active state and then to an expired state based on a defined time window, creating a current solution space including a plurality of solutions, wherein each of the plurality of solutions includes a list of unused active effects, inserting property instances into each of the plurality of solutions when the property instance enters to active state, pruning solutions from the current solutions space which have not used a property instance entering the expired state, and computing a new solution space based on the current solution space and target transition. | 04-15-2010 |
| 20100095256 | Power State Transition Verification For Electronic Design - Various implementations of the invention may be applied to generate an auxiliary verification statement. The auxiliary verification statement defines properties that may be employed to check if the power domains are active at appropriate times. Particularly, the auxiliary verification statement checks to ensure that power domain transitions do not interfere with the operation of the device design. With various implementations of the invention, an auxiliary verification statement may be generated by first determining a set of properties instantiated in a verification statement and then synthesizing the auxiliary verification statement based upon the determined properties, the corresponding device design and the power domains. In some implementations, the auxiliary verification statement instantiates properties that check if the power domains related to the properties in the verification statement are active when the verifications statement is exercised. In various implementations, this is accomplished by substituting select ones of the properties in the verification statement with select properties corresponding to the power domain. | 04-15-2010 |
| 20100095257 | ELECTROMAGNETIC FIELD ANALYSIS OF SEMICONDUCTOR PACKAGE WITH SEMICONDUCTOR CHIP MOUNTED THEREON - An electromagnetic field analysis of a semiconductor package with a semiconductor chip mounted thereon can be performed simply with a high accuracy. First modeling and second modeling of the semiconductor package with the semiconductor chip mounted thereon are carried out, thereby performing first and second electromagnetic field analyses. Results of the first and second electromagnetic field analyses are synthesized to determine electrical characteristics of the semiconductor package. Specifically, an inductance analysis is performed with the entire semiconductor chip regarded as a dielectric, thereby determining an inductance component of an equivalent circuit. A capacitance analysis is performed with the semiconductor chip regarded as a dielectric having a metal thin film on its surface, thereby determining a capacitance component of an equivalent circuit. Results of the inductance analysis and the capacitance analysis are synthesized to determine an equivalent circuit. | 04-15-2010 |
| 20100095258 | Wiring layout method of integrated circuit and computer-readable medium storing a program executed by a computer to execute the same - A wiring layout method includes designing a layout of a power wiring for an integrated circuit; designing a layout of plural signal wirings for the integrated circuit; comparing the signal frequency; classifying the signal wirings; calculating an evaluation value of a temperature rise; and modifying the layouts of the integrated circuit. | 04-15-2010 |
| 20100100859 | DESIGN METHODOLOGY FOR PREVENTING FUNCTIONAL FAILURE CAUSED BY CDM ESD - A design methodology which prevents functional failure caused by CDM ESD events. A transistor model is used to model the final states of cells, and a simulator is then used to identify invulnerable cells. Cells that are potential failure sites are then identified. The cells which have been identified as being potential victims are replaced by the previously-identified invulnerable cells that have the identical logic function. On the other hand, if a cell with identical function cannot be found, an invulnerable buffer cell (that will not effect logic function) can be inserted in front of the potential victim transistor as protection. By replacing all the potential victim cells with cells which have been determined to be invulnerable, the resulting design will be guaranteed to be CDM ESD tolerant. | 04-22-2010 |
| 20100100860 | METHOD AND APPARATUS FOR DEBUGGING AN ELECTRONIC SYSTEM DESIGN (ESD) PROTOTYPE - Using a vector-based emulation technique, a hardware-based prototyping system reduces time-consuming recompilation and reduces the iteration time for a verification run. The vector-based emulation technique takes advantage of information derived from user-defined probe points, automatically generated probe points and low-latency snapshots. Using a bounded-cycle simulation technique, the hardware-based prototyping system can provide complete or partial simulation traces covering interested signals and can efficiently evaluates assertions. A user is therefore able to debug in a real system test and to identify causes of fault conditions interactively under a controlled vector debugging environment. | 04-22-2010 |
| 20100107130 | 1XN BLOCK BUILDER FOR 1XN VLSI DESIGN - Embodiments that generate 1×N building block representations for an IC design via a GUI of a 1×N block builder are disclosed. Some embodiments enable, via a GUI, selection of a logical function for a 1×N building block. The embodiments also comprise enabling selection of an implementation from a number of implementations of the logical function and automatically generating a 1×N building block representation of the logical function based on the selected implementation. The generated 1×N building block representation comprises an RTL description of the 1×N building block. Further embodiments comprise an apparatus having a GUI generator, a logical function selector to select a logical function, an implementation selector to select an implementation of the logical function from a number of implementations, and a 1×N building block generator to generate a 1×N building block representation of the 1×N building block based on the selected implementation. | 04-29-2010 |
| 20100107131 | METHOD AND APPARATUS FOR MEMORY ABSTRACTION AND VERIFICATION USING SAME - A computer implemented representation of a circuit design including memory is abstracted to a smaller netlist, which can be analyzed by standard verification tools and by other tools that operate on netlists. The correctness of such systems can require reasoning about a much smaller number of memory entries than exist in the circuit design, and by abstracting such memories to a smaller number of entries, the computational complexity of the verification problem is substantially reduced. | 04-29-2010 |
| 20100107132 | METHOD AND APPARATUS FOR MEMORY ABSTRACTION AND FOR WORD LEVEL NET LIST REDUCTION AND VERIFICATION USING SAME - A computer implemented representation of a circuit design including memory is abstracted to a smaller netlist by replacing memory with substitute nodes representing selected slots in the memory, segmenting word level nodes, including one or more of the substitute nodes, in the netlist into segmented nodes, finding reduced safe sizes for the segmented nodes and generating an updated data structure representing the circuit design using the reduced safe sizes of the segmented nodes. The correctness of such systems can require reasoning about a much smaller number of memory entries and using nodes having smaller bit widths than exist in the circuit design. As a result, the computational complexity of the verification problem is substantially reduced. | 04-29-2010 |
| 20100107133 | Method for increasing cell uniformity in an integrated circuit by adjusting cell inputs to design process - A method of making instances of a reference cell more uniform across an integrated circuit (IC) by providing a nominal cell for the reference cell and modifying an initial IC layout description to create input into an Optical Proximity Correction (OPC) engine, so as to make the cell instances more like the nominal cell during an IC layout process. | 04-29-2010 |
| 20100107134 | Designing apparatus, designing method, and designing program for semiconductor integrated circuit - A designing apparatus includes an initial estimating portion, a general power supply noise analyzing portion, a layout designing portion, a detail estimating portion, a detail power supply noise analyzing portion, and a layout adjusting portion. The initial estimating portion estimates general values of an entire consumed current and an entire on-chip capacitance. Based on the estimated general values, the general power supply noise analyzing portion creates a lumped constant circuit model so as to conduct a power supply noise analysis, for computing a current-capacitance ratio. Based on the current-capacitance ratio, the layout designing portion performs placement of cells for each of predetermined regions obtained by dividing a placement region. The detail estimating portion creates a lumped constant circuit model for each of the predetermined regions so as to estimate detail values of the consumed current and the on-chip capacitance for each of the predetermined regions. Based on the detail values, the detail power supply noise analyzing portion conducts a detail power supply noise analysis. Based on a result of the detail power supply noise analysis, the layout adjusting portion performs adjustment of the placement of the cells. | 04-29-2010 |
| 20100115480 | LOGIC CIRCUIT DESIGN VERIFICATION APPARATUS, LOGIC CIRCUIT DESIGN VERIFICATION METHOD , AND MEDIUM STORING LOGIC CIRCUIT DESIGN VERIFICATION PROGRAM - A logic circuit design verification apparatus includes an inputting unit configured to input a circuit description and an assertion description, an extracting unit configured to extract signal names from the circuit description input by the inputting unit, a lack detector configured to detect a signal name not included in a postulation and a verification requirement in the assertion description input by the inputting unit among the signal names extracted by the extracting unit, and an outputting unit configured to output the signal name detected by the lack detector. | 05-06-2010 |
| 20100115481 | Shape-Based Geometry Engine To Perform Smoothing And Other Layout Beautification Operations - A shape-based layout beautification operation can be performed on an IC layout to correct layout imperfections. A shape is described by edges (and vertices) related according to specified properties. Each shape can be configured to match specific layout imperfection types. Corrective actions can then be associated with the shapes, advantageously enabling efficient formulation and precise application of those corrective actions. Corrective actions can include absolute, adaptive, or replacement-type modifications to the detected layout imperfections. A concurrent processing methodology can be used to minimize processing overhead during layout beautification, and the actions can also be incorporated into a lookup table to further reduce runtime. A layout beautification system can also be connected to a network across which shapes, actions, and IC layout data files can be accessed and retrieved. | 05-06-2010 |
| 20100122226 | LAYOUT DENSITY VERIFICATION SYSTEM AND LAYOUT DENSITY VERIFICATION METHOD - A layout density verification system has: a model generation unit configured to generate a macro model for use in metal density check, with respect to a macro included in a layout data; and a metal density check unit configured to perform the metal density check of the layout data by using the macro model. The macro model includes: an inner region; and an outer region surrounding the inner region and located between the inner region and an outer boundary of the macro. The inner region is masked by metal while a metal layout within the outer region is maintained. A width of the outer region inward from the outer boundary of the macro is equal to or larger than a width of one side of a window as a check unit at a time of the metal density check. | 05-13-2010 |
| 20100122227 | System and Technique of Pattern Matching and Pattern Replacement - A system and technique to specifies patterns to search for in an integrated circuit layout, and specifies proposed replacement patterns. A description file includes specifications for one or more patterns to be searched for. In the description file, for each pattern, there may be one or more proposed replacement patterns. The description file is read. Pattern matches, if any, in a layout are found. A proposed replacement pattern is tested in place of a matched pattern. If acceptable, the proposed pattern may be used to replace the matched pattern. | 05-13-2010 |
| 20100125821 | Design support method - A method for a design support is provided. The method includes a computer that executes processes of detecting a combination of vias comprising a target via and a neighboring via-; calculating a distance between the combination of the target via and the neighboring via, replacing a shape of the target via and a shape of at least one of the neighboring via with a shape of an exposure pattern of the via, searching the adjacent wiring arranged within the distance between the vias or less from a position of the target via after the process of replacing, and converting the position of the neighboring via to which the process of replacing is applied to the position searched by the process of searching and storing the position in the database; and outputting the layout data converted by the process of converting. | 05-20-2010 |
| 20100131909 | FAST LITHOGRAPHY COMPLIANCE CHECK FOR PLACE AND ROUTE OPTIMIZATION - A computer is programmed to use at least one rule to identify from within a layout of an IC design, a set of regions likely to fail if fabricated unchanged. An example of such a rule of detection is to check for presence of two neighbors neither of which fully overlaps a short wire or an end of a long wire. The computer uses at least another rule to change at least one region in the set of regions, to obtain a second layout which is less likely to fail in the identified regions. An example of such a rule of correction is to elongate at least one of the two neighbors. The computer may perform optical rule checking (ORC) in any order relative to application of the rules, e.g. ORC can be performed between detection rules and correction rules i.e. performed individually on each identified region prior to correction. | 05-27-2010 |
| 20100138800 | PRINTED CIRCUIT BOARD ANALYZING SYSTEM, PRINTED CIRCUIT BOARD DESIGNING ASSISTING SYSTEM, THEIR METHODS, AND PROGRAM - A printed circuit board analyzing system for analyzing the whole circuit of a multilayer printed circuit board to perform circuit analysis of noise propagation in the printed circuit board having structure in which the shapes of stacked conductor planes are different or planes are provided side by side in the same layer by quickly providing an adjacent interference part equivalent circuit model representing noise interference parts causing interference between adjacent opposed planes and by coupling the plane pairs to the adjacent interference part equivalent circuit. | 06-03-2010 |
| 20100146466 | METHODS AND SYSTEMS FOR WIRING SYSTEMS ANALYSIS AND VERIFICATION - A method for visually verifying an implementation of a design is described. The method includes integrating logical design data, physical design data, and physical implementation data into a common data format and graphically displaying the commonly formatted data to provide a visualization of the design, the visualization including a spatial context component associated with the physical implementation data. | 06-10-2010 |
| 20100153893 | CONSTRAINT MANAGEMENT AND VALIDATION FOR TEMPLATE-BASED CIRCUIT DESIGN - A technique for constraint management and validation for template-based device designs is disclosed. The technique includes generating a template-level representation of an electronic device design based on a transistor-level representation of the electronic device design. The template-level representation includes one or more hierarchies of templates. Each template represents a corresponding portion of the electronic device design. The technique further includes determining constraint declarations associated with the electronic device design and verifying whether there is a functional equivalence between the template-level representation to a register-transfer-level (RTL) representation of the electronic device design. The technique additionally includes verifying whether the constraint declarations are valid and verifying the electronic device design responsive to verifying the functional equivalence and verifying the constraint declarations. | 06-17-2010 |
| 20100153894 | METHOD AND SYSTEM FOR SEMICONDUCTOR DESIGN HIERARCHY ANALYSIS AND TRANSFORMATION - A method and apparatus for partitioning of the input design into repeating patterns called template cores for the application of reticle enhancement methods, design verification for manufacturability and design corrections for optical and process effects is accomplished by hierarchy analysis to extract cell overlap information. Also hierarchy analysis is performed to extract hierarchy statistics. Finally template core candidates are identified. This allows to the design to be made amenable for design corrections or other analyses or modifications that are able to leverage the hierarchy of the design since the cell hierarchy could otherwise be very deep or cells could have significant overlap with each other. | 06-17-2010 |
| 20100162190 | FEASIBILITY OF IC EDITS - One embodiment relates to a computer method of evaluating proposed edits to a target layer of an integrated circuit. In the method, a number of editable regions is determined for metal layers overlying the target layer, where an editable region for a metal layer is laterally arranged between segments of the metal layer. The method identifies a number of possible vertical milling paths that extend from an exterior surface of the integrated surface to the target layer. Each possible vertical milling path passes through at least one editable region. The method generates a number of possible edit plans that are based on both the proposed edits and the number of possible vertical milling paths, where each edit plan places edits in a different combination of possible vertical milling paths. | 06-24-2010 |
| 20100162191 | METHOD AND SYSTEM FOR PERFORMING CELL MODELING AND SELECTION - An improved method, system, and computer program product for selecting components for an early stage electronic design is disclosed. A library of cells is modeled and is characterized by parameter combinations, where the cell modeling information is based upon ranking and scoring of the cells in the cell library. Based upon design specification information for an electronic design, the cell modeling data is used to select one or more representative cells for the early stage design based upon the list of ranked cells. The rankings provide an indication of the appropriateness of the selected cells for the early stage design. The pre-modeling of the cells provides high efficiency at run-time when there is a need to quickly select cells for the early stage design. | 06-24-2010 |
| 20100162192 | Logic Injection - A technique for reducing a circuit listing. According to examples of the technique, at least a portion of a circuit listing is analyzed to identify occurrences of a circuit structure made up of a plurality of circuit components. For each identified occurrence of the defined circuit structure, an injection data object is created corresponding to the plurality of components, and the injection data object is substituted into the portion of the circuit listing in place of the plurality of components. For each occurrence of the defined structure, one or more properties of the occurrence of the defined structure may be determined and contained by the corresponding injection data object. | 06-24-2010 |
| 20100169853 | Method and System for Implementing Graphical Analysis of Hierarchical Coverage Information Using Treemaps - An improved method, system, user interface, and computer program product is disclosed for performing graphical analysis of coverage. According to some approaches, a graphical user interface uses treemaps to provide analysis of verification coverage. This allows the user to efficiently obtain the overall and/or complete picture of the coverage space, as well as the relative size of nodes in terms of number of coverage elements contained in them. Moreover, the present treemap approach provides relative comparison of coverage of the nodes and allows the user to identify whether there is any missing coverage, and if so, whether the missing coverage evenly balanced. This information is very useful for the decision made by the user regarding overall coverage and steps to be taken to improve the coverage. | 07-01-2010 |
| 20100169854 | ESD PROTECTION VALIDATOR, AN ESD VALIDATION SYSTEM AND A METHOD OF VALIDATING ESD PROTECTION FOR AN IC - Disclosed is an electrostatic discharge (ESD) protection validator, a method of validating ESD protection for an IC and an ESD validation system. In one embodiment, the ESD protection validator includes: (1) a circuit analyzer configured to compare component information of the IC with predefined ESD protection elements to identify ESD cells of the IC and (2) an ESD cell verifier configured to compare physical attributes associated with the identified ESD cells to ESD protection requirements and determine compliance therewith. | 07-01-2010 |
| 20100169855 | METHOD AND SYSTEM DETECTING METAL LINE FAILURE - In a method of detecting metal line failures for a full-chip, a first net-list is converted to a second net-list. The first net-list includes first information related to elements and metal lines, and the second net-list includes second information susceptible to direct current analysis. Current densities of the metal lines are calculated by performing the direct current analysis on the second net-list. Defective metal lines among the metal lines are detected based on the current densities of the metal lines. | 07-01-2010 |
| 20100175033 | SCATTEROMETRY METROLOGY TARGET DESIGN OPTIMIZATION - A metrology target design may be optimized using inputs including metrology target design information, substrate information, process information, and metrology system information. Acquisition of a metrology signal with a metrology system may be modeled using the inputs to generate one or more optical characteristics of the metrology target. A metrology algorithm may be applied to the characteristics to determine a predicted accuracy and precision of measurements of the metrology target made by the metrology system. Part of the information relating to the metrology target design may be modified and the signal modeling and metrology algorithm may be repeated to optimize the accuracy and precision of the one or more measurements. The metrology target design may be displayed or stored after the accuracy and precision are optimized. | 07-08-2010 |
| 20100175034 | LAYOUT VERIFICATION DEVICE, LAYOUT VERIFICATION PROGRAM, AND LAYOUT VERIFICATION METHOD OF LAYOUT PATTERN OF SEMICONDUCTOR DEVICE - A layout verification device according to the present invention includes a layout verification unit that outputs a first error graphic corresponding to an area where there is an inconsistency with a design rule in a first layout pattern, and includes a target error graphic setting unit that sets a processing target area including the first error graphic, an error graphic search unit that searches a second error graphic included in a processing target area of a second layout pattern where verification by the layout verification unit has already been performed, and an error graphic equivalence judgment unit that judges that the first error graphic and the second error graphic are non-equivalent when a second target vertex coordinate of the second error graphic does not match any one of a plurality of peripheral vertex coordinates set in grid intersections adjacent to the first target vertex coordinate of the first error graphic. | 07-08-2010 |
| 20100175035 | INTEGRATED CIRCUIT STRUCTURE INCORPORATING AN INDUCTOR, AN ASSOCIATED DESIGN METHOD AND AN ASSOCIATED DESIGN SYSTEM - Disclosed are embodiments of a circuit (e.g., an electrostatic discharge (ESD) circuit), a design methodology and a design system. In the circuit, an ESD device is wired to a first metal level (e.g., M1). An inductor is formed in a second metal level (e.g., M5) above the first metal level and is aligned over and electrically connected in parallel to the ESD device by a single vertical via stack. The inductor is configured to nullify, for a given application frequency, the capacitance value of the ESD device. The quality factor of the inductor is optimized by providing, on a third metal level (e.g., M3) between the second metal level and the first metal level, a shield to minimize inductive coupling. An opening in the shield allows the via stack to pass through, trading off Q factor reduction for size-scaling and ESD robustness improvements. | 07-08-2010 |
| 20100175036 | LOGIC CIRCUIT MODEL VERIFYING METHOD AND APPARATUS - To a logic circuit model, a test pattern by a combination of a first logical value A representing 0 or 1 and a second logical value B representing 1 or 0 as an inverse value corresponding to the first logical value A is given to calculate an output of the logic circuit model with a logical operation and, when the output is compared with an expected value for the test pattern and they are equal to each other, it is determined that the operation of the logic circuit model is correct. With the second logical value B representing 1 when the first logical value represents 0 and the second logical value B representing 0 when the first logical value A represents 1, a logical operation of the logic circuit model is performed. | 07-08-2010 |
| 20100180239 | Method for defect diagnosis and management - A method for defect diagnosis and management, which is implemented in a process for fabricating an article, comprising the following steps: obtaining an inspection image of the article, wherein the inspection image shows at least one defect of the article; retrieving a design layout corresponding to the inspection image, wherein the design layout has a plurality of conductive regions; matching the inspection image and the design layout for correcting the coordinates of the defect on the design layout; and determining overlaps between the defect and the conductive regions to judge whether the defect causes an open failure or a short failure. Via this method, the accurate coordinates of the defect on the design layout can be found, so that the defect can be further judged as to whether it will cause a failure, or not. | 07-15-2010 |
| 20100180240 | OPTIMIZING SYSTEMS-ON-A-CHIP USING THE DYNAMIC CRITICAL PATH - The Global Dynamic Critical Path is used to optimize the design of a system-on-a-chip (SoC), where hardware modules are in different clock domains. Control signal transitions of the hardware modules are analyzed to identify the Global Dynamic Critical Path. Rules are provided for handling specific situations such as when concurrent input control signals are received by a hardware module. A configuration of the hardware modules is modified in successive iterations to converge at an optimum design, based on a cost function. The cost function can account for processing time as well as other metrics, such as power consumed. For example, during the iterations, hardware modules which are in the Global Dynamic Critical Path can have their clock speed increased and/or additional resources can be added, while hardware modules which are not in the Global Dynamic Critical Path can have their clock speed decreased and/or unnecessary resources can be removed. | 07-15-2010 |
| 20100180241 | METHOD OF DESIGNING SEMICONDUCTOR DEVICE AND DESIGN PROGRAM - A semiconductor device has an interconnect structure that includes a main interconnection and a contact structure. Parameters contributing to parasitic capacitance and interconnect resistance of the interconnect structure include: main parameters including width/thickness of the main interconnection; and sub parameter. Variation of each parameter from a design value caused by manufacturing variability is represented within a predetermined range. A method of designing the semiconductor device includes: calculating the maximum capacitance value, the minimum capacitance value, the maximum resistance value and the minimum resistance value of the interconnect structure under a condition that respective variation amplitudes of the main parameters do not simultaneously take maximum values and variation of the sub parameter is fixed to a predetermined value; generating a CR-added netlist; and performing operation verification of the semiconductor device by using the CR-added netlist. | 07-15-2010 |
| 20100185992 | System for Quickly Specifying Formal Verification Environments - Computer-implemented techniques are disclosed for defining an environment for formal verification of a design-under-test. Initially there is extraction of design inputs by a design analysis module, and presentation of the inputs on a graphical user interface. Behavior options for the design inputs are offered on the graphical user interface for selection by an operator. Environment code that is descriptive of the design inputs and selected behavior options is emitted, typically in a hardware description language, for submission to a formal verification tool. A meta-code file containing the assigned behavior options is generated to aid subsequent sessions. | 07-22-2010 |
| 20100185993 | METHOD FOR SCALABLE DERIVATION OF AN IMPLICATION-BASED REACHABLE STATE SET OVERAPPROXIMATION - A method, system and computer program product for integrating implication-based analysis and equivalent gate analysis to maintain transitive reduction in an implication graph over a sequence of graph operations. One or more gates of a design are identified that are equivalent in all reachable states. Equivalent gates are assigned to an equivalence class when all gates within the equivalence class are equal. During the implication-based analysis the system determines when one or more implication paths are associated with the one or more equivalence classes, and an implication is generated at the implication path associated with the equivalence classes. A transitively reduced graph is received depicting the implications and equivalence classes of the design. When one or more operations are assigned to the transitively reduced graph, the graph is automatically adjusted to maintain transitive reduction. | 07-22-2010 |
| 20100185994 | Topological Pattern Matching - Techniques for more efficiently identifying specific topological patterns in microdevice design data, such as layout design data. A user provides a topological pattern matching tool with a pattern template. In response, the topological pattern matching tool will analyze the pattern template to create a set of “design rule check” operations that can be performed to identify topological features of the layout design that will include the set of topological features specified for the template. The topological pattern matching tool also specifies properties that should be determined for each set of topological features identified by a design rule check operation. Once the design rule check operations have been created, the tool applies them to the layout design data being analyzed. The results produced by the design rule check operations will be a group of topological features in the layout design that encompass the topological features specified for the template. The results also will include a set of properties for each of the identified topological features. Next, the pattern matching tool creates a search graph based upon the results of the design rule check operations. Once the search graph is constructed, the pattern matching tool traverses the search graph to identify combinations of nodes connected by graph edges representing feature characteristics that match the constraints specified for the pattern template. For each such identified combination of nodes, the tool will output the arrangement of geometric elements corresponding to the nodes as a topological match to the original template. | 07-22-2010 |
| 20100185995 | Electrostatic Damage Protection Circuitry Verification - Techniques for efficiently determining whether an interconnect line has an impedance component value below a maximum specified value. A specified maximum impedance component value is used to limit the number of interconnect lines that are analyzed by a parasitic extraction analysis process. An analysis window is created based upon the characteristics of the interconnect lines and the specified maximum impedance component value. The size of the window corresponds to the minimum length of the interconnect line that would have the specified maximum impedance component value. Once the analysis window has been created, the interconnect lines are examined to determine if any of them reaches to (or beyond) the analysis window, whereby interconnect lines that exceed the specified maximum impedance component value can be identified. If there are any remaining interconnect lines that have not been determined to exceed the specified maximum impedance component value through the use of the analysis window, then the impedance component values of these remaining interconnect lines can be specifically determined using a parasitic extraction process. | 07-22-2010 |
| 20100192113 | METHOD AND APPARATUS FOR MANAGING VIOLATIONS AND ERROR CLASSIFICATIONS DURING PHYSICAL VERIFICATION - Some embodiments provide a system for managing violations during physical verification. The system may identify a design-rule-check (DRC) violation by applying a set of DRC rules to a layout. The system can then receive an error classification from the user which specifies how the DRC violation is to be handled. Next, the system can store the DRC violation, the user-selected error classification, and a user identifier associated with the user in a database. If the user is not authorized to approve the error classification, the database can indicate that the error classification has not been approved. Later, a user who is authorized to approve the error classification can approve the error classification. The system can determine if a cell is known, and if so, the system can use the violations and error classifications stored in the database to speed up the verification process. | 07-29-2010 |
| 20100192114 | METHOD AND APPARATUS FOR PERFORMING ABSTRACTION-REFINEMENT USING A LOWER-BOUND-DISTANCE - Embodiments of the present invention provide methods and apparatuses for verifying the functionality of a circuit. The system can determine a lower-bound-distance (LBD) value, such that the LBD value is associated with an LBD abstract model of the CUV which does not satisfy a property. The system can use an abstraction-refinement technique to determine whether the CUV satisfies the property. The system can determine an upper-bound-distance value for an abstract model which is being used in the abstraction-refinement technique, and can determine whether the LBD value is greater than or equal to the upper-bound-distance value. If so, the system can conclude that the abstract model does not satisfy the property, and hence, the system can decide not to perform reachability analysis on the abstract model that is currently being used in the abstraction-refinement technique. | 07-29-2010 |
| 20100192115 | POWER-AWARE DEBUGGING - A debugging system produces displays in response to an IC design and results of a logic simulation of IC behavior based on the IC design. The IC design includes a hardware description language (HDL) model of the IC describing the IC as comprising cell instances communicating via data signals and power sources for supplying power to the cell instances. The IC design also includes power definition markup language (PDML) model describing a power intent of the IC design. The debugging system generates displays representing HDL code that are annotated to indicate how the power intent of the IC design described by the PDML model relates to the portion of the HDL model represented by the display. The debugging system also generates signals trace displays indicating how both the logic and power intent of the IC design affect the value of a user-selected signal at a user-selected time during the logic simulation. | 07-29-2010 |
| 20100199241 | Method and System for Automated Use of Uninterpreted Functions in Sequential Equivalence Checking - A method, system and computer program product for automated use of uninterpreted functions in sequential equivalence checking. A first netlist and a second netlist may be received and be included in an original model, and from the original model, logic to be abstracted may be determined. A condition for functional consistency may be determined, and an abstract model may be created by replacing the logic with abstracted logic using one or more uninterpreted functions. One or more functions may be performed on the abstract model. For example, the one or more functions may include one or more of a bounded model checking (BMC) algorithm, an interpolation algorithm, a Boolean satisfiability-based analysis algorithm, and a binary decision diagram (BDD) based reachability analysis algorithm, among others. | 08-05-2010 |
| 20100199242 | Verification Test Failure Analysis - Methods and apparatuses are provided that allow for efficient analysis of a graph describing tests, elements of a device design and test results. In various implementations of the invention, a relationship between the elements of a device design, and test results is performed. An entropy value is determined for each corresponding element based upon the test results. The entropy value may assist test engineers in identifying the elements of the device design needing redesign. | 08-05-2010 |
| 20100205572 | ADAPTIVE MESH RESOLUTION IN ELECTRIC CIRCUIT SIMULATION AND ANALYSIS - An adaptive mesh of virtual nodes is provided to analyze the performance of a power/ground plane pair having an irregular shape. Plane transmission line characteristics and regional modal resonances can be modeled accurately, and with a significant decrease in simulation time as compared to traditional methods. A variable-sized cell structure is constructed with smaller cells in irregular regions and with larger cells in uniform regions. Grid nodes may thus stay aligned along length and width to allow parameters of equivalent circuit models to be scaled appropriate to the cell size. | 08-12-2010 |
| 20100205573 | LAYOUT MODIFICATION ENGINE FOR MODIFYING A CIRCUIT LAYOUT COMPRISING FIXED AND FREE LAYOUT ENTITIES - The invention relates to a layout modification engine ( | 08-12-2010 |
| 20100205574 | SUPPORT APPARATUS AND METHOD - A design support apparatus includes: a logical expression substitution unit to substitute a part of the logical expression, which includes a function expression of the design variables and a quantifier attached to the design variable, with a substitution variable; a quantifier elimination unit to generate a relational expression including the substitution variable and design variables without the quantifier by eliminating the design variable to which the quantifier is attached from the logical expression; a sampling point generation unit to generate a plurality of sampling points corresponding to the design variables and the substitution variable included in the relational expression; a possible range computation unit to compute, for each of the sampling points, a possible range that the relational expression may take, by calculating values of remaining design variables included in the relational expression based on the relational expression; and a possible range display unit to display the possible range. | 08-12-2010 |
| 20100211921 | DEVELOPMENT VERIFICATION APPARATUS FOR UNIVERSAL CHIP - A development verification apparatus for verification of universal chips, including an object design module for storing and executing the object code of the chip to be verified, a control processing module for executing the control program etc. of the user of the development verification apparatus, a power management module for managing the power and charging the battery, and an extended function module for implementing developing function in various fields. | 08-19-2010 |
| 20100218148 | Method and System for Sequential Netlist Reduction Through Trace-Containment - Methods and systems are provided for sequential netlist reduction through trace-containment for a circuitry design netlist by first identifying a cut of the netlist and enumerating a set of mismatch traces. Perform time-bounded unfolding of a cofactored version of the cut to reflect the sequential cofactor for a specific input i and temporal uncorrelation constraints for the set of inputs ‘J’. Determine whether there is trace containment by performing equivalence checking with respect to the cut of the netlist under temporal uncorrelation constraints for the set of inputs ‘J’. In response to detecting trace containment, simplify the netlist by merging the input ‘i’ to a constant. | 08-26-2010 |
| 20100218149 | METHOD AND APPARATUS FOR HARDWARE DESIGN VERIFICATION - An apparatus for verifying an operation of a hardware descriptor program under test includes a lexical analyzer, a parsing engine and a generator. The lexical analyzer receives input/output (I/O) information of hardware descriptor language code that represents a circuit description of an integrated circuit to be tested. The lexical analyzer performs lexical analysis on the I/O information of the hardware descriptor language code so as to generate a stream of tokens. The parsing engine interprets the stream of tokens representing the I/O information of the hardware descriptor language code based on an interpretation of rules required to test a plurality of functions capable of being executed by the integrated circuit. The generator generates verification module code based on the interpretation of the stream of tokens representing the I/O information of the hardware descriptor language code and the rules interpretation. | 08-26-2010 |
| 20100218150 | Logic Design Verification Techniques for Liveness Checking - A technique for verification of a logic design (embodied in a netlist) using a liveness-to-safety conversion includes assigning liveness gates for liveness properties of the netlist and assigning a single loop gate to provide a loop signal for the liveness gates. Assertion of the single loop gate is prevented when none of the liveness gates are asserted. A first state of the netlist is sampled and the sampled first state provides an initial state for a first behavioral loop for at least one of the liveness gates following the assertion of the single loop gate. The sampled first state of the first behavioral loop is compared with a later state of the first behavioral loop to determine if the sampled first state is repeated. A liveness violation is returned when the sampled first state is repeated and an associated one of the liveness gates remains asserted for a duration of the first behavioral loop. | 08-26-2010 |
| 20100218151 | WIRING DESIGN METHOD FOR WIRING BOARD - A wiring design method for a wiring board comprises, if design rule errors are found in the wiring design, selecting one of the design rule errors as a selected design rule error, specifying a predetermined number of the second connection terminals as selected second connection terminals that correspond to the selected design rule error, and moving the selected second connection terminals to predetermined coordinate positions. Each time when the selected second connection terminals are moved to the post-movement coordinate positions, the method comprises connecting the second connection terminals and the first connection terminals, conducting the design rule check, and determining whether no design rule errors are detected newly and the selected design rule error is not detected either. | 08-26-2010 |
| 20100223583 | HIERARCHICAL FEATURE EXTRACTION FOR ELECTRICAL INTERACTION CALCULATIONS - A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions. | 09-02-2010 |
| 20100229134 | LAYOUT VERIFICATION METHOD - A layout verification method for verifying a layout of a semiconductor device by a computer having a memory storing layout data and information of operation conditions for a plurality of operation modes in which the semiconductor device is expected to assume during its testing and practical use, the semiconductor device including a semiconductor substrate of one conductivity type, a plurality of wells accommodating at least one of the circuit elements and being applicable to a plurality of different bias voltages in dependence of the operation modes, the method includes specifying combination of all the adjacent pairs of the wells located adjacently to each other within the semiconductor substrate, and the distance of each of all the adjacent pairs of the wells in reference to the layout data, determining, for each of the wells. | 09-09-2010 |
| 20100229135 | METHOD AND APPARATUS FOR INSERTING METAL FILL IN AN INTEGRATED CIRCUIT ("IC") LAYOUT - Some embodiments of the invention provide a method for inserting several fills in an integrated circuit (“IC”) layout. The method identifies a set of potential fills in a region of an IC layout, where the set of potential fills has a first fill size, wherein the first fill size is from a set of fill sizes. The method specifies a halo around each potential fill in the set of potential fills. For each potential fill, the method determines whether the specified halo overlaps with a foreign object in the region of the layout. For each potential fill, the method specifies a legal fill in the region of the IC layout if the specified halo does not overlap with a foreign object in the region of the IC layout. The method inserts at least one legal fill in the region of the IC layout. In some embodiments, the halo is a spacing halo. | 09-09-2010 |
| 20100235795 | EXECUTION MONITOR FOR ELECTRONIC DESIGN AUTOMATION - Embodiments of a computer system, a method, a graphical user interface and a computer-program product (i.e., software) for use with the computer system are described. A chip designer may use these devices and techniques to configure and monitor the execution of tasks in a user-configurable electronic-design-automation (EDA) flow associated with a circuit or chip design. In particular, using an intuitive and interactive graphical user interface in EDA software, the chip designer can configure and initiate execution of the EDA flow. Then, during execution of EDA tasks in the EDA flow, an execution monitor in the graphical user interface may provide a graphical representation of real-time execution status information for the EDA tasks. Moreover, using the EDA software, the chip designer can debug the circuit or chip design if any errors or problems occur. | 09-16-2010 |
| 20100235796 | VERIFICATION APPARATUS - A design verification apparatus for a semiconductor device includes: a storage for storing layout information of the semiconductor device, the layout information including information of interconnection regions and a via regions; and a controller for dividing the interconnection regions into wire regions and cross regions, the cross regions corresponding to the via regions, respectively, the wire regions extending between the cross regions, respectively, and extracting at least one of the wire regions as a candidate having a potential risk of future disconnection defect on the basis of the length of the wire regions. | 09-16-2010 |
| 20100235797 | MACRO LAYOUT VERIFICATION APPARATUS - A macro layout verification apparatus for verifying a layout of a macro to be placed as a functional block on a semiconductor device. The apparatus includes: a unit, which assumes as a virtual wiring line, a wiring line that uses an unused intra-macro channel located adjacent to an intra-macro wiring line; a unit which calculates a parallel wiring length along which the virtual wiring line and the intra-macro wiring line run; and a unit which outputs information concerning the virtual wiring line when the parallel wiring length exceeds a reference value defined as a design rule. | 09-16-2010 |
| 20100242003 | Hierarchical Verification Of Clock Domain Crossings - The invention provides for the hierarchical verification of clock domain crossings. In various implementations of the invention, a device design is partitioned into blocks. Subsequently, a block level clock domain crossing verification process is performed on selected ones of the blocks. Verification interface files are generated by the block level clock domain crossing process. After which, a top level clock domain crossing verification process is performed over the entire design. In various implementations, the top level clock domain crossing verification process utilizes the verification interface files to verify clock domain crossing signals between blocks. Additionally, in some implementations, blocks not verified during block level verification are verified during top level verification. With some implementations of the invention, the device design is partitioned based input from a user of the implementation. Furthermore, in various implementations, the specific clock domain crossing verification checks employed during block level verification and top level verification are specified by a user of the implementation. | 09-23-2010 |
| 20100242004 | METHOD OF SEMICONDUCTOR CIRCUIT DEVICE - A designing method of a semiconductor circuit device includes the following steps. The steps are: generating a circuit diagram data indicating a semiconductor circuit device which includes power source separation regions, each provided with cells which include retention flip-flops; generating a net list between the power source separation region and the node based on the circuit diagram data; when an output of a first power source separation region is connected an input of a second power source separation region, and a first power source for the first power source separation region is turned off, searching a first searched cell indicating a retention flip-flop closest to the output of the first power source separation region from the first power source separation region based on the net list; searching a second searched cell between the first searched cell and the output of the first power source separation region from the first power source separation region based on the net list; replacing the first power source for an output of the first searched cell by a second power source which supplies the same voltage as the first power source and is in an on-state; and replacing the first power source for the second searched cell by the second power source. | 09-23-2010 |
| 20100242005 | System and method for design, procurement and manufacturing collaboration - A method for designing an electronic component includes receiving a device criteria (e.g., a parametric value, procurement value, etc.) from a designer, querying a database for devices corresponding to the device criteria, querying the database for procurement data and/or engineering data associated with the corresponding devices, presenting the devices to the designer based on the procurement data, and receiving input from the designer identifying one of the presented devices as a selected device. In a particular method, the returned devices are sorted based on one or more procurement values (e.g., manufacturer, price, availability, manufacturer status, etc.), and presented to the designer in a ranked list. Objects representative of the selected devices are then entered into a design file, and the objects are associated with the device's engineering and/or procurement data. In a particular embodiment, the objects are associated with the engineering data by embedding the engineering data in the file object. Optionally, data can be associated with the objects via links to the database. Types of engineering data that can be associated with design file objects include, but are not limited to, device footprint data, device pinout data, device physical dimension data, parametric data, and packaging data. Additionally, connection data and annotation data can be entered into the design file objects by the designer. | 09-23-2010 |
| 20100251192 | CIRCUIT DESCRIPTION GENERATING APPARATUS AND FUNCTION VERIFICATION METHOD - A circuit description generating apparatus has an ID addition part configured to add a common ID to a command inputted to a verification target circuit described by a circuit description language and data corresponding to the command, a bit width adjusting part configured to adjust a bit width of an ID of the command and an ID of the data along a signal path which pass through inside of the verification target circuit, and a circuit description generating part configured to generate a circuit description corresponding to the verification target circuit, the circuit description including the command and data with the IDs of which bit widths are adjusted by the bit width adjusting part. | 09-30-2010 |
| 20100251193 | Computer-readable recording medium storing verification support program, verification support apparatus, and verification support method - A verification support apparatus and method are provided. The verification support apparatus executing a simulation controlling a communication between a first hardware model in communication with a bus model and adapted to the same first specifications as the bus model, and a second hardware model in communication with the bus model and adapted to second specifications differing from those of the bus model, the apparatus includes a reception unit that receives data based on the second specifications from the second hardware model, a conversion unit that, based on the first specifications, converts the data received by the reception unit into data adapted to the first specifications; and a transmission unit that transmits the data converted by the conversion unit, via the bus model, to a hardware model which is a transmission destination. | 09-30-2010 |
| 20100251194 | APPARATUS FOR AIDING DESIGN OF SEMICONDUCTOR DEVICE AND METHOD - An apparatus for aiding a design of a semiconductor device including a plurality of wirings, the apparatus has a display, a memory that stores information corresponding to the wirings, and a processor that obtains a power consumption value of each wiring in reference to the information about the wirings stored in the memory, and displays each of the wirings on the display in a manner that each wiring is distinguishable as to the obtained power consumption value of the each wiring. | 09-30-2010 |
| 20100251195 | WIRING VERIFICATION SYSTEM, WIRING VERIFICATION METHOD, AND WIRING VERIFICATION PROGRAM PRODUCT - A wiring verification system is provided which is capable of simultaneously solving problems of wiring constraints on each board and of total skew in a wire passing through a plurality of boards. Board data, external connection board data, inter-board connection information, and wiring constraints are inputted in advance. When a system netlist creating unit (including a software means) creates a system netlist showing a theoretical connection relation of each board, an external connection tracing unit (including a software means) extracts external connection information based on the system netlist. An external load producing unit (including a software means) produces an external dummy load converted to a wire length or wire delay of the outside based on extracted external connection information. A wiring verification unit (including a software means) performs verification of a wiring state of an entire board by using the produced external dummy load. This enables proper distribution of wiring constraints on each board and solution of the total skew simultaneously. | 09-30-2010 |
| 20100251196 | Method and System for Designing a Structural Level Description of an Electronic Circuit - A method and system for designing a structural level description of an electronic circuit with functional behavior described by a plurality of rules, the circuit being specified by data path and control path elements wherein at least one control path element is provided in a form of unresolved variable. The design comprises extracting a plurality of unresolved variables among the control path elements and automated processing of data path and control path elements for accomplishing a state machine formulation, wherein the states of the state machine include states representing at least combinations of unresolved variables and corresponding transitions satisfying said plurality of rules and predefined design criteria. | 09-30-2010 |
| 20100262940 | Accurate Approximation of Resistance in a Wire with Irregular Biasing and Determination of Interconnect Capacitances in VLSI Layouts in the Presence of Catastrophic Optical Proximity Correction - The Width Bias Calculator (WBC) calculates electrical values by effectively averaging the electrical values to either side of a target wire shape whereby values are approximated for design validation without a significant impact on performance or memory consumption. | 10-14-2010 |
| 20100269077 | Trace Containment Detection of Combinational Designs via Constraint-Based Uncorrelated Equivalence Checking - Methods and systems are provided for producing more efficient digital circuitry designs by identifying trace-containment for a sequential circuitry design netlist through the use of constraint-based uncorrelated equivalence checking. A set of candidate input netlist sets n | 10-21-2010 |
| 20100269078 | AUTOMATIC APPROXIMATION OF ASSUMPTIONS FOR FORMAL PROPERTY VERIFICATION - One embodiment provides a system, comprising methods and apparatuses, for simplifying a set of assumptions for a circuit design, and for verifying the circuit design by determining whether the circuit design satisfies a set of assertions when the simplified set of assumptions is satisfied. During operation, the system can simplify the set of assumptions by identifying, for an assertion in the set of assertions, a first subset of assumptions which, either directly or indirectly, shares logic with the assertion. Furthermore, the system can modify the first subset of assumptions to obtain a second subset of assumptions which either over-approximates or under-approximates the first subset of assumptions. Then, the system can refine the second subset of assumptions to either prove or falsify the assertion. | 10-21-2010 |
| 20100269079 | Analyzing Multiple Induced Systematic and Statistical Layout Dependent Effects On Circuit Performance - A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to a separate systematic, parametric variation associated with semiconductor manufacturing of an integrated circuit layout; generating, for each variation model, a netlist update attributable to the associated variation, wherein the netlist update is an update with respect to an original netlist extracted from the integrated circuit layout; and storing the netlist updates generated for each of the processing conditions. | 10-21-2010 |
| 20100275171 | PACKAGE DESIGNS FOR FULLY FUNCTIONAL AND PARTIALLY FUNCTIONAL CHIPS - A method including obtaining an operational status of a first processor core, where the first processor core is associated with a plurality of processor cores located on a chip; configuring a first IO block of a package design based on the operational status of the first processor core, where the package design is based on a fully functional chip; and configuring a stackup of the package design after configuring the first IO block for use with the chip. | 10-28-2010 |
| 20100287515 | INTERACTIVE CHECKER IN A LAYOUT EDITOR - Methods, articles of manufacture and apparatus for testing design layouts. Design layout software may be configured to display a layout diagram in a first area of a graphical user interface (GUI) screen. Parameters for testing the layout may be entered in a second area of the GUI screen. Upon receiving one or more test parameters, the layout software may be configured to identify portions of the layout that do not conform to design rules based on the test parameters. | 11-11-2010 |
| 20100299643 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE, PROGRAM FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND PROGRAM FOR GENERATING MASK DATA - A method for manufacturing a semiconductor device includes the steps of reading physical layout data of a circuit to be manufactured and performing calculation to modify a pattern width in the physical layout data by a predetermined amount; reading a physical layout and analyzing a pattern that is predicted to remain as a step difference of a predetermined amount or more in a case where a planarization process is performed on a planarizing film on a pattern by a quantitative calculation by using at least one of a density of patterns, a pattern width, and a peripheral length of a range of interest and a range in the vicinity of the range of interest; and reading data of the pattern that is predicted to remain as a step difference, and making a correction to a layout in which a step difference of a predetermined amount or more does not remain. | 11-25-2010 |
| 20100306720 | Programmable Electrical Rule Checking - Electrical rule checking techniques for analyzing integrated circuit design data to identify specified circuit element configurations. Both tools and methods implementing these techniques may be employed to identify circuit element configurations using both logical and physical layout information for the design data. A set of commands are provided that will allow a user to program a programmable electrical rule check tool to identify a wide variety of circuit element configurations, using both logical and physical layout data, as desired by the user. | 12-02-2010 |
| 20100306721 | WRITE ERROR VERIFICATION METHOD OF WRITING APPARATUS AND CREATION APPARATUS OF WRITE ERROR VERIFICATION DATA FOR WRITING APPARATUS - A write error verification method of a writing apparatus verifying a write error after a write operation being started in the writing apparatus to which layout data containing a figure pattern to be formed is input and which forms the figure pattern on a target object based on the layout data input, the write error verification method includes: if a write error occurs in a process between input of the layout data into the writing apparatus and inspection of the target object on which the figure pattern is formed, selecting a part of the layout data necessary for operation of a function that has caused the write error; extracting parts of the layout data corresponding to a selected part of the layout data for all of a plurality of portions of the target object if a pattern indicated by the selected part of the layout data is arranged at the plurality of portions of the target object; creating verification data by deleting at least one parts extracted for at least one portions other than a portion that has caused the write error from extracted parts of the layout data and by using remaining data; and reproducing the operation of the function that has caused the write error using the verification data to output a result of the reproducing. | 12-02-2010 |
| 20100306722 | Implementing A Circuit Using An Integrated Circuit Including Parametric Analog Elements - An environment and method are provided for designing and implementing a circuit comprising an integrated circuit (IC) including a number of parametric analog elements for which operating parameters can be set. Generally, the method comprises: specifying requirements for the circuit including physical properties to be sensed by the circuit and actions to be taken by the circuit; designing the circuit based on the specified requirements and resources available on the IC; and setting parameters of at least one of the parametric analog circuit elements of the IC based on the circuit design. In one embodiment, the specifying, designing, and setting parameters steps are performed using a computer executable code embodied in a computer readable medium on a server coupled to a client computer through an internet protocol network. Other embodiments are also provided. | 12-02-2010 |
