Entries |
Document | Title | Date |
20080201670 | Using constrained scan cells to test integrated circuits - Various new and non-obvious apparatus and methods for testing an integrated circuit are disclosed. In one exemplary embodiment, a control point is selected in an integrated circuit design. Scan cells in the integrated circuit design are identified that can be loaded with a set of fixed values in order to propagate a desired test value to the control point. The integrated circuit design is modified to include circuit components configured to load the scan cells in the integrated circuit design with the set of fixed values during a test phase. The one or more scan cells may be identified by justifying the control point to the scan cells, thereby determining values that the scan cells must output in order to drive the control point to the desired test value. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods or computer-readable design information for any of the disclosed apparatus are also disclosed. | 08-21-2008 |
20080209365 | Yield analysis and improvement using electrical sensitivity extraction - A method and apparatus are described for determining an accurate yield prediction for an integrated circuit by combining conventional yield loss analysis (such as extracted from physical dimension information concerning a circuit layout) with extracted electrical sensitivity and/or functional sensitivity information for circuit elements (such as nets connecting logic blocks or other signal lines) to obtain an actual performance-based probability of failure (POF) for the overall circuit. | 08-28-2008 |
20080209366 | METHOD AND APPARATUS FOR ANALYZING CIRCUIT MODEL BY REDUCTION AND COMPUTER PROGRAM PRODUCT FOR ANALYZING THE CIRCUIT MODEL - Provided are a method and apparatus for analyzing a circuit model by reducing, and a computer program product for analyzing the circuit model. The circuit model at least includes independent current source models, resistance models, and capacitance models. Also, the circuit model forms a resistance capacitance (RC) network with independent current sources. The method includes selecting a node to be removed using resistance information and comparing conductance of a capacitor for a given time step and the total conductance of the node. Further, the method includes removing the selected nodes and generating RC elements and independent current sources using adjacent nodes, which maintain the accuracy of node voltages of a circuit reduced in an accuracy order used for entrywise perturbation of the corresponding circuit equation. Moreover, an efficient method of handling the independent current sources while reducing the circuit is provided. | 08-28-2008 |
20080209367 | RELIABILITY DESIGN METHOD - The reliability design method of this invention includes an aged deterioration target extracting step of obtaining a deterioration part where a characteristic is deteriorated through aging in a semiconductor integrated circuit device having a structure corresponding to an initial mask layout pattern; an aged deterioration executing step of creating a deteriorated mask layout pattern corresponding to a structure of the semiconductor integrated circuit device resulting from the aging by modifying the initial mask layout pattern; and an aged deterioration coping step of evaluating a characteristic of the semiconductor integrated circuit device having the structure corresponding to the deteriorated mask layout pattern. In the aged deterioration coping step, the initial mask layout pattern is corrected on the basis of an evaluation result. | 08-28-2008 |
20080216027 | Electronic Design for Integrated Circuits Based on Process Related Variations - An electronic design is generated for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension variations to the integrated circuit. The generating includes adjusting the electronic design based on predictions of topographical and topographical-related feature dimension variations by a pattern-dependent model. An RC extraction tool is used in conjunction with the generating and adjusting of the electronic design. The process includes a fabrication process that will impart topographical variation to the integrated circuit and a lithography or etch process. Placement attributes for elements of the integrated circuit are determined. | 09-04-2008 |
20080222579 | Moment-Based Method and System for Evaluation of Metal Layer Transient Currents in an Integrated Circuit - A moment-based method and system for evaluation of metal layer transient currents in an integrated circuit provides a computationally efficient evaluation of transient current magnitudes through each interconnect in the metal layer. The determinable magnitudes include peak, rms and average current, which can be used in subsequent reliability analyses. Interconnect path nodes are traversed and circuit moments are either retrieved from a previous interconnect delay analysis or are computed. For each pair of nodes, current moments are computed from the circuit moments. The average current is computed from the zero-order circuit moment and the peak and rms currents are obtained from expressions according to a lognormal or other distribution shape assumption for the current waveform at each node. | 09-11-2008 |
20080222580 | SYSTEM AND METHOD FOR MANAGING THE DESIGN AND CONFIGURATION OF AN
INTEGRATED CIRCUIT SEMICONDUCTOR DESIGN - A system and methods that facilitate the design process and minimize the time and effort required to complete the design and fabrication of an integrated circuits (IC) are described. The system and method utilize a plurality of repositories, rules engines and design and verification tools to analyze the workload and automatically produce a hardened GDSII description or other representation of the device. The system and method securely maintains synthesizable RTL on a server in a data center while providing designers access to portions of the mechanism by way of a network portal. | 09-11-2008 |
20080222581 | Remote Interface for Managing the Design and Configuration of an Integrated Circuit Semiconductor Design - A software system for facilitating the design process and minimizing the time and effort required to complete the design and fabrication of an integrated circuits (IC) is described. The software system utilizes a data center having a plurality of repositories, rules engines and design and verification tools to automatically produce a hardened GDSII description or other representation of the device in response to the formation of a electronic license agreement. Designers select contractual terms for incorporating third party intellectual property and then design and initiate manufacture of the IC by way of a network portal. | 09-11-2008 |
20080222582 | System and method for automated electronic device design - A system for the automated formation and control and execution of an electronic device design flow is disclosed which can enable more efficient electronic device design methodology with higher quality of results. Such a system as analysis methods, techniques, and tools, a knowledge database, a design database a controller and reasoner, are described. | 09-11-2008 |
20080235636 | Identifying Radiation-Induced Inversions - A semiconductor layout design analyzer alerts a user of areas in a semiconductor layout design that may be candidates for radiation induced inversion. The analyzer includes means for gathering information, means for identifying, and means for alerting the user. The means for gathering gathers, from the layout design, placement information for thick oxide, low-doped p-type single crystal silicon, and n-type silicon. The means for identifying identifies, in the layout design, thick oxide overlaying low-doped p-type single crystal silicon and abutting n-type silicon. The means for alerting the user alerts the user of the identified areas of thick oxide. | 09-25-2008 |
20080235637 | METHOD FOR HEURISTIC PRESERVATION OF CRITICAL INPUTS DURING SEQUENTIAL REPARAMETERIZATION - A method, system, and computer program product for preserving critical inputs. According to an embodiments of the present invention, an initial design including one or more primary inputs which cannot be eliminated, one or more primary inputs which can be eliminated, one or more targets, and one or more state elements are received. A cut of said initial design including one or more cut gates is identified, and a relation of one or more values producible to said one or more cut gates in terms of said one or more primary inputs which cannot be eliminated, said one or more primary inputs which can be eliminated and said one or more state elements is computed. Said relation is synthesized to form a gate set, and an abstracted design is formed from said gate set. Verification is performed on said abstracted design to generate verification results. | 09-25-2008 |
20080235638 | DESIGN STRUCTURE FOR RADIATION HARDENED PROGRAMMABLE PHASE FREQUENCY DIVIDER CIRCUIT - A design structure embodied in a machine readable medium includes information for designing, manufacturing and/or testing a programmable phase frequency divider circuit implemented in CMOS technology for space applications. The programmable phase frequency divider consists of three radiation hardened D-type flip flops and combinational logic circuits to provide the feedback controls that allow programmable frequency division ratios from 1 to 8. The radiation hardened D-type flip flop circuits are designed to keep on running properly at GHz frequencies even after a single event upset (SEU) hit. The novel D-type flip flop circuits each have two pairs of complementary inputs and outputs to mitigate SEU'S. The combinational logic circuits are designed to utilize the complementary outputs in such a way that only one of the four dual complementary inputs to any D-type flip flop gets flipped at most after an SEU hit. | 09-25-2008 |
20080235639 | Method of Generating a Functional Design Structure - A method in a computer-aided design system for generating a functional design model of a circuit that compensates for changes in resistance of a buried resistor by using a waveform that is representative of the thermal characteristics of the buried resistor. | 09-25-2008 |
20080244475 | Network based integrated circuit testline generator - A network based integrated circuit testline generating system and method of using the same is described. The system includes a user interface for generating and submitting requests which specify types and configurations of needed testlines for device parametric test. A testline generator receives the requests and creates a layout data base which includes layout information of needed testlines. | 10-02-2008 |
20080244476 | System and method for simultaneous optimization of multiple scenarios in an integrated circuit design - The present invention provides a system and method for concurrently performing analysis and optimization of an integrated circuit (IC) design in multiple scenarios. The system is based on a distributed computing model, where any optimization change introduced in one scenario is immediately tested in all other scenarios. This ensures that modifications made to the design do not affect other scenarios. The invention significantly reduces the execution time of the optimization and signoff flows in the design of ICs. In addition, the computing means required for simultaneously testing multiple scenarios are standard and affordable. | 10-02-2008 |
20080244477 | Simulation Model for a Semiconductor Device Describing a quasi-Static density of a Carrier as a Non-quasi-static model - There is disclosed a simulation model and method for designing a semiconductor device being used for a simulation apparatus for designing a semiconductor device that includes using assuming units as to carrier transient density and current flow of electrodes along with a non-quasi-static model describing unit of the simulation apparatus. A simulation apparatus and computer readable medium with a simulation program for executing the method are also included. | 10-02-2008 |
20080244478 | MODEL GENERATION METHOD AND MODEL GENERATION APPARATUS OF SEMICONDUCTOR DEVICE - A model generation method for generating a semiconductor device model used for power supply noise analysis, is performed by, calculating noise values for various circuit elements based on current source noise waveforms calculated in accordance with a current flowing from a power supply when a state of the elements changes, determining the time when the change of state of the elements causing the current source noise occurs in relation to successive timing windows each having a predetermined time width, and calculating noise by unit time and adding up for each divided unit time the noise value calculated for all elements whose timing window is present in the unit time, wherein a timing determination unit determines the worst case and other noise generation timing based on the noise generated in each unit time. | 10-02-2008 |
20080244479 | STRUCTURE FOR INTRINSIC RC POWER DISTRIBUTION FOR NOISE FILTERING OF ANALOG SUPPLIES - A design structure for intrinsic RC power distribution for noise filtering of analog supplies. The design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes a voltage regulator; a variable resistor coupled to the voltage regulator; and a performance monitor and control circuit providing a feedback loop to the variable resistor. | 10-02-2008 |
20080256499 | USING CONSTRAINTS IN DESIGN VERIFICATION - A method for generating a constraint for generating a constraint for use in the verification of an integrated circuit design includes identifying a target in a netlist (N) of the design and creating an overapproximate abstraction (N′) of the netlist. A space state (S′) is created by enumerating the states of N′ from which the identified target may be asserted. A constraint space C′ is then derived from the state space S′, where C′ is the logical complement of S′. The process is repeated for multiple selected targets and the constraint spaces from each iteration are logically ANDed. Creating an overapproximate abstraction may include replacing a sequential gate with a random gate. Identifying a sequential gate may include selecting a target in the netlist, performing underapproximate verification of the target, and, if a spurious failure occurs, selecting a gate further down the fanin chain of the currently selected gate. | 10-16-2008 |
20080270951 | Embedded Test Circuit For Testing Integrated Circuits At The Die Level - A design structure instantiated in a machine readable medium; the design structure includes all of the necessary information for designing a test circuit. The test circuit is used for performing device-specific testing and acquiring parametric data on integrated circuits, for example ASICs, such that each chip is tested individually without excessive test time requirements, additional silicon, or special test equipment. The design structure includes at least one test circuit and may be integrated into an IC design, along with all of the required manufacturing data for producing a final design structure. The final design structure may be in the form of a GDS storage medium or another form of medium suitable for sending the final data structure to, for example, a manufacturer, foundry, customer, or other design house. | 10-30-2008 |
20080270952 | Dynamic sampling of functional simulation to determine whether to perform both functional and timing simulation - A method for simulating a system normally performs functional simulation of the system without performing timing simulation of the system. The method dynamically samples the functional simulation of the system at intervals to determine whether the functional simulation has entered into a new phase. Where the functional simulation has entered into a new phase, the method performs both the functional simulation and the timing simulation of the system for one or more intervals. | 10-30-2008 |
20080270953 | IC CHIP AT-FUNCTIONAL-SPEED TESTING WITH PROCESS COVERAGE EVALUATION - Methods, systems and program products for evaluating an IC chip are disclosed. In one embodiment, the method includes running a statistical static timing analysis (SSTA) of a full IC chip design; creating at-functional-speed test (AFST) robust paths for an IC chip, the created robust paths representing a non-comprehensive list of AFST robust paths for the IC chip; and re-running the SSTA with the SSTA delay model setup based on the created robust paths. A process coverage is calculated for evaluation from the SSTA runnings; and a particular IC chip is evaluated based on the process coverage. | 10-30-2008 |
20080276206 | METHOD FOR PERFORMING FAILURE MODE AND EFFECTS ANALYSIS OF AN INTEGRATED CIRCUIT AND COMPUTER PROGRAM PRODUCT THEREFOR - A method for performing failure mode and effects analysis (FMEA) on integrated circuits including preparing a FMEA database of an integrated circuit under design and computing FMEA results from the FMEA database. Information is automatically extracted from an integrated circuit description. The extraction of information includes reading integrated circuit information, partitioning the circuit in invariant and elementary sensitive zones (SZ), using the information in the preparation step of a FMEA database. Optionally a FMEA validation stage may be performed with which FMEA computed results are compared with FMEA measured results to obtain FMEA validated results. | 11-06-2008 |
20080282207 | Method and System for Conjunctive BDD Building and Variable Quantification Using Case-Splitting - A method, apparatus and computer-readable medium for conjunctive binary decision diagram building and variable quantification using case-splitting are presented. A BDD building program builds a BDD for at least one node in a netlist graph representation of a circuit design. One or more variables are selected for case-splitting. The variable is set to a constant logical value and then the other. A BDD is built for each case. The program determines whether the variable is scheduled to be quantified out. If so, the program combines the BDDs for each case according to whether the quantification is existential or universal. If the variable is not scheduled to be quantified, the program combines the BDDs for each case so that the variable is introduced back into the resulting BDD, which has a reduced number of peak live nodes. | 11-13-2008 |
20080282208 | Integrated Circuit Having Anti-counterfeiting Measures - An article of manufacture, for example, a product or portion of a product produced by an IP design house which, when manufactured, causes random failures in a counterfeit integrated circuit. The article of manufacture ( | 11-13-2008 |
20080295045 | Method for Creating Hdl Description Files of Digital Systems, and Systems Obtained - The invention relates to a method comprising the following steps: HDL instruction sequences which are to be at the origin of memory elements during the synthesis of the system are automatically localised in the original HDL description files; and so-called SCAN HDL instructions are inserted into at least some of the HDL description files in an automatic sequential manner and without relational or functional analysis of the identified memory elements, ensuring that at least one so-called SCAN channel is obtained during the synthesis of the system, linking the memory elements. | 11-27-2008 |
20080295046 | Predicting IC manufacturing yield based on hotspots - One embodiment of the present invention provides a system that predicts a manufacturing yield of a chip. During operation, the system first receives a chip layout. Next, the system identifies hotspots within the chip layout, wherein a hotspot is a location within the chip layout wherein a yield-indicative variable value falls in a low manufacturable range. The system then obtains yield scores for the hotspots, wherein a yield score indicates a failure probability for a corresponding hotspot. Next, the system predicts the manufacturing yield for the chip based on the hotspots and the yield scores for the hotspots. | 11-27-2008 |
20080295047 | Stage yield prediction - In one embodiment, a method for predicting yield during the design stage includes receiving defectivity data identifying defects associated with previous wafer designs, and dividing the defects into systematic defects and random defects. For each design layout of a new wafer design, yield is predicted separately for the systematic defects and the random defects. A combined yield is then calculated based on the yield predicted for the systematic defects and the yield predicted for the random defects. | 11-27-2008 |
20080295048 | Inline defect analysis for sampling and SPC - In one embodiment, an inline defect analysis method includes receiving geometric characteristics of individual defects and design data corresponding to the individual defects, determining which of the individual defects are likely to be nuisance defects using the geometric characteristics and the corresponding design data, and refraining from sampling the defects that are likely to be nuisance defects. | 11-27-2008 |
20080301596 | Method and System for Testing Bit Failures in Array Elements of an Electronic Circuit - The invention relates to a method and system for testing bit failures in array elements of an electronic circuit. Said method comprising the steps of changing an original hardware representation (DD) of the array such that errors can be injected in a memory by manipulation of associated read and/or write logic of the memory via input signals, building an emulator model (SME) from said changed hardware representation for emulating the array, and injecting errors into the changed hardware representation for determining the array to get stick capabilities. | 12-04-2008 |
20080307373 | Apparatus, method and computer program for managing circuit optimization information - A circuit optimization information management apparatus provides information to be used when a circuit parameter optimization program is executed to design an integrated circuit. The apparatus includes an accumulator for registering information relating to a candidate of a circuit type used in a design target circuit, a simulation test bench circuit corresponding to the circuit type, a simulation test input waveform and a circuit performance evaluation function for evaluating simulation results, and a feeder for selecting, in response to selection of the circuit type used in the design target circuit, information relating to the test bench circuit, the test input waveform and the performance evaluation function, corresponding to the selected circuit type registered in the accumulator and feeding the selected information to the circuit parameter optimization program. | 12-11-2008 |
20080313581 | INDEPENDENT MIGRATION OF HIERARCHICAL DESIGNS WITH METHODS OF FINDING AND FIXING OPENS DURING MIGRATION - Methods of independently migrating a hierarchical design are disclosed. A method for migrating a macro in an integrated circuit comprises: determining an interface strategy between a base cell in the macro and the macro, the base cell including an interface element involved in the interface strategy; migrating the base cell independently with respect to the macro based on the interface strategy; initially scaling the macro; swapping the migrated base cell into the macro; and legalizing content of the initially scaled macro. | 12-18-2008 |
20080313582 | Accurate Transistor Modeling - A method and system for generating transistor models. In one embodiment, the method includes generating a transistor model that characterizes a topology of a circuit, and characterizes at least one coupling or at least one interaction between at least two transistors of the circuit. | 12-18-2008 |
20080313583 | Apparatus and Method for Testing Sub-Systems of a System-on-a-Chip Using a Configurable External System-on-a-Chip - An apparatus and method are provided in which a previously verified SoC is coupled to a SoC under test via a communication bus or other type of communication interface. The previously verified SoC is provided with the same test stimuli as the SoC under test and thus, generates expected test results data. The test stimuli are sent to the SoC under test via a peripheral communication interface between the previously verified SoC and the SOC under test. The SoC under test generates actual test result data that is output to the previously verified SoC. The previously verified SoC may then compare the expected test results data with the actual test result data generated by the SoC under test to determine if they match. If the two sets of data do not match, then a mismatch notification may be generated and output. | 12-18-2008 |
20080320421 | FEATURE EXTRACTION THAT SUPPORTS PROGRESSIVELY REFINED SEARCH AND CLASSIFICATION OF PATTERNS IN A SEMICONDUCTOR LAYOUT - A system, method and program product for searching and classifying patterns in a VLSI design layout. A method is provided that includes generating a target vector using a two dimensional (2D) low discrepancy sequence; identifying layout regions in a design layout; generating a feature vector for a layout region; comparing a subset of sequence values in the target vector with sequence values in the feature vector as an initial filter, wherein the system for comparing determines that the layout region does not contain a match if a comparison of the subset of sequence values in the target vector with sequence values in the feature vector falls below a threshold; and outputting search results. | 12-25-2008 |
20090007030 | DESIGN-BASED MONITORING - A method for monitoring fabrication of an integrated circuit (IC) on a semiconductor wafer includes generating a product design profile (PDP) using an electronic design automation (EDA) tool, the PDP comprising an indication of a site in a layer of the IC that is susceptible to a process fault. Upon fabricating the layer of the IC on the wafer, a process monitoring tool is applied to perform a measurement at the site in the layer responsively to the PDP. | 01-01-2009 |
20090007031 | METHOD AND SYSTEM FOR IMPLEMENTING CACHED PARAMETERIZED CELLS - Parameterized cells are cached and provided by the plug-in to increase the speed and efficiency of an application for circuit design. This allows source design to be read-interoperable and also enables some basic write-interoperability in the source design. | 01-01-2009 |
20090007032 | METHOD AND APPARATUS FOR SUBSTRATE NOISE ANALYSIS USING SUBSTRATE TILE MODEL AND TILE GRID - A method is provided to evaluate substrate noise propagation in an integrated circuit design, the method comprising: providing a tile definition that specifies an electrical model associated with instances of the tile; mapping a plurality of respective tile instances to respective locations of the substrate; obtaining respective waveforms indicative of digital switching induced power grid fluctuations associated with the respective identified contacts; and associating a voltage with a selected tile instance of the tile grid that is indicative of substrate noise injection due to waveforms associated with contacts encompassed by the selected tile instance. | 01-01-2009 |
20090007033 | Method to transfer failure analysis-specific data between data between design houses and fab's/FA labs - A method and system for an IC design house to transfer design and layout information to a fabrication or failure analysis facility on a need-to-know basis to enable effective failure analysis while not providing unnecessary or extraneous information. | 01-01-2009 |
20090013290 | Method and System for Electromigration Analysis on Signal Wiring - The invention relates to an electromigration analysis method and a system for analyzing one or more nets in a digital integrated circuit design that are at risk of electromigration. The method comprises the steps of providing at least one interconnect between a driver cell and at least one load cell; applying same extracted netlist data for noise and/or timing analysis and for electromigration analysis; modeling the driver cell by a train of trapezoidal voltage pulses transmitted from the driver cell to the one or more load cells through the at least one interconnect; extracting at least a slew rate of a driver voltage signal (U | 01-08-2009 |
20090019403 | CIRCUIT WIRING INTERFERENCE ANALYSIS DEVICE, INTERFERENCE ANALYSIS PROGRAM, DATABASE USED IN INTERFERENCE ANALYSIS DEVICE, AND ASYMMETRICALLY CONNECTED LINE MODEL - An interference analysis device that analyzes interference includes an input unit | 01-15-2009 |
20090019404 | METHOD FOR CALCULATING DIFFICULTY LEVEL OF ROUTING IN NETLIST - The invention provides a method capable of calculating a difficulty level of routing at a high processing speed with good calculating accuracy. The method involves: performing hierarchical clustering on cells in a netlist so as to successively group the cells to be connected to each other through a larger number of nets (S | 01-15-2009 |
20090024966 | METHOD OF OPTIMIZED GRADIENT COIL DESIGN - The present invention relates to a method of discretization of the continuous current solution of a gradient coil design that allows satisfaction of the target field quality characteristics as well as other characteristics such as minimization of the energy/inductance, minimization of the residual eddy current effect, minimization of the thrust forces on the coil and cold shields, coil resistance thus the power dissipated by the coil, etc. The method of optimized gradient coil design can be applied to the design of axial or transverse gradient coils. The method of this invention includes the steps of defining at least one, and more commonly numerous performance characteristics of the desired gradient coil, concurrently varying discretization parameters to develop numerous possible hypothetical gradient coil designs, evaluating the designs to determine whether the defined performance characteristics are met by each design and selecting one design. | 01-22-2009 |
20090024967 | COMPUTER-IMPLEMENTED METHODS, SYSTEMS, AND COMPUTER-READABLE MEDIA FOR DETERMINING A MODEL FOR PREDICTING PRINTABILITY OF RETICLE FEATURES ON A WAFER - Computer-implemented methods, systems, and computer-readable media for determining a model for predicting printability of reticle features on a wafer are provided. One method includes generating simulated images of the reticle features printed on the wafer using different generated models for a set of different values of exposure conditions. The method also includes determining one or more characteristics of the reticle features of the simulated images. In addition, the method includes comparing the one or more characteristics of the reticle features of the simulated images to one or more characteristics of the reticle features printed on the wafer using a lithography process. The method further includes selecting one of the different generated models as the model to be used for predicting the printability of the reticle features based on results of the comparing step. | 01-22-2009 |
20090024968 | Method of designing semiconductor integrated circuit and mask data generation program - A method of designing a semiconductor integrated circuit includes: generating a layout data indicating a layout; and generating a mask data based on the layout data. The generating the mask data includes: referring to the layout data to extract a parameter that specifies a layout pattern around a target transistor included in the semiconductor integrated circuit, wherein the parameter includes at least a width of a device isolation structure around the target transistor; correcting a gate length and a gate width of the target transistor to offset a variation of a characteristic of the target transistor from a design value, the variation depending on the extracted parameter; and generating the mask data from the layout data in which the gate length and the gate width are corrected. | 01-22-2009 |
20090037853 | ASYNCHRONOUS, MULTI-RAIL DIGITAL CIRCUIT WITH GATING AND GATED SUB-CIRCUITS AND METHOD FOR DESIGNING THE SAME - A computer readable storage medium includes executable instructions to analyze an asynchronous, multi-rail digital circuit to identify a gating sub-circuit and a gated sub-circuit. The asynchronous, multi-rail digital circuit is transformed to segregate the gating sub-circuit and the gated sub-circuit. | 02-05-2009 |
20090037854 | Test Method and System for Characterizing and/or Refining an IC Design Cycle - Systems and methods are provided for refining a design cycle for an integrated circuit. An integrated circuit design is generated. A plurality of non-critical paths within the integrated circuit design are identified. A set of at least one of the plurality of non-critical paths is modified to produce a modified design in which the sensitivity of each of the set of non-critical paths to at least one parameter is enhanced. Each parameter is either a design parameter or a process parameter. An integrated circuit is fabricated according to the modified design. The fabricated integrated circuit is evaluated to measure a set of timing data representing each of the plurality of non-critical paths. The value of the parameter is determined from the measured set of timing data. | 02-05-2009 |
20090037855 | SIMULATION METHOD AND COMPUTER-READABLE STORAGE MEDIUM - A simulation method to be implemented in a computer causes the computer to execute a procedure carrying out a weighting with respect to layout parameters of a circuit, which is an analyzing target, based on priority information of cells forming the circuit, and converting the weighted layout parameters into physical characteristics and storing the physical characteristics in a memory part, a procedure converting the physical characteristic read from the memory part into circuit parameters and storing the circuit parameters into the memory part, and analyzing the circuit based on a net list including the circuit parameters read from the memory part. | 02-05-2009 |
20090037856 | SIMULATION METHOD AND COMPUTER-READABLE STORAGE MEDIUM - A simulation method, to be implemented in a computer, carries out a simulation of a semiconductor integrated circuit. The simulation method carries out a layout analysis based on layout data of a circuit formed by cells and stores values of layout parameters obtained by the layout analysis. Basic cell characteristics of the cells are read from a net list representing the extracted basic cell characteristics by the layout parameters and the basic cell characteristics represented by the layout parameters are stored. The stored values of the layout parameters are read and substituted into the basic cell characteristics represented by the layout parameters to obtain cell characteristics, and the cell characteristics are stored. An operation of the circuit is analyzed using the cell characteristics that are obtained. | 02-05-2009 |
20090055782 | Secure Yield-aware Design Flow with Annotated Design Libraries - A method for designing and manufacturing integrated circuits is provided. The method includes providing a modeling parameter set for manufacturing an integrated circuit; dividing the modeling parameter set into time-dependent data and time-independent data; saving substantially all time-independent data into a design library; and saving substantially all time-dependent data into a design-for-manufacturing (DFM) data kit, wherein the DFM data kit is external to the design library. | 02-26-2009 |
20090055783 | COMPUTER-IMPLEMENTED METHODS FOR DETERMINING IF ACTUAL DEFECTS ARE POTENTIALLY SYSTEMATIC DEFECTS OR POTENTIALLY RANDOM DEFECTS - Various computer-implemented methods for determining if actual defects are potentially systematic defects or potentially random defects are provided. One computer-implemented method for determining if actual defects are potentially systematic defects or potentially random defects includes comparing a number of actual defects in a group to a number of randomly generated defects in a group. The actual defects are detected on a wafer. A portion of a design on the wafer proximate a location of each of the actual defects in the group and each of the randomly generated defects in the group is substantially the same. The method also includes determining if the actual defects in the group are potentially systematic defects or potentially random defects based on results of the comparing step. | 02-26-2009 |
20090064062 | Modeling Silicon-On-Insulator Stress Effects - A method and system for modeling silicon-on-insulator shallow trench isolation stress effect is described. The method includes creating instance parameters that define dimensions of a body-tie enclosure of gate and gate-end. The instance parameters are added to a netlist. The netlist and a lookup table are used to generate a mobility multiplier. The mobility multiplier is added to the netlist and a circuit simulation program runs the netlist having the instance parameters and the mobility multiplier. | 03-05-2009 |
20090064063 | Algorithmic reactive testbench for analog designs - An Algorithmic Reactive Testbench (ART) system is provided. The ART system is a high level verification environment with a user program in which on or more analog testbenches are instantiated and operated as prescribed in the program algorithm, and the properties of the unit testbenches (test objects) can be influenced by prior analysis of themselves or other tests. The results of the analysis may also affect the flow of the program itself. In the ART system, modification of the properties of a unit testbench occurs separately in the user program after definition of the unit testbench in the program (test object). A test object is a representation of a unit testbench along with its complete simulation setup and all associated data for the simulation. The test object may also contain various properties including information reflecting the status of the test object. The modification of a property of a test object is an act of communication in the ART system from the ART program to the test object. | 03-05-2009 |
20090070717 | Method and System for Generating Coverage Data for a Switch Frequency of HDL or VHDL Signals - The present invention relates to a method for generating coverage data for a switch frequency of HDL or VHDL signals with the steps of providing a HDL or VHDL hardware description model ( | 03-12-2009 |
20090077507 | Method of Generating Technology File for Integrated Circuit Design Tools - A method and system for extracting the parasitic capacitance in an IC and generating a technology file for at least one or more IC design tools are provided. Parasitic extraction using the preferred method can significantly reduce field solver computational intensity and save technology file preparation cycle time. The network-based technology file generation system enables circuit designers to obtain a desired technology file in a timely manner. The common feature of the various embodiments includes identifying common conductive feature patterns for a given technology generation. Capacitance models created from the identified patterns are used to assemble the required technology files for IC design projects using different technology node and different process flows. | 03-19-2009 |
20090077508 | ACCELERATED LIFE TESTING OF SEMICONDUCTOR CHIPS - Improved techniques for accelerated life testing of a sample of semiconductor chips advantageously enable more effective testing and better estimation of lifetime. Full-chip temperature maps are computed at sets of operating and testing conditions. Evaluating the temperature maps enables operations such as: temperature-aware design changes, including adding and/or configuring heating elements, cooling elements, thermal diodes, or sensors; determination of accelerated testing conditions; avoidance of harmful conditions during accelerated testing; and the better estimation of lifetime. Iteration of the computing and the evaluating refines the accelerated testing conditions. Measuring actual testing conditions and computing a full-chip temperature map using the actual testing conditions enables the estimation of lifetime to account for the actual testing conditions. A lifetime acceleration factor map based, at least in part, on the temperature maps is used to produce the estimated lifetime. Failure analysis improves accuracy of the estimated lifetime. | 03-19-2009 |
20090077509 | METHOD FOR CONTROLLING SHEET RESISTANCE OF POLY IN FABRICATION OF SEMICONDUCTOR DEVICE - A method for controlling the sheet resistance of poly in the fabrication of a semiconductor device. In one example embodiment, a method for controlling the sheet resistance of a poly in the fabrication of a semiconductor device includes various steps. First, detection is made whether or not an N-ion implantation area and a resistance area overlap with each other within the layout of a cell to be formed on a semiconductor wafer. Next, an LDD dummy area is generated in the area on the layout where the N-ion implantation area exists if such overlap is found. Then, detection is made whether or not a P-ion implantation area and a resistance area overlap with each other within the layout. Finally, an LDD dummy area is generated in the area on the layout where the P-ion implantation area exists if such overlap is found. | 03-19-2009 |
20090083681 | Methods and apparatuses for designing integrated circuits using virtual cells - Methods and apparatuses for analyzing and/or designing integrated circuits using virtual transparent cells disclosed. Some embodiments comprise calculating model values for virtual transparent cells or elements of an integrated circuit design varying a transparency variable in modeling equations, and allowing replacement of the cell with a wire based upon the calculations. Varying the value of the transparency value for the calculations may allow the virtual transparent cells to be continuously modeled between a wire and a conventional version of the cell. Some embodiments may comprise a cell library with one or more modeling formulas for one or more virtual transparent cells and a response module to calculate different model values of the modeling formulas. | 03-26-2009 |
20090089723 | Circuit design using a spreadsheet - A circuit design method is provided that includes creating a plurality of macros each for one of a plurality of logic gates, storing the created macros, and creating a circuit design using a spreadsheet program, the circuit design being represented by the plurality of macros. | 04-02-2009 |
20090094567 | IMMUNITY TO CHARGING DAMAGE IN SILICON-ON-INSULATOR DEVICES - Method embodiments herein determine a connection order in which connections will be made to connect active devices to antennas within a given circuit design. The method also evaluates the possibilities that these connections to the antennas will cause charging damage in the devices that are connected to the antennas. Such possibilities are based on the connection order, the size of the antennas, and the likelihood that charges will flow from the antennas through insulators of the devices. If a significant possibility for damage exists, the method can reduce the size of the antenna. | 04-09-2009 |
20090100387 | HDL processing method and computer-readable storage medium - A Hardware Description Language (HDL) processing method is implemented in a computer and processes a HDL file which is written in HDL having a hierarchical structure including three or more hierarchical levels in a Computer-Aided Design (CAD) which supports hardware design. The HDL processing method analyzes the hierarchical structure of the HDL and obtaining an analysis result, and processes the HDL one at a time for each hierarchical level based on the analysis result or, process the HDL one at a time by a parallel distributed processing for each hierarchical level based on the analysis result. | 04-16-2009 |
20090106712 | RELIABILITY EVALUATION AND SYSTEM FAIL WARNING METHODS USING ON CHIP PARAMETRIC MONITORS - A method of reliability evaluation and system fail warning using on chip parametric monitors. The method includes determining impact of parametric variation on reliability by identifying key parametric questions to be answered by stress, identifying parametric macros for each parameter, and identifying layout sensitive areas of evaluation. The process can also include a set of parametric macros in one of a test site or a product to be stressed, testing the set of parametric macros prior to start of stress and at each stress read out, and setting life time parameter profile for technology. | 04-23-2009 |
20090106713 | DESIGN STRUCTURE INCORPORATING SEMICONDUCTOR DEVICE STRUCTURES THAT SHIELD A BOND PAD FROM ELECTRICAL NOISE - Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes active circuitry on a substrate, a bond pad carried by the substrate, and a shielding structure disposed between the substrate and the bond pad. The shielding structure includes a plurality of electrically characterized devices configured to reduce noise transmission from the active circuitry to the bond pad. | 04-23-2009 |
20090113357 | MONITORING IONIZING RADIATION IN SILICON-ON INSULATOR INTEGRATED CIRCUITS - A method, device and system for monitoring ionizing radiation, and design structures for ionizing radiation monitoring devices. The method including: collecting an ionizing radiation induced charge collected by the depletion region of a diode formed in a silicon layer below an oxide layer buried below a surface of a silicon substrate; and coupling a cathode of the diode to a precharged node of a clocked logic circuit such that the ionizing radiation induced charge collected by a depletion region of the diode will discharge the precharged node and change an output state of the clocked logic circuit. | 04-30-2009 |
20090113358 | MECHANISM FOR DETECTION AND COMPENSATION OF NBTI INDUCED THRESHOLD DEGRADATION - The embodiments of the invention provide a design structure for detection and compensation of negative bias temperature instability (NBTI) induced threshold degradation. A semiconductor device is provided comprising at least one stress device having a voltage applied to its gate node and at least one reference device having a zero gate-to-source voltage. A controller is also provided to configure node voltages of the device and/or the reference device to reflect different regions of device operations found in digital and analog circuit applications. Moreover, the controller measures a difference in current between the stress device and the reference device to determine whether NBTI induced threshold degradation has occurred in the stress device. The controller also adjusts an output power supply voltage of the stress device until a performance of the stress device matches a performance of the reference device to account for the NBTI induced threshold degradation. | 04-30-2009 |
20090113359 | Model Based Microdevice Design Layout Correction - Shapes neighboring a potential manufacturing fault within a microdevice design layout are identified. Models are employed to determine the affect of the shapes upon the potential manufacturing fault. Possible adjustments to the shapes are modeled. The possible adjustments facilitating resolution of the potential manufacturing fault. | 04-30-2009 |
20090113360 | METHOD FOR COMPUTING THE SENSISTIVITY OF A VLSI DESIGN TO BOTH RANDOM AND SYSTEMATIC DEFECTS USING A CRITICAL AREA ANALYSIS TOOL - A method of estimating integrated circuit yield comprises providing an integrated circuit layout and a set of systematic defects based on a manufacturing process. Next, the method represents a systematic defect by modifying structures in the integrated circuit layout to create modified structures. More specifically, for short-circuit-causing defects, the method pre-expands the structures when the structures comprise a higher systematic defect sensitivity level, and pre-shrinks the structures when the structures comprise a lower systematic defect sensitivity level. Following this, a critical area analysis is performed on the integrated circuit layout using the modified structures, wherein dot-throwing, geometric expansion, or Voronoi diagrams are used. The method then computes a fault density value, random defects and systematic defects are computed. The fault density value is subsequently compared to a predetermined value, wherein the predetermined value is determined using test structures and/or yield data from a target manufacturing process. | 04-30-2009 |
20090119623 | Method of labelling swappable pins for integrated circuit pattern matching - The present invention seeks to provide a simple, but novel regime, for re-labelling swappable pins that permits swappability information to be maintained without significantly increasing computational complexity and is conducive to inexact pattern matching for the purposes of developing more complex logical processing blocks from elementary components in design analysis. The method comprises a recursive application of a simple labelling procedure. This method is repeated recursively until all gate instances in the circuit fragment have been assigned a swappability number. | 05-07-2009 |
20090125852 | METHOD AND APPARATUS FOR NET-AWARE CRITICAL AREA EXTRACTION - In one embodiment, the present invention is a method and apparatus for net-aware critical area extraction. One embodiment of the inventive method for determining the critical area of an integrated circuit includes modeling a net corresponding to the integrated circuit as a graph, the net comprising a plurality of interconnected shapes spanning one or more layers of the integrated circuit, identifying one or more core elements in the graph, the core elements including bridges, articulation points, and biconnected components, computing a first Voronoi diagram for a core portion of the graph on a selected layer, including the core elements, emphasizing regions in the first Voronoi diagram where a critical radius is known, computing a second, higher-order Voronoi diagram in accordance with the emphasized regions, and computing the critical area in accordance with the higher-order Voronoi diagram. | 05-14-2009 |
20090125853 | CIRCUIT STRUCTURE OF INTEGRATED CIRCUIT - A circuit structure of an integrated circuit is provided. The circuit structure is adapted for a circuit layout of a wafer. The circuit structure at least includes a first array cell and a second array cell. The second array cell and the first array cell are connected to each other and have a connecting area, wherein the second array cell is shifted a distance along the connecting area. Therefore, the result of yield enhancement is achieved. | 05-14-2009 |
20090125854 | Automated generation of theoretical performance analysis based upon workload and design configuration - A method of more efficiently, easily and cost-effectively analyzing the performance of a device model is disclosed. Embodiments enable automated generation of theoretical performance analysis for a device model based upon a workload associated with rendering graphical data and a configuration of the device model. The workload may be independent of design configuration, thereby enabling determination of the workload without simulating the device model. Additionally, the design configuration may be updated or changed without re-determining the workload. Accordingly, the graphical data may comprise a general or random test which is relatively large in size and covers a relatively large operational scope of the design. Additionally, the workload may comprise graphical information determined based upon the graphical data. Further, the theoretical performance analysis may indicate a graphics pipeline unit of the device model causing a bottleneck in a graphics pipeline of the device model. | 05-14-2009 |
20090132972 | METHOD AND APPARATUS FOR DETERMINING ELECTRO-MIGRATION IN INTEGRATED CIRCUIT DESIGNS - A method and apparatus for determining electro-migration (EM) in integrated circuit designs is disclosed. In one embodiment, a method includes pre-characterizing an output current waveform for a logic cell of the circuit at selected load and input slew points, estimating an effective load and operating slews at a chip level of the circuit and directly generating an equivalent current source waveform at output, evaluating current densities through a metal segment of the circuit using a fast solver, parametrically representing process variations and a netlist to parametrically model the interconnect variations of the circuit, and determining current densities for selected yield numbers using a parametrically generated current source on an interconnect network, wherein calculated results statistically predict a point of current density less than 9−σ a through any metal segment in the parametrically modeled circuit. The method may further include comparing selected current densities with predetermined EM guidelines. | 05-21-2009 |
20090132973 | DESIGN STRUCTURE OF AN INTEGRATION CIRCUIT AND TEST METHOD OF THE INTEGRATED CIRCUIT - A design structure for an integrated circuit which includes: a first flip-flop which is capable of flushing and which operates by using a first clock signal CLK | 05-21-2009 |
20090132974 | METHOD FOR SEMICONDUCTOR CIRCUIT - Capacity-gate voltage characteristics of a field-effect transistor having plural gates are measured against a voltage change in each one of the gates for an inverted MOSFET and for an accumulated MOSFET, respectively. These measurements together with numerical simulations provided from a model for quantum effects are used to determine flat band voltages between the plural gates and a channel. Next, an effective normal electric field is calculated as a vector line integral by using a set of flat band voltages for the measured capacity as a lower integration limit. Lastly, mobility depending on the effective normal electric field is calculated from current-gate voltage characteristic measurements and capacity measurements in a source-drain path, and the calculated mobility is substituted into an equation for a current-voltage curve between source and drain. | 05-21-2009 |
20090138834 | Structure for a Duty Cycle Measurement Circuit - A design structure for a circuit for measuring the absolute duty cycle of a signal anywhere on an integrated circuit device is provided. The circuit has a plurality of substantially identical pulse shaper elements, each of which expand the pulse of an input signal whose duty cycle is to be measured by a same amount. The outputs of the pulse shaper elements may be coupled to substantially identical divider circuits whose outputs are coupled to a multiplexer that selects two inputs for output to a set of master/slave configured flip-flops, one input serving as a clock and the other as data to the flip-flops. The flip-flops sample the divider outputs selected by the multiplexer to detect if the dividers have failed or not. The outputs of the flip-flops are provided to an XOR gate which outputs a duty cycle signal indicative of the duty cycle of the input signal. | 05-28-2009 |
20090138835 | IDENTIFYING LAYOUT REGIONS SUSCEPTIBLE TO FABRICATION ISSUES BY USING RANGE PATTERNS - A range pattern is matched to a block of an IC layout by slicing the layout block and the range pattern, followed by comparing a sequence of widths of layout slices to a sequence of width ranges of pattern slices and if the width of any layout slice falls outside the width range of a corresponding pattern slice then the layout block does not match the range pattern. If the comparison succeeds, further comparisons are made between a sequence of lengths of layout fragments in each layout slice and a sequence of length ranges of pattern fragments in corresponding pattern slices. If the length of any layout fragment falls outside the length range of a corresponding pattern fragment then the block does not match the range pattern. If all lengths are within their respective ranges, then the block matches the pattern, although additional constraints are checked in some embodiments. | 05-28-2009 |
20090144674 | Timing Analysis When Integrating Multiple Circuit Blocks While Balancing Resource Requirements And Accuracy - An aspect of the present invention provides for timing analysis when integrating multiple circuit blocks while balancing resource requirements and accuracy. In an embodiment, an optimized model for a circuit block is created by combining information provided by two different models of the same circuit block and performing timing analysis based on the optimized model. In an embodiment, the two models correspond to black box and interface timing models. In the optimized model, ports for which only timing arc information is deemed necessary are modeled using corresponding information from the black box model, while ports for which more accurate or detailed information is deemed necessary are modeled using corresponding information from the interface timing model. The optimized model enables the integration to be performed with a balance of resource requirements and accuracy. | 06-04-2009 |
20090144675 | TRANSACTION BASED VERIFICATION OF A SYSTEM ON CHIP ON SYSTEM LEVEL BY TRANSLATING TRANSACTIONS INTO MACHINE CODE - In a transaction-based verification environment for complex semiconductor devices, enhanced verification efficiency may be achieved by providing a transaction to machine code translator and an appropriate interface that enables access of the translated machine code instruction by a CPU under test. In this manner, transaction-based test environments may have a high degree of re-usability and may be used for verification on block level and system level. | 06-04-2009 |
20090150835 | TECHNIQUE FOR GENERATION OF LOAD-SLEW INDICES FOR CIRCUIT CHARACTERIZATION - A method and system for generation of low-slew indices for circuit characterization are disclosed. In one embodiment, a method for automatically generating a subset of sampling points from a set of load and slew points for circuit characterization includes iteratively obtaining sampling points such that error between an actual value and an interpolated intermediate value is below or equal to a threshold error value. The subset of sampling points is then formed from the iteratively obtained sampling points. | 06-11-2009 |
20090150836 | Intelligent Pattern Signature Based on Lithography Effects - The present invention is directed to an improved method, system, and computer program product for accessing and analyzing patterns in the integrated circuit design. The method, system or computer program product includes generating an intelligent signature for a pattern. The derived pattern signature is an intelligent pattern identifier because it retains only essential information about a pattern that corresponds to lithography printable portions of the pattern. Accordingly, one pattern signature can represent a group of design patterns that are equivalents from a lithography perspective. | 06-11-2009 |
20090158224 | DESIGN STRUCTURE INCLUDING FAILING ADDRESS REGISTER AND COMPARE LOGIC FOR MULTI-PASS REPAIR OF MEMORY ARRAYS - Disclosed is design structure including an integrated circuit having a system for moving a failing address into a new FAR by utilizing the functional compare circuitry during BIST of redundant memory elements. Disclosed is an any-for-any scheme that eliminates the tri-state address bus. The design structure allows for easy, discrete scaling with the addition of more FARs, while also allowing larger addresses with no additional control circuit overhead. | 06-18-2009 |
20090172609 | JITTER AMOUNT ESTIMATING METHOD, METHOD FOR CALCULATING CORRELATION BETWEEN AMOUNT OF SIMULTANEOUSLY OPERATING SIGNAL NOISE AND JITTER AMOUNT, AND RECORDING MEDIUM - An SSO noise calculating unit estimates the amount of simultaneously operating signal noise caused by simultaneous operations of input/output pins peripheral to a power supply voltage pin as a center. A PLL jitter calculating unit estimates the amount of jitter occurring at the power supply voltage pin by using as an input the estimated amount of simultaneously operating signal noise, and by referencing a correlation between the amount of simultaneously operating signal noise and the amount of jitter, which indicates a correlation calculated beforehand between the amount of simultaneously operating signal noise and the amount of jitter. | 07-02-2009 |
20090172610 | System and method for circuit simulation - In a circuit simulation system, a storage section is configured to store a circuit data, an analysis condition data and an output data. An initial data setting section reads out the circuit data and the analysis condition data from the storage section and sets an initial data and a convergence condition for a solution calculating process based on the circuit data and the analysis condition data. A processing section generates a circuit equation to each of a voltage variable and a current variable based on the circuit data, and executes the solution calculating process based on the initial data to calculate a solution. A convergence determining section executes a convergence determining process of whether or not the solution meets the convergence condition, on the voltage variable. An output section stores the solution into the output data when it is determined to meet the convergence condition. A repetition control section controls the processing section to calculate a next solution by using the solution as the initial data, when it is determined not to meet the convergence condition. | 07-02-2009 |
20090172611 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Manufacturing a semiconductor device by measuring an electrical characteristic of a plurality of semiconductor elements, defining layout parameters on the basis of layout data and deciding a functional relationship between the layout parameters and the electrical characteristic, extracting values of the layout parameters from design layout data of the semiconductor device, calculating a predicted electrical characteristic of the semiconductor device, calculating a difference between a target electrical characteristic and the predicted electrical characteristic of the semiconductor device, generating a plurality of candidates of the values of the layout parameters, selecting a specific value from among the candidates so as to decrease the difference between the target electrical characteristic and the predicted electrical characteristic, changing the design layout data on the basis of the specific value, and manufacturing the semiconductor device on the basis of the changed design layout data. | 07-02-2009 |
20090172612 | STATIC HAZARD DETECTION DEVICE, STATIC HAZARD DETECTION METHOD, AND RECORDING MEDIUM - There is provided a check target extraction unit that receives logic circuit information describing a logic circuit, and extracts at least one set of a start point register and an end point register from registers in the logic circuit, the start point register outputting an exception signal to be supplied to the end point register via the propagation control circuit, and a static hazard detection unit that determines whether, for the at least one set extracted by the check target extraction unit, there are a plurality of paths through which propagation of an exception signal from a start point register to an end point register is possible when the propagation control circuit, in response to a control signal, inhibits propagation of the exception signal. | 07-02-2009 |
20090172613 | Mutual Inductance extraction using dipole approximations - Various methods for analyzing mutual inductance in an integrated circuit layout are disclosed. In one exemplary embodiment, for instance, a circuit description indicative of the layout of signal wires and ground wires in the circuit is received. The signal wires and the ground wires are grouped into at least a first bundle and a second bundle, wherein the first bundle and the second bundle each comprise a respective signal-wire segment and one or more corresponding ground-wire segments. A representative dipole moment is calculated for the first bundle. Using the representative dipole moment, the mutual inductance between the first bundle and the second bundle is calculated. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing design databases created or modified using any of the disclosed techniques are also disclosed. | 07-02-2009 |
20090187866 | Electrical Parameter Extraction for Integrated Circuit Design - A system, method, and computer readable medium for generating a parameterized and characterized pattern library for use in extracting parasitics from an integrated circuit design is provided. In an embodiment, a layout of an interconnect pattern is provided. A process simulation may be performed on the interconnect pattern. In a further embodiment, the interconnect pattern is dissected into a plurality of segments taking into account OPC rules. A parasitic resistance and/or parasitic capacitance associated with the interconnect pattern may be determined by a physical model and/or field solver. | 07-23-2009 |
20090187867 | Techniques for Verifying Error Detection of a Design Rule Checking Runset - A technique for verifying error detection of a design rule checking runset includes assigning first shapes for a first layer of an integrated circuit design to a first cell and assigning second shapes for a second layer of the integrated circuit design to a second cell. Design rule checking is then performed on the first and second cells. Whether the design rule checking runset is functioning properly is then determined based on whether an error is detected in the design rule checking of the first and second cells. | 07-23-2009 |
20090193369 | PROCESS FOR DESIGN OF SEMICONDUCTOR CIRCUITS - The present invention generates model scenarios of semiconductor chip design and uses interpolation and Monte Carlo, with random number generation inputs, techniques to iteratively assess the models for a more comprehensive and accurate assessment of design space, and evaluation under projected manufacturing conditions. This evaluation information is then incorporated into design rules in order to improve yield. | 07-30-2009 |
20090193370 | Bondwire Design - A system and method of designing the physical shape of and determining the electromagnetic characteristics of a bondwire in an electrical circuit, comprising the steps of enabling a user to define the position of the bondwire in the electrical circuit layout, defining the position and loop shape of the bondwire in a 3D representation of the electrical circuit, segmenting the bondwire into discrete segments, determining the electromagnetic characteristics of each of the bondwire segments thereby to determine the overall electromagnetic characteristics of the bondwire. | 07-30-2009 |
20090193371 | METHOD AND DEVICES TO ASSIST IN DETERMINING THE FEASIBILITY OF A COMPUTER SYSTEM - The invention concerns a method and devices for analyzing the feasibility of a computer system composed of subsystems, each having functions. After having determined the functional architecture of the computer system comprising at least one subsystem and at least one function, the characteristics of the functions implemented are imported from a database. The user determines the number of subsystems and the number of connectors per subsystem. He then distributes the functions to the subsystems and enters the characteristics of the connectors and the characteristics of the subsystems. The computer system is analyzed in light of the information provided by the user and the characteristics of the functions implemented in order to determine the feasibility of the computer system. | 07-30-2009 |
20090199137 | SYSTEM AND METHOD FOR MULTI-EXPOSURE PATTERN DECOMPOSITION - Some embodiments provide a method and system for identifying error markers for patterns within a design layout that do not meet the manufacturing constraints. Some embodiments extend a region from the error marked region to extract a pattern for decomposition analysis. Some embodiments compare the extracted pattern to known patterns stored in a library, which also stores at least one previously computed decomposition solution for each known pattern. For an extracted pattern existing within the library, some embodiments retrieve the previously computed decomposition solution from the library. For an extracted pattern that does not exist within the library, some embodiments use one or more simulations to determine a decomposition solution for the extracted pattern. The resulting decomposition solution replaces the extracted pattern within the design layout producing a variant of the original layout that contains the decomposed solution for the pattern. | 08-06-2009 |
20090199138 | Method and Apparatus for Evaluating Integrated Circuit Design Model Performance Using Basic Block Vectors and Fly-By Vectors Including Microarchitecture Dependent Information - A test system or simulator includes an IC test application sampling software program that executes test application software on a semiconductor die IC design model. The test application sampling software includes trace, simulation point, CPI error, clustering and other programs. IC designers utilize the test application sampling software to evaluate the performance characteristics of IC designs with test software applications. The test application sampling software generates basic block vectors (BBVs) and fly-by vectors (FBVs) from instruction trace analysis of test application software. The test application sampling software analyzes microarchitecture dependent information that it uses to generate the FBVs. Test application sampling software generates a reduced representative test application software program from the BBV and FBV data utilizing an instruction budgeting method. Designers use the test system with test application sampling software to evaluate IC design models by using the representative test application software program. | 08-06-2009 |
20090199139 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR IMPROVED ELECTRICAL ANALYSIS - An improved method, system, user interface, and computer program product is described for using a memory and learning component to improve capacitance and resistance estimates based on the types of layouts and devices being evaluated. According to some approaches, a learning component is implemented that uses recommended test sets from the evaluation component to automatically test the extraction estimates against the field solver. Variability models from manufacturing or electrical analysis may also be used to select a series of objects (unique conductor geometries) that make up a conduction path or net or specific conductor geometries for evaluation and additional learning improvement. | 08-06-2009 |
20090204930 | IPHYSICAL DESIGN SYSTEM AND METHOD - A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency. | 08-13-2009 |
20090210830 | SYSTEM AND METHOD FOR ESTIMATING TEST ESCAPES IN INTEGRATED CIRCUITS - A method for designing an integrated circuit including estimating a test escape rate for tests of interest, a test coverage calculator and a system for estimating a test escape rate for tests of interest associated with a portion of an integrated circuit (IC) die. In one embodiment the method includes the step of: estimating a test escape rate for a set of fault tests to be performed on an IC under design based on an estimated yield and a combined coverage of the set of fault tests; the combined coverage accounting for overlapping coverage among the set of fault tests. | 08-20-2009 |
20090210831 | CMOS Circuit Leakage Current Calculator - This invention provides a method for determining leakage current in a CMOS circuit having several devices. It includes the steps of reading a netlist which describes the circuit and includes information on both these devices in the circuit and how these devices are interconnected. Next, an input signal state data file is generated which provides all of the possible input states for the circuit. A determination is made of which devices in the circuit are in an OFF state for each of the input signal states provided. Then the leakage current for each of these devices in the OFF state is computed for each of the input signal states. | 08-20-2009 |
20090210832 | Verification of Spare Latch Placement in Synthesized Macros - A method to assess spare latch placement in a macro, the method comprises steps of: determining a location for each spare latch in the macro; examining local clock buffers associated with the macro to locate any local clock buffers without a spare latch directly attached to clock nets driven by said local clock buffer; measuring a distance between each of the local clock buffers without spare latches and a closest spare latch; running statistics for the local clock buffers from the measuring step; and locating macros with inadequate spare latch placement using the statistics. | 08-20-2009 |
20090217219 | Method for designing an integrated circuit - A method for designing an integrated circuit is specified, in which upper and lower limits of dependent component parameters and of environment parameters ( | 08-27-2009 |
20090217220 | METHOD OF DESIGNING AN ELECTRONIC DEVICE AND DEVICE THEREOF - A plurality of sequential nodes in a design file for an electronic device are identified and an effective switching capacitance is determined for a first sequential node of the plurality of sequential nodes based upon statically predicted operation of a first device downstream from the first sequential node. The effective switching capacitance for the first sequential node is stored, and the process is repeated for the other identified sequential nodes in the design file. | 08-27-2009 |
20090217221 | SYSTEM AND METHOD TO OPTIMIZE SEMICONDUCTOR POWER BY INTEGRATION OF PHYSICAL DESIGN TIMING AND PRODUCT PERFORMANCE MEASUREMENTS - A system and method is provided for optimizing semiconductor power by integration of physical design timing and product performance measurements. The method includes: establishing a timing run and identifying a sigma code for the timing run; establishing ring oscillator bins and respective code; identifying a required timing run for a second level assembly to satisfy a selected voltage bin; timing a product using the required timing run; testing a ring oscillator of the product using the timing to obtain physical design identification; recording the physical design identification and the sigma code for the timing run; and using the recorded physical design identification and the sigma code to set a voltage for the product to optimize power. | 08-27-2009 |
20090217222 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: a plurality of processor elements each including a test circuit which tests whether there is a failure in the processor element and outputs a result of the test; a plurality of switch boxes provided so as to be respectively associated with processor elements, each of the switch boxes configured to have a table to store information of another processor element and transmit information of a corresponding processor element to the other processor element based on information stored in the table; a plurality of identification circuits provided so as to be respectively associated with processor elements, each of the identification circuits configured to identify a defective processor element on the basis of the result of the test and output location information of the defective processor element; and a transmission circuit configured to transmit the location information of the defective processor element output from the identification circuit to the switch boxes. | 08-27-2009 |
20090222773 | LEAKAGE CURRENT ANALYZING APPARATUS, LEAKAGE CURRENT ANALYZING METHOD, AND COMPUTER PRODUCT - A leakage current analyzing apparatus receives input of data used for analysis and indicating intra/inter-chip variation concerning the gate length of transistors constituting cells in a circuit to be designed, where the inter-chip variation is handled as a discrete probability density distribution R. Using the data input, the leakage current analyzing apparatus obtains a cumulative probability density for a leakage current value (of the circuit) that is equal to or less than each arbitrary leakage current value I | 09-03-2009 |
20090235212 | DESIGN STRUCTURE, FAILURE ANALYSIS TOOL AND METHOD OF DETERMINING WHITE BUMP LOCATION USING FAILURE ANALYSIS TOOL - A failure analysis tool, a method of using the tool and a design structure for designing a mask for protecting a critical area of wiring failure in a semiconductor chip during packaging is provided. The failure analysis tool includes a computer infrastructure operable to determine a risk area for wiring layer failure during solder bump formation by determining a distance from a center of a chip to a location for a solder bump processing and identifying an area at an edge of the location for the solder bump processes at a predetermined distance and greater from the center of the chip. | 09-17-2009 |
20090235213 | Layout-Versus-Schematic Analysis For Symmetric Circuits - Techniques for reducing the complexity of Electronic Design Automation Layout-Versus-Schematic algorithms to approximately O(n) for graphs without type-3 symmetries. | 09-17-2009 |
20090241075 | TEST CHIP VALIDATION AND DEVELOPMENT SYSTEM - Embodiments of an IC design system for test row/structure layout design are described in this application. The design system may include a test chip complier database, a test chip complier engine (TCCE), and a user interface module. The TCCE may be configured to communicate with at least the test chip compiler database and the user interface module, and configured to allow a user to automatically generate a test chip layout by providing an integrated circuit design system. With the system, a user can automatically generate a design by specifying the test row or test structure layout requirements for the design using sets of predefined templates, changing design template parameters using a table driven input format, scheduling generation of the design on a preferred layout design tool, visually inspecting the generated design for errors, and/or applying version controls to the generated design. Other embodiments are described. | 09-24-2009 |
20090249265 | PRINTED CIRCUIT BOARD DESIGNING APPARATUS AND PRINTED CIRCUIT BOARD DESIGNING METHOD - A method for designing a printed circuit board includes: determining a distance along a conductive line between an electronic component and a signal source which are mounted on the printed circuit board, the signal source transmitting a signal to the electronic component; calculating a maximum distance for preventing a voltage across the electronic component in a steady state from being superimposed with a reflected signal reflected from at the signal source, the maximum distance being between the electronic component and the signal source, the voltage caused by the signal, and simulating whether an amplitude of a voltage applying across the electronic component is within a given range when the distance is longer than the maximum distance. | 10-01-2009 |
20090249266 | Displacing Edge Segments On A Fabrication Layout Based On Proximity Effects Model Amplitudes For Correcting Proximity Effects - Techniques for forming a mask fabrication layout for a physical integrated circuit design layout include correcting the fabrication layout for proximity effects using a proximity effects model. A proximity effects model is executed to produce an initial output. The initial output is based on a first position for a segment in a fabrication layout. The first position is displaced from a corresponding original edge in the original fabrication layout by a distance equal to an initial bias. The model is also executed to produce a second output based on a second position for the segment. The second position is displaced from the corresponding original edge by a distance equal to a second bias. An optimal bias for the segment is determined based on the initial output and the second output. The segment is displaced in the fabrication layout from the corresponding edge based on the optimal bias. | 10-01-2009 |
20090254871 | Methods for Hierarchical Noise Analysis - Systems and methods for hierarchical noise analysis of digital circuits, wherein analysis of a cell is based on the configuration of the cell itself and also the upstream circuit components that are connected to the inputs of the cell. One embodiment comprises a method for noise analysis in an electronic circuit such as a digital CMOS circuit. The method includes identifying a cell and identifying the inputs of the cell. For each of the inputs of the cell, a corresponding first upstream circuit component is identified. The identified component is the first component upstream from the cell's input and is directly connected to the input. A noise analysis for the cell is performed based upon the configuration of the cell in combination with the identified upstream circuit components. The result of the analysis for the combination of the cell and the upstream circuit components can then be stored. | 10-08-2009 |
20090254872 | Method for Designing and Manufacturing a PMOS Device with Drain Junction Breakdown Point Located for Reduced Drain Breakdown Voltage Walk-in - A PMOS device can be designed and manufactured in accordance with the invention to locate its drain junction breakdown point and maximum impact ionization point to reduce or eliminate drain breakdown voltage walk-in. In some embodiments, the drain junction breakdown point and maximum impact ionization point are located sufficiently far from the gate that the device exhibits no significant drain breakdown voltage walk-in. The device can be a high voltage power transistor having an extended drain region including a P-type lightly doped drain (P-LDD) implant, with drain junction breakdown and maximum impact ionization points appropriately located by controlling the implant dose employed to produce the P-LDD implant. Other aspects of the invention are methods for designing a PMOS device including by determining relative locations of the gate and at least one of the drain junction breakdown and maximum impact ionization points to reduce drain breakdown voltage walk-in, and methods for manufacturing integrated circuits including any embodiment of the PMOS device of the invention. | 10-08-2009 |
20090276735 | System and Method of Correcting Errors in SEM-Measurements - Embodiments of the invention relate to correcting errors in scanning electron measurements during measuring structural dimensions of an integrated circuit for optical proximity correction by extracting feature edges of a test pattern within an image, calculating at least one scaling error of the image by comparing the extracted feature edges of assist structures with a layout pattern, modifying feature edges of test structures within the test pattern by incorporating the at least one scaling error so as to at least partially compensate the scaling errors, and verifying a model for optical proximity corrections and/or model input data by using the modified feature edges of the test structures. | 11-05-2009 |
20090276736 | Test Pattern Based Process Model Calibration - Embodiments of the present invention provide a method for performing lumped-process model calibration. The method includes creating a plurality of sub-process models for a set of sub-processes; creating a lumped-process-model incorporating said set of sub-processes; calculating a first set of output patterns from a set of test patterns by using said plurality of sub-process models; calculating a second set of output patterns from said set of test patterns by using said lumped-process-model; and adjusting process parameters used in said lumped-process-model to calculate said second set of output patterns to match said first set of output patterns. A computer system for performing the lumped-process model calibration is also provided. | 11-05-2009 |
20090276737 | TOOL FOR CHARGE TRAPPING MEMORY USING SIMULATED PROGRAMMING OPERATIONS - A method for simulating operation of a charge trapping memory cell which computes the amount of charge trapped by determining first tunneling current through the tunneling layer, determining second tunneling current out of the charge trapping layer to the gate, determining third tunneling current escaping from traps in the charge trapping layer and tunneling out to the gate, and integrating said tunneling currents over a time interval. A change in threshold voltage can be computed for a transistor including the charge trapping structure. The parameter set can include only physical parameters, including layer thickness, band offsets and dielectric constants. | 11-05-2009 |
20090288046 | CIRCUIT DESIGN PROCESSES - A method for designing a circuit. The method includes (i) providing a netlist of a design and (ii) dividing the netlist into N user logics, N being a positive integer. After said dividing the netlist is performed, the N user logics in N macro test wrappers are instantiated resulting in N instantiated logics. After said instantiating the N user logics is performed, the N instantiated logics are processed. After said processing is performed, a result of said processing is back-annotated to the netlist. | 11-19-2009 |
20090288047 | METHOD AND APPARATUS FOR USING A DATABASE TO QUICKLY IDENTIFY AND CORRECT A MANUFACTURING PROBLEM AREA IN A LAYOUT - One embodiment provides a system for using a database to quickly identify a manufacturing problem area in a layout. During operation, the system receives a first check-figure which identifies a first area in a first layout, wherein the first area is associated with a first feature. Next, the system determines a first sample using the first check-figure, wherein the first sample represents the first layout's geometry within a first ambit of the first check-figure, wherein the first sample's geometry is expected to affect the shape of the first feature. The system then performs a model-based simulation using the first sample to obtain a first simulation-result which indicates whether the first feature is expected to have manufacturing problems. Next, the system stores the first simulation-result in a database which is used to quickly determine whether a second feature is expected to have manufacturing problems. | 11-19-2009 |
20090288048 | ANALYSIS OF STRESS IMPACT ON TRANSISTOR PERFORMANCE - Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation. | 11-19-2009 |
20090288049 | Method for Rapid Estimation of Layout-Dependent Threshold Voltage Variation in a MOSFET Array - An automated method for estimating layout-induced variations in threshold voltage in an integrated circuit layout. The method begins with the steps of selecting a diffusion area within the layout for analysis. Then, the system identifies Si/STI edges on the selected area as well as channel areas and their associated gate/Si edges. Next, the threshold voltage variations in each identified channel area are identified, which requires further steps of calculating threshold voltage variations due to effects in a longitudinal direction; calculating threshold voltage variations due to effects in a transverse direction; and combining the longitudinal and transverse variations to provide an overall variation. Finally, a total variation is determined by combining variations from individual channel variations. | 11-19-2009 |
20090293023 | Generation of standard cell library components with increased signal routing resources - Generating cells with increased signal routing resources. In an embodiment, power and ground buses in a metal layer of a source cell are identified and removed. Any vias terminating on the removed buses may also be removed. Additional via and connections are added to other desired layers to provide connectivity to the nodes disconnected due to the earlier removal. According to an aspect of the present invention, such connections are added during a chip design phase (i.e., when the cell instances are incorporated into an integrated circuit, sought to be designed). | 11-26-2009 |
20090293024 | Detecting Circuit Design Limitations and Stresses Via Enhanced Waveform and Schematic Display - A method and apparatus are provided for implementing enhanced detection of circuit design limitations and stresses via enhanced waveform and schematic display. A selected simulation is run, for example, a transient, an AC, or a DC simulation. Then a displayed schematic highlights problem areas using a color set selected by a circuit designer. | 11-26-2009 |
20090293025 | SEMICONDUCTOR CIRCUIT DESIGN SUPPORT TECHNIQUE - Designation of observation points in an observation target circuit for which operations are observed in simulation is accepted, and circuit data of an observation circuit is attached to circuit data of the observation target circuit so that the observation circuit is connected to the observation target circuit according to designation data of the observation points. At this time, a double-buffer configuration is adopted for the observation circuit, and the number of occurrence times of a specific state at a specific observation point during a first period and the number of occurrence times of the specific state at the specific observation point during a second period are alternately outputted and stored into RAM. | 11-26-2009 |
20090300557 | OPC MODELS GENERATED FROM 2D HIGH FREQUENCY TEST PATTERNS - A method of generating a scalable OPC model for composing reticle pattern files from IC layouts using 2D test patterns is disclosed. The 2D test patterns include basic features which replicate features found in advanced ICs. Variations of feature dimensions and structure pitches provide measurement data which enables the scalability of the OPC model. A method of checking reticle pattern files for features which cannot be modeled by the scalable OPC model is also disclosed. | 12-03-2009 |
20090300558 | USE OF STATE NODES FOR EFFICIENT SIMULATION OF LARGE DIGITAL CIRCUITS AT THE TRANSISTOR LEVEL - A method is provided for simulating a sequential digital circuit module given a set of input conditions and a current state for the circuit. The method comprises initiating all state nodes of the circuit module to logic values stored in the current state, initializing all sequential submodules of the circuit module to the states stored in the current state, simulating the circuit module after initialization, and after completion of the simulation step, reporting the output logic values and associated delays and storing the logic values of the state nodes and the states of the sequential modules in the next state in the circuit module, multiple value changes in the state nodes of the circuit module being recorded on the next state. | 12-03-2009 |
20090307637 | METHOD OF DESIGNING MULTI-STATE RESTORE CIRCUITRY FOR RESTORING STATE TO A POWER-MANAGED FUNCTIONAL BLOCK - Methods of designing and testing restore logic for restoring values to storage elements of power-managed logic circuitry. In one implementation, a design method disclosed includes providing a design of the logic circuitry that, when instantiated, will have a number of states it can be returned to upon repowering-up the logic circuitry. Values held by the storage elements are determined and utilized to categorize the storage elements into categories that allow the development of restore logic that will restore the state of the power-managed logic circuitry that is appropriate to the particular powering-up. The restore logic design is tested by modeling it and the power-managed logic circuitry in a hardware description language and simulating the number of states over a number of test cases. If the design and testing are successful, the restore logic can be optimized for instantiation into an actual integrated circuit. | 12-10-2009 |
20090307638 | TRUSTWORTHY STRUCTURAL SYNTHESIS AND EXPERT KNOWLEDGE EXTRACTION WITH APPLICATION TO ANALOG CIRCUIT DESIGN - A system and method that does trustworthy multi-objective structural synthesis of analog circuits, and extracts expert analog circuit knowledge from the resulting tradeoffs. The system defines a space of thousands of possible topologies via a hierarchically organized combination of designer-trusted analog building blocks, the resulting topologies are guaranteed trustworthy. The system can perform a search based on a multi-objective evolutionary algorithm that uses an age-layered population structure to balance exploration vs. exploitation, with operators that make the search space a hybrid between vector-based and tree-based representations. A scheme employing average ranking on Pareto fronts is used to handle a high number of objectives. Good initial topology sizings are quickly generated via multi-gate constraint satisfaction. To explicitly capture expert analog design knowledge, data mining is employed on the sized circuits to: automatically generate a decision tree for navigating from performance specifications to topology choice, to do global nonlinear sensitivity analysis, and to generate analytical models of performance tradeoffs. | 12-10-2009 |
20090307639 | METHODS AND DEVICES FOR INDEPENDENT EVALUATION OF CELL INTEGRITY, CHANGES AND ORIGIN IN CHIP DESIGN FOR PRODUCTION WORKFLOW - The technology disclosed relates to granular analysis of design data used to prepare chip designs for manufacturing and to identification of similarities and differences among parts of design data files. In particular, it relates to parsing data and organizing into canonical forms, digesting the canonical forms, and comparing digests of design data from different sources, such as designs and libraries of design templates. Organizing the design data into canonical forms generally reduces the sensitivity of data analysis to variations in data that have no functional impact on the design. The details of the granular analysis vary among design languages used to represent aspects of a design. For various design languages, granular analysis includes partitioning design files by header/cell portions, by separate handling of comments, by functionally significant/non-significant data, by whitespace/non-whitespace, and by layer within a unit of design data. The similarities and differences of interest depend on the purpose of the granular analysis. The comparisons are useful in many ways. | 12-10-2009 |
20090307640 | Methods and Devices for Independent Evaluation of Cell Integrity, Changes and Origin in Chip Design for Production Workflow - The technology disclosed relates to granular analysis of design data used to prepare chip designs for manufacturing and to identification of similarities and differences among parts of design data files. In particular, it relates to parsing data and organizing into canonical forms, digesting the canonical forms, and comparing digests of design data from different sources, such as designs and libraries of design templates. Organizing the design data into canonical forms generally reduces the sensitivity of data analysis to variations in data that have no functional impact on the design. The details of the granular analysis vary among design languages used to represent aspects of a design. For various design languages, granular analysis includes partitioning design files by header/cell portions, by separate handling of comments, by functionally significant/non-significant data, by whitespace/non-whitespace, and by layer within a unit of design data. The similarities and differences of interest depend on the purpose of the granular analysis. The comparisons are useful in many ways. | 12-10-2009 |
20090307641 | FAST EVALUATION OF AVERAGE CRITICAL AREA FOR IC LAYOUTS - Method and apparatus for approximating the average critical area of a layout or layout region, involving summing, over all the object segments of interest, respective critical area contribution values that are dependent upon particular layout parameters of the objects, each of the contribution values being representative of a plurality of defect sizes, and being defined such that for each defect size in the plurality of defect sizes, and for a particular defect type, the contribution values collectively count all critical areas arising due to the object segments of interest only once. | 12-10-2009 |
20090313589 | METHOD FOR DESIGNING OVERLAY TARGETS AND METHOD AND SYSTEM FOR MEASURING OVERLAY ERROR USING THE SAME - A method for designing an overlay target comprises selecting a plurality of overlay target pairs having different overlay errors or offsets, calculating a deviation of the simulated diffraction spectrum for each overlay target pair, selecting a plurality of sensitive overlay target pairs by taking the deviation of the simulated diffraction spectrum into consideration, selecting an objective overlay target pair from the sensitive overlay target pairs by taking the influence of the structural parameters to the simulated diffraction spectrum into consideration, and designing the overlay target pair based on the structural parameter of the objective overlay target pair. | 12-17-2009 |
20090319963 | METHOD FOR ESTIMATION OF TRACE INFORMATION BANDWIDTH REQUIREMENTS - A method of evaluating the feasibility of a CoreSight trace architecture in a SoC before the hardware and/or firmware is available allowing for better die size estimates (IO count and gate count) and package requirement for the design in the early stages of planning. | 12-24-2009 |
20090319964 | METHOD AND APPARATUS FOR THERMAL ANALYSIS - Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout that includes numerous circuit modules. The method divides the IC design layout into a set of elements, where at least one element includes several wires. The method computes a set of conductivity groups of values for the set of elements. The method identifies a temperature distribution for the IC design layout based on the set of conductivity groups of values. In some embodiments, each of these elements corresponds to a particular portion of a particular layer of the IC design layout. Each element includes several nodes. Each conductivity group of values is defined by entry values. Each entry value describes how heat flow at a particular node of the element is affected by a temperature change at another particular node of the element. | 12-24-2009 |
20090319965 | METHOD AND APPARATUS FOR THERMAL ANALYSIS OF THROUGH-SILICON VIA (TSV) - Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout. The IC design layout includes several wiring layers in some embodiments. The IC design layout includes a substrate that has at least one through-silicon via (“TSV”). The method divides the IC design layout into a set of elements. The method identifies a temperature distribution for the IC design layout by using the set of elements. In some embodiments, at least one element includes a metal component and a non-metal component. The non-metal component is silicon in some embodiments, and a dielectric in other embodiments. | 12-24-2009 |
20090319966 | Method for analyzing and designing semiconductor device and apparatus for the same - In a support apparatus for analysis and design of a semiconductor device, a function indicating an impurity concentration distribution in a channel region of a first transistor in a depth direction is set. A structure data indicating a structure of a transistor device and a measurement value of each of electric characteristics of the transistor are related. A Poisson's equation, which is express by using the function, is solved by using a depletion layer width as a variable to calculate a surface potential, and a first calculation value of the electric characteristic of the first transistor is calculated by using the surface potential. A determining section determines the function to indicate the impurity concentration distribution of a first transistor when a measurement value corresponding to a first structure data which indicates a structure of the first transistor, and the first calculation value are substantially coincident with each other, and stores the function in the storage section. The above operations are repeated until the first calculation value and the measurement value are substantially coincident with each other. | 12-24-2009 |
20090319967 | ANALYSIS AND DESIGN APPARATUS FOR SEMICONDUCTOR DEVICE AND ANALYSIS AND DESIGN METHOD FOR SEMICONDUCTOR DEVICE - An analysis and design apparatus for semiconductor device, includes a storage portion, a parameter setting portion, an element characteristic calculation portion, and a determination portion. The storage portion stores structure information and measured values of a transistor. The parameter setting portion divides a channel region into a plurality of regions, and temporarily sets a plurality of impurity concentrations for the plurality of regions as a plurality of parameters. The element characteristic calculation portion calculates a plurality of effective impurity concentrations in the plurality of regions based on the plurality of parameters, calculates a surface potential by solving a Poisson equation using the plurality of effective impurity concentrations, and calculates calculated values of electric characteristics of the transistor using the surface potential. The determination portion compares the calculated values with measured values read from the storage portion based on the structure information, determines the plurality of parameters for the transistor when the measured values correspond to the calculated values. | 12-24-2009 |
20090327981 | Semiconductor device or printed wiring board design method and design support system that implements settings by using a semiconductor device model that expresses parasitic elements that occur when packaged - Correction circuit models are acquired for correcting electrical characteristic parameters that change upon mounting on a board. The correction circuit models are added to a separate model that represents a separate semiconductor device in isolation to create a semiconductor device model that represents the semiconductor device in a board-mounted state. An equivalent circuit model that represents an adjustment-object system is connected to the semiconductor device model that was created, and based on the semiconductor device model to which the equivalent circuit model is connected, adjustment-object values relating to the adjustment-object system are calculated. These adjustment-object values are compared with limit values that were determined in advance, and based on the results of comparison, a design guide is determined for adjusting the adjustment-object system. | 12-31-2009 |
20100005432 | FLOATING NET INSPECTION METHOD - A floating net inspection method includes: providing a netlist which describes a circuit structure of an application circuit, the application circuit including a plurality of transistors; coupling a power supply port and a signal input port of the application circuit to voltage sources, respectively; generating test voltages respectively through the voltage sources, such that the test voltages are applied to the transistors, the test voltages being larger than a reference voltage, and determining whether a connecting node of one of the transistors is floating on the basis of whether a voltage of the connecting node is larger than the reference voltage. | 01-07-2010 |
20100017762 | IMPLEMENTING INTEGRATED CIRCUIT YIELD ESTIMATION USING VORONOI DIAGRAMS - A method for implementing integrated circuit yield estimation includes computing Voronoi regions for an original integrated circuit layout; for each bisector segment of the Voronoi regions and one or more failure mechanisms, computing a failure probability based on geometric parameters of corresponding Voronoi edge regions associated with the bisector segment, using pre-computed failure probabilities as a function of edge orientation and spacing for the failure mechanisms; for each segment of a design edge bounded by bisectors, computing a change in the failure probability based on the geometric parameters of the Voronoi regions, using pre-computed change in failure probabilities for the failure mechanisms; encoding the computed failure probabilities for each Voronoi region in a manner suitable for visual differentiation by a user; and encoding the computed change in failure probabilities by directional displacement of a layout edge segment that would result in a decrease in failure probability. | 01-21-2010 |
20100017763 | Stochastic Steady State Circuit Analyses - A method for simulating a system without a time invariant or periodically time-varying steady state is provided. The method limits the number of states included in a Markov chain model by discretizing the states based on Gaussian decomposition, utilizes a state exploration algorithm that discovers only recurrent states, and/or utilizes a state truncation algorithm that eliminates states with negligible stationary probabilities. | 01-21-2010 |
20100023897 | Property-Based Classification In Electronic Design Automation - One or more properties can be associated with a design object in a microdevice design. These properties then can be used to classify relationships in a circuit design, such as a layout circuit design. In some implementations, the various relationships can be classified based upon the similarity or dissimilarity of the associated property values. | 01-28-2010 |
20100023898 | CIRCUIT DESIGN ASSISTING APPARATUS, COMPUTER-READABLE MEDIUM STORING CIRCUIT DESIGN ASSISTING PROGRAM, AND CIRCUIT DESIGN ASSISTING METHOD - A circuit design assisting apparatus for assisting designing of a circuit is provided. The apparatus includes a storage unit that stores information regarding a configuration of components used in a design-target circuit and wirings between the components, an acquiring unit that acquires label setting information that associates a label with the configuration information indicating the components of the design-target circuit and the wirings between the components, a selecting unit that selects, from the storage unit, information having a configuration that matches the configuration information included in the acquired label setting information. and a setting unit that sets a label that is associated with the configuration information by the acquired label setting information to the information selected by the selecting unit and registering the set label in the storage unit. | 01-28-2010 |
20100023899 | ANALYSIS OF STRESS IMPACT ON TRANSISTOR PERFORMANCE - Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation. | 01-28-2010 |
20100023900 | ANALYSIS OF STRESS IMPACT ON TRANSISTOR PERFORMANCE - Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation. | 01-28-2010 |
20100023901 | ANALYSIS OF STRESS IMPACT ON TRANSISTOR PERFORMANCE - Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation. | 01-28-2010 |
20100023902 | ANALYSIS OF STRESS IMPACT ON TRANSISTOR PERFORMANCE - Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation. | 01-28-2010 |
20100031207 | ANALYZING APPARATUS AND ANALYZING METHOD - In an analyzing apparatus, an input accepting unit accepts input information including an analysis condition of a circuit element (circuit) to be analyzed, an analysis-SPICE-file generating unit generates an analysis SPICE file based on the input information, and an analysis-SPICE-file executing unit executes the analysis SPICE file, thereby analyzing the characteristic of the circuit element. | 02-04-2010 |
20100037189 | Power factor correction using hierarchical context of a power monitoring system - Automated power factor correction analysis methods based on an automatically determined hierarchy representing how IEDs and transformers are linked together in an electrical system for reducing a utility bill, releasing capacity to the electrical system, reducing losses, and/or improving voltages. The automatically determined hierarchy places the system elements in spatial context and is exploited by the power factor correction analysis methods to identify power factor correction opportunities. Recommendations are made as to sizing and location of capacitors within the hierarchy where power factor improvements can be achieved. Harmonic distortion levels can be checked first to determine whether safe levels exist for capacitor banks. Recommendations are also checked to avoid leading power factors anywhere in the system due to the addition of capacitor banks. Capacitor bank location is tailored to the end-user's goal for power factor correction. Cost savings and payback periods associated with any ameliorative power factor correction activities are also determined. | 02-11-2010 |
20100042958 | ANALYSIS OF STRESS IMPACT ON TRANSISTOR PERFORMANCE - Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation. | 02-18-2010 |
20100042959 | Test pattern coverage through parallel discard, flow control, and quality metrics - A method, computer program product, and data processing system that controls test packets that are sent to a coordinating computer system is provided. A node computer system runs a test case that results in one or more test result packets. Control data structures are received from one or more coordinating computer systems. The resulting test result packets are compared to the one or more received data structures. The comparison reveals whether one or more of the test result packets include results requested by the coordinating computer systems. Test result packets are selected when the comparison reveals that the selected test result packets include results requested by the coordinating computer systems. Selected test result packets are sent to one of the coordinating computer systems and unselected test result packets are discarded by the node. | 02-18-2010 |
20100050137 | AUTOMATED ISOLATION OF LOGIC AND MACRO BLOCKS IN CHIP DESIGN TESTING - A method and system for testing a synthesized design of a semiconductor chip. The method includes inputting a macro test Input/Output (I/O) name of the semiconductor chip, along with associated attributes and a netlist, where the netlist is a synthesized design of the semiconductor chip. The method includes tracking the macro test I/O to a chip test I/O. The method further includes detecting mismatches between attributes associated with the macro test I/O and the chip test I/O. Subsequently, reporting any mismatches between the attributes associated with the macro test I/O and the chip test I/O. | 02-25-2010 |
20100058258 | Method of Estimating a Leakage Current in a Semiconductor Device - In a method of estimating a leakage current in semiconductor device, a chip including a plurality of cells is divided into segments by a grid model. Spatial correlation is determined as spatial correlation between process parameters concerned with the leakage currents in each of the cells. A virtual cell leakage characteristic function of the cell is generated by arithmetically operating actual leakage characteristic functions. A segment leakage characteristic function is generated by arithmetically operating the virtual cell leakage characteristic functions of each cell in the segment. Then, a full chip leakage characteristic function is generated by statistically operating the segment leakage characteristic functions of each segment in the chip. Accordingly, the computational loads of Wilkinson's method for generating the full chip leakage characteristic function may be remarkably reduced. | 03-04-2010 |
20100064265 | RF CIRCUIT, CIRCUIT EVALUATION METHOD, ALGORITHM AND RECORDING MEDIUM - It is required to qualitatively design a circuitry device in which not only in a small-signal simulation but also in a large-signal simulation, loop oscillation and motorboating oscillation of an amplifier are precisely predicted to suppress oscillation without severing a loop or without inserting a circulator. To remove insertion loss due to a probe resistor Rx, a negative resistor −Rx/2 is arranged at both ends thereof. To prevent consumption of a DC bias in the probe, a DC block is applied. Further, to remove thermal noise caused by an actual resistor to reduce influence on a noise factor NF, the noise temperature (environmental temperature) of the actual resistor is set to zero Kelvin. | 03-11-2010 |
20100064266 | VERIFICATION SUPPORT APPARATUS, VERIFICATION SUPPORT METHOD, AND COMPUTER PRODUCT - A computer-readable recording medium stores therein a verification support program that causes a computer to execute receiving a hardware description of a combinational circuit to be verified; extracting, from the hardware description, a conditional branch description expressing conditional branch processing; identifying, from among conditional branch descriptions extracted at the extracting of a conditional branch description and based on a description sequence in the hardware description, a combination of conditional branch descriptions having a hierarchical relation; extracting, from among combinations of conditional branch descriptions identified at the identifying, a combination having a potential to satisfy a specified condition; creating a simulation program that causes the specified condition for the conditional branch descriptions included in the combination extracted at the extracting of the combination to be satisfied; and outputting, as assertion information of the combinational circuit, the simulation program created for each combination at the creating. | 03-11-2010 |
20100064267 | Semiconductor device design support apparatus and substrate netlist generation method - A semiconductor device design support apparatus for generating a substrate netlist so as to be able to perform substrate noise analysis with high accuracy in a short time. The semiconductor device design support apparatus comprises a unit that divides a semiconductor device layout into a plurality of segments and generates a macro-model of the segments by using a current waveform of an instance included in the divided segments; a unit that replaces a pattern (termed as “substrate interface”) that is designed to be an interface with a substrate with respect to the segments, by a prescribed substrate interface diagram; and a unit that generates a substrate netlist, based on the substrate interface diagram of the plurality of segments. | 03-11-2010 |
20100064268 | Capacitor arrangement method and layout apparatus - A layout apparatus stores a plurality of capacitor cells which are classifiable into a first classification for identifying capacitor cells having different sizes by frequency characteristic correlating with gate width of a capacitor and a second classification for identifying capacitor cells having different frequency characteristics by cell size. The layout apparatus: recognizes a plurality of combinations of a directed frequency characteristic and arrangement area; selects, for each of the combinations, capacitor cells corresponding to the directed frequency characteristic based on the first classification; reads out the capacitor cells in the descending order of cell size from the selected capacitor cells; arranges the read out capacitor cells to fill the directed arrangement area; checks a violation of capacitor density for all the directed arrangement areas of the plurality of combinations; replaces, when detecting the violation, a capacitor cell having larger gate width out of the arranged capacitor cells with a capacitor cell having smaller gate width besides the same cell size as the capacitor cell having larger gate width in accordance with the second classification; and retries checking the violation of capacitor density after finishing the replacement. | 03-11-2010 |
20100070934 | Analysis of Physical Systems via Model Libraries Thereof - A model library contains one or more storable models of a physical system each constructed by numerically solving relationships between a characteristic of the physical system given a set of model parameters. Such a model may be retrieved from the library according to values assigned to the model parameters and used to determine a corresponding characteristic of the physical system without repeating the numerical solution method originally used to create the model. Instead, a mapping may be applied to the storable model to seamlessly obtain the characteristic upon request. | 03-18-2010 |
20100070935 | Method and Apparatus for Merging EDA Coverage Logs of Coverage Data - An electronic design automation technology merges coverage logs. The coverage logs are generated by verification of a hardware description language circuit design. The coverage logs are merged as the coverage logs are generated, without waiting for all pending coverage logs. | 03-18-2010 |
20100070936 | WAIVER MECHANISM FOR PHYSICAL VERIFICATION OF SYSTEM DESIGNS - A method of waiving verification failures is disclosed. The method generally includes the steps of (A) generating a plurality of circuit error files by performing a plurality of physical verifications on a plurality of circuit designs, the circuit error files containing a plurality of circuit errors of the circuit designs, (B) generating a system error file by performing an additional physical verification on a system design, the system error file containing a plurality of system errors of the system design, the system design incorporating the circuit designs, (C) generating a valid error file by removing the circuit errors from the system error file, the valid error file containing a plurality of valid errors comprising a subset of the system errors and (D) storing the valid error file in a recording medium. | 03-18-2010 |
20100070937 | CIRCUIT VERIFICATION APPARATUS, CIRCUIT VERIFICATION METHOD, AND RECORDING MEDIUM - A circuit verification apparatus includes a code coverage measurement point extracting unit which reads a device-under-test circuit description written in a hardware description language and metrics information including information about multiple measurement objects, extracts multiple measurement points for code coverage measurement from the device-under-test circuit description, and generates a database including only predetermined measurement points among the extracted multiple measurement points. The circuit verification apparatus also includes an assertion converting unit configured to convert each of the predetermined measurement points to a corresponding assertion description and a code coverage result decompressing unit configured to receive the database and an assertion result obtained by performing measurement based on the assertion description and generate a code coverage result. | 03-18-2010 |
20100070938 | Preconditioning For EDA Cell Library - A characterized cell library for EDA tools includes one or more mathematical models for each cell, and one or more preconditioning functions (and/or inverse preconditioning functions) for each mathematical model. Each mathematical model represents a performance parameter (e.g., delay, power consumption, noise) or a preconditioned performance parameter of the cell. The preconditioning functions convert an operating parameter (e.g., input slew, output capacitance) associated with the performance parameter into a preconditioned input variable for the mathematical models. In doing so, the preconditioning functions allow for more accurate modeling of complex data relationships without increasing the complexity (e.g., order and number of coefficients) of the mathematical models. Also, because the cell library can be substantially similar to conventional polynomial-based cell libraries except for the inclusion of preconditioning functions, preconditioning does not significantly increase storage requirements and conventional EDA tools can be readily adapted to use the preconditioned cell library. | 03-18-2010 |
20100077364 | METHOD AND APPARATUS FOR DESIGNING AN INTEGRATED CIRCUIT - Method and apparatus for designing an integrated circuit, IC, layout by identifying one or more defects in a feature within the IC layout. Determining if an identified defect is improvable. Calculating an improvability metric of the IC layout based on the number of improvable defects and the total number of identified defects. | 03-25-2010 |
20100083198 | METHOD AND SYSTEM FOR PERFORMING STATISTICAL LEAKAGE CHARACTERIZATION, ANALYSIS, AND MODELING - A method, system, and computer program product are disclosed for performing statistical leakage power characterization to estimate yield of a circuit in terms of leakage power. According to some approaches, this is performed with consideration of bi-exponential modeling. | 04-01-2010 |
20100083199 | Increasing Scan Compression By Using X-Chains - To increase scan compression during testing of an IC design, an X-chain method is provided. In this method, a subset of scan cells that are likely to capture an X are identified and then placed on separate X-chains. A configuration and observation modes for an unload selector and/or an unload compressor can be provided. The configuration and observation modes provide a first compression for non-X-chains that is greater than a second compression provided for X-chains. ATPG can be modified based on such configuration and observation modes. This X-chain method can be fully integrated in the design-for-test (DFT) flow, requires no additional user input, and has negligible impact on area and timing. Test generation results on industrial designs demonstrate significantly increased compression, with no loss of coverage, for designs with high X-densities. | 04-01-2010 |
20100088655 | YIELD EVALUATING APPARATUS AND METHOD THEREOF - A yield evaluating apparatus and a method thereof are provided. The yield evaluating apparatus includes a spatial correlation module. The spatial correlation module receives at least one process-related data and a plurality of circuit layouts and obtains a correlation coefficient between unit elements in the circuit layouts according to the process-related data. The spatial correlation module calculates a spatial correlation between elements in each of the circuit layouts according to the correlation coefficient and selects one of the circuit layouts according to the spatial correlations. | 04-08-2010 |
20100088656 | PROPERTY CHECKING SYSTEM, PROPERTY CHECKING METHOD, AND COMPUTER-READABLE STORAGE MEDIUM - Checking efficiency of property checking is improved. The operation synthesis tool synthesizes an RTL circuit description from a behavioral level circuit description. In addition, the property generating unit generates a behavioral level property from the behavioral level circuit description. Subsequently, the property converting unit converts the generated behavioral level property into an RTL property. The model checking unit then checks the RTL circuit description by model checking technique using the RTL property. | 04-08-2010 |
20100088657 | EXPERT SYSTEM-BASED INTEGRATED INDUCTOR SYNTHESIS AND OPTIMIZATION - Apparatus and method for designing an electrical component in an integrated circuit, the apparatus comprising a processor, a user interface, and memory for storing data, the interface enabling a user to input a desired characteristic of the electrical component, such as inductance L or quality factor Q at an operating frequency f for an integrated spiral inductor, and the processor being adapted to determine sufficient optimal characteristics of the electrical component to define the electrical component for fabrication in the integrated circuit, the processor being adapted to combine the user desired characteristic with other preset characteristics of the electrical component or the integrated circuit, to define a first model of the electrical component, to simulate the model having the combined characteristics to determine performance, and to draw on a rule-set of expert knowledge relating to the general dependency of at least one design criterion, such as a physical, geometrical or performance characteristic, with another design criterion in order to enable modification of the model, thereby iteratively to determine a design solution for the electrical component through one or more simulations and modifications using the rule-set. | 04-08-2010 |
20100095254 | SYSTEM AND METHOD FOR TESTING PATTERN SENSITIVE ALGORITHMS FOR SEMICONDUCTOR DESIGN - A system and method for generating test patterns for a pattern sensitive algorithm. The method comprises the steps extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns. | 04-15-2010 |
20100100857 | GENERIC NON-VOLATILE SERVICE LAYER - Method and apparatus for constructing and operating an integrated circuit in an electronic device. In some embodiments, a generic service layer is integrated in a three dimensional integrated circuit and tested using a testing pattern stored in a non-volatile memory. The generic service layer is reconfigured to a permanent non-testing functional component of the integrated circuit. | 04-22-2010 |
20100100858 | Systems and Methods for Certifying a Racked Computer Assembly - In some embodiments, a method for testing a chassis including one or more information handling systems is provided. The method includes receiving a chassis configuration specification that defines a set of required components for a chassis configuration, generating one or more test images based at least the received chassis configuration specification, automatically determining components of the chassis, testing the determined components of the chassis using the one or more generated test images, and reporting results from the testing to a user. | 04-22-2010 |
20100107129 | Indeterminate State Logic Insertion - Illustrative embodiments provide a computer-implemented method for resolving indeterminate states by inserting logic into a design. The computer-implemented method receives an original design input from a requester to form a received input and determines whether the received input contains an indeterminate output. Responsive to a determination that the received input contains an indeterminate output, the computer-implemented method generates a temporary design from the received input, wherein the temporary design contains “unique” output and all inputs, updates the temporary design, and synthesizes the original design and each temporary design individually to form a synthesized original design and a set of synthesized temporary designs. The computer-implemented method merges the synthesized original design with the set of synthesized temporary design to form a final design; and returns the final design to the requester. | 04-29-2010 |
20100115478 | METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODCUT FOR PARALLELIZING TASKS IN PROCESSING AN ELECTRONIC CIRCUIT DESIGN - Disclosed are a method, a system, and a computer program product for implementing compact manufacturing model during various stages of electronic circuit designs. In some embodiments, the method loads the full design database information on the master; distributes the tasks to be processed in parallel; loads a full design on a master; spawns a plurality of slave sessions; sends to at least one slave a nutshell representation of the electronic circuit design; identifies a task to perform in parallel and sends the task to be performed in parallel; and receives execution results or processing results from some of the plurality of slaves and updates one or more databases to incorporate the execution or processing results. In some embodiments, the method allows speeding up the applications without major rewrite without a need for design partition, and without memory penalty. | 05-06-2010 |
20100115479 | Method for generating pattern, method for manufacturing semiconductor device, semiconductor device, and computer program - A method for generating a pattern includes reading out an interconnect layout and a hole layout, the interconnect layout prescribing interconnect patterns, the hole layout prescribing hole patterns configured to connect to the interconnect patterns; extracting one of the hole patterns to be connected within the same interconnect layer level to one of the interconnect patterns in a pattern processing area; extracting a first processing area including the extracted hole pattern; calculating a first pattern density of the interconnect patterns included in the first processing area; and generating first additional patterns in the first processing area based on the first pattern density. | 05-06-2010 |
20100122222 | System and Method for Three-Dimensional Variational Capacitance Calculation - Capacitance extraction techniques are provided. In one aspect, a method for analyzing variational coupling capacitance between conductors in an integrated circuit design is provided. The method comprises the following steps. Coupling capacitance is computed between conductors of interest from the design using a set of floating random walk paths. One or more of the conductors are perturbed. Any of the floating random walk paths affected by the perturbation are modified. The coupling capacitance between the conductors of interest is recomputed to include the modified floating random walk paths. | 05-13-2010 |
20100122223 | Techniques for Computing Capacitances in a Medium With Three-Dimensional Conformal Dielectrics - Techniques for capacitance extraction from an integrated circuit design are provided. In one aspect, a method for determining coupling capacitance between conductors within an integrated circuit design is provided comprising the following steps. A three-dimensional representation of the integrated circuit design is generated based on three-dimensional technology and three-dimensional geometric input about the integrated circuit. Conductors of interest are selected from the design. Three-dimensional coupling capacitance between the selected conductors is determined. Further, a first and a second conductor can be selected from the conductors of interest. A Gaussian surface can be created around the first conductor. A random walk path can be created starting at a randomly selected point on the Gaussian surface and terminating on the second conductor. The random walk path can be used to compute the three-dimensional coupling capacitance between the first and second conductors, which can be separated from one another by multilayered dielectric media. | 05-13-2010 |
20100122224 | METHOD AND APPARATUS FOR DESIGNING AN INTEGRATED CIRCUIT - Method and apparatus for designing an integrated circuit by providing an IC layout design. Adding one or more assist features to the IC layout design. Identifying which of the one or more added assist features in the IC layout design will cause one or more defects in the resultant wafer die manufactured from the IC layout design. Amending the one or more identified assist features. | 05-13-2010 |
20100122225 | PATTERN SELECTION FOR LITHOGRAPHIC MODEL CALIBRATION - The present invention relates generally to methods and apparatuses for test pattern selection for computational lithography model calibration. According to some aspects, the pattern selection algorithms of the present invention can be applied to any existing pool of candidate test patterns. According to some aspects, the present invention automatically selects those test patterns that are most effective in determining the optimal model parameter values from an existing pool of candidate test patterns, as opposed to designing optimal patterns. According to additional aspects, the selected set of test patterns according to the invention is able to excite all the known physics and chemistry in the model formulation, making sure that the wafer data for the test patterns can drive the model calibration to the optimal parameter values that realize the upper bound of prediction accuracy imposed by the model formulation. | 05-13-2010 |
20100131907 | APPARATUS, METHOD AND COMPUTER-READABLE CODE FOR AUTOMATED DESIGN OF PHYSICAL STRUCTURES OF INTEGRATED CIRCUITS - Apparatus, methods, and computer readable code for computing parameters related to layout schemes of integrated circuits are disclosed herein. In some embodiments, an actual layout scheme is computed, for example, for a netlist. In some embodiments, one o or more layout schemes are scored based on, for example, susceptibility to failure and/or yield in manufacturing. | 05-27-2010 |
20100131908 | SUB-CIRCUIT PATTERN RECOGNITION IN INTEGRATED CIRCUIT DESIGN - A method and system for sub-circuit pattern recognition in integrated circuit design is disclosed. In one embodiment, a method for recognizing a pattern circuit in a target circuit, includes encoding the pattern circuit and the target circuit by processing a first netlist of the pattern circuit and a second netlist of the target circuit, generating a cross-linked data structure based on attributes and connectivity information of at least two devices and at least one net from the first netlist, and identifying an instance of the pattern circuit in the target circuit based on an associative mapping between the pattern circuit and a sub-circuit of the target circuit using a device integer array and a net integer array. Each of the first netlist and the second netlist is based on the at least two devices and the at least one net connecting the at least two devices. | 05-27-2010 |
20100138799 | ANALYSIS APPARATUS - An analysis apparatus for a printed circuit board includes a converting portion that rewrites physical property data of a wiring layer in contact with a mounting surface having the part corresponding to an extracted electronic part data to a value based on the physical property data of an electronic part, and converts the physical property data of a region having the electronic part corresponding to the electronic part data extracted by the extracting portion to the physical property data of an insulating layer. | 06-03-2010 |
20100169849 | Extracting Consistent Compact Model Parameters for Related Devices - A method, apparatus and program product are provided for extracting parameters for compact models for semiconductor devices. A first set of parameters associated with first and second semiconductor devices is defined and has the same value for all devices. A second set of parameters associated with the semiconductor devices is defined having values that differ among the devices. Data is measured from the semiconductor devices related to the first and second set of parameters. A mathematical relationship is established between the measured data, and the values of the second set of parameters are adjusted to fit the established mathematical relationship. The mathematical relationship may also be a correlation of the measured data from the first semiconductor device with the measured data from the second semiconductor device creating a data set for parameter extraction. Parameters may then be extracted from the data set related to the first and second semiconductor devices. | 07-01-2010 |
20100169850 | ANALYZER AND METHODS FOR ARCHITECTURALLY INDEPENDENT NOISE SENSITIVITY ANALYSIS OF INTEGRATED CIRCUITS HAVING A MEMORY STORAGE DEVICE - Method of analyzing noise sensitivity of integrated circuits having at least one memory storage device and a noise sensitivity analyzer. In one embodiment, the noise sensitivity analyzer includes: (1) a circuit reservoir configured to receive and store a model of a circuit having at least one memory storage device to be analyzed, (2) a circuit parser configured to identify nodes of the model and (3) a circuit evaluator configured to apply a large test current to each of the nodes for multiple circuit states of the at least one memory storage device and determine which of the nodes are sensitive nodes. | 07-01-2010 |
20100169851 | SUPPORT METHOD AND DESIGN SUPPORT APPARATUS - A design support method for causing a computer using layout data for providing a layout in which macro cells are arranged and in which power supply wirings are formed at certain intervals in each wiring layer to execute, the method including: extracting a set of adjacent macro cells from the layout data; specifying a region located between macro cells that constitute the set of adjacent macro cells extracted in the extracting step from among row regions included in the layout represented by the layout data; detecting a power supply wiring of a specific wiring layer in a projection area located above the region specified in the specifying step, the specific wiring layer being higher than a bottom layer of the layout represented by the layout data; and outputting a region where no power supply wiring of the specific wiring layer is detected in the detecting step. | 07-01-2010 |
20100169852 | SYSTEM AND METHOD FOR DETECTING ONE OR MORE WINDING PATHS FOR PATTERNS ON A RETICLE FOR THE MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUITS - A system and method for detecting one or more winding paths for patterns on a reticle for the manufacture of semiconductor integrated circuits. A method for detecting invalid winding path in a layout design. The method includes the step of obtaining a first winding path parameter and a second winding path parameter. The method includes defining a first plurality of reticle patterns in accordance with the first winding path parameter and the second winding path parameter. The first winding path parameter has a first value. The first plurality of reticle patterns is associated with the least one winding path. The method additionally includes defining a second plurality of reticle patterns in accordance with the second winding path parameter and the second winding path parameter. The first winding path parameter has a second value. The second plurality of reticle patterns is associated with the at least one winding path. Moreover, the method includes comparing the first plurality of reticle patterns against the second plurality of reticle patterns. | 07-01-2010 |
20100192112 | DIAGNOSTIC APPARATUS FOR SEMICONDUCTOR DEVICE, DIAGNOSTIC METHOD FOR SEMICONDUCTOR DEVICE, AND MEDIUM STORING DIAGNOSTIC PROGRAM FOR SEMICONDUCTOR DEVICE - A diagnostic apparatus for semiconductor device includes a fault cell list generation unit configured to extract fault cell candidates corresponding to light emission position information, to generate a fault cell list on the basis of the light emission image information, and to generate a transistor circuit network list showing connection relations of the transistors and a diagnostic pattern, a light emission point dictionary generation unit configured to execute simulation concerning a substrate current of a transistor and to generate a light emission point dictionary comprising a substrate current of the transistor, a fault circuit network extraction unit configured to extract a second fault circuit network candidate from among the first fault circuit network candidates, and an output unit configured to output the second fault circuit network candidate. | 07-29-2010 |
20100199238 | Systematic Method for Variable Layout Shrink - A method for integrated circuit design includes providing a layout of an integrated circuit; determining key parameters of the integrated circuit; determining target values of the key parameters; and performing a first shrinkage of the layout using a first shrink percentage to generate a shrunk layout. The shrunk layout is evaluated by generating values of the key parameters from the shrunk layout. A portion of the values of the key parameters failing to meet respective ones of the target values is found. Guidelines for tuning manufacturing processes of the shrunk layout are provided, so that the portion of the values of the key parameters can meet the respective ones of the target values. | 08-05-2010 |
20100199239 | SIMULATION METHOD AND SIMULATION PROGRAM - There is a need for keeping the amount of data to be saved and a simulation process time almost constant irrespectively of a hierarchical level of a hierarchical circuit to be simulated. This simulation method includes a first process and a second process. The first process saves result data obtained from simulating an interface node between higher-level and lower-level hierarchies in accordance with a result of simulation using hierarchical circuit data hierarchized for multiple hierarchies. The second process uses result data saved by the first process to reproduce internal node data not saved by the first process. Result data for the interface node between hierarchies indirectly determines a value for the internal node. Result data to be saved is data concerning the interface node between hierarchies. The amount of saved data and the time needed for the second process are independent of a hierarchical level or a higher-level or lower-level hierarchy. | 08-05-2010 |
20100199240 | Parallel Electronic Design Automation: Shared Simultaneous Editing - A method to simultaneously allow multiple users to edit in shared areas of a master design includes displaying the master design, allowing a first user to edit in a shared area of the design, while simultaneously allowing a second user to edit in a shared area of the design while preserving the integrity of the design. | 08-05-2010 |
20100218146 | SYNTHESIS USING MULTIPLE SYNTHESIS ENGINE CONFIGURATIONS - Disclosed herein are representative embodiments of methods, systems, and apparatus for performing synthesis. For example, in one exemplary method disclosed herein, a high-level description of a complete circuit design is partitioned into a plurality of sections. Two or more synthesis engine configurations are selected for a respective one of the sections. The respective one of the sections is synthesized using the two or more selected synthesis engine configurations, thereby generating two or more gate-level descriptions. A gate-level description of the complete circuit design is generated that includes at least a portion of one of the gate-level descriptions. Computer-readable media storing instructions for causing a computer to perform any of the disclosed methods are also disclosed herein. | 08-26-2010 |
20100218147 | CIRCUIT SPECIFICATION DESCRIPTION VISUALIZING DEVICE, CIRCUIT SPECIFICATION DESCRIPTION VISUALIZING METHOD AND STORAGE MEDIUM - A design analyzing device includes a circuit specification description analyzing section configured to create structure data about an assertion description, a pass pattern creating section configured to create data about a plurality of pass patterns for which the assertion description passes from the structure data, a matching waveform calculating section configured to create waveform data for each signal in a circuit defined by the assertion description and correlation data that indicates a correlation between the waveform of each signal and a partial expression in the assertion description based on data of each of the plurality of pass patterns, and a display data outputting section configured to output display data about a diagram showing the correlation between each partial expression and the waveform of each signal for each pass pattern. | 08-26-2010 |
20100229133 | Property-Based Classification In Electronic Design Automation - One or more properties can be associated with a design object in a microdevice design. These properties then can be used to classify relationships in a circuit design, such as a layout circuit design. In some implementations, the various relationships can be classified based upon the similarity or dissimilarity of the associated property values. | 09-09-2010 |
20100242000 | USING LAYOUT ENUMERATION TO FACILITATE INTEGRATED CIRCUIT DEVELOPMENT - A method for using layout enumeration to facilitate integrated circuit development includes defining an initial set of design ground rules represented in a notation compatible with a coarse placement grid, for a given layer(s) of an integrated circuit device; defining an initial region of interest for the integrated circuit device; enumerating, according to the initial set of design ground rules, each legal design layout for a given layer of the integrated circuit device in the initial region of interest; running a manufacturing simulation of the enumerated legal design layout data and, responsive to determining one or more failing layouts resulting therefrom, further determining whether the failing layouts may be eliminated by changes in technology parameters and/or updated ground rules. Upon eliminating the one or more failing layouts for the initial region of interest, expanding the initial region of interest and repeating the enumerating, manufacturing simulation, and triage assessment. | 09-23-2010 |
20100242001 | Parameter Drift Prediction - A set of parameter drifts is recorded over a period of time for each of a series of stress tests on a system at various stress levels. Each set of the recorded parameter drifts is plotted as parameter drift versus time. The plots are then time shifted in relation to a reference plot to form a single parameter drift plot. A non-linear equation is fitted to the single parameter drift plot and then used to predict parameter drift over the life of the system. | 09-23-2010 |
20100242002 | Method and apparatus for analyzing structure of complex material layer, and storage medium storing program for causing a computer to execute thereof method - A structure analysis apparatus ( | 09-23-2010 |
20100251191 | EXTRACTING HIGH FREQUENCY IMPEDANCE IN A CIRCUIT DESIGN USING AN ELECTRONIC DESIGN AUTOMATION TOOL - Exemplary impedance extraction methods, systems, and apparatus are described herein. In one exemplary embodiment, for instance, a signal-wire segment of a circuit layout is selected. A predetermined number of return paths are identified for the selected signal-wire segment. The selected signal-wire segment and the identified return paths are further segmented into a plurality of bundles, which comprise signal-wire subsegments and one or more associated return-path subsegments that are parallel to and have the same length as the signal-wire subsegments. Loop inductance values and loop resistance values are determined and stored for the signal-wire subsegments in the bundles for at least one frequency of operation. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing data or information created or modified using any of the disclosed techniques are also disclosed. | 09-30-2010 |
20100269073 | Proprietary circuit layout identification - A method is provided for identifying use of a proprietary circuit layout. A representation of a layout of a circuit is input and the locations of a set of predetermined physical features of the circuit are identified. This set of locations is then compared with a previously generated characteristic pattern file, the characteristic pattern file comprising a representation of relative locations of a set of these predetermined physical features in the proprietary circuit layout. If the set of locations matches the relative locations of the characteristic pattern file, then an output is generated indicating that use of the proprietary circuit design has been found. | 10-21-2010 |
20100269074 | Predictive Power Management Semiconductor Design Tool and Methods for Using Such - Various embodiments of the present invention provide systems and methods for improved semiconductor design. For example, various embodiments of the present invention provide methods for semiconductor design that include receiving a semiconductor design with at least a first function circuit and a second function circuit; simulating the semiconductor design using a first instruction and a second instruction; determining a power state transition between the first instruction and the second instruction; and augmenting the semiconductor design to implement the determined power state transition. Simulating the semiconductor design using a first instruction and a second instruction identifies an indication of a first subset of the first function circuit and the second function circuit used in executing the first instruction and a second subset of the first function circuit and the second function circuit used in executing the second instruction. The power state transition accommodates at least one power attribute selected from a group consisting of: an inrush current value, and an overall power dissipation value. | 10-21-2010 |
20100269075 | METHOD AND SYSTEM FOR SELECTIVE STRESS ENABLEMENT IN SIMULATION MODELING - A method and system for modeling an integrated circuit. The method includes converting a representation of the integrated circuit into design shapes of design levels of a design of the integrated circuit; adding control shapes to the design, the control shapes not defining any physical part of the integrated circuit; extracting layout-dependent stress parameters of the devices from the design levels of the design based on the control shapes and the design shapes; converting the layout-dependent stress parameters to stress parameters using a stress algorithm; generating stressed device parameters from the stress parameters using a compact model; and simulating performance of the integrated circuit using the stressed device parameters in a simulation model of the integrated circuit design. | 10-21-2010 |
20100269076 | TEST PATTERN GENERATION APPARATUS, TEST PATTERN GENERATION METHOD, AND MEDIUM STORING TEST PATTERN GENERATION PROGRAM - A test pattern generation apparatus includes an activation rate setting unit configured to set an activation rate of a cell, a test pattern generator configured to generate a test pattern based on the activation rate set by the activation rate setting unit, a supply voltage calculator configured to calculate a supply voltage of a semiconductor integrated circuit using the test pattern generated by the test pattern generator, and an output unit configured to output the test pattern generated by the test pattern generator when the supply voltage calculated by the supply voltage calculator fulfills the target supply voltage. | 10-21-2010 |
20100281442 | TECHNIQUE FOR DETERMINING CIRCUIT INTERDEPENDENCIES - Embodiments of a device (such as a computer system or a circuit tester), a method, and a computer-program product (i.e., software) for use with the device are described. These systems and processes may be used to statistically characterize interdependencies between sub-circuits in an integrated circuit (which are referred to as ‘aggressor-victim relationships’). In particular, statistical relationships between the aggressors and victims are determined from values of a performance metric (such as clock speed) when the integrated circuit fails for a group of state-change difference vectors. Using these statistical relationships, a worst-case sub-group of the state-change difference vectors, such as the worst-case sub-group, is selected. This sub-group can be used to accurately test the integrated circuit. | 11-04-2010 |
20100281443 | Change Point Finding Method and Apparatus - A change point finding method applied to a logic circuit is provided. The method first defines an indication map and performs a functional equivalent check to judge whether the indication map is correct. When a result is confirmative, the method adds a trap to an RTL HDL of the logic circuit, so that a plurality of comparing points are generated in an APR gate level HDL of the logic circuit. Then the method performs a backward functional equivalent check on the APR gate level HDL of the logic circuit to find a change point according to the comparing points. | 11-04-2010 |
20100306719 | Integrated Circuit Cell Library with Cell-Level Process Compensation Technique (PCT) Application and Associated Methods - A layout of cells is generated to satisfy a netlist of an integrated circuit. Cell-level process compensation technique (PCT) processing is performed on a number of levels of one or more cells in the layout to generate a PCT processed version of the one more cells in the layout. An as-fabricated aerial image of each PCT processed cell level is generated to facilitate evaluation of PCT processing adequacy. Cell-level circuit extraction is performed on the PCT processed version of each cell using the generated as-fabricated aerial images. The cell-level PCT processing and cell-level circuit extraction are performed before placing and routing of the layout on a chip. The PCT processed version of the one or more cells and corresponding as-fabricated aerial images are stored in a cell library. | 12-02-2010 |