| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 714820000 | Plural parallel devices of channels | 6 |
| 20100241938 | SYSTEM AND METHOD FOR ACHIEVING IMPROVED ACCURACY FROM EFFICIENT COMPUTER ARCHITECTURES - This invention provides a system and method that can employ a low-instruction-per-second (lower-power), highly parallel processor architecture to perform the low-precision computations. These are aggregated at high-precision by an aggregator. Either a high-precision processor arrangement, or a low-precision processor arrangement, employing soft-ware-based high-precision program instructions performs the less-frequent, generally slower high-precision computations of the aggregated, more-frequent low-precision computations. One final aggregator totals all low-precision computations and another high-precision aggregator totals all high-precision computations. An equal number of low precision computations are used to generate the error value that is subtracted from the low-precision average. A plurality of lower-power processors can be arrayed to provide the low-precision computation function. Alternatively a plurality of SIMD can be used to alternately conduct low-precision computations for a predetermined number of operations and high-precision operations on a fewer number of operations. In an embodiment, aggregation can include summing values within predetermined ranges of orders of magnitude, via an adding tree arrangement, so that significant digits therebetween are preserved. | 09-23-2010 |
| 20110214043 | HIGH INTEGRITY DATA BUS FAULT DETECTION USING MULTIPLE SIGNAL COMPONENTS - Methods and apparatus are provided for verifying the integrity of a signal transmitted across a multiple rail data bus. The method and apparatus provide for independently processing a signal by a first processor and a second processor, the first and second processors being connected in parallel thereby generating a first processed signal and a second processed signal. Each of the processed signals is split into a first component sequence and a second component sequence, the first component sequences being different from the second component sequences. It is then determined that the first component sequences are not identical and that the second component sequences are not identical. If either of the first component sequences is not identical, or if either of the second component sequences is not identical, then an error signal is transmitted to a receiving device via a first or second rail of the bus. | 09-01-2011 |
| 20120023389 | REAL-TIME ERROR DETECTION BY INVERSE PROCESSING - Processors, microprocessors and logical block systems and methods, error detection systems and methods, and integrated circuits are disclosed. In an embodiment, a logic-based computing system includes a first processing core; a second processing core generated from the first processing core and including an inverted logical equivalent of the first processing core such that an output of the second processing core is a complement of an output of the first processing core; and comparator logic coupled to receive the outputs of the first and second processing cores as inputs and provide an error output if the output of the second processing core is not the complement of the output of the first processing core. | 01-26-2012 |
| 714821000 | Transmission facility | 3 |
| 20120030549 | DATA TRANSMISSION DETECTING DEVICE, DATA TRANSMISSION DETECTING METHOD AND ELECTRONIC DEVICE THEREOF - A data transmission detecting device including a detecting module and a detection value calculating module is provided. The detecting module has a plurality of receiving terminals and receives a first data and a second data during a first period. The detecting module calculates a total detection value according to the first data and the second data, and performs an error check comparison by comparing the total detection value with an error check code. When the detecting module again receives the first data during a second period, the detection value calculating module transmits an auxiliary detection value to the detecting module, so that the detecting module calculates a corresponding total detection value according to the auxiliary detection value, and performs the error check comparison by comparing the total detection value with the error check code. The first period and the second period are two successive periods adjacent to each other. | 02-02-2012 |
| 20120240017 | DATA TRANSMITTING DEVICE, DATA RECEIVING DEVICE, DATA TRANSMITTING/RECEIVING DEVICE, AND CONTROLLING METHOD OF DATA TRANSMITTING/RECEIVING DEVICE - In a system, a data receiving device comprises a timing signal generation unit that generates a timing signal used for receiving the divided transmission data in each of the transmission paths, a data receiving unit that receives the divided transmission data transmitted by the data transmitting device for each of the transmission paths by using the timing signal generated by the timing signal generation unit, and an error detection unit that extracts the error detection information from the divided transmission data received for each of the transmission paths by the data receiving unit and detects an error of transmission data included in the divided transmission data by using the extracted error detection information. | 09-20-2012 |
| 20150039979 | METHOD AND APPARATUS FOR CONCEALING ERROR IN COMMUNICATION SYSTEM - A method and an apparatus for concealing an error of an apparatus for receiving an audio frame in a communication system are provided. The includes determining whether the error occurs in a current audio frame that is received from a transmitter, determining whether the audio frame includes a signal that corresponds to a preset specific frequency when the error occurs, setting a gain of the signal that corresponds to the specific frequency to be lower than a preset limit value if the audio frame includes the signal, and concealing the error of the current audio frame based on a previous audio frame of the audio frame in which the error occurs and the gain of the signal that corresponds to the set specific frequency. | 02-05-2015 |
