Entries |
Document | Title | Date |
20080222501 | Analyzing Test Case Failures - Apparatus and method for categorizing test failures are disclosed. In one embodiment, a data set of a current test failure is compared with the data sets of historical test failures to result in a set of correspondence values. The current test failure is categorized with respect to the historical test failures at least in part on the basis of the correspondence values. | 09-11-2008 |
20080222502 | ERROR DETERMINING APPARATUS AND METHOD - An error determining apparatus includes an Error Detection Code (EDC) error detector to detect an EDC error of data read from an optical disk, a continuity error detector to detect a continuity error of a currently decoded address by comparing the currently decoded address and a previously decoded address, and an error determiner to receive information on the previously determined error state and to determine a final error state of the currently decoded address of the optical disk based on the EDC error detected by the EDC error detector, the continuity error detected by the continuity error detector, and the previously determined error state. | 09-11-2008 |
20080229179 | Data access detection - Systems, methods, and computer program products that can be used concurrently or alternatively to detect errors in data as well as to protect access to data are provided. Embodiments enable a coherent data set (CDS) which is a data set guaranteed to be genuine and error-free at run-time. Embodiments provide systems, methods, and computer program programs to create a CDS, identify a CDS, and verify the coherency of a data set purported to be a CDS. Embodiments further enable privileged functions which are functions that can only be accessed by a restricted set of other privileged functions. Embodiments provide systems, methods, and computer program products to create, identify, and protect access to privileged functions. | 09-18-2008 |
20080244371 | METHOD AND DEVICE FOR DATA INTEGRITY CHECKING - The present invention relates to high speed datapaths, sometimes including mixed digital and analog voltage signals. In particular, it relates to error checking strategies for large data volumes, in digital and/or analog domains and to analog signal patterns that accelerate charge loading of micromirrors in an SLM. Particular aspects of the present invention are described in the claims, specification and drawings. | 10-02-2008 |
20080294971 | TRANSPARENT ENVELOPE FOR XML MESSAGES - Transforming portions of a message to a destination via a communication protocol. A message is received. It is detected whether the received message includes an encoded envelope. The encoded envelope includes a stack defining parameters including information for handling the received message in an original format. If the received message includes the encoded envelope, the defined parameters are transformed to coded parameters in a common format. The coded parameters express the same information for handling the received message in the communication protocol. The encoded envelope is encapsulated in the received message, and the received message in the common format is delivered to the destination. If the received message does not include an encoded envelope, coded parameters are generated in the common format for the received message by encoding addressing information from the received message. The received message having the coded parameters in the common format is delivered to the destination. | 11-27-2008 |
20080301538 | Method and Apparatus for Detecting Video Data Errors - The present invention provides a method and apparatus for detecting video data errors, said video data including a plurality of successive frame image data, said method comprising the steps of acquiring the processing sequence information of two frame image data in said video data, said two frame image data being immediately adjacent in the processing sequence, one after the other, determining the processing sequence information difference between two frame image data, comparing said information difference with a reference value and judging, based on said comparison result, whether there is a frame image data miss between said two frame image data. The method and apparatus provided by the invention can, not only judge whether there is a frame image data missing between the two immediate adjacent frames, but also determine the amount of the missing frame image data and performs a restoring and correcting process. | 12-04-2008 |
20080320376 | ERROR DETECTION DEVICE - A data buffer control unit obtains data from a cache according to a command retained in a command queue retaining a command(s) for reading data from the cache, and a magic ID generation circuit generates a magic ID. The data buffer control unit assigns the data obtained from the cache with the magic ID, writes the assigned data to a data buffer, and returns the magic ID to the command queue. When the data buffer control unit receives a read request and the magic ID which is returned to the command queue, it reads the data, which corresponds to the read request, from the command queue and compares the magic ID assigned in the read data and the received magic ID. If the two magic IDs compared by the data buffer control unit are not identical, a packet generator detects an error and reports the error to a host. | 12-25-2008 |
20090006933 | Server Directory Schema Comparator - The embodiments generally relate to systems and methods for determining changes in a directory schema. In embodiments, directory changes are recorded in a change log. The change log may have one or more entries. A determination is made as to which change log entries should be retrieved. Once retrieved, the directory schema changes are determined. In embodiments, the directory changes are then interpreted for presentation to a user. | 01-01-2009 |
20090006934 | Triggering diagnostic operations within a data processing apparatus - A data processing apparatus | 01-01-2009 |
20090006935 | Methods, Systems, and Products for Verifying Integrity of Web-Server Served Content - Methods, systems, and products are disclosed for verifying the integrity of web server content. A request for a Uniform Resource Locator is received, with the request originating from a referring Uniform Resource Locator. A response to the request is communicated. The requested Uniform Resource Locator is stored along with the referring Uniform Resource Locator, a status code associated with the response, and a file size associated with the response. Logical rules are applied and a report is generated which pinpoints the URLs in error. | 01-01-2009 |
20090172507 | Information Processing System - According to one embodiment, an information processing system is coupled to a number of sensors for receiving information generated by the sensors. The information processing system generates records from the received information and binds the records in a multi-dimensional structure including a temporal dimension and another dimension including other records that share a common criterion. The information processing system compares a particular record against other records to detect an abnormality of the particular record. | 07-02-2009 |
20090177954 | CODE ERROR DETECTING DEVICE, WIRELESS SYSTEM AND CODE ERROR DETECTING METHOD - A code error detecting device that can more precisely detect a code error due to a delayed wave is disclosed. The code error detecting device includes a receiving antenna ( | 07-09-2009 |
20090193324 | IMAGE DATA TEST UNIT, IMAGE APPARATUS HAVING THE SAME, AND METHOD OF TESTING IMAGE DATA USING THE SAME - An image data test unit includes a data acquisition unit configured to acquire image data having individual frames, an image data temporary storage unit configured to receive the acquired image data from the data acquisition unit to store a certain amount of the image data, and a test calculation unit configured to sequentially receive the image data from the image data temporary storage unit to store a certain amount of the image data, and compare the stored image data with pre-set test elements. In addition, an image apparatus having the image data test unit and a method of testing image data using the image data test unit are also provided. | 07-30-2009 |
20090210777 | Method and Device for Comparing Data in a Computer System Having at Least Two Execution Units - A method for comparing data in a computer system having at least two execution units, the comparison of the data taking place in a comparison unit and each execution unit processing input data and generating output data, wherein one execution unit specifies to the comparison unit that the next piece of output data is to be compared to a piece of output data of the at least second execution unit, and thereupon a comparison of the at least two output data takes place. | 08-20-2009 |
20090249174 | Fault Tolerant Self-Correcting Non-Glitching Low Power Circuit for Static and Dynamic Data Storage - In a computer system in which personalization data for an ASIC is stored in latches, this data is susceptible to soft errors. Many computer systems require high levels of error detection, error correction, fault isolation, fault tolerance, and self-healing. In order to complete an ASIC design and release it to a foundry, it must first be verified that the design meets the frequency requirements of its specification. A fault tolerant, self-correcting, non-glitching, low power circuit is described which meets all the requirements for reliability, while also eliminating any requirement to add area or power to the ASIC in order to meet the frequency specification for personalization latches. By using the circuits as a repeatable structure, the verification of the self-healing property is simplified relative to a collection of Error Correction Code usages of various bit widths. | 10-01-2009 |
20090254798 | METHOD AND DEVICE FOR PROCESSING A DATA STREAM - A method of processing a stream of coded data before decoding comprises a step of detecting missing or erroneous data in the stream of coded data. | 10-08-2009 |
20090287986 | MANAGING STORAGE OF INDIVIDUALLY ACCESSIBLE DATA UNITS - A method includes determining a length of a file and storing the length of the file in a first memory location. An endpoint of a last complete record within the file is determined and the endpoint is stored in a second memory location. The length of the file stored in the first memory location is compared to a current length of the file, and a data structure associated with the file is updated beginning at the endpoint if the current length of the file exceeds the length of the file stored in the first memory location. | 11-19-2009 |
20090292979 | Methods and Apparatus for Monitoring Abnormalities in Data Stream - A technique for monitoring a primary data stream comprising a plurality of secondary data streams for abnormalities is provided. A deviation value for each of two or more of the plurality of secondary data streams is determined. The two or more deviation values of the two or more secondary data streams are combined to form a combined deviation value. An abnormality signal is generated based at least in part on the combined deviation value. | 11-26-2009 |
20100005376 | METHOD AND APPARATUS FOR REPAIRING HIGH CAPACITY/HIGH BANDWIDTH MEMORY DEVICES - Memory systems, systems and methods are disclosed that may include a plurality of stacked memory device dice and a logic die connected to each other by through silicon vias. One such logic die includes an error code generator that generates error checking codes corresponding to write data. The error checking codes are stored in the memory device dice and are subsequently compared to error checking codes generated from data subsequently read from the memory device dice. In the event the codes do not match, an error signal can be generated. The logic die may contain a controller that records the address from which the data was read. The controller or memory access device may redirect accesses to the memory device dice at the recorded addresses. The controller can also examine addresses or data resulting in the error signals being generated to identify faults in the through silicon vias. | 01-07-2010 |
20100058156 | FTP DEVICE AND METHOD FOR MERCHANT DATA PROCESSING - A method begins by receiving at least a portion of a merchant master file. The method continues, for a merchant data file, by determining whether a corresponding merchant profile record exists within a merchant profile database. The method continues, when the corresponding merchant profile record exists in the merchant profile database, by comparing the merchant data file with the corresponding merchant profile record. The method continues, when an inconsistency exists between the corresponding merchant profile record and the merchant data file, by determining status of the merchant data file with respect to the at least a portion of the merchant master file. The method continues, when the status of the merchant data file is a first status level, by generating an inconsistency message that identifies the inconsistency. | 03-04-2010 |
20100058157 | System And Method For Analyzing A Plurality Of Information Systems - A system for analyzing an information system comprising a computer readable medium; and a set of computer readable instructions embodied in the computer readable medium for transmitting an audit application to a first store controller so that the audit application can generate audit data representing audit information from the first store controller, receiving audit data from the first store controller, transmitting an audit application to a second store controller so that the audit application can generate audit data representing audit information from the second store controller, receiving audit data from the second store controller, determining a comparison basis according to the audit information from the first store controller, comparing the audit date from the second store controller to the comparison basis, generating a set of comparison data resulting from the comparison, displaying items from the second store controller that are different from the comparison basis. | 03-04-2010 |
20100058158 | METHOD AND SYSTEM FOR DETECTING GAPS IN A DATA STREAM - Systems and methods are described which allow the detection of gaps in a set of data. These systems and methods may include defining streams of data from a network topology, associating incoming data with one or more of these streams, and processing these streams. A gap may be detected by comparing the times of events in the stream. If a gap is detected remedial action may be taken, and processing of the streams temporarily halted. Processing of the streams may continue when data for a certain stream is received, or after the lapse of a certain period of time. | 03-04-2010 |
20100100799 | FAULT DETECTION APPARATUS, FAULT DETECTION METHOD, AND FAULT DETECTION PROGRAM - A comparison unit compares polarities of a plurality of redundant input signals. A comparison-result storing unit stores a comparison result of the comparison unit for each predetermined sampling cycle. A judgment unit judges whether the redundant input signals are normal using a plurality of comparison results for a predetermined number of samplings in a time-series order from a latest comparison result among a plurality of comparison results stored in the comparison-result storing unit. | 04-22-2010 |
20100107043 | NETWORK DEVICE AND METHOD OF CONTROLLING THE SAME - A network device and a method for controlling the same. The device and method each performed the operations of transforming an input signal so as to allow the input signal to be divided according to frequency bands and resolutions, comparing the transformed input signal with abnormal signal information stored in an abnormal signal database (DB), and determining whether the input signal is a normal signal. When the input signal is a normal signal, the network and method each perform the operation of delivering the transformed input signal to a codec. | 04-29-2010 |
20100138730 | FAULT DETECTION USING EMBEDDED WATERMARKS - Detection of faults in a transmitted signal stream occurs by recovering, from the information stream, a water mark embedded in the stream prior to transmission. The embedded watermark has data characteristic of stream quality. Thereafter, the at least one watermark property is analyzed to detect faults in the received information stream. | 06-03-2010 |
20100185927 | Microprocessor System for Controlling at Least Partly Safety-Critical Processes - The invention relates to a microprocessor system ( | 07-22-2010 |
20100241937 | TRANSMISSION DEVICE ESTIMATION METHOD AND ESTIMATING UNIT - An estimating unit includes: an error detecting unit which detects an error among a plurality of frames received from an interface unit of a transmission device; a request sending unit which produces a first frame including a data collection request for requesting data collection upon the error detecting unit detecting the error, and which sends the first frame to the interface unit; an extracting unit which extracts, from the plurality of frames received from the interface unit, a second frame including the error detected by the error detecting unit and a third frame including a reply of the interface unit to the data collection request; and a saving unit in which the second frame extracted by the extracting unit is saved. | 09-23-2010 |
20100275108 | Error Detection in Critical Repeating Data in a Wireless Sensor System - Provided are methods, systems, and apparatus for error detection of bits of a data packet received at a receiver unit by detecting corrupted data bits. | 10-28-2010 |
20100287457 | APPARATUS FOR APPENDING CYCLIC REDUNDANCY CHECK IN COMMUNICATION SYSTEM - The apparatus for appending CRC to the data or signaling to be transmitted in the communication systems is proposed in present invention. If the length of the CRC-bit sequence is 16, one of the CRC generation polynomials listed in present invention can be adopted. If the length of the CRC bit sequence is 18, one of the CRC generation polynomials listed in present invention can be adopted. If the length of the CRC bit sequence is 20, one of the CRC generation polynomials listed in present invention can be adopted. With the optimized CRC generation polynomials proposed in present invention, mistakes in signaling detection can be effectively reduced so that system spectrum utility can be improved. | 11-11-2010 |
20100318887 | DATA VERIFICATION USING CHECKSUM SIDEFILE - Exemplary method, system, and computer program product embodiments for data verification in a storage system are provided. A read of data is asynchronously submitted to nonvolatile storage media. A read of a first checksum signature is submitted to a solid state, sidefile memory location of a storage controller in the storage subsystem. The first checksum signature is representative of the data previously written to the nonvolatile storage media. A second checksum signature is calculated from the read of the data. The first and second checksum signatures are compared. If a match is not determined, a critical event is reported. | 12-16-2010 |
20100332957 | Arithmetic circuit, arithmetic processing device, and arithmetic processing method - In an arithmetic circuit, every time a numerical value is stored in a register, a partial solution is predicted on the basis of the numerical value, an intermediate value is generated by a predetermined calculation using one or more predicted partial solutions, an extended sign bit is appended to the intermediate value by sign extension, and the intermediate value to which the extended sign bit is appended is stored in the register. In addition, the solution is generated on the basis of the one or more partial solutions. A value of a sign bit constituting the intermediate value stored in the register is compared with a value of the extended sign bit stored in the register, and an error signal is outputted when the value of the sign bit is different from the value of the extended sign bit. | 12-30-2010 |
20110041047 | TEST AND MEASUREMENT INSTRUMENT WITH BIT-ERROR DETECTION - A test and measurement instrument including an input configured to receive a signal and output digitized data; a memory configured to store reference digitized data including a reference sequence; a pattern detector configured to detect the reference sequence in the digitized data and generate a synchronization signal in response; a memory controller configured to cause the memory to output the reference digitized data in response to the synchronization signal; and a comparator configured to compare the reference digitized data output from the memory to the digitized data. | 02-17-2011 |
20110060976 | METHOD AND DEVICE FOR PROCESSING SIGNAL DATA - A method of processing signal data comprises receiving signal data, calculating a first k-th moment from the signal data based on a first number of samples N | 03-10-2011 |
20110072337 | DATA RECEIVING METHOD, ELECTRONIC APPARATUS AND STORAGE SYSTEM HAVING DATA RECEIVING MECHANISM - A data receiving method for an electronic system including a host apparatus and a target apparatus, wherein the host apparatus transmits at least one request to the target apparatus for requesting at least one desired data, and the target apparatus transmits the desired data to the host apparatus according to the request. The data receiving method comprises: (a) generating a statistic value according to a number of the requests; (b) varying the statistic value according to a number of the desired data; and (c) determining whether data received by the host apparatus is the desired data corresponding to the request or not according to the static value, to thereby determine whether the data received by the host apparatus is stored to the host apparatus or not. | 03-24-2011 |
20110126085 | METHOD OF SIGNATURE VERIFICATION - A method of detecting a fault including generating at least one blinded data value based on at least one input value and at least one blinding parameter selected from a plurality of blinding parameters generating a first signature based on said at least one blinded data value; selecting, from a memory storing a plurality of reference signatures, one or more reference signatures and comparing said first signature with said one or more reference signatures in order to detect a fault. | 05-26-2011 |
20110131477 | Systems and Methods for Analyzing and Affecting Subtle Energy - Systems and methods for analyzing and affecting manifestations of subtle energy resonance are provided. A memory array associated with a transducer is read and stored in a memory of an analysis device. The memory array is then exposed to an energy environment which causes changes to the memory array. A second reading of the memory array indicates the changes to the memory array as compared to the first reading. The detected changes are analyzed and used to generate an energy signature and a report concerning any combination of the changes, the rate of changes, and the generated energy signature. The energy data concerns subtle energy in a designated energy environment which may include one or more animate or inanimate crystalline resonators. Tuning of a generator allows for manipulation of cell resonance, which may be used for research or in order to produce a desired resonance. | 06-02-2011 |
20110138263 | APPARATUS AND METHOD FOR AUTOMATIC CONFIGURATION OF LIGHTING CONTROLLERS - A lighting system controller is provided that is configured to automatically synchronize a lighting controller with a centralized configuration. In a particular example, this automatic synchronization activity may include modifying the configuration of the lighting controller to match configuration information stored locally on the lighting system controller. Conversely, this automatic synchronization activity may include modifying the locally stored configuration information to match the current configuration of the lighting controller. In some examples, the lighting system controller is configured to use cyclic redundancy checks when determining whether to modify configuration information. | 06-09-2011 |
20110138264 | Verification Of Data Stream Computations Using Third-Party-Supplied Annotations - A third party that performs data stream computation is requested to return not only the solution to the computation, but also “annotations” to the original data stream. The annotations are then used by the data owner (in actuality, a “verifier” associated with the data owner) to check the results of the third party's computations. As implemented, the verifier combines the annotations with the original data, performs some computations, and is then assured of the correctness of the provided solution. The cost of verification is significantly lower to the data owner than the cost of fully processing the data “in house”. | 06-09-2011 |
20110145685 | TRANSPARENT ENVELOPE FOR XML MESSAGES - Transforming portions of a message to a destination via a communication protocol. A message is received. It is detected whether the received message includes an encoded envelope. The encoded envelope includes a stack defining parameters including information for handling the received message in an original format. If the received message includes the encoded envelope, the defined parameters are transformed to coded parameters in a common format. The coded parameters express the same information for handling the received message in the communication protocol. The encoded envelope is encapsulated in the received message, and the received message in the common format is delivered to the destination. If the received message does not include an encoded envelope, coded parameters are generated in the common format for the received message by encoding addressing information from the received message. The received message having the coded parameters in the common format is delivered to the destination. | 06-16-2011 |
20110154171 | Blanking Primitives Masking Circuit - A blanking primitive masking circuit has a detection and handling circuit that receives data containing blanking primitives. The detection and handling circuit generates a dynamic blanking signal when blanking primitives are detected. The received data is delayed and provided to a pattern detector that generates a synchronization signal provided to a memory and a phase sync signal provided to the detection and handling circuit and to a comparator. The comparator receives reference data from the memory, the delayed data, and the dynamic blanking signal. The comparator compares the reference data with the delayed data and generates bit error outputs from mismatched reference data bits and delayed data bits when the dynamic blanking signal from the detection and handling circuit is absent and suppressing the generation bit error outputs when the blanking primitive are in the delay data and the dynamic blanking signal is present. | 06-23-2011 |
20110154172 | APPARATUS AND METHOD FOR ASSESSING IMAGE QUALITY IN REAL-TIME - An apparatus and method for assessing image quality in real-time in consideration of both a coding error generated in an image processing process and a packet error generated in an image transmission process are provided. The apparatus for assessing image quality in real-time includes: an image quality measurement unit measuring image degradation generated in processing an image; a packet degradation detection unit detecting a packet error generated in transmitting the image; and final outcome drawing unit finally assessing the quality of the image in consideration of both a degradation degree of the image measured by the image quality measurement unit and the packet error measured by the packet degradation detection unit. | 06-23-2011 |
20110185268 | Storage apparatus and data verification methd in storage apparatus - When a data write request to a disk drive | 07-28-2011 |
20110197113 | ABNORMALITY DETECTION SYSTEM, ABNORMALITY DETECTION METHOD, AND ABNORMALITY DETECTION PROGRAM STORAGE MEDIUM - Even if data includes a defect or an outlier in features thereof, the influence of the defect or the outlier of the features is suppressed to perform a highly precise abnormality detection, and data including high-dimensional features is processable to accomplish the highly stable detection of an abnormality. | 08-11-2011 |
20110219289 | COMPARING VALUES OF A BOUNDED DOMAIN - Methods, systems, and computer-readable media to compare values of a bounded domain are disclosed. A particular method includes, for each value in a bounded domain, determining a corresponding set of allowable errors associated with the value. The sets of allowable errors are stored at a memory. The method includes determining a comparison score between a first value of the bounded domain and a second value of the bounded domain based on a comparison of a first set of allowable errors corresponding to the first value and a second set of allowable errors corresponding to the second value. | 09-08-2011 |
20110271170 | DETERMINING PAGE FAULTING BEHAVIOR OF A MEMORY OPERATION - Embodiments of the invention relate to page faulting of memory operations in a subject code block. An aspect of the invention concerns an apparatus comprising a component for identifying a first object node having a first dependency path and second object node having a second dependency path, and a component for calculating a numerical difference between a first addressing value and a second addressing value, where the first and second addressing values are respectively associated with the first and second dependency paths. The apparatus may include a dependency generator for ordering a subject order list of the subject code block in an object dependency non-page-faulting order when the numerical difference is equal to or less than an assigned memory page size. | 11-03-2011 |
20110314360 | GLONASS DATA BIT EDGE DETECTION - Apparatus and methods for detecting data bit edge in a meander encoded information bit from a satellite positioning system (SPS) such as GLONASS (Global Navigation Satellite System) are discussed. A method comprises receiving meander encoded data samples from a meander encoded information bit. The method includes computing a set of accumulated values for a corresponding set of hypotheses, each of the hypotheses corresponding to a hypothesized bit edge phase. The process of computing an accumulated value of the set of accumulated values includes providing a toggled subset of the meander encoded data samples, and integrating the toggled subset of the meander encoded data samples with an un-toggled subset of the meander encoded data samples to produce the accumulated value. The method also includes selecting a best hypothesis from the set of hypotheses corresponding to a maximum value of the set of accumulated values, wherein the best hypothesis represents the data bit edge. | 12-22-2011 |
20120151307 | CHECKSUM VERIFICATION ACCELERATOR - Disclosed is a method and system for validating a data packet by a network processor supporting a first network protocol and a second network protocol and utilizing shared hardware. The network processor receives a data packet; identifies a network packet protocol for the data packet; and processes the data packet according to the network packet protocol comprising: updating a first register with a first partial packet length specific to the first network protocol; updating a second register with a second partial packet length specific to the second network protocol; and updating a third register with a first checksum computed from fields independent of the network protocol. The system produces a second checksum utilizing a function that combines values from the first register, the second register, and the third register. The system validates the data packet by comparing the data packet checksum to the second checksum. | 06-14-2012 |
20120159290 | VALIDATION ANALYSIS OF HUMAN TARGET - Technology for testing a target recognition, analysis, and tracking system is provided. A searchable repository of recorded and synthesized depth clips and associated ground truth tracking data is provided. Data in the repository is used by one or more processing devices each including at least one instance of a target recognition, analysis, and tracking pipeline to analyze performance of the tracking pipeline. An analysis engine provides at least a subset of the searchable set responsive to a request to test the pipeline and receives tracking data output from the pipeline on the at least subset of the searchable set. A report generator outputs an analysis of the tracking data relative to the ground truth in the at least subset to provide an output of the error relative to the ground truth. | 06-21-2012 |
20120159291 | METHOD FOR DETECTING RETURN LINK PACKET ERROR IN HUB WHICH COMMUNICATES WITH SATELLITE TERMINAL AND APPARATUS THEREOF - A technology in which it is detected whether errors occur in a packet received from a satellite terminal device, a modulation and coding (MODCOD) value is calculated according to a result of the detection and the calculated MODCOD value is transmitted to the satellite terminal device, so that pack loss is reduced based on the yield of actual traffic when the satellite terminal device transmits a return link packet. A plurality of return link packets are received from the satellite terminal device. An occurrence of a packet error is detected by generating a first return link packet by sequentially assembling the plurality of return link packets and performing a comparison analysis by comparing the first return link packet with a second return link packet that is newly received. | 06-21-2012 |
20120166919 | DATA PROCESSING DEVICE AND METHOD FOR CHECKING PARAMETER VALUES OF THE DATA PROCESSING DEVICE - A data processing device acquires a first parameter value of a hardware component, and calculates a first prediction value of the first parameter using a prediction algorithm. If a difference of the first prediction value and the first parameter falls within a deviation range, the first parameter value is determined as a real value and is stored. Otherwise, the device acquires a second parameter value of the hardware component that follows the first parameter value, and calculates a second prediction value of the second parameter value. If a difference between the second prediction value and the second parameter value falls with a second deviation range, the first parameter value is determined as a real value and is stored. Otherwise, the first parameter value is determined as a false value and is abandoned. | 06-28-2012 |
20120266055 | Systems and Methods for Short Media Defect Detection - Various embodiments of the present invention provide systems and methods for media defect detection. As an example, a data processing circuit is disclosed that includes a defect detector circuit and a comparator circuit. The defect detector circuit is operable to calculate a correlation value combining at least three of a data input derived from a medium, a detector extrinsic output, a detector intrinsic output and a decoder output. The comparator circuit is operable to compare the correlation value to a threshold value and to assert a media defect indicator when the correlation value is less than the threshold value. | 10-18-2012 |
20130047058 | Systems and Methods for Qualitative Media Defect Determination - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a media defect detector circuit. The media defect detector circuit is operable to compare a data input derived from a medium against at least a first defect level to yield a first level output, and a second defect level to yield a second level output; and provide a combination of the first level output and the second level output as a defect quality output. A value of the defect quality output corresponds to a likelihood of a defect of the medium. | 02-21-2013 |
20130091408 | ENHANCING ACCURACY OF SERVICE LEVEL AGREEMENTS IN ETHERNET NETWORKS - A method of determining frame loss between two management points (C, D) in an Ethernet network, in which the said management points each transmit frames to each other and each of the said two management points transmits in regular intervals to the other measurement messages which contain current counts of frames transmitted and received by the respective transmitting management point. At least one of the said two management points responds to a received management message to compute from counts of actual packets transmitted and/or received by a given one of the management points the frame loss at said given management point. At least one of the management points computes the said frame loss only once in a measurement interval which consists of a multiplicity of said regular intervals and employs in the computation the counts indicated by the measurement message most recently received by said one of the management points. | 04-11-2013 |
20130159821 | Method, System and Device for Monitoring Error Code of Common Public Radio Interface (CPRI) link - A method, system and device for monitoring error code of CPRI link are disclosed. The method comprises: a CPRI link data transmitting end forming data to be transmitted into frames, outputting data, and calculating to obtain FCS of each frame; the CPRI link data transmitting end adds FCS of a former frame into FCS field of a current frame when forming frame; a CPRI link data receiving end splitting frame of received frame data to obtain FCS of the former frame carried in the current frame, calculating received frame data to obtain FCS of the current frame, caching FCS of the current frame, comparing FCS of the former frame which is carried in the current frame with cached FCS of the former frame, and judging CPRI link has error codes if the comparison result is inconsistent. Error code condition of CPRI link can be monitored without influencing normal service operation. | 06-20-2013 |
20130212452 | Apparatus and Method for Comparing Pairs of Binary Words - An apparatus for comparing pairs of binary words includes an intermediate value determiner and an error detector. The intermediate value determiner determines an intermediate binary word so that the intermediate binary word is equal to a reference binary word for a first pair of equal or inverted binary words, so that the intermediate binary word is equal to the inverted reference binary word for a second pair of equal or inverted binary words and so that the intermediate binary word is unequal to the reference binary word and the inverted reference binary word for a pair of unequal and uninverted binary words, if the intermediate value determiner works faultlessly. Further, the error detector provides an error signal based on the intermediate binary word so that the error signal indicates whether or not the binary words of a pair of binary words are equal or inverted. | 08-15-2013 |
20130305129 | Systems and Methods for Media Defect Detection - Various embodiments of the present invention provide systems and methods for media defect detection. For example, a data transfer system is disclosed that includes a data detector, a defect detector and a gating circuit. The data detector provides a soft output, and the defect detector is operable to receive the soft output and the data signal, and to assert a defect indication based at least in part on the soft output and the data signal. The gating circuit is operable to modify the soft output of the detector whenever the defect indication is asserted. | 11-14-2013 |
20140095963 | PATTERN-DEPENDENT SHORT MEDIA DEFECT DETECTION - Systems and methods for computing sign disagreement between Le and La signals may implement one or more operations including, but not limited to: receiving an extrinsic log likelihood ratio (LLR) value; incrementing a sign-disagreement counter according to a sign disagreement between the extrinsic LLR value and an a priori LLR value; providing a value of the sign-disagreement counter to a binary short media defect (SMD) detector. | 04-03-2014 |
20140108896 | ERROR DETECTING DEVICE AND METHOD OF A DUAL CONTROLLER SYSTEM - An error detecting device of a dual controller system is provided. The first controller receives a sensing data from a sensor to calculate and generate a first data and outputs a final data if an error is not detected by comparing the first data with a second data transmitted from a second controller. The CAN transceiver receives the final data from the first controller and transmits the final data through a CAN bus. The second controller receives the sensing data from the sensor to calculate and generate a second data and transmits to the first controller an interrupt signal which prevents an output of the final data if an error is detected by comparing the second data with the final data fed back from the CAN transceiver. Accordingly, output transmission to the vehicle is controlled and the stability and reliability of the output data is increased. | 04-17-2014 |
20140173392 | HARDWARE ENFORCED PROTECTION OF SOFTWARE DATA STRUCTURES - Methods, systems, and computer program products are provided for hardware enforced data protection mechanisms to protect software data structures. Software data structures can be protected against malicious software or software code errors that may result in data/buffer overruns or failures in computing systems. Software data structures are identified that need to be validated before they are used by software programs. A hardware mechanism receives instructions from various security privilege levels and validates an entire software data structure before the software data structure is used by software programs. Being able to detect whether a software data structure is corrupted improves defenses and security against malicious or erroneous code, provides a method for early identification, isolation, ease of debugging of software, and protects overall system integrity in computer systems and applications thereof. | 06-19-2014 |
20140189475 | ERROR DETECTION AND CORRECTION SCHEME FOR A MEMORY DEVICE - An embodiment of a method of operating a memory device includes reading data from a memory array into a data buffer, checking the data using a first checker, checking the data using a second checker, and when an error is detected by the first checker and the error is not detected by the second checker returning the data to the memory array from the data buffer. | 07-03-2014 |
20140195883 | Apparatus, System, and Method for Matching Patterns with an Ultra Fast Check Engine - A check engine includes a plurality of comparators each including a first directional characteristic aligned to store at least one reference bit included in a set of reference bits, and a second directional characteristic aligned to present at least one target bit included in a set of target bits. Each of the plurality of comparators is configured to produce an output representing a level of matching between the at least one target bit and the at least one reference bit, based on a relative alignment between the first directional characteristic and the second directional characteristic. The check engine is configured such that the outputs of the plurality of comparators are combined to produce a combined output. The check engine is configured to determine that the set of target bits matches the set of reference bits based on the combined output of the plurality of comparators. | 07-10-2014 |
20140201607 | One-time programmable integrated circuit security - One-time programmable integrated circuit security is described. An example of a method of protecting memory assets in an integrated circuit includes sampling values of multiple OTP memory arrays and comparing the sampled value of each OTP memory array with the sampled value of each other OTP memory array and with an unprogrammed OTP memory array value. The method further includes determining if an integrated circuit performance fault has occurred based on the compared sampled values, booting the integrated circuit, and operating the integrated circuit with access to memory determined by the fault occurrence determination. | 07-17-2014 |
20140215294 | ERROR DETECTION AND CORRECTION OF ONE-TIME PROGRAMMABLE ELEMENTS - A circuit includes a first one-time programmable (OTP) element and a second OTP element. The circuit also includes error detection circuitry coupled to receive a first representation of data from the first OTP element. The circuit further includes output circuitry responsive to an output of the error detection circuitry to output an OTP read result based on the first representation of the data or based on a second representation of the data from the second OTP element. | 07-31-2014 |
20140223269 | MEMORY CONTROLLER WITH WRITE DATA ERROR DETECTION AND REMEDIATION - A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition. | 08-07-2014 |
20140237329 | Ratio-Adjustable Sync Mark Detection System - Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for detecting a sync mark with a ratio-adjustable detection system. | 08-21-2014 |
20140281845 | HIGH SPEED SERIAL DATA RECEIVER ARCHITECTURE WITH DUAL ERROR COMPARATORS - A receiver path including first, second, third, and fourth comparator modules. The first comparator module is configured to generate, based on a signal received via the receiver path, a first digital output signal indicative of a sum of first data in the received signal and a first error. The second comparator module is configured to generate, based on the signal received via the receiver path, a second digital output signal indicative of a sum of second data in the received signal and a second error. The third comparator module is configured to generate, based on the signal received via the receiver path, a third digital output signal indicative of the first data in the received signal. The fourth comparator module is configured to generate, based on the signal received via the receiver path, a fourth digital output signal indicative of the second data in the received signal. | 09-18-2014 |
20140304575 | DIGITAL-ANALOG CONVERSION APPARATUS AND METHOD - An apparatus and a method for digital-analog conversion are provided. The apparatus includes a first cell matrix for outputting a current of a signal corresponding to a number of Most Significant Bits (MSBs) of an input digital signal, a second cell matrix for outputting a current of a signal corresponding to a number of Least Significant Bits (LSBs) of the input digital signal, an amplifier for amplifying the output current of the second cell matrix at a preset amplification, and an adder for adding the output current of the first cell matrix and the output current of the amplifier. | 10-09-2014 |
20140325322 | SEMICONDUCTOR INTEGRATED CIRCUIT AND DRIVE APPARATUS INCLUDING THE SAME - A semiconductor integrated circuit includes a first transmission circuit generating and outputting a first transmission signal reflecting a first data signal supplied from outside, a first reception circuit reproducing the first data signal based on a first reception signal, a first isolation element isolating the first transmission circuit from the first reception circuit and transmitting the first transmission signal as the first reception signal, a second transmission circuit generating and outputting a second transmission signal reflecting a second data signal supplied from outside, a second reception circuit reproducing the second data signal based on a second reception signal, a second isolation element isolating the second transmission circuit from the second reception circuit and transmitting the second transmission signal as the second reception signal, and a third transmission circuit generating and outputting a third transmission signal reflecting the second data signal. | 10-30-2014 |
20140331112 | Margin Test Methods and Circuits - Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing. | 11-06-2014 |
20150019939 | DEVICE AND METHOD FOR IMPROVED LOST FRAME CONCEALMENT - A method and system are described herein that employ a lost frame concealment technique for processing data frames received during transmission over a communications channel. The lost frame concealment technique involves determining whether a current data frame is a bad frame, performing source decoding on the current data frame with one or more parameters that are limited by a first set of one or more values if the current data frame is a bad frame, and performing source decoding on the current data frame with one or more parameters that are not limited if the current data frame is a good frame. | 01-15-2015 |
20150039978 | Systems and Methods for Hybrid Priority Based Data Processing - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing. | 02-05-2015 |
20150095748 | CODE-ASSISTED ERROR-DETECTION TECHNIQUE - A method of operation in a memory controller is disclosed. The method includes generating first error information for a selectively dynamic-bus-inversion (DBI)-encoded data word. The selectively DBI-encoded data word is for transfer to a memory device. Second error information associated with the selectively DBI-encoded data word is received from the memory device. Errors in the data word are detected by comparing the first error information to the second error information. The detecting includes evaluating the DBI-encoding of the selectively DBI-encoded data word. | 04-02-2015 |
20150100865 | APPARATUS AND METHOD FOR DETERMINING ONE OF CONTROL UNITS TO PERFORM A VERIFICATION PROCESS ON DATA - Plural control-units each perform a verification process for verifying validity of data. A first storage stores, for each control-unit, an index value indicating a load on the each control-unit activating the verification process, in association with each combination of a rate of a data-amount processed in the verification process executed by the each control-unit and a utilization rate of the each control-unit. A second storage stores, in association with each control-unit, information on a data-amount currently being processed in the verification process activated by the each control-unit and the utilization rate of the each control-unit. A first control-unit determines an index value, for each control-unit, by referring to information in the first storage based on information on a data-amount to be processed in a target verification process and information in the second storage, and determines a second control-unit to activate the target verification process, based on the determined index values. | 04-09-2015 |
20150293810 | CONTENT ADDRESSABLE MEMORY WITH ERROR DETECTION - A content addressable memory (CAM) includes a first entry which includes one or more bits, a second entry which includes one or more bits, first comparison circuitry configured to compare each bit of a comparand to a corresponding bit of the one or more bits of the first entry and to provide a hit/miss indicator in response thereto, and second comparison circuitry configured to compare each bit of the one or more bits of the first entry to a corresponding bit of the one or more bits of the second entry and to provide a fault indicator in response thereto. | 10-15-2015 |
20150309863 | PRACTICAL DYNAMIC PROOFS OF RETRIEVABILITY - Certain embodiments of the present invention involve a method of storing an erasure coded copy of block data, and storing newly updated block data into a separate erasure-coded log structure. The method also includes auditing both the erasure copy of block data and the newly updated block data. The erasure copy of block data and the newly updated block data are probabilistically checked during the audit. In certain other embodiments the newly updated block data is stored in a log structure. | 10-29-2015 |
20150339183 | CONTROLLER, STORAGE DEVICE, AND CONTROL METHOD - According to embodiments, a controller is provided with a receiving unit which receives data and a first redundant bit generated by coding the data by using a first generator polynomial, a coding unit which codes the data by using a second generator polynomial having a common factor with the first generator polynomial to generate a second redundant bit, and an error check unit which determines whether there is difference between the input data to coding by using the first generator polynomial and the input data to coding by using the second generator polynomial by dividing an XOR operation result of the first redundant bit and a result of a bit shift of the second redundant bit by the common factor. | 11-26-2015 |
20160048423 | TRANSMISSION CONTROL CHECKING FOR INTERCONNECT CIRCUITRY - Transmission control checking circuitry adds control check data to a transaction response which is received at a transaction master and compared with expected data at the transaction master. The expected data having control check data may be a unique transaction identifier. The transaction master generated the unique transaction identifier when it generated the transaction request and will check that the transaction responses include that unique transaction identifier. In this way, errors in the control of transmission of transactions (e.g., misrouting) may be detected. | 02-18-2016 |
20160062813 | WIRELESS COMMUNICATION DEVICE - According to an embodiment, a wireless communication device, which complies with plural communication methods, includes a storing circuit and a received data selection determining circuit. The storing circuit sequentially stores a first received data until the first received data reaches a predetermined data size. When it is assumed that a radio signal complies to a second communication method, a first period is longer than a second period. The first period is a period from a first time when a reception of the radio signal is started to a second time when the first received data with the data size is stored. The second period is a period from the first time to a time when a second reception start signal is detected. The received data selection determining circuit determines a selection of the first received data, when the second reception start signal is not detected at the second time. | 03-03-2016 |
20160062921 | APPLICATION PROCESSOR AND DATA PROCESSING SYSTEM INCLUDING THE SAME - A data processing system includes an application processor, a memory device, and a channel connecting the application processor and the memory device. The application processor encrypts first data using a first encryption key and a first initialization vector in response to a write command, and transmits first encrypted data to the memory device through the channel. The memory device decrypts the first encrypted data using a second encryption key and a second initialization vector, and stores first decrypted data in a memory core. The second encryption key and the second initialization vector are stored in the memory device. The first encryption key is the same as the second encryption key, and the first initialization vector is the same as the second initialization vector. | 03-03-2016 |
20160077904 | INTEGRATED CIRCUIT AND METHOD OF DETECTING A DATA INTEGRITY ERROR - An integrated circuit comprises a write bus coupled to a register for storing control data. A storage unit is arranged to store reference signature data encoding a reference collective state of the register. First logic circuitry generates actual signature data encoding the actual collective state of the register. Second logic circuitry is coupled to the storage unit, receives the actual signature data and compares the actual signature data with the reference signature data. The second logic circuitry comprises an alert output to provide an alert signal in response to the comparison identifying a difference between the actual signature data and the reference signature data, thereby ensuring detection of a data integrity error in respect of the register. An alert inhibitor comprises a control input and is responsive to the control input and arranged to inhibit selectively onward propagation of the alert signal from the alert output. | 03-17-2016 |
20160092293 | SEMICONDUCTOR MEMORY DEVICE - The present invention provides a semiconductor memory device that can perform failure detection of an address decoder by a simple method with a low area overhead. The semiconductor memory device includes: a first memory array having a plurality of first memory cells arrange in matrix; a plurality of word lines provided corresponding to each of the memory cell rows; an address decoder for selecting a word line from the word lines based on the input address information; a second memory array that is provided adjacent to the first memory array in the column direction, having a plurality of second memory cells able to read address information used in the selection of the previously stored word line, according to the selection of the word line extended to the second memory array; and a comparison circuit for comparing the input address information with the address information read from the second memory array. | 03-31-2016 |
20160093354 | SHORT DETECTION AND INVERSION - In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell. | 03-31-2016 |
20160094244 | APPARATUS AND METHOD FOR RESOURCE ALLOCATION - An apparatus and a method for allocating network resources in a fair manner. The method includes determining for a first matrix of a certain dimension and a corresponding set of predetermined numbers, a second allocation matrix, wherein the numbers allocated to cells of the second matrix are such that the sum of the numbers in any row, column, diagonal, or anti-diagonal equal the same number. Based on predetermined priorities, a row, column, diagonal, or an anti-diagonal of the second allocation matrix is selected to correspond to the | 03-31-2016 |
20160124788 | METHOD FOR DETECTION OF SOFT MEDIA ERRORS FOR HARD DRIVE - Some embodiments are directed to a method, corresponding system, and corresponding apparatus for detecting unexpectedly high latency, due to excessive retries of a given storage device of a set of storage devices. Some embodiments may comprise a processor and associated memory. Some embodiments may monitor one or more completion time characteristics of one or more accesses between the given storage device and one or more host machines. Some embodiments may then compare the one or more completion time characteristics with a given threshold. As a result of the comparison, some embodiments may report, by the one or more host machines, at least one error associated with the given storage device. The error may be unreported by the set of storage devices. | 05-05-2016 |
20160188392 | FAST APPROXIMATE CONFLICT DETECTION - The present disclosure is directed to fast approximate conflict detection. A device may comprise, for example, a memory, a processor and a fast conflict detection module (FCDM) to cause the processor to perform fast conflict detection. The FCDM may cause the processor to read a first and second vector from memory, and to then generate summaries based on the first and second vectors. The summaries may be, for example, shortened versions of write and read addresses in the first and second vectors. The FCDM may then cause the processor to distribute the summaries into first and second summary vectors, and may then determine potential conflicts between the first and second vectors by comparing the first and second summary vectors. The summaries may be distributed into the first and second summary vectors in a manner allowing all of the summaries to be compared to each other in one vector comparison transaction. | 06-30-2016 |
20160188399 | VALIDATE WRITTEN DATA - Data and a first error detection code related to the data is received. That the received data is written correctly to a memory is validated based on the first error detection code and/or a comparison of the written data to the received data. An alert is generated if it is determined that the written data is incorrect. | 06-30-2016 |
20160203036 | MACHINE LEARNING-BASED FAULT DETECTION SYSTEM | 07-14-2016 |
20160253228 | ERROR DETECTION CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME | 09-01-2016 |
20160378580 | SYSTEM FOR CHECKING THE INTEGRITY OF A COMMUNICATION BETWEEN TWO CIRCUITS - A method of verifying integrity of communications between a master circuit and a slave circuit includes updating a first cyclic multibit signature based on each transaction sent by the master circuit to the slave circuit. A second cyclic multibit signature is updated based on each transaction received by the slave circuit. One or more bits based on the second cyclic multibit signature are compared with corresponding bits based on the first cyclic multibit signature, with a number of the one or more bits being less than a total number of bits of the second cyclic signature. Error conditions are detected and responded based on the comparing. | 12-29-2016 |
20190147965 | MEMORY SYSTEM INCLUDING A MEMORY DEVICE, AND METHODS OF OPERATING THE MEMORY SYSTEM AND MEMORY DEVICE | 05-16-2019 |