| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 714732000 | Signature analysis | 29 |
| 20080256407 | PROCESS AND SYSTEM FOR THE VERIFICATION OF CORRECT FUNCTIONING OF AN ON-CHIP MEMORY - A method is for making an integrated circuit with built-in self-test. The method includes forming at least one nonvolatile read only memory (ROM) to store ROM code and forming a logic self-test circuit to verify a correct functioning of the at least one nonvolatile ROM. Moreover, the method includes defining, in the logic self-test circuit, a logic self-test core to process the ROM code and to generate a flag based upon a control signature and defining, in the logic self-test circuit, a nonvolatile storage block, coupled to the logic self-test core, to store the control signature. Furthermore, the method includes writing the ROM code to the at least one nonvolatile ROM and writing the control signature to the nonvolatile storage block, during a same fabrication step. | 10-16-2008 |
| 20080263421 | Electrical Diagnostic Circuit and Method for the Testing and/or the Diagnostic Analysis of an Integrated Circuit - An electrical diagnostic circuit and testing method is disclosed. In one embodiment the electrical diagnostic circuit for testing an integrated circuit includes a number of external inputs, a plurality of essentially similar, series-connected switching units and a circuit output. The switching units are constructed to be controllable in such a manner that an input signal present at the internal input of the switching unit, in dependence on a control signal of the switching unit, can either be forwarded unchanged to the internal input of the switching unit in each case arranged downstream, or can be combined with the test signal in each case present at the external input. | 10-23-2008 |
| 20080263422 | CONTROL OF THE INTEGRITY OF A MEMORY EXTERNAL TO A MICROPROCESSOR - A method for recording at least one information block in a first volatile memory external to a circuit, a first digital signature being calculated based on information and data internal to the circuit and a second digital signature being calculated based on first signatures of a group of information blocks and on a digital quantity internal to the circuit and assigned to said group. A method for checking the content of an information block recorded by this recording method. | 10-23-2008 |
| 20090031180 | Method for Discovering and Isolating Failure of High Speed Traces in a Manufacturing Environment - A mechanism is provided for discovering and isolating failure of high speed traces in a manufacturing environment. The mechanism utilizes transmit pre-emphasis and receiver equalization in combination with attenuated wrap plugs to enhance discovery and isolation of manufacturing defects in the manufacturing environment. The mechanism adjusts pre-emphasis and equalization in real time in high speed devices, allowing for much greater variation to compensate for design margins and specification variances. While the card is under test with wrap-backs installed, the pre-emphasis and receiver equalization are brought to the limits while logging the bit error rate to a non-volatile memory element. The mechanism then compares the bit error rate information to empirically derived signatures for failure isolation. | 01-29-2009 |
| 20090077439 | INTEGRATED CIRCUIT TEST METHOD AND TEST APPARATUS | 03-19-2009 |
| 20090094495 | MODULATION SIGNATURE TRIGGER - A trigger generator and trigger method are provided for determining whether or not a signal under test matches a modulation signature. The modulation signature may be provided as a magnitude signature, a phase signature or both. When the magnitude values, phase values, or both of a signal under test are the same as their respective modulation signature, an error computation will be close to zero. If this value is within a threshold value, a trigger signal or other indication of a match is produced. | 04-09-2009 |
| 20090106614 | SYSTEM AND METHOD FOR SIGNATURE-BASED SYSTEMATIC CONDITION DETECTION AND ANALYSIS - Disclosed are embodiments of a system, method and service for detecting and analyzing systematic conditions occurring in manufactured devices. Each embodiment comprises generating a unique signature for each of multiple tested devices. The signatures are generated based on an initial set of signature definitions and the values for those signature definitions that are derived at least in part from selected testing data. A systematic condition is detected based on commonalities between the signatures. The systematic condition is then analyzed, alone or in conjunction with additional information, in order to develop a list of underlying similarities between the devices. The analysis results can be used to refine the systematic condition detection and analysis processes by revising the signature definitions set and/or by modifying data selection. | 04-23-2009 |
| 20090144594 | METHOD AND APPARATUS FOR DESCRIBING AND TESTING A SYSTEM-ON-CHIP - The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip. | 06-04-2009 |
| 20090144595 | BUILT-IN SELF-TESTING (BIST) OF FIELD PROGRAMMABLE OBJECT ARRAYS - A field programmable object array integrated circuit has built-in self-testing capability. The integrated circuit comprises an array of programmable objects, a plurality of interfaces, and a controller. The array of objects is designed to operate at an operational clock speed during non-testing operation, wherein the design of the objects is not constrained to require within an object extra circuitry not essential to non-testing operation to facilitate built-in self-testing. The interfaces are connected to the objects to enable communication with the objects and to thereby facilitate built-in self-testing of the objects. The controller causes a selected subset of the objects to be activated and configured for testing, to stimulate the selected subset for some time with an input test pattern delivered via the interfaces while the selected subset of objects operates at the operational clock speed, and to observe a response of the selected subset of objects. | 06-04-2009 |
| 20090271675 | RADIATION INDUCED FAULT ANALYSIS - A method of locating a defect of a failed semiconductor device which includes applying a test pattern to the failed semiconductor device and providing failed semiconductor device test responses as a pass signature, applying radiation to each of multiple locations of circuitry of a correlation semiconductor device with sufficient energy to induce a fault in the circuitry, applying the test pattern to the correlation semiconductor device while the radiation is applied to the location and comparing correlation semiconductor device test responses with the pass signature for each location, and determining a defect location of the failed semiconductor device in which correlation semiconductor device test responses at least nearly match the pass signature. The radiation may be a laser beam. The method may include determining an exact match or a near match based on a high correlation result. Asynchronous scanning may be used to provide timing information. | 10-29-2009 |
| 20090282306 | ERROR DETECTION ON PROGRAMMABLE LOGIC RESOURCES - Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic. | 11-12-2009 |
| 20090307549 | PROCESSOR TEST SYSTEM UTILIZING FUNCTIONAL REDUNDANCY - A system and method for testing a processor. The system includes a gold processor and a test processor, wherein the test processor is the device under test (DUT). The test processor and the gold processor are identical. A first memory is coupled to the gold processor by a first memory bus and a second memory, independent of the first, is coupled to the test processor by a second memory bus. The first and second memories are identical. A memory bus comparator coupled to the first and second memory buses compares memory bus signals generated by the gold and test processors, and selectively provide a first indication if a mismatch occurs. A peripheral bus comparator is also coupled to the gold and test processors, and compares downstream transactions generated by the gold and test processors and to provide a second indication if a peripheral bus comparison results in a mismatch. | 12-10-2009 |
| 20090327824 | TECHNIQUES FOR PERFORMING A LOGIC BUILT-IN SELF-TEST IN AN INTEGRATED CIRCUIT DEVICE - A method, system and computer program product for performing device characterization Logic Built-In Self-Test (LBIST) in an IC device. Test parameters of the LBIST are saved in a memory of the IC device, and nominal operational parameters of the IC device are used to define a signature of the LBIST. A determination whether the LBIST is passed or failed is made within the characterized IC device. | 12-31-2009 |
| 20100017667 | Method and Device to Detect Failure of Static Pervasive Control Signals - A method and circuits for monitoring and detecting an error in the static pervasive signals applied to input/output pins of an integrated circuit during functional operation of the integrated circuit. The method and circuits provide a signal signature of each of one or more groups of the static pervasive signals and then monitoring the signal signature for any change of logic level. | 01-21-2010 |
| 20110047427 | Integrated Circuit Including a Programmable Logic Analyzer with Enhanced Analyzing and Debugging Capabilities and a Method Therefor - An integrated circuit including a logic analyzer with enhanced analyzing and debugging capabilities and a method therefor. In one embodiment, an integrated circuit includes a logic analyzer having a first input receiving a plurality of signals and an output for providing an indication of a detection, by the logic analyzer, of at least one trigger event; and a built in self test block having a first input for receiving one or more of the signals appearing at the first input of the logic analyzer, a second input coupled to the output of the logic analyzer for selectively enabling the BIST block, the BIST block generating and maintaining a signature based upon the first and second inputs thereof. | 02-24-2011 |
| 20110060954 | SEMICONDUCTOR DEVICE AND METHOD FOR VALIDATING A STATE THEREOF - A semiconductor device comprises processing logic arranged to execute program instructions. The semiconductor device further comprises signature generation logic arranged to receive at least one value from at least one internal location of the semiconductor device, and to generate a current signature value, based on the at least one received value. Validation logic is arranged to validate the current signature value generated by the signature generation logic. The processing logic is further arranged, upon execution of a signature validation instruction, to enable the validation of the current signature value provided by the validation logic. | 03-10-2011 |
| 20110126065 | MICROPROCESSOR COMPRISING SIGNATURE MEANS FOR DETECTING AN ATTACK BY ERROR INJECTION - A method for monitoring the execution of a sequence of instruction codes in an integrated circuit comprising a central processing unit provided for executing such instruction codes. Current cumulative signatures are produced using deterministic address, control or data logic signals involved in the execution of the sequence and taken off at various points of the integrated circuit. A final cumulative signature is compared with an expected signature and an error signal is produced if the two signatures are not identical. Particularly useful to secure integrated circuits for smart cards. | 05-26-2011 |
| 20110138240 | ERROR DETECTION ON PROGRAMMABLE LOGIC RESOURCES - Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic. | 06-09-2011 |
| 20120159274 | APPARATUS TO FACILITATE BUILT-IN SELF-TEST DATA COLLECTION - Techniques are disclosed relating to testing logic in integrated circuits using an external test tool. In one embodiment, an integrated circuit includes a logic unit and a self-test unit. The self-test unit is configured to receive an expected signature value that corresponds to an expected output value of the logic unit, and to compare the expected signature value and an actual signature value generated from an actual output value from the logic unit. In some embodiments, the integrated circuit further includes a pseudo-random pattern generator configured to provide an input value to the logic unit, and the logic unit is configured to generate the actual output value based on the provided input value. In some embodiments, the integrated circuit further includes a multiple-input signature register (MISR) configured to generate the actual signature value based on the actual output value and a seed value. | 06-21-2012 |
| 20120260141 | LEARNING SIGNATURES FOR APPLICATION PROBLEMS USING TRACE DATA - The problem signature extraction technique extracts problem signatures from trace data collected from an application. The technique condenses the manifestation of a network, software or hardware problem into a compact signature, which could then be used to identify instances of the same problem in other trace data. For a network configuration, the technique uses as input a network-level packet trace of an application's communication and extracts from it a set of features. During the training phase, each application run is manually labeled as GOOD or BAD, depending on whether the run was successful or not. The technique then employs a learning technique to build a classification tree not only to distinguish between GOOD and BAD runs but to also sub-classify the BAD runs into different classes of failures. Once a classification tree has been learned, problem signatures are extracted by walking the tree, from the root to each leaf. | 10-11-2012 |
| 20140006889 | SIGNATURE COMPRESSION REGISTER INSTABILITY ISOLATION AND STABLE SIGNATURE MASK GENERATION FOR TESTING VLSI CHIPS | 01-02-2014 |
| 20140026008 | WRITING SCHEME FOR PHASE CHANGE MATERIAL-CONTENT ADDRESSABLE MEMORY - A system for programming a phase change material-content addressable memory (PCM-CAM). The system includes a receiving unit for receiving a word to be written in the PCM-CAM. The word includes low bits represented by a low resistance state in the PCM-CAM and high bits represented by a high resistance state in the PCM-CAM. The system includes a writing unit configured to repeatedly write the low bits in memory cells of the PCM-CAM until the resistance of the memory cells are below a threshold value, and to write high bits in memory cells of the PCM-CAM only once. | 01-23-2014 |
| 20140157072 | SELF EVALUATION OF SYSTEM ON A CHIP WITH MULTIPLE CORES - A method and structure tests a system on a chip (SoC) or other integrated circuit having multiple cores for chip characterization to produce a partial good status. A Self Evaluation Engine (SEE) on each core creates a quality metric or partial good value for the core. The SEE executes one or more tests to create a characterization signature for the core. The SEE then compares the characterization signature of a core with a characterization signature of neighboring cores to determine the partial good value for the core. The SEE may output a result to create a full characterization map for detailed diagnostics or a partial good map with values for all cores to produce a partial good status for the entire SoC. | 06-05-2014 |
| 20140157073 | SELF EVALUATION OF SYSTEM ON A CHIP WITH MULTIPLE CORES - A method and structure tests a system on a chip (SoC) or other integrated circuit having multiple cores for chip characterization to produce a partial good status. A Self Evaluation Engine (SEE) on each core creates a quality metric or partial good value for the core. The SEE executes one or more tests to create a characterization signature for the core. The SEE then compares the characterization signature of a core with a characterization signature of neighboring cores to determine the partial good value for the core. The SEE may output a result to create a full characterization map for detailed diagnostics or a partial good map with values for all cores to produce a partial good status for the entire SoC. | 06-05-2014 |
| 20150113348 | IMPLEMENTING MISR COMPRESSION METHODS FOR TEST TIME REDUCTION - A method and circuits for implementing multiple input signature register (MISR) compression for test time reduction, and a design structure on which the subject circuits reside are provided. The MISR compression circuit includes a first MISR, a second MISR provided with the first MISR, and a compressor to compress MISR data positioned in one of between the first MISR and second MISR and after the second MISR. | 04-23-2015 |
| 20160025809 | Accelerated And Accuracy-Enhanced Delay And Noise Injection Calculation For Analysis Of A Digital Circuit Using Grid Computing - A computer system with one or more processors and memory performs a breadth-first-search for an analysis of a digital circuit that includes a plurality of components. The computer system identifies two or more N generation components, initiates processing of the two or more N generation components, and subsequent to initiating the processing of the two or more N generation components, receives results of processing a subset, less than all, of the two or more N generation components. Prior to receiving results of processing all of the N generation components, the computer system identifies one or more N+1 generation components, and initiates processing of the one or more identified N+1 generation components. Subsequently, the computer system receives results of processing at least a subset of the one or more identified N+1 generation components. | 01-28-2016 |
| 20160077154 | METHOD FOR SPEEDING UP BOOLEAN SATISFIABILITY - A method for transforming a tautology check of an original logic circuit into a contradiction check of the original logic circuit and vice versa comprises interpreting the original logic circuit in terms of AND, OR, MAJ, MIN, XOR, XNOR, INV original logic operators; transforming the original circuit obtained from the interpreting, into a dual logic circuit enabled for a checking of contradiction in place of tautology and vice versa, by providing a set of switching rules configured to switch each respective one of the original logic operators INV, AND, OR, MAJ, XOR, XNOR, MIN into a respective switched logic operator INV, OR, AND, MAJ, XNOR, XOR, MIN; and complementing outputs of the original circuit by adding an INV at each output wire. The method further provides testing in parallel the satisfiability of the original logic circuit, and the satisfiability of the dual logic circuit with inverted outputs. Responsive to one of the parallel tests finishing, the other parallel test is caused to also stop. | 03-17-2016 |
| 20160084907 | TEST DEVICE AND METHOD - A test device for testing a device under test (DUT) includes an integrated control interface adaptable for a plurality of different communication standards. The integrated control interface can be adapted to be compliant with the communication standard used by a DUT connected to the test device. | 03-24-2016 |
| 20160161557 | Determining Transient Error Functional Masking And Propagation Probabilities - A method, system and product for determining transient error functional masking and propagation probabilities. An Error Infliction Probability of pair of nodes (source and destination) is representative of a Transient Error happening on a source node propagating to the destination node. The probability is computed by simulating a propagation of a transient error for plurality of cycles in a given trace. The simulation utilizes values from the trace for nodes that are not influenced by the error (but may influence its propagation). A plurality of cycle-simulations may be performed and a ratio of a number of times the transient error propagated to the destination node compared to a number of cycles examined may be used to compute the error infliction probability. | 06-09-2016 |
