Entries |
Document | Title | Date |
20080244326 | Prognosis of faults in electronic circuits - A process for a prognosis of faults in electronic circuits identifies parameters of a circuit under test. An upper and a lower limit is determined for one or more components of the circuit under test. A population of faulty and non-faulty circuits are generated for the circuit under test, and feature vectors are generated for each faulty and non-faulty circuit. The feature vectors are stored in a fault dictionary, and a feature vector for an implementation of the circuit under test in a field operation is generated. The feature vector for the implementation of the circuit under test in the field operation is compared to the feature vectors in the fault dictionary. | 10-02-2008 |
20080320335 | Test Automation Via RFID Technology - A method and system receives test requirements and test settings in order to design a test. An identifier is assigned to the test that was designed and the test is stored in a database using the identifier to identify the test. In addition, the test is printed on at least one sheet or form and a wireless read/write device is programmed with the identifier assigned to the test. The wireless read/write device is attached to the sheet on which the test was printed. Thus, the sheet and the wireless read/write device can be provided to a test operator to allow the test operator to wirelessly read the identifier from the wireless read/write device. Then, the test operator can access the test from the database based on the identifier read from the wireless read/write device. The test instructions (comprising the test requirements and test settings) are provided from the database to the operator to perform the test and potentially produce a physical test output. The test instructions are provided to the operator through a graphic user interface. | 12-25-2008 |
20090024875 | SERIAL ADVANCED TECHNOLOGY ATTACHMENT DEVICE AND METHOD TESTING THE SAME - A serial advanced technology attachment (SATA) device is provided. The SATA device includes a digital block and an analog black. The digital block is configured to generate and output an out-of-band (OOB) control signal. The analog block is configured to receive the OOB control signal, which has been output from the digital block, to receive the OOB control signal again after outputting it, and then output the OOB control signal to the digital block. | 01-22-2009 |
20090044057 | System and Method for Controlling Synchronous Functional Microprocessor Redundancy during Test and Analysis - A system for testing a processor. The system includes a gold processor and a test access port (TAP). A processor that is a under test (DUT) is coupled to both the gold processor and the TAP. Test signals are simultaneously provided to both the gold processor and the DUT such that the gold processor and the DUT operate in synchronous functional lockstep. The TAP may also input test signals into the gold processor and DUT simultaneously and access data from each of these processors through separate test data out (TDO) connections. Test output data accessed from the gold processor may be compared to test output data accessed from the DUT to determine if any differences are present. The comparison data generated may then be used for analysis purposes. | 02-12-2009 |
20090044058 | System and Method for Controlling Synchronous Functional Microprocessor Redundancy during Test and Method for Determining Results - A system for testing a processor. The system includes a gold processor and a test access port (TAP). A processor that is a device under test (DUT) is coupled to both the gold processor and the TAP. In the first mode, the TAP provides test signals to both the gold processor and the DUT while they operate in synchronous functional lockstep. In the second mode, the TAP provides signals to the gold processor. In the third mode, the TAP provides test signals to the DUT. A host computer coupled to the interface control unit executes a software application to cause the TAP to drive test signals and to access test output data from the gold processor and the DUT. Test output data accessed from the gold processor may be compared to that accessed from the DUT to determine any differences. The comparison data generated may then be used for further analysis. | 02-12-2009 |
20090144587 | DEVICE AND METHOD FOR ELECTRONIC CONTROLLING - An electronic controlling device and method is disclosed. One embodiment provides at least one module performing specific functions within one of a plurality of module modes on reception of a corresponding module mode request. A system control unit is provided to operate the at least module in one of a plurality of module modes by distributing a corresponding system mode request. The at least one module is adapted to translate the distributed system mode request to a module mode request which is configurable. | 06-04-2009 |
20090292953 | MODIFYING CONNECTION RECORDS - Systems and methods to modify a set of connection records are described. A determination is made that an application failed to access a first database via a connection record, where the connection record includes data to access the first database. A determination is made that a second database is accessible, where the second database is a failover database to the first database. A set of connection records associated with the first database is modified to enable access to the second database. | 11-26-2009 |
20100031091 | HARDWARE DIAGNOSTICS DETERMINATION DURING INITIAL PROGRAM LOADING - Disclosed are a method, system and computer program product for determining hardware diagnostics during initial program loading (IPL). A space is allocated for a diagnostics hardware table storing hardware identifications corresponding to hardware to be tested. A hardware monitor function detects new and/or defective hardware. Hardware can be manually selected. A runtime diagnostics detects defective hardware. The hardware identifications corresponding to the new, failing, and/or selected hardware are added to the diagnostics hardware table. The hardware identification to be tested is acquired during the building of a system Hardware Objects Model (HOM). A diagnostics flag is set within HOM according to the diagnostics hardware table. Diagnostics are performed per HOM diagnostics flag indication. The diagnostics table is cleared, and the operating system is run. At system runtime, diagnostics code monitors for runtime error. If an error is detected but cannot be isolated to defective hardware, the suspected hardware identification will be added to diagnostics hardware table so that it can be verified on the next system IPL. | 02-04-2010 |
20100241906 | SHARING SINGLE TESTER AMONG PLURALITY OF ACTIVE COMMUNICATION LINKS - A test system for testing a communication system having a plurality of communication links is disclosed. The test system has a single tester for performing various measurement and diagnostic tasks on a single link. The test system also has a switching system for independently testing any link by coupling the tester into any one link. The tester is coupled into the link by coupling the tester input to the link's transmitter and the tester output to the link's receiver. The switching system couples the tester such that all remaining links of the communication system have a unique one of the plurality of transmitters coupled to a unique one of the plurality of receivers, whereby the operation of the communication system can be maintained while testing individual links. | 09-23-2010 |
20100251029 | IMPLEMENTING SELF-OPTIMIZING IPL DIAGNOSTIC MODE - A method, apparatus and computer program product are provided for implementing self-optimizing initial program load (IPL) diagnostics. A control flag is set to identify a self-optimizing IPL diagnostics mode. The self-optimizing IPL diagnostics mode includes collecting a list of new parts and collecting a list of identified failed parts. Hardware is identified and initialized for running diagnostics on the collected list of flagged parts. Diagnostics are run only on the initialized flagged hardware. | 09-30-2010 |
20100262867 | ASSISTING FAILURE MODE AND EFFECTS ANALYSIS OF A SYSTEM COMPRISING A PLURALITY OF COMPONENTS - A method of assisting failure mode and effects analysis of a system having a plurality of components includes obtaining data associated with a component, or a group of components, of the system. The component or the group is associated with component type data or group type data, respectively, that includes data relating to at least one failure feature common to all components or groups, respectively, of that type. The component/group data and the component/group type data can then be stored and/or transferred for use in a failure mode and effects analysis of the system. | 10-14-2010 |
20100281307 | Systems and methods for identifying a relationship between multiple interrelated applications in a mainframe environment - Systems and methods are provided for identifying a relationship between multiple interrelated applications running in a mainframe environment. A repository is created to store information describing the multiple interrelated applications from the mainframe environment. A target application among the multiple interrelated applications is identified, and a frequency and a dependency relationship between the application and the multiple interrelated applications is determined. The relationship is displayed via a user interface. The relationship may be used to identify a cause of a failure in a mainframe environment. | 11-04-2010 |
20100332909 | CIRCUITS, SYSTEMS, APPARATUS AND PROCESSES FOR MONITORING ACTIVITY IN MULTI-PROCESSING SYSTEMS - An electronic circuit includes a first processor ( | 12-30-2010 |
20110022897 | MICROCONTROLLER DEVICE, MICROCONTROLLER DEBUGGING DEVICE, METHOD OF DEBUGGING A MICROCONTROLLER DEVICE, MICROCONTROLLER KIT - A microcontroller device comprising a receiver component configured to receive a one or more reset signals for the microcontroller device; an identification component configured to identify a source of the or each reset signals received by the receiver component; a time interval determining component configured to determine a length of a time interval in accordance with the identified source of the or each reset signals received by the receiver component; a voltage setting component configured to set a voltage of an output of the microcontroller device to a first value on receipt of a reset signal by the receiver component; and a control component configured to maintain the voltage of the output at the first value for the duration of the determined length of the time interval; and set the voltage of the output to a second value on substantial completion of the determined length of the time interval. | 01-27-2011 |
20110041013 | ELECTRONIC DEVICE AND METHOD FOR VERIFYING CORRECT PROGRAM EXECUTION - An electronic device is provided which comprises a microprocessor for executing a program code and a first hardware code path verifying (CPV) stage coupled to the microprocessor. The hardware CPV stage comprises a first error detection code (EDC) generator configured to continuously determine an error detection code on a continuous sequence of code relating to an actually executed portion of the program code and to compare the actual error detection code with a predetermined error code so as to verify correct execution of the program code and to indicate an error. | 02-17-2011 |
20110083045 | METHODS AND SYSTEMS FOR PROVISIONING AND MAINTAINING A CIRCUIT IN A DATA NETWORK - A disclosed example method involves at a network management module, receiving a request for logical circuit data associated with a network circuit. In addition, the example method involves requesting the logical circuit data from a legacy logical element in communication with a network device of the network circuit. The logical circuit data is received from the legacy logical element. The logical circuit data is indicative of whether the network circuit has failed. | 04-07-2011 |
20110131455 | INTEGRATED BUS CONTROLLER AND POWER SUPPLY DEVICE FOR USE IN A PROCESS CONTROL SYSTEM - An integrated bus controller and power supply device includes a typical or standard bus controller and a bus power supply disposed in a common housing, the size and external configuration of which may match a standard bus controller device associated with a typical I/O communication network. The bus controller may store and implement one or more control routines using one or more field devices connected to the I/O communication network while the bus power supply generates and provides the appropriate power signal to the bus of the I/O communication network, the power signal being used to power the field devices connected to the I/O communication network. The integrated bus controller and power supply device can be easily connected to the bus of the I/O communication network to provide both bus controller functionality and bus power supply functionality on the I/O communication network, without the need of configuring and attaching separate, dedicated bus controller and power supply devices to the bus and having to wire these devices together using multiple different terminal blocks. | 06-02-2011 |
20110161740 | APPARATUS AND METHOD FOR SELECTING CANDIDATE FOR FAILURE COMPONENT - An apparatus for selecting a candidate for a failure component causing errors from a plurality of components included in a network system, the apparatus includes a processor for executing a procedure. The procedure includes determining a relation class of a relation among the plurality of components on the basis of configuration information of the network system, each of the relations being classified into one of the relation classes in accordance with a direction of an error propagation, determining an investigation range for each component having an error on the basis of investigation information including an error type of an error occurred in the each component and an investigation direction corresponding to the relation class, the investigation range being a set of the components to be investigated, and selecting a component on the basis of an appearance frequency of each component in the investigation ranges as the candidate. | 06-30-2011 |
20120124427 | METHOD AND DEVICE FOR ERROR CONTROL IN AN OVERALL SYSTEM HAVING MULTIPLE INSTALLATIONS - A method for error control in an overall system having multiple installations, the installations communicating with one another via a data transmission system having a predefined transmission bandwidth, at least one installation component of each installation transmitting a predefined piece of information in a defined time slot of the transmission bandwidth of the data transmission system. In order to be able to perform an anticipatory machine diagnosis of the overall system, information concerning an error diagnosis of the installation components of each installation is transmitted via the predefined transmission bandwidth of the data transmission system, at least one installation component of each installation to be monitored for errors transmitting its error diagnosis data via an unassigned time slot within the transmission bandwidth of the data transmission system to a central evaluation unit which receives the error diagnosis data of all installation components of the installations to be monitored via the data transmission system. | 05-17-2012 |
20120239983 | COMPUTERISED STORAGE SYSTEM COMPRISING REPLACEABLE UNITS FOR MANAGING TESTING OF REPLACEMENT UNITS - A method for use in a computerized storage system comprising one or more replaceable units, for managing testing of one or more replacement units, where the storage system is automatically placed in a testing mode in response to a given unit being replaced and if testing fails the storage system automatically fails back to a service mode. | 09-20-2012 |
20130007530 | VERIFYING CORRECTNESS OF REGULAR EXPRESSION TRANSFORMATIONS THAT USE A POST-PROCESSOR - A method for determining correctness of a transformation between a first finite state automaton (FSA) and a second FSA, wherein the first FSA comprises a representation of a regular expression, and the second FSA comprises a transformation of the first FSA includes determining a third FSA, the third FSA comprising a cross product of the second FSA and a post-processor; determining whether the first FSA and the third FSA are equivalent; and in the event that the first FSA is determined not to be equivalent to the third FSA, determining that the transformation between the first FSA and the second FSA is not correct. | 01-03-2013 |
20130031418 | TESTING AND OPERATING A MULTIPROCESSOR CHIP WITH PROCESSOR REDUNDANCY - A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping. | 01-31-2013 |
20130111272 | FAULT DETECTION BASED ON DIAGNOSTIC HISTORY | 05-02-2013 |
20130311833 | COMPUTING DEVICE AND METHOD FOR TESTING COMPONENTS OF THE COMPUTING DEVICE - A method of testing components of a computing device by obtaining a serial number of the computing device, and searching a database for test results of the computing device by using the serial number. The method determines whether the computing device has passed an electronic circuitry test when the electronic circuitry test result of the computing device has been found in the database, and tests components of the computing device when the computing device has passed the electronic circuitry test. A component test result of the computing device is saved in the database, and displayed on the display. | 11-21-2013 |
20140149800 | TEST METHOD AND TEST CONTROL APPARATUS - Provided is a method for testing an apparatus including a first to third processors, a first circuit that connects the first and second processors, and a second circuit that connects the second and third processors. The method includes generating a test instruction sequence by prepending an additional instruction sequence to a certain instruction sequence which includes an instruction(s) for controlling the apparatus to execute a process using the first circuit. The additional instruction sequence does not change an operation result of an instruction included in the certain instruction sequence. The test instruction sequence includes an instruction(s) for controlling the apparatus to execute a process using the second circuit. The test method includes judging whether the first and second circuits are faulty, by controlling the apparatus to execute the test instruction sequence from a beginning of the certain instruction sequence, and from a beginning of the additional instruction sequence, respectively. | 05-29-2014 |
20140201575 | MULTI-CORE PROCESSOR COMPARISON ENCODING - Systems and methods to test processor cores of a multi-core processor microchip are provided. Comparison circuitry may be configured to compare data output from processor cores of a microchip. An encoding module may be configured to encode received data by initially assigning binary bit values to the processor cores. Based on at least one of a number of the processor cores and a first binary bit value, a first additional binary bit may be added to the first binary bit value. The first binary bit value may be assigned to a first processor core of the plurality of processor cores. | 07-17-2014 |
20140281735 | SYSTEM AND METHOD FOR MULTICORE PROCESSING - A method and apparatus for an asynchronous multicore common debugging system is described. Debug signals from a plurality of processor cores are synchronized to a common timing domain. Processing completed within the plurality of processor cores during a common timing interval is tracked. A single debugging tool chain is utilized to provide debugging results in response to the tracking the processing completed within the plurality of processor cores during the common timing interval. | 09-18-2014 |
20150033082 | Method and Apparatus for Multi-chip Reduced Pin Cross Triggering To Enhance Debug Experience - Embodiments include apparatuses, systems, and methods for reduced pin cross triggering to enhance a debug experience. A time-division packetizing (TDP) technique may be employed to facilitate communication of triggers between integrated circuits (ICs) connected in series forming a TDP communication ring. The ICs on the TDP communication ring may each include a cross trigger interconnect structure for interpreting between trigger signals and hardware core instructions. The serial TDP communication across the ICs on the TDP communication ring allows the ICs to be connected in a manner that each cross trigger interconnect structure on each IC may function as if it were part of a single cross trigger interconnect structure across all of the ICs on the TDP communication ring. The individual ICs may operate asynchronously and a trigger clock may be passed along with other trigger data to implement the debugging techniques uniformly on each IC. | 01-29-2015 |
20150067406 | TESTING SYSTEM AND METHOD FOR FAN MODULE - Testing system includes a testing device and a testing circuit board connected to the testing device. The testing device includes a storing module, a transmit-receive module, and an analyzing module. A number of specification parameters of a fan module is stored in the storing module. The transmit-receive module sends a testing code to the testing circuit board. The testing circuit board responds to the testing code to detect a number of running information of the fan module, and sends the running information to the transmit-receive module. The analyzing module receives the number of running information from the transmit-receive module and compares the number of running information with the number of specification parameters for determining whether the fan is qualified. The disclosure further provides a testing method. | 03-05-2015 |
20150100833 | METHOD AND APPARATUS FOR GENERATING TEST BENCH FOR VERIFICATION OF PROCESSOR DECODER - A method and apparatus for generating a test bench for verifying a processor decoder are provided. The method including receiving an architecture description comprising processor decoder information, parsing the received architecture description into information for verifying the processor decoder, and generating the test bench to verify the processor decoder based on the parsed information. | 04-09-2015 |
20160378628 | HARDWARE PROCESSORS AND METHODS TO PERFORM SELF-MONITORING DIAGNOSTICS TO PREDICT AND DETECT FAILURE - Hardware processors and methods to perform self-monitoring diagnostics to predict and detect failure are described. In one embodiment, a hardware processor includes a plurality of cores, and a diagnostic hardware unit to isolate a core of the plurality of cores at run-time, perform a stress test on an isolated core, determine a stress factor from a result of the stress test, and store the stress factor in a data storage device. | 12-29-2016 |