Entries |
Document | Title | Date |
20080201614 | Peripheral component interconnect bus test system and method therefor - A peripheral component interconnect (PCI) bus test system and method therefor, that is applied in a PCI test card. The PCI test card includes a static random-access-memory (SRAM). In the method, the data transaction of the PCI bus signal is disintegrated into a separate data operation, while eliminating the waveform interfering transaction. Through comparing the waveform of the data operation as separated from a PCI bus signal with the standard PCI bus waveform, the quality of the PCI bus signals can be precisely analyzed, thus realizing the hardware test of PCI bus. | 08-21-2008 |
20080215926 | Dubug by a Communication Device - An embodiment of the present invention includes a communication system configured to conform to SATA or SAS standards and causing communication between one or more hosts and a SATA device. The communication system includes a communication device adapted to generate debug information incorporated through one or more links using an analyzer to identify problems associated with the communication system. | 09-04-2008 |
20080256395 | DETERMINING AND ANALYZING A ROOT CAUSE INCIDENT IN A BUSINESS SOLUTION - A method, system and computer program product for analyzing a state changing event are disclosed. According to an embodiment, a method for analyzing a state changing event comprises: detecting a state changing event of a first resource; tracing a dependence link beginning at the first resource to a resource that the first resource depends on until finding a second resource having a state changing event that is not dependent on any resource with a state changing event; and identifying the state changing event of the second resource as a root cause incident for analysis. | 10-16-2008 |
20080270844 | SYSTEM AND METHOD FOR TRACING ACCELERATION IN AN EMBEDDED DEVICE - A system and method for tracing acceleration in an embedded device. Various embedded devices that generate debug trace output for which the usage of the processor can benefit from optimization include mobile phones, TV set-top-boxes, and networking equipment. Tracing acceleration is accomplished using a logic unit that is implemented in hardware, which thereby enables the processing of tracing data to be handled in parallel to the operation of the processor. | 10-30-2008 |
20080288825 | STORAGE SUBSYSTEM, STORAGE SYSTEM, AND COMMUNICATION CONTROL METHOD - In a storage subsystem which is connected to an IP network, by excluding an improper packet, security is heightened, and a performance of communication to a logical unit of storage subsystem is maintained and secured. In the storage subsystem, a function which carries out filtering of a packet other than an iSCSI packet is provided. With respect to only the packet passed through the function, its accessibility to the logical unit is filtered. Also, traffic of all received packets, and a traffic lob of a packet judged to be discarded by the above filtering is recorded. By using this information, controlling such as a cut-off process of improper communication, QoS securement for normal communication and so on, are carried out. | 11-20-2008 |
20080320338 | METHODS, SYSTEMS, AND MEDIA TO CORRELATE ERRORS ASSOCIATED WITH A CLUSTER - Methods, systems, and media for correlating error events of a cluster are disclosed. Embodiments may identify systems of a cluster potentially impacted by an error and identify one or more error events associated with those systems. Then, embodiments may select one of the identified error events based upon data associated with the identified error event, disregarding other identified error events generated for the same error or errors symptomatic of the error, to report the error to a maintenance provider via a single error event. Many embodiments may identify one or more error events potentially resulting from the same error by identifying error events within a specified time period of the event that triggered the correlation. Several embodiments correlate the error events in an environment that is substantially independent of the cluster. Further embodiments obtain data that describes system interconnections of the cluster and generate a topology based upon the data. | 12-25-2008 |
20090013215 | Storage control device and enclosure-unit power control method - The storage control device of the present invention switch-connects each of enclosures and individually stops the transmission of power to the enclosures that are not being accessed in order to reduce the power consumption amount. A plurality of additional enclosures are switch-connected via an inter-device switch to a base enclosure. Drives that have not been accessed for a predetermined period of time or more undergo spindown. If all the drives in the enclosure then assume the spindown state, the supply of power to each of the drives from the intra-enclosure power supply is stopped. In cases where all the drives in a certain enclosure have undergone spindown, the base enclosure turns OFF the switch in the power distribution circuit connected to this enclosure. As a result, the transmission of power to this enclosure is stopped. The fault diagnosis section detects a fault that has occurred with communications that employ the inter-device switch and specifies the point of the fault occurrence. | 01-08-2009 |
20090024877 | System and Method for Creating Different Start Cache and Bus States Using Multiple Test Patterns for Processor Design Verification and Validation - A system and method for creating different start cache and bus states using multiple test patterns for processor design verification and validation is presented. A test pattern generator/tester re-uses test patterns in different configurations that alter cache states and translation lookaside buffer (TLB) states, which produces different timing scenarios on a broadband bus. The test pattern generator/tester creates multiple test patterns for a multi-processor system and executes the test patterns repeatedly in different configurations without rebuilding the test patterns. This enables a system to dedicate more time executing the test patterns instead of building the test patterns. By repeatedly executing the same test patterns in a different configuration, the invention described herein produces different start cache states, different TLB states, along with other processor units, each time the test patterns execute that, in turn, changes the bus timing. | 01-22-2009 |
20090037776 | Recovering From A Failed I/O Controller In An Information Handling System - An information handling system includes first and second input/output (I/O) controllers, a detector for detecting an I/O controller failure, and an I/O recovery unit. The first I/O controller adaptively controls a first and a second I/O slot. The second I/O controller adaptively controls a third and a fourth I/O slot. Lastly, the I/O recovery unit, responsive to a detected I/O controller failure, operatively couples/decouples the first and second I/O slot to/from the first I/O controller, operatively couples/decouples the third and fourth I/O slot to/from the second I/O controller, and operatively decouples/couples the first and second I/O slot from/to the third and fourth I/O slot according to an I/O failure recovery protocol, the I/O failure recovery protocol provided for adapting one of either the first and second I/O controllers to operatively couple to the first, second, third and fourth I/O slots as a function of the detected I/O controller failure. | 02-05-2009 |
20090083585 | METHOD OF PRESSURE TESTING FOR PERIPHERAL COMPONENT INTERCONNECT (PCI) BUS STAGE - A method of pressure testing for peripheral component interconnect (PCI) bus stage that is used in the overall pressure testing of PCI bus. The method includes the steps of reviewing all the PCI buses in a system; obtaining a tree-shaped structure of the all the PCI buses and PCI devices of the entire system, and selecting from them a branch of PCI bus as an object of testing; performing peripheral component interconnect function test, input/output function test, and memory mapping function test of the PCI bus relative to this object of testing; and selecting a branch of PCI bus from among the remaining branches of PCI buses of the system as an object of testing to proceed with the related tests of PCI bus mentioned above, until all the branches of PCI buses to be tested have finished testing. | 03-26-2009 |
20090100296 | System and method for verifying the transmit path of an input/output component - A system and method for verifying the transmit path of an input/output device such as a network interface circuit. The device's operation with various different input sources (e.g., hosts, input buses) and output sources (e.g., output buses, networks) is modeled in a verification layer that employs multiple queues to simulate receipt of input data, submission to an output port and transmission from the device. Call backs are employed to signal completion of events related to receipt of data at the device and modeling of data processing within the verification layer. As call backs are resolved, corresponding tasks are executed to advance the processing of the data through the verification layer. A device-specific algorithm is executed in the verification layer to predict the ordering of output from the device, and that output is compared to the predicted output by a transmission checker. | 04-16-2009 |
20090100297 | System and method for verifying the receive path of an input/output component - A system and method for verifying the receive path of an input/output device such as a network interface circuit. The device's operation with various different input sources (e.g., networks) and output sources (e.g., hosts, host buses) is modeled in a verification layer that employs multiple queues to simulate receipt of packets, calculation of destination addresses and storage of the packet data by the device. Call backs are employed to signal completion of events related to storage of packet data by the device and modeling of data processing within the verification layer. Processing of tokens within the verification layer to mimic the device's processing of corresponding packets is performed according to a dynamic DMA policy modeled on the device's policy. The policy is dynamic and can be updated or replaced during verification without interrupting the verification process. | 04-16-2009 |
20090113250 | SERVICE TESTING - Communication symmetry is leveraged to facilitate testing of network services. To identify, isolate, understand, and resolve problems a test client is employed. In accordance with one aspect, a service can be provided for execution on a service consumer while the test client resides on a service provider. Roles are reversed to provide more testing freedom on the provider side and less intrusion on the consumer side. Additionally or alternatively, a service and/or test client can be shipped to consumers to aid testing in a real execution environment | 04-30-2009 |
20090119546 | METHOD FOR RECOVERING FROM PCI BUS FAULT, RECORDING MEDIUM AND COMPUTER - A bus fault detecting unit | 05-07-2009 |
20090119547 | SYSTEM AND ARTICLE OF MANUFACTURE FOR HANDLING A FABRIC FAILURE - Provided are a method, system, and program for handling a fabric failure. A module intercepts a signal indicating a failure of a path in a fabric providing a connection to a shared device. The module generates an interrupt to a device driver in an operating system providing an interface to the shared device that is inaccessible due to the path failure. The device driver requests information from the module on a status of a plurality of devices that are not accessible due to the path failure and receives information indicating the inaccessible device. The device driver reconfigures to discontinue use of the inaccessible device. | 05-07-2009 |
20090158096 | Spatial Monitoring-Correlation Mechanism and Method for Locating an Origin of a Problem with an IPTV Network - A spatial monitoring-correlation mechanism and a method are described herein for determining an origin of a problem within an Internet Protocol Television (IPTV) network by using topology information about the IPTV network and at least one error notification (e.g., packet loss notification-retransmission request) that is generated by at least one component (e.g., set-top box) within the IPTV network. | 06-18-2009 |
20090164851 | PRESERVATION OF ERROR DATA ON A DISKLESS PLATFORM - Systems and articles of manufacture for preserving error data on a computing platform that lacks non-volatile storage (e.g., a “diskless” platform) are provided. In response to detecting a platform error (e.g., automatically by hardware, software, or manually by a user when a wait or loop condition is suspected), platform error data may be gathered and temporarily stored in volatile storage accessible on the platform. In order to preserve the platform error data in the event power is lost after the error, the platform error data is transferred to a target system with access to non-volatile storage. Once the target system indicates the platform error data has been stored in non-volatile storage, the volatile storage used to temporarily store the platform error data may be freed-up. | 06-25-2009 |
20090187794 | SYSTEM AND METHOD FOR PROVIDING A MEMORY DEVICE HAVING A SHARED ERROR FEEDBACK PIN - A system and method for providing a memory device having a shared error feedback pin. The system includes a memory device having a data interface configured to receive data bits and CRC bits, CRC receiving circuitry, CRC creation circuitry, a memory device pad, and driver circuitry. The CRC receiving circuitry utilizes a CRC equation for the detection of errors in one or more of the received data and the received CRC bits. The CRC creation circuitry utilizes the CRC equation for the creation of CRC bits consistent with data to be transmitted to a separate device bits. The memory device pad is configured for reporting of any errors detected in the received data and the received CRC bits. The driver circuitry is connected to the memory device pad and merged with one or more other driver circuitries resident on one or more other memory devices into an error reporting line. | 07-23-2009 |
20090187795 | Network performance and reliability evaluation taking into account multiple traffic matrices - Network performability characteristics with improved accuracy are derived by taking into account, in the various analyzed network failure states, attributes of elements at the logical level other than just the capacities of edges, as well as by taking into account one or more “abstract components,” such as scheduled maintenance, and by using multiple traffic matrices. | 07-23-2009 |
20090210751 | METHOD, SYSTEM AND PROGRAM PRODUCT FOR NON-DISRUPTIVE I/O ADAPTER DIAGNOSTIC TESTING - A primary I/O adapter and a redundant I/O adapter of a data processing system are assigned to support access to a system resource. While the primary I/O adapter is in service and the redundant I/O adapter is not in service in providing access to the system resource, a fail over command is issued to remove the primary I/O adapter from service and place the redundant I/O adapter in service in supporting access to the system resource. While the redundant I/O adapter is in service and the primary I/O adapter is not in service in providing access to the system resource, diagnostic testing on the primary I/O adapter is performed. In response to the diagnostic testing revealing no fault in the primary I/O adapter, a fail back command is issued to restore the primary I/O adapter to service and to remove the redundant I/O adapter from service. | 08-20-2009 |
20090217103 | LOGICAL TO PHYSICAL CONNECTIVITY VERIFICATION IN A PREDEFINED NETWORKING ENVIRONMENT - A method, information system, and computer readable storage medium verify predefined connectivity for I/O devices. Current predefined logical connection data and actual physical connection data is gathered. The predefined logical connection data and the actual physical connection data are formatted into a plurality of sortable tables. At least a portion of the predefined logical connection data is formatted into a predefined channels table and at least a portion of the actual physical connection data is formatted into a node information table. The portion of the predefined logical connection data is compared with the portion of the actual physical connection data. The portion of the predefined logical connection data is determined to substantially match/not match the portion of the actual physical connection data. At least one predefined logical connection associated with the predefined logical connection data that fails to substantially match the actual physical connection data is displayed to a user. | 08-27-2009 |
20090222698 | METHOD AND APPARATUS FOR ENTERING MONITOR STATE BY AN ACCESS TERMINAL IN WIRELESS COMMUNICATION SYSTEMS - A method and apparatus for processing of Monitor state by an access terminal is provided, comprising issuing a ControlChannelMAC.Activate command, issuing a ForwardTrafficChannelMAC.Activate command, issuing a SharedSignalingMAC.Activate command, issuing an OverheadMessage.Activate command, setting an internal variable NumAccessAttempts to ‘0’, determining whether a current superframe number is in a PageTimes array, determining whether there is a paging error in the current superframe, if the current superframe is in a PageTimes array, and defining paging error event in Control Channel MAC, if there is a paging error in the current superframe. | 09-03-2009 |
20090249126 | TESTING DEVICE FOR USB I/O BOARD - A testing device for a USB I/O board includes USB plugs connected to the USB I/O board, a connector connected to the USB I/O board, an indication module, and a testing module including data output terminals connected to the USB plugs, data reception terminals connected to the connector, and indication terminals connected to the indication module. The testing module sends a testing signal to the USB I/O board via the data output terminals, and receives the testing signal from the USB I/O board via the data reception terminals. The testing module compares the testing signal to a threshold signal stored in the testing module. If the testing signal and the threshold signal are not substantially the same, the testing module generates an alarm signal to drive the indication module via the indication terminal. The indication module indicates the USB I/O board is abnormal. | 10-01-2009 |
20090265584 | STORAGE CONTROL UNIT WITH CONTROL SIGNAL PATH BETWEEN COUPLED CONTROLLERS - Provided is a storage control unit capable of, even when a failure occurs in access from a control unit to storage devices and the access from the control unit to the storage devices is switched to access via an alternate path, continuing I/O access to the storage devices without interrupting I/O requests from a host. | 10-22-2009 |
20090282293 | SYSTEMS, METHODS AND APPARATUS FOR DETECTING REMOTE CONTROL ERRORS - Apparatus, systems and methods are described that facilitate the detection of errors within a remote control for a controlled device. A remote control detects an error condition during operation and transmits information regarding the error to a controlled device. The information regarding the error may be analyzed to determine the source of the problem in the remote control and/or possible solutions. | 11-12-2009 |
20100011253 | Circuit Arrangement for monitoring errors during signal transmission - A circuit arrangement, having a circuit and a computer unit is provided, in which the circuit and the computer unit are connected to one another via multiple lines for transmitting a number of signals which are embodied as information signals. The circuit has a multiplexer for combining signals, the multiplexer being connected to the computer unit via an additional line. | 01-14-2010 |
20100017661 | METHOD FOR DETECTING A FAULT ON A DATA LINE - Multiple embodiments relate to a method for detecting a fault on a data line in a bus system in a two-line data network having at least two control units. A data signal is emitted by a transmitter-receiver unit on the two data lines as a differential voltage signal that includes a defined quiescent current. The data lines are mutually connected through a resistance bridge for detecting the middle voltage. The middle voltage is detected directly by a microcontroller after a low-pass filter or as a digital value after an analog-to-digital conversion. The result is displayed and/or stored. A circuit arrangement for implementing the method is also provided. | 01-21-2010 |
20100050022 | COMPUTER SYSTEM AND METHOD FOR PERFORMING FAILURE DETECTING PROCESSING FOR A LOGICAL PATH - Provided is a computer system including at least one host computer; and at least one storage system, characterized in that: the storage system has a disk drive and a disk controller, and provides a storage area of the disk drive as at least one logical unit; upon detecting a failure in a logical path serving as an access route from the host computer to the logical unit, the host computer specifies logical paths for accessing the same logical unit that is connected to the logical path where the failure is detected; the host computer executes failure detecting processing for the specified logical paths to judge whether the specified logical paths are normal or not; the host computer selects normal logical paths out of the specified logical paths; and the host computer accesses the logical unit via the normal logical paths selected. | 02-25-2010 |
20100095160 | Storage Area Network (SAN) Link Integrity Tester - A tester that generates various data patterns to assure that link receivers and transmitters are functioning properly (i.e., are functioning according to a relevant network specification) across the entire storage area network. In various embodiments, this tester may be used in Fibre Channel type SANs or in fiber connectivity (FICON) type SANs. | 04-15-2010 |
20100100773 | INPUT/OUTPUT DEVICE WITH CONFIGURATION, FAULT ISOLATION AND REDUNDANT FAULT ASSIST FUNCTIONALITY - A process control system is provided having a plurality of I/O devices in communication using a bus. A primary redundant I/O device and a secondary redundant I/O device are coupled to the bus, where the secondary redundant I/O device is programmed to detect a primary redundant I/O device fault. The secondary redundant I/O device, upon detecting the primary redundant I/O device fault, publishes a primary redundant I/O device fault message on the bus. The controller may deactivate the primary redundant I/O device and activate the secondary redundant I/O device responsive to the primary redundant I/O device fault message. | 04-22-2010 |
20100153787 | METHODS AND APPARATUS TO DETECT AN ERROR CONDITION IN A COMMUNICATION NETWORK - Methods and apparatus to detect an error condition in a communication network are disclosed herein. An example method of detecting an error condition in a communication network includes collecting first metric data from a first endpoint device, the first metric data being related to a first connection between the first endpoint device and a communication network; collecting second metric data from a second endpoint device, the second metric data being related to a second connection between the second endpoint device and the communication network; determining if at least one of the first and second metric data are indicative of the error condition; when the at least one of the first and second metric data are indicative of the error condition, identifying a point of correlation between the first and second connections; identifying a network element based on the point of correlation; and performing an evaluation of the network element. | 06-17-2010 |
20100229046 | Bus Guardian of a User of a Communication System, and a User of a Communication System - A monitoring unit which is locally assigned to a bus controller of a user of a communication system, for monitoring and controlling the access to a data bus. Bus controller accesses data bus via a bus driver, and monitoring unit monitors and controls the access authorization of bus driver to data bus. In order to detect also permanent disturbances of bus controller and resulting errors of bus controller when accessing data bus monitoring unit has an arrangement for implementing a question-answer communication with bus controller and that it enables the bus controller to access data bus only if the question-answer communication establishes a proper functioning of bus controller. | 09-09-2010 |
20100241907 | NETWORK MONITOR AND CONTROL APPARATUS - A network monitor and control apparatus for controlling the monitoring of a network are provided. The network monitor includes an error monitor including an error information gatherer for gathering error information of a monitor target apparatus; and a monitor result notifier for notifying of monitor results, wherein if there are N types of monitor target functions, the error monitor includes N error information gatherers for the respective N types of monitor target functions (N=1, 2, 3, . . . ) and wherein each of the N error information gatherers gathers the error information from one of an existing monitor target apparatus and a newly added monitor target apparatus on a per monitor target function basis. | 09-23-2010 |
20100251030 | Apparatus, System and Method for a Go/No Go Link Integrity Tester - An apparatus, system and method for a go/no go tester that uses various data patterns to assure that equipments, systems and networks using data links, receivers and transmitters are working within the range of predetermined requirements of standards, specifications and protocols. The apparatus, system and methods can be used in at least one of SAS/SATA and Fibre Channel systems based on integrated circuit devices used within the apparatus of the invention. | 09-30-2010 |
20100262869 | Error Detection in a Networked Embedded System - A method for detecting errors in a networked embedded system having a multiplicity of components. Error and/or diagnostic data which are relevant to a component are stored in a set of further components of the networked embedded system and are determined if necessary (for example if a disturbance, error or failure occurs). This method is used, in particular, to find error and/or diagnostic data relating to a failed component of a networked embedded system. | 10-14-2010 |
20110066895 | SERVER NETWORK DIAGNOSTIC SYSTEM - Methods and systems for implementing such methods for providing server fault notifications, diagnostic and system management information may include, but are not limited to: receiving a network fault status request input; illuminating one or more server node fault indicators for one or more degraded server nodes having one or more faults; receiving a server node fault status request input for a degraded server node having one or more faults; and displaying one or more diagnostic service notifications for one or more faults of the degraded server node. | 03-17-2011 |
20110066896 | ATTACK PACKET DETECTING APPARATUS, ATTACK PACKET DETECTING METHOD, VIDEO RECEIVING APPARATUS, CONTENT RECORDING APPARATUS, AND IP COMMUNICATION APPARATUS - A network interface ( | 03-17-2011 |
20110099430 | METHOD AND SYSTEM TO MONITOR A DIVERSE HETEROGENEOUS APPLICATION ENVIRONMENT - A method to detect potential problems within a heterogeneous and diverse application environment. Operations data is received from a plurality of application servers within the application environment. The operations data pertains to operations performed at the plurality of application servers over a predetermined time interval. The operations data is aggregated. The aggregated data is compared to reference data, and a potential problem within the application environment is detected if the aggregated data deviates from the reference data in a predetermined manner. | 04-28-2011 |
20110107152 | METHODS AND SYSTEMS FOR MONITORING QUALITY OF A VIDEO/AUDIO PLAYBACK DEVICE - A computer-implemented method, executable software product, and system for performing a test of an audio/video playback device are described. The audio/video playback device includes at least one main processor, interfaces, and additional processors. The main processor(s) communicate with the additional processors through the interfaces. The method, software product, and system include monitoring at least part of the interfaces for communications between the main processor(s) and the additional processors. The method, system and software product also include storing the communications in a raw format during the test. The method, software product and system also include translating the communications from the raw format to human-readable format after the test concludes and displaying the human-readable format of the communications. In some aspects, the method and system also include reading and storing run time data during the test such that the reading and storing is Heisenberg-friendly. | 05-05-2011 |
20110113290 | METHOD AND SYSTEM FOR TESTING CONFIGURATION OF ENVIRONMENTS - A method and system for testing configuration of environments are provided. A probe for connection to a network and/or devices interacts to launch a configuration analyser tool. The configuration analyser tool includes a test mechanism for running a set of tests for the probe relating to connectivity and configuration of attached networks and devices before connection and suggesting solutions to test results. The tests may be externalised and dynamically loaded at run time of the configuration analyser tool. | 05-12-2011 |
20110126057 | AUTOMATIC TESTING SYSTEM AND METHOD FOR JUDGING WHETHER UNIVERSAL SERIAL BUS DEVICE IS CONFIGURED TO COMPUTER - An automatic testing system and method for judging whether a universal serial bus device is configured to a computer are provided. The automatic testing system includes a computer and a testing device for testing the universal serial bus device. By judging whether the universal serial bus device is configured to the computer, the automatic testing system could determine the timing of performing an automatic testing procedure on the universal serial bus device. | 05-26-2011 |
20110126058 | STORAGE CONTROLLER AND STORAGE CONTROL METHOD - This storage controller includes a port unit and multiple processing units for inputting and outputting data to and from a storage apparatus. The port unit sorts the data I/O requests given from a host system to the corresponding processing units according to a table pre-defining the storage apparatus or a storage area in the storage apparatus to perform data I/O processing allocated to each of the processing units. The processing unit inputs data in the corresponding storage apparatus or the corresponding storage area according to the data I/O request sorted to itself from the port unit and, upon detecting a blockage of the other processing unit due to a failure, updates the table retained in each of the port units so as to sort the storage apparatuses or the storage areas allocated to the other processing unit to the remaining unblocked processing units. | 05-26-2011 |
20110145655 | INPUT/OUTPUT HUB TO INPUT/OUTPUT DEVICE COMMUNICATION - Example apparatus and methods virtualize a circuit disposed between an input/output (I/O) hub and an I/O device. The I/O hub is configured to communicate PCIe slot control and status signals with an I/O device via an interface. The example apparatus and methods selectively intercept and transform signals passing between the I/O hub and the I/O device. The example apparatus and methods may also provide intercepted signals to a sideband monitor. | 06-16-2011 |
20110173502 | UNIVERSAL SERIAL BUS SYSTEM AND METHOD - When a controller identifies a universal serial bus (USB) device connected to a USB interface, it outputs a control signal to close a relay and a first start test signal to an electronic device to test a USB interface of the electronic device. When the test of the USB interface is completed, to the controller adds one to an inside counter, and determines whether the count value reaches a preset count value. If the count value reaches the preset count value, the controller outputs a finish test signal to the electronic device. If the count value does not reach the preset count value, the controller controls the closed relay to open and outputs a second start test signal to close a next relay to test a next USB interface of the electronic device corresponding to the now closed relay. | 07-14-2011 |
20110179312 | System and Method for Recovery From Uncorrectable Bus Errors in a Teamed NIC Configuration - A method for recovery from uncorrectable errors in an information handling system including an operating system (OS) and one or more network interface cards (NICs) is provided. The method may include detecting an uncorrectable error; determining whether the uncorrectable error is isolated to a particular NIC; determining whether the particular NIC is teamed with one or more other NICs; and notifying the OS of a successful recovery from the uncorrectable error if it is determined that (a) the uncorrectable error is isolated to a particular NIC, and (b) the particular NIC is teamed with one or more other NICs. | 07-21-2011 |
20110191637 | Method and apparatus for SAS speed adjustment - A method for maintaining reliable communication between a command initiator and a target device is provided. After the command initiator detects an error corresponding to the target device and a path between the command initiator and the target device, the command initiator performs a downshift evaluation. The initiator maintains a transmission speed if the downshift evaluation determines that forgoing a transmission speed downshift is required, and reduces the transmission speed if the downshift evaluation determines that transmission speed downshift is required. The command initiator then logs the downshift evaluation result and reports any transmission speed change to a user. | 08-04-2011 |
20110258492 | DEVICE FOR TESTING SERIAL INTERFACE - A device for testing a serial interface of a circuit board. The device includes a testing serial interface, a memory, a processor. The testing serial interface is coupled to the serial interface of the circuit board. The processor is electrically connected between the memory and the at least one testing serial interface. The processor is configured for receiving first serial data from the circuit board via the testing serial interface, converting the first serial data to parallel data, and writing the parallel data into the memory, and also configured for reading the parallel data from the memory, converting the parallel data to second serial data and transmits the second serial data to the circuit board via the testing serial interface. | 10-20-2011 |
20110283151 | INTERNET SERVER APPARATUS AND PROGRAM CAUSING A SERVER APPARATUS TO IMPLEMENT FUNCTIONS OF PREPARATION PROCESSING FOR DIRECT CONNECTION OF AN APPLIANCE IN A PRIVATE NETWORK AND A MOBILE TERMINAL OUTSIDE THE PRIVATE NETWORK - A server apparatus, a mobile terminal, an electric appliance, a communication system, a communication method and a program for notifying a mobile terminal user in the open of the cause of a failure of P2P connection. In a communication system, an electric appliance ( | 11-17-2011 |
20110320881 | ISOLATION OF FAULTY LINKS IN A TRANSMISSION MEDIUM - Isolation of faulty links in a transmission medium including a method that includes receiving an atomic data unit via a multi-link transmission medium that has a plurality of transmission links An error condition is detected and it is determined that the error condition is isolated to a single transmission link. It is determined if the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer. If the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer then: identifying the single transmission link as a faulty transmission link; resetting the timer; and outputting an identifier of the single transmission link. | 12-29-2011 |
20120005539 | Peripheral Component Interconnect Express Root Port Mirroring - An information handling system includes a peripheral component interconnect express root complex, a basic input output system, and a root complex mirroring block. The peripheral component interconnect express root complex includes a plurality of peripheral component interconnect express ports. The basic input output system is in communication with the peripheral component interconnect express root complex, and is configured to detect a peripheral component interconnect express adaptor configuration, and to set a peripheral component interconnect express mirroring setting based on the peripheral component interconnect express adaptor configuration. The root complex mirroring block is in communication with the basic input output system, and is configured to mirror data between a first peripheral component interconnect express adaptor and a second peripheral component interconnect express adaptor based on the peripheral component interconnect express mirroring setting. | 01-05-2012 |
20120017121 | MONITORING NETWORK PERFORMANCE AND DETECTING NETWORK FAULTS USING ROUND TRIP TRANSMISSION TIMES - A computer program product is provided for performing a method including: receiving transmission data over a selected time interval for each of a plurality of communication paths; calculating an average round-trip transmission time for each of the plurality of communication paths over the time interval; comparing an average round-trip transmission time for a communication path having the highest average round-trip transmission time to a threshold value and to a multiple of an average round-trip transmission time for a communication path having the lowest average round-trip transmission time; and determining, based on a result of comparing the highest round-trip transmission time to the threshold value and to a multiple of the lowest round-trip transmission time, whether the time period indicates a delay in communication between the I/O subsystem and the control unit requiring at least one of a monitoring action and a recovery action. | 01-19-2012 |
20120017122 | INPUT/OUTPUT DEVICE WITH CONFIGURATION, FAULT ISOLATION AND REDUNDANT FAULT ASSIST FUNCTIONALITY - A process control system is provided having a plurality of I/O devices in communication using a bus. A primary redundant I/O device and a secondary redundant I/O device are coupled to the bus, where the secondary redundant I/O device is programmed to detect a primary redundant I/O device fault. The secondary redundant I/O device, upon detecting the primary redundant I/O device fault, publishes a primary redundant I/O device fault message on the bus. The controller may deactivate the primary redundant I/O device and activate the secondary redundant I/O device responsive to the primary redundant I/O device fault message. | 01-19-2012 |
20120030519 | INTEGRATED DISSIMILAR HIGH INTEGRITY PROCESSING - A self-checking network is provided, comprising a first command processor configured to execute a performance function and a second command processor configured to execute the performance function, coupled to the first command processor. The self-checking network also comprises a first monitor processor configured to execute a monitor function that is coupled to the first command processor and a second monitor processor configured to execute the monitor function that is coupled to the second command processor. The first and second command processors compare outputs, the first and second monitor processors compare outputs, and the first monitor processor determines whether an output of the first command processor exceeds a first selected limit. | 02-02-2012 |
20120144245 | COMPUTING DEVICE AND METHOD FOR DETECTING PCI SYSTEM ERRORS IN THE COMPUTING DEVICE - A method for detecting peripheral component interconnect (PCI) system errors is applied in a computing device. The computing device includes a north bridge, a baseboard management controller (BMC) connected to the north bridge, and a PCI bus connected to the north bridge. The north bridge detects a PCI system error of the PCI bus, and notifies the BMC of the PCI system error. In response to notification of the PCI system error, the BMC records error information of the PCI system error in a storage system of the computing device. | 06-07-2012 |
20120166886 | NON-DISRUPTIVE FAILOVER OF RDMA CONNECTION - A novel RDMA connection failover technique that minimizes disruption to upper subsystem modules (executed on a computer node), which create requests for data transfer. A new failover virtual layer performs failover of an RDMA connection in error so that the upper subsystem that created a request does not have knowledge of an error (which is recoverable in software and hardware), or of a failure on the RDMA connection due to the error. Since the upper subsystem does not have knowledge of a failure on the RDMA connection or of a performed failover of the RDMA connection, the upper subsystem continues providing requests to the failover virtual layer without interruption, thereby minimizing downtime of the data transfer activity. | 06-28-2012 |
20120204066 | Diagnostics for a Serial Communications Device - A serial communications device comprises a controller to obtain digital diagnostic data representative of operational characteristics of the serial communications device, memory to store the digital diagnostic data and at least one interface, including an interface to serially communicate data via a serial cable. The serial communications device also comprises a signal controller configured to encode the digital diagnostic data onto a serial data signal for transmission via the serial cable by adjusting signal levels of the serial data signal while preserving original data in the serial data signal. Encoding the digital diagnostic data includes serializing the digital diagnostic data, determining a series of signal levels for the serialized digital diagnostic data based on a signal encoding map, and adjusting signal levels for the serial data signal based on the determined series of signal levels. | 08-09-2012 |
20120304017 | SYSTEMS AND METHODS FOR 1553 BUS OPERATION SELF CHECKING - Systems and methods for 1553 bus operation self checking are provided. In one embodiment, a fault tolerant computer comprises a self-checking processor pair that includes a master processor, a checking processor, and self-checking pair logic; a 1553 bus transceiver; and a device comprising 1553 self-checking logic coupled between the self-checking processor pair and the 1553 bus transceiver, wherein the 1553 self-checking logic manages data communication between the 1553 bus transceiver and the self-checking processor pair. The 1553 self-checking logic includes a primary logic and a secondary logic that operate in lock-step. When the 1553 self-checking logic writes data to the 1553 bus transceiver, the 1553 self-checking logic compares a first 1553 formatted message generated by the primary logic to a second 1553 formatted message generated by the secondary logic, and generates an error indication when the first 1553 formatted message does not match the second 1553 formatted message. | 11-29-2012 |
20120317446 | COMPLIANCE MODE DETECTION FROM LIMITED INFORMATION - Consistent with embodiments of the present disclosure, a method involves a redriver circuit with compliance test mode features. A redriver circuit is configured to process received compliance patterns for a compliance test mode. A compliance test mode is detected by a redriver circuit having a first input port and a second input port. The redriver detects the presence of a remote receiver termination on both input ports, monitors both input ports to detect received data and enters compliance test mode in response to no received data being detected on the input ports for a set period of time. Compliance patterns are tracked by monitoring for valid signal levels on the second input port. De-emphasis is controlled on at least one input port in response thereto. | 12-13-2012 |
20130013962 | COMPUTING DEVICE AND METHOD FOR ANALYZING INTEGRALITY OF SERIAL ATTACHED SCSI SIGNALS - In a method for analyzing integrality of serial attached SCSI (SAS) signals using a computing device, the computing device connects to a signal measuring device and an electronic device. A group of test parameters, an intensity grade of a SAS signal, and a total number are set for evaluating integrality of the SAS signal. The intensity grade of the SAS signal is adjusted through an SAS interface of the electronic device. The signal measuring device measures test parameters of the SAS signal, and a test number is recorded when the test parameters of the SAS are measured. The method analyzes the integrality of the SAS signal to find an optimal SAS signal when the test number equals the total number, and determines an intensity grade of the optimal SAS signal as a driving parameter of the SAS interface. | 01-10-2013 |
20130139005 | USB TESTING APPARATUS AND METHOD - A Universal Serial Bus (USB) testing apparatus includes a Central Processing Unit (CPU); a Southbridge; a Baseboard Management Controller (BMC), connected with the Southbridge via USB. The BMC determines if a test starts or finishes, generates a first instruction of creating a virtual control computer when determining the test starts, creates a control module and a comparing module in a memory unit which are running to become the virtual control computer, and connects the memory unit with the BMC according to the first instruction. The control module sends control data to the CPU. The comparing module obtains feedback data from the CPU and compares the control data with the obtained data to determine if the control data is consistent with the obtained data, thereby determining whether the USB is working normally. | 05-30-2013 |
20130191692 | INITIALIZATION OF GPU USING ROM-BASED INITIALIZATION UNIT AND PROGRAMMABLE MICROCONTROLLER - An approach is disclosed for performing initialization operations for a graphics processing unit (GPU). The approach includes detecting errors while performing one or more initialization operations. Further, the approach includes releasing a holdoff on a communication link that couples the GPU to a memory bridge and causing debug output to be displayed to a user that indicates the error. | 07-25-2013 |
20130238942 | PORT TEST DEVICE FOR MOTHERBOARDS - A port test device for a motherboard includes a conversion member and a test apparatus. The motherboard comprising a serial attached small computer system interface (SAS) port and a serial advanced technology attachment (SATA) port. The conversion member includes a SAS connector and a SATA connector, the SATA connector is coupled to the SATA port, and is electronically connected to the SAS port. The test apparatus is selectively coupled to the SAS port or the SAS connector. | 09-12-2013 |
20130297976 | Network Fault Detection and Reconfiguration - Scalable means are provided for diagnosing the health of a parallel system comprising multiple nodes interconnected using one or more switching networks. The node pings other nodes via different paths at regular intervals. If more than a threshold number of pings are missed from a node, the system performs fault detection by entering a freeze state in which nodes do not send or receive any messages except ping messages. If ping messages still fail to reach destination nodes, the parallel system identifies faulty components that are causing ping messages to fail. Once the faulty component is identified, the parallel system is unfrozen by allowing nodes to communicate all messages. If redundant computers and/or switches are present, the parallel system is automatically reconfigured to avoid the faulty components. | 11-07-2013 |
20130326280 | DEBUGGING METHOD, CHIP, BOARD, AND SYSTEM - Embodiments of the present invention provide a debugging method, a chip, a board, and a system and relate to the communications field. Remote debugging can be performed on a board having no main control CPU without affecting hardware distribution and software performance. The method includes: receiving, by an Ethernet port, a data packet and determining a current service type according to a service identifier carried in the data packet; when determining the current service type is a debugging service, writing the data packet into a memory through a bus and sending an interruption notification to a CPU through the bus; reading, by the CPU, the data packet from the memory according to the interruption notification, obtaining a debugging instruction by parsing the data packet, and sending the debugging instruction to an ASIC through a protocol conversion module. | 12-05-2013 |
20140025999 | TWO-WIRE COMMUNICATION SYSTEM FOR HIGH-SPEED DATA AND POWER DISTRIBUTION - Various embodiments of the present invention provide a two-wire (e.g., unshielded twisted pair) bus system that is simple (e.g., no microcontroller required in slave devices), synchronous with embedded clock information, inexpensive, automotive EMC compliant, and has sufficient speed and bandwidth for a large number of slave devices/peripherals, and also provides various protocols that can be used in various communication systems such as a two-wire bus system. The two-wire bus optionally may be self-powered, i.e., the master device may provide power to the slave devices over the two-wire bus. | 01-23-2014 |
20140108870 | Concurrent Host Operation And Device Debug Operation WIth Single Port Extensible Host Interface (XHCI) Host Controller - An improved USB host controller and method supports concurrent host and device debug operations with only one usable USB port. The described embodiments save silicon cost and avoid additional connectors, which are undesirable in ever-smaller devices. | 04-17-2014 |
20140115404 | DIAGNOSTIC AND MANAGING DISTRIBUTED PROCESSOR SYSTEM - A network of microcontrollers for monitoring and diagnosing the environmental conditions of a computer is disclosed. The network of microcontrollers provides a management system by which computer users can accurately gauge the health of their computer. The network of microcontrollers provides users the ability to detect system fan speeds, internal temperatures and voltage levels. The invention is designed to not only be resilient to faults, but also allows for the system maintenance, modification, and growth—without downtime. Additionally, the present invention allows users to replace failed components, and add new functionality, such as new network interfaces, disk interface cards and storage, without impacting existing users. One of the primary roles of the present invention is to manage the environment without outside involvement. This self-management allows the system to continue to operate even though components have failed. | 04-24-2014 |
20140122938 | TEST APPARATUS - A test apparatus for a server includes a first connection unit coupled to a mother board of the server, a second connection unit coupled to a device under test, a data transmission unit, a processing unit, and a network unit. According to a selection signal, the data transmission unit switches one of data transmission modes to perform data transmission between the first connection unit and the second connection unit. The processing unit controls the data transmission unit to perform a first test program for the mother board through the first connection unit, or perform a second test program for the device under test through the first connection unit and the second connection unit. The network unit receives a control signal generated by an external apparatus, so that the external apparatus controls the processing unit to perform the first test program and the second test program through the network unit. | 05-01-2014 |
20140143607 | Dedicated Network Diagnostics Module for a Process Network - A network diagnostic module coupleable to a distributed process control network that controls an industrial process via field devices coupled to the network includes a power block coupleable to the network and configured to power the network diagnostic module with energy received from the network, a communications block coupleable to the network and configured to bi-directionally communicate over the network, and a diagnostics block coupleable to the network and configured to make diagnostic measurements of network and protocol parameters of the network. The network diagnostic module is not itself a field device that detects or controls any process variable of the industrial process, enabling the network diagnostic module to be placed essentially anywhere along the network to permanently monitor the network. | 05-22-2014 |
20140149801 | METHOD AND APPARATUS FOR ISOLATING A FAULT IN A CONTROLLER AREA NETWORK - A controller area network (CAN) has a plurality of CAN elements including a communication bus and controllers. A method for monitoring the CAN includes identifying each of the controllers as one of an active controller and an inactive controller. A fault-active controller isolation process is executed to detect and isolate presence of a fault-active controller. A fault isolation process can be executed to detect and isolate presence of one of a wire open fault, a wire short fault and a controller fault when one of the controllers is identified as an inactive controller. Presence of a fault associated with a persistent bus disturbance in the CAN is detected when a bus error count is greater than a predetermined threshold continuously for a predetermined period of time. | 05-29-2014 |
20140189435 | System and method to extend the capabilities of a web browser of a web application issue root cause determination techniques - Disclosed is a system and method for extending the web application root cause determination functionality to a web browser. In one aspect, the present invention plots the network topology diagram for the web application by executing network trace commands. In another aspect, the present invention allows user to upload their web application network topology diagram. In another aspect, the present invention allows user to build their web application network topology diagram using UI Devices Toolkit. The present invention collects the information relating to the web application issue from various entities such as network infrastructure devices, servers through ICMP, SNMP, TRAP, SYS/APPLOG, HTTP and Network traffic analysis. In one aspect, the present invention highlights the entity in the web application network topology diagram based on the collected information and provides the experts recommended suggestion for the issue through Internet web search query. | 07-03-2014 |
20140195859 | Automated Testing of Hot Swap Scenarios of Field Replaceable Units in a Storage System - System and method for automated testing of hot swap scenarios of field replaceable units (FRUs) in a storage system comprises an external automation server that distributes control signals to actuation systems within a number of FRUs. Power for the actuation systems may be provided by the external automation server or by self-contained power supplies with each actuation system. The actuation systems are responsive to the control signals to move the storage devices back-and-forth thereby electrically and physically disconnecting the storage device's mating connector from the backplane connector. This approach provides a high degree of automation while closely emulating customer hot swap scenarios. | 07-10-2014 |
20140289570 | VIRTUAL BASEBOARD MANAGEMENT CONTROLLER - A system firmware agent providing the capabilities of a Baseboard Management Controller (BMC) from within System Management Mode (SMM) is discussed. A virtual BMC provides dedicated communication channels for system firmware, other BMCs in the platform and remote management agents. The virtual BMC may monitor the status of the system, record system events, and control the system state. | 09-25-2014 |
20140304554 | ENABLING COMMUNICATION OVER CROSS-COUPLED LINKS BETWEEN INDEPENDENTLY MANAGED COMPUTE AND STORAGE NETWORKS - Embodiments relate to providing communication over cross-coupled links between independently managed compute and storage networks. An aspect includes coupling an independently managed local subsystem with an independently managed remote subsystem over cross-coupled links, whereby each subsystem includes compute entities and storage entities. Unique identifiers are assigned to all the compute entities and the storage entities in the local network and the remote network. A determination is then made as to whether each entity is in the local subsystem or the remote subsystem. Accordingly, a global broadcast tree is built to bridge the compute entities in the local subsystem to the storage entities in both the local and remote subsystem. Responsive to an error in a layer of the local subsystem external to a cross-coupled link, the cross-coupled link in the local subsystem is disabled. Accordingly, the remote subsystem may detect that the link has failed. | 10-09-2014 |
20140304555 | UNIVERSAL SERIAL BUS TESTING DEVICE - A USB testing device is provided for an electronic device having a USB port. The USB testing device includes a first USB control unit, a second USB control unit, and a micro-processor. When the first USB control unit has received power, the first USB control unit processes a connection test via a first data port. When the second USB control unit has received the power, the second USB control unit processes a connection test via a second data port. When the USB testing device is connected to the USB port, the micro-processor provides power to the first USB control unit. When the first USB control unit receives power, the first USB control unit provides power to the second USB control unit after waiting for a predetermined period of time. The electronic device determines whether the first and second data ports are operating properly. | 10-09-2014 |
20140325285 | SERIAL ATTACHED SCSI EXPANDER AND METHOD FOR DEBUGGING FAULTS THEREOF - Serial Attached SCSI (SAS) expander includes an exposed SAS interface connector, a microcontroller unit (MCU), a smart port, and an SAS expander chip. The SAS interface connector is coupled to a host personal computer (PC) to receive commands sent from the host PC. When a fault occurs in the SAS expander or a connected storage device, the MCU enables the smart port in response to a first control command sent from the host PC, reads status information from the SAS expander chip through the smart port in response to a status reading command sent from the host PC, and sends read status information back to the host PC for analyzing. MCU obtains detailed fault information from the SAS expander chip through the smart port in response to a detailed fault information obtaining command sent from the host PC and sends the obtained detailed fault information back to the host PC. | 10-30-2014 |
20140337674 | Network Testing - A network testing method implemented in a software-defined network (SDN) is disclosed. The network testing method comprising providing a test scenario including one or more network events, injecting said one or more network events to the SDN using an SDN controller, and gathering network traffic statistics. A network testing apparatus used in a software-defined network (SDN) also is disclosed. The network testing apparatus comprising a testing system to provide a test scenario including one or more network events, to inject said one or more network events to the SDN using an SDN controller, and to gather network traffic statistics. Other methods, apparatuses, and systems also are disclosed. | 11-13-2014 |
20140351654 | PCIE SWITCH-BASED SERVER SYSTEM, SWITCHING METHOD AND DEVICE - A PCIE switch-based server system, switching method and device are disclosed. The system includes: an active PCIE switch device, where the active PCIE switch device includes a communication interface and a first PCIE switch module, and the first PCIE switch module includes at least two first PCIE ports; a standby PCIE switch device, where the standby PCIE switch device includes a communication interface and a first PCIE switch module, and the first PCIE switch module includes at least two first PCIE ports; where the communication interface of the active PCIE switch device and the communication interface of the standby PCIE switch device are interconnected, so that the standby PCIE switch device obtains switch network configuration information of the active PCIE switch device through the communication interface of the active PCIE switch device and the communication interface of the standby PCIE switch device. | 11-27-2014 |
20140359373 | SYSTEMS AND METHODS TO DETECT BUS NETWORK FAULT AND TOPOLOGY - Systems for helping identify faults on a bus, as well as to determine the topology of a bus network, are disclosed. A system according to one embodiment includes a bus interface for connecting to a bus and a switch coupled to the bus interface, the switch configured to alternate between an open state and a closed state. The system is connected to the bus via the bus interface when the switch is in the closed state, and the system is disconnected from the bus via the bus interface when the switch is in the open state. | 12-04-2014 |
20140365832 | TECHNIQUES AND CONFIGURATIONS FOR COMMUNICATION BETWEEN DEVICES - Techniques and configurations are disclosed herein for communication between devices. In some embodiments, a bus for communication between first and second devices may include a transmit buffer and one or more processing devices. The one or more processing devices may be configured to receive first asynchronous data from an operating system, running on a central processing unit of the first device, on an operating system signal path; transmit the first asynchronous data from the first device to the second device on a command signal path; transmit first data from the transmit buffer to the second device at a first fixed packet frequency on a transmit signal path; and receive data from the second device at a second fixed packet frequency on a receive signal path different from the transmit signal path. Other embodiments may be disclosed and/or claimed. | 12-11-2014 |
20140380103 | ELECTRONIC DEVICE CAPABLE OF BEING DEBUGGED VIA EARPHONE PORT - An electronic device includes an earphone port, an audio amplifier, a digital processor, a multi-way selection switch, and an earphone detection response circuit. The earphone port includes left and right channel pins. The audio amplifier includes an earphone left channel output pin and an earphone right channel output pin. The digital processor includes a data transmission pin and a data receive pin. The multi-way selection switch includes four switches electrically connected between the data transmitting pin and the left channel pin, the data receive pin and the right channel pin, the earphone left channel output pin and the left channel pin, and the earphone right channel output pin and the right channel pin, respectively. The earphone detection response circuit turns on a first switch and a second switch, and turns off a third switch and a fourth switch when the earphone port does not receive an earphone. | 12-25-2014 |
20150026526 | TECHNIQUES FOR TESTING ENCLOSURE MANAGEMENT CONTROLLER USING BACKPLANE INITIATOR - One aspect of the present disclosure relates to a backplane initiator for testing enclosure management controller. The backplane initiator includes: an initiator board and an initiator control application. The initiator board includes initiator controller, at least one SGPIO interface, at least one SMBus interface, and a first communication interface. The initiator controller is configured to transmit control commands and data according to enclosure management protocol through the SGPIO interface and the SMBus interface to an EMC. The initiator control application, when executed on a computing device having a second communication interface in communication with the first communication interface, is configured to establish a communication channel with the initiator controller through the first and second communication interfaces, and instruct the initiator controller to transmit a first control command and first control data according to enclosure management protocol through the SGPIO interface and the SMBus interface to the EMC. | 01-22-2015 |
20150039944 | System and Method of High Integrity DMA Operation - A system and method for direct memory access (DMA) operation provides for receiving DMA requestors, assigning the received DMA requestors to one or more of a plurality of DMA engines for processing the received DMA requestors, and if one of the received DMA requestors is a safety requestor, assigning the safety requestor to at least two DMA engines of the plurality of DMA engines for processing the safety requestor, disabling a bus interface for coupling at least one DMA engine of the at least two DMA engines to memories, comparing the outputs of the at least two DMA engines, and generating an error message if the comparison of the outputs of the at least two DMA engines are different from each other. | 02-05-2015 |
20150052404 | OVERRIDING LATENCY TOLERANCE REPORTING VALUES IN COMPONENTS OF COMPUTER SYSTEMS - The disclosed embodiments provide a system that operates a processor in a computer system. During operation, the system uses the processor to maintain a count of outstanding input/output (I/O) requests for a component in the computer system. Next, the system facilitates efficient execution of the processor by overriding a latency tolerance reporting (LTR) value for the component based on the count. | 02-19-2015 |
20150074466 | COORDINATION OF SPARE LANE USAGE BETWEEN LINK PARTNERS - Various examples of techniques for identifying a corrupt data lane and using a spare data lane are described herein. Some examples include a method of coordinating spare lane usage between link partners. One such example comprises analyzing data from a link partner to identify a corrupt lane, and communicating the corrupt lane to the link partner, wherein the communication does not require sideband communication channel. In some embodiments, communicating the corrupt lane to the link partner comprises identifying a transmit lane corresponding to the corrupt lane, transmitting a set of data intended for a corresponding transmit lane using a spare data lane, and transmitting bad data to the link partner using the corresponding transmit lane. | 03-12-2015 |
20150095713 | Diagnosis For A Server Motherboard - A server motherboard diagnosis method, system, and related circuit system. A management module of the server motherboard and peripheral devices managed by the management module are capable of being powered by a server power source and a USB port. In response to the management module and the peripheral devices being powered by the USB port, a power supply line of the server power source is isolated, as by: identifying the peripheral devices, in response to the management module and the peripheral devices being powered by the USB port; for each of the identified peripheral devices, initializing the peripheral device, and then shutting down the power supply of the peripheral device; establishing a communication between the management module and a diagnosis host through the USB port; and executing a command in response to the command being received from the diagnosis host. | 04-02-2015 |
20150095714 | Diagnosis For A Server Motherboard - A server motherboard diagnosis method, system, and related circuit system. A management module of the server motherboard and peripheral devices managed by the management module are capable of being powered by a server power source and a USB port. In response to the management module and the peripheral devices being powered by the USB port, a power supply line of the server power source is isolated, as by: identifying the peripheral devices, in response to the management module and the peripheral devices being powered by the USB port; for each of the identified peripheral devices, initializing the peripheral device, and then shutting down the power supply of the peripheral device; establishing a communication between the management module and a diagnosis host through the USB port; and executing a command in response to the command being received from the diagnosis host. | 04-02-2015 |
20150113333 | DATA PROCESSING SYSTEM AND OPERATING METHOD THEREOF - An operating method of a data processing system includes calculating a test result by performing a test for measuring characteristics of each of lanes included in the data processing system, and selecting one or more operating lanes among the lanes based on the test result. | 04-23-2015 |
20150121149 | ERROR DETECTION ON A LOW PIN COUNT BUS - Systems and methods that implement communication of error information on a bus, including a bus having a small number of pins are disclosed. In one embodiment, an apparatus includes an interface circuit configured to couple to a bus and one or more sideband signals. The sideband signals may be used to communicate error information such as parity information for a bus that does not otherwise have this capability. In some embodiments, parity information may be driven on the bus during a portion of a bus transaction corresponding to unused address bits. | 04-30-2015 |
20150149832 | BUS PRESSURE TESTING SYSTEM AND METHOD THEREOF - A bus pressure testing system and method thereof are disclosed, where a peripheral component interconnect express (PCI-E) device is used to initialize a central processing unit (CPU), peripheral component interface express (PCI-E) device interface and memory according to a testing model, generate a data transmission path corresponding to the testing model, produce a pressure data stream by using the PCI-E device, and test a bus for its pressure by flowing the pressure data transmission stream on the data transmission path. As such, the pressure testing may be enhanced in practicability. | 05-28-2015 |
20150301916 | user station of a bus system and method for transmitting data between user stations of a bus system - A user station ( | 10-22-2015 |
20150324261 | Data Encoding Using Spare Channels in a Memory System - Implementations of encoding techniques are disclosed. The encoding technique, such as a Data bus Inversion (DBI) technique, is implementable in a vertically-stacked memory module, but is not limited thereto. The module can be a plurality of memory integrated circuits which are vertically stacked, and which communicate via a bus formed in one embodiment of channels comprising Through-Wafer Interconnects (TWIs), but again is not limited thereto. One such module includes spare channels that are normally used to reroute a data signal on the bus away from faulty data channels. In one disclosed technique, the status of a spare channel or channels is queried, and if one or more are unused, they can be used to carry a DBI bit, thus allowing at least a portion of the bus to be assessed in accordance with a DBI algorithm. Depending on the location and number of spare channels needed for rerouting, DBI can be apportioned across the bus in various manners. Implementations can also be used with other encoding techniques not comprising DBI. | 11-12-2015 |
20150324265 | TESTING I/O TIMING DEFECTS FOR HIGH PIN COUNT, NON-CONTACT INTERFACES - Indirect testing of multiple I/O interface signal lines concurrently. A system distributes a test data sequence to a group of signal lines. Each signal line receives the test data sequence and checks for errors in receiving the test data sequence at an associated I/O buffer. The system includes an error detection mechanism for each signal line. The system also includes an error detection mechanism for the group of multiple signal lines. If the I/O buffer receives any bit of the test data sequence incorrectly, the signal line error detection indicates an error. The group error detection accumulates pass/fail information for all signal lines in the group. Rather than sending a pass/fail indication on every cycle of the test, the group error detection can count pass/fail information for all signal lines of the group for all bits of the test data sequence and indicate error results after the entire test data is received. | 11-12-2015 |
20150324268 | Method, Device, and System for Processing PCIe Link Fault - In a Peripheral Component Interconnect Express (PCIe) system, a first PCIe apparatus determines that at least one of lanes of a link between the first PCIe apparatus and a second PCIe apparatus is disabled, wherein the link includes M lanes numbered in a first order. Based upon the determination, the first PCIe apparatus obtains a number N indicating a number of available lanes of the link by performing a lane negotiation with the second PCIe apparatus. Then, a processor determines that N11-12-2015 | |
20150370296 | Power Sequencing by Slave Power Sequencers Sharing a Command Bus - Embodiments provide apparatuses and systems in which slave power sequencers share a command bus and power sequence respective power groups through power sequence states of a power sequencing protocol in response to commands on the command bus. In some examples, a system may include a master power sequencer to output onto a command bus a command to perform a power sequencing protocol for transitioning the system from a first power state to a second power state, and a plurality of slave power sequencers sharing the command bus, each slave power sequencer to power sequence a respective power group to a next power sequence state in response to the command. Other examples are described and claimed. | 12-24-2015 |
20150370671 | TEST VIRTUAL VOLUMES FOR TEST ENVIRONMENTS - For test virtual volume operation testing, an identification module determines if an input/output (I/O) operation for a test virtual volume is directed to volume contents data. A disposition module executes the I/O operation in response to the I/O operation being directed to the volume contents data and declines the I/O operation in response to the I/O operation not being directed to the volume contents data. | 12-24-2015 |
20150370683 | APPARATUS AND METHOD FOR IDENTIFYING A CAUSE OF AN ERROR OCCURRING IN A NETWORK CONNECTING DEVICES WITHIN AN INFORMATION PROCESSING APPARATUS - An information processing apparatus includes a plurality of devices, each including a memory that stores link-status information indicating whether or not an error occurs in a link connected to the each device. When a first device among the plurality of devices fails to receive within a predetermined time period a response for a request that has been transmitted by the first device, the first device obtains the link-status information from relevant devices each related to at least one of transfer of the request and transfer of the response, and identifies a link in which the error has occurred or a device that is connected to the link, based on the obtained link-status information. | 12-24-2015 |
20160004617 | AUTOMATIC TEST PATTERN GENERATION FOR A RECONFIGURABLE INSTRUCTION CELL ARRAY - An instruction cell array is provided that comprises an array of tiles. Each tile includes a set of input/output (I/O) ports for switching between a plurality of input channels and a plurality of corresponding output channels. In addition, each tile includes an instruction cell comprising a plurality of dedicated logic gates for producing an instruction cell output from selected ones of the tile's input channels. Each I/O port is configured to select from the tile's instruction cell output and from the input channels for the remaining I/O ports for the tile to form the I/O port's output channels. To prevent combinatorial loops during an automatic test pattern generation (ATPG) of the array, the instruction cell array disclosed herein is configured in the testing mode such at least a subset of the I/O ports for each tile prevent any of their output channels from being formed as combinatorial signals. | 01-07-2016 |
20160055070 | SEMICONDUCTOR DEVICE AND FAULT DETECTION METHOD THEREFOR - According to one embodiment, a semiconductor device includes a memory-transfer control unit that controls data transfer between a memory and a sound unit. A plurality of sound data transfer routes are configured by one memory-transfer control unit and one sound unit. The semiconductor device outputs reproduction sound data via at least one sound data transfer route and acquires at least two pieces of recording sound data on account of one piece of reproduction sound data via at least two sound data transfer routes. | 02-25-2016 |
20160077942 | STORAGE SYSTEM AND TEST METHOD FOR TESTING PCI EXPRESS INTERFACE - Provided is a storage system and a test method for a testing Peripheral Component Interconnect Express (PCI Express) interface. The storage system of the present invention includes a plurality of DMA memory units storing test data, a data processing unit connected to the plurality of DMA memory units, wherein a predetermined amount of data is transmitted at least once from a first processing (such as an SAS control chip) to the plurality of DMA memory units through a PCI Express interface and the data processing unit, transmission information is generated and recorded during data transmission, and the transmission information is outputted by the data processing unit while data transmission is completed or an interrupt is generated due to an error occurred during data transmission, and a test unit testing the PCI Express interface based on the transmission information outputted by the data processing unit. | 03-17-2016 |
20160092392 | ADAPTIVE TERMINATION SCHEME FOR LOW POWER HIGH SPEED BUS - Methods and apparatus relating to an adaptive termination scheme for a low power, high speed bus are described. In an embodiment, logic at least partially causes termination of a portion (e.g., one or more transmission lines) of an interconnect. The logic adaptively optimizes the number of lines that are to be terminated based on one or more operating conditions of the interconnect. Other embodiments are also disclosed. | 03-31-2016 |
20160110275 | METHOD AND APPARATUS FOR OFFLOADING FUNCTIONAL DATA FROM AN INTERCONNECT COMPONENT - An interconnect offload component arranged to operate in an offloading mode, and a memory access component for enabling access to a memory element for functional data transmitted over a debug network of a signal processing device. In the offloading mode the interconnect offload component is arranged to receive functional data from an interconnect client component for communication to a destination component, and forward at least a part of the received functional data to a debug network for communication to the destination component via the debug network. The memory access component is arranged to receive a debug format message transmitted over the debug network, extract functional data from the received debug format message, said functional data originating from an interconnect client component for communication to a memory element, and perform a direct memory access to the memory element comprising the extracted functional data. | 04-21-2016 |
20160132089 | SYSTEM AND METHOD FOR DISTRIBUTING ELECTRICAL POWER - A bus for distributing electrical power to a plurality of sets of electrical devices is disclosed. The bus includes one or more bus separators and a plurality of bus sections. The plurality of bus sections includes at least a first bus section and a second bus section electrically coupled to each other via a bus separator, where the first bus section is electrically connectable to a first set of electrical devices having a first importance metric and the second bus section is electrically connectable to a second set of electrical devices having a second importance metric different from the first importance metric. The bus separator is configured to isolate the first bus section and the second bus section based on occurrence of a fault condition. A Direct Current power distribution system employing the bus and a method for distributing electrical power via the bus are also disclosed. | 05-12-2016 |
20160147628 | DETECTING AND SPARING OF OPTICAL PCIE CABLE CHANNEL ATTACHED IO DRAWER - A method, system and computer program product are provided for detecting state and sparing of optical Peripheral Component Interconnect Express (PCI-Express or PCIE) cable channels attached to an IO drawer. System firmware is provided for implementing health check functions and state detection and sparing functions. One or more optical cables are connected between a host bridge and a PCIE enclosure, each optical cable includes one or more spare optical channels. An identified failed optical channel is rerouted to the spare optical channel. | 05-26-2016 |
20160196194 | AUTOMATIC HARDWARE RECOVERY SYSTEM | 07-07-2016 |