| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 711208000 | Segment or page table descriptor | 25 |
| 20080263315 | COMPUTER MEMORY ADDRESSING MODE EMPLOYING MEMORY SEGMENTING AND MASKING - A computer addressing mode and memory access method rely on a memory segment identifier and a memory segment mask for indicating memory locations. In this addressing mode, a processor receives an instruction comprising the memory segment identifier and memory segment mask. The processor employs a two-level address decoding scheme to access individual memory locations. Under this decoding scheme, the processor decodes the memory segment identifier to select a particular memory segment. Each memory segment includes a predefined number of memory locations. The processor selects memory locations within the memory segment based on mask bits set in the memory segment mask. The disclosed addressing mode is advantageous because it allows non-consecutive memory locations to be efficiently accessed. | 10-23-2008 |
| 20090019255 | System and Method for Cache-Locking Mechanism Using Segment Table Attributes for Replacement Class ID Determination - A system, method, and program product are provided that identifies a cache set using Segment LookAside Buffer attributes. When an effective address is requested, an attempt is made to load the received effective address from an L2 cache. When this attempt results in a cache miss, the system identifies a segment within the Segment LookAside Buffer that includes the effective address. A class identifier is retrieved from the identified segment within the Segment LookAside Buffer. This class identifier identifies a cache set selected from the cache for replacement. Data is then reloaded into the cache set of the cache by using the retrieved class identifier that corresponds to the effective address. | 01-15-2009 |
| 20090037689 | Optimal Use of Buffer Space by a Storage Controller Which Writes Retrieved Data Directly to a Memory - A storage controller which uses the same buffer to store data elements retrieved from different secondary storage units. In an embodiment, the controller retrieves location descriptors ahead of when data is available for storing in a target memory. Each location descriptor indicates the memory locations at which data received from a secondary storage is to be stored. Only a subset of the location descriptors may be retrieved and stored ahead when processing each request. Due to such retrieval and storing of limited number of location descriptors, the size of a buffer used by the storage controller may be reduced. Due to retrieval of the location descriptors ahead, unneeded buffering of the data elements within the storage controller is avoided, reducing the latency in writing the data into the main memory, thus improving performance. | 02-05-2009 |
| 20090063809 | SYSTEM AND METHOD FOR PARALLEL SCANNING - A system and method for parallel scanning among multiple scanning entities. According to various embodiments of the present invention, buffers are allocated from a pool of memory pages, with one packet being located on each page. Each of the pages is mapped such that unprivileged scanners, privileged scanners, and hardware-based scanners are all capable of accessing the pages. By having the packets located on separate pages, additional data other than the packets at issue do not have to be shared, and copying is not necessary to complete the scanning process. | 03-05-2009 |
| 20090113165 | Method and System for Automatically Distributing Real Memory Between Virtual Memory Page Sizes - A method, system and computer program product for allocating real memory to virtual memory page sizes when all real memory is in use is disclosed. In response to a page fault, a page frame for a virtual page is selected. In response to determining that said page does not represent a new page, a page is paged-in into said page frame a repaging rate for a page size of the page is modified in a repaging rates data structure. | 04-30-2009 |
| 20090172345 | TRANSLATION MANAGEMENT OF LOGICAL BLOCK ADDRESSES AND PHYSICAL BLOCK ADDRESSES - Systems and/or methods that facilitate PBA and LBA translations associated with a memory component(s) are presented. A memory controller component facilitates determining which memory component, erase block, page, and data block contains a PBA in which a desired LBA and/or associated data is stored. The memory controller component facilitates control of performance of calculation functions, table look-up functions, and/or search functions to locate the desired LBA. The memory controller component generates a configuration sequence based in part on predefined optimization criteria to facilitate optimized performance of translations. The memory controller component and/or associated memory component(s) can be configured so that the translation attributes are determined in a desired order using the desired translation function(s) to determine a respective translation attribute based in part on the predefined optimization criteria. The LBA to PBA translations can be performed in parallel by memory components. | 07-02-2009 |
| 20090172346 | TRANSITIONING BETWEEN SOFTWARE COMPONENT PARTITIONS USING A PAGE TABLE POINTER TARGET LIST - Embodiments of apparatuses, articles, methods, and systems for intra-partitioning components within an execution environment, and transitioning between partitions using a page table pointer target list are generally described herein. Other embodiments may be described and claimed. | 07-02-2009 |
| 20090187732 | DYNAMIC ADDRESS TRANSLATION WITH DAT PROTECTION - What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of any one of a region first table, a region second table, a region third table, or a segment table are obtained. Based on the obtained initial origin address, a segment table entry is obtained which contains a format control and DAT protection fields. If the format control field is enabled, obtaining from the translation table entry a segment-frame absolute address of a large block of data in main storage. The segment-frame absolute address is combined with a page index portion and a byte index portion of the virtual address to form a translated address of the desired block of data. If the DAT protection field is not enabled, fetches and stores are permitted to the desired block of data addressed by the translated virtual address. | 07-23-2009 |
| 20090198953 | Full Virtualization of Resources Across an IP Interconnect Using Page Frame Table - An addressing model is provided where devices, including I/O devices, are addressed with internet protocol (IP) addresses, which are considered part of the virtual address space. A task, such as an application, may be assigned an effective address range, which corresponds to addresses in the virtual address space. The virtual address space is expanded to include Internet protocol addresses. Thus, the page frame tables are also modified to include entries for IP addresses and additional properties for devices and I/O. Thus, a processing element, such as an I/O adapter or even a printer, for example, may also be addressed using IP addresses without the need for library calls, device drivers, pinning memory, and so forth. This addressing model also provides full virtualization of resources across an IP interconnect, allowing a process to access an I/O device across a network. | 08-06-2009 |
| 20120191942 | FACILITATING MANAGEMENT OF STORAGE OF A PAGEABLE MODE VIRTUAL ENVIRONMENT ABSENT INTERVENTION OF A HOST OF THE ENVIRONMENT - Host page management assist functions are employed to manage storage of a pageable mode virtual environment. These functions enable storage to be managed by a processor of the environment absent intervention of a host of the environment. The functions include a resolve host page function; a pin function; and unpin functions. | 07-26-2012 |
| 20120221829 | METHOD FOR MANAGING A MEMORY APPARATUS - A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: recording valid/invalid page position information of at least one block; and moving valid data contained in at least a valid page of the block according to the valid/invalid page position information; where the block is an erasing unit. For example, the valid/invalid page position information may contain relative position information of the valid data in the block. More particularly, the valid/invalid page position information may contain a plurality of bits, the ranking of each bit may represent a page address offset of each page within the block, and each bit may respectively indicate whether each page in the block is valid or invalid. | 08-30-2012 |
| 20130007409 | ON-DEMAND PAGING-IN OF PAGES WITH READ-ONLY FILE SYSTEM - Disclosed is a computer implemented method to resume a process at an arrival machine that is in an identical state to a frozen process on a departure machine. The arrival machine receives checkpoint data for the process from the departure machine. It creates the process. It updates a page table, wherein the page table comprises a segment, page number, and offset corresponding to a page of the process available from a remote paging device, wherein the remote paging device is remote from the arrival machine. It resumes the process and responsively generates a page fault for the page. It looks up the page in the page table, responsive to the page fault. It determines whether the page is absent in the arrival machine. It transmits a page-in request to the departure machine, responsive to a determination that the page is absent. It receives the page from the departure machine. | 01-03-2013 |
| 20130019081 | SYSTEMS AND METHODS FOR MEMORY REGION DESCRIPTOR ATTRIBUTE OVERRIDEAANM MOYER; WILLIAM C.AACI Dripping SpringsAAST TXAACO USAAGP MOYER; WILLIAM C. Dripping Springs TX US - A memory protection unit (MPU) is configured to store a plurality of region descriptor entries, each region descriptor entry defining an address region of a memory, an attribute corresponding to the region, and an attribute override control corresponding to the attribute. A memory access request to a memory address is received and determined to be within a first address region defined by a first region descriptor entry and within a second address region defined by a second region descriptor entry. When the attribute override control of the first region descriptor entry indicates that override is to be performed, the value of the attribute of the first region descriptor entry is applied for the memory access. When the attribute override control of the second region descriptor entry indicates that override is to be performed, the value of the attribute of the second region descriptor entry is applied for the memory access. | 01-17-2013 |
| 20130080736 | SYSTEMS AND METHODS FOR UNIQUELY DEFINING FORTRAN RUN TIME TYPE DESCRIPTORS FOR POLYMORPHIC ENTITIES - Systems and methods disclosed herein uniquely define each type of Fortran type descriptor within an executable file or shared library to allow for a rapid determination of how the dynamic type of one object (e.g., a first polymorphic entity) relates to that of another object (e.g., a second polymorphic entity) while allowing for the lazy loading of shared libraries. In one aspect, type descriptor definitions are instantiated (e.g., during compile-time) in each object file in which polymorphic entities are defined, each type descriptor definition is marked with a singleton attribute, and each group of common type descriptor definitions is associated with a COMDAT group to ensure that only a single copy of each type descriptor is defined in a corresponding executable file at a particular address in memory to which polymorphic entities can reference. Type descriptor addresses can be compared to determine dynamic type relations between polymorphic entities. | 03-28-2013 |
| 20130262817 | HYBRID ADDRESS TRANSLATION - Embodiments of the invention relate to hybrid address translation. An aspect of the invention includes receiving a first address, the first address referencing a location in a first address space. The computer searches a segment lookaside buffer (SLB) for a SLB entry corresponding to the first address; the SLB entry comprising a type field and an address field and determines whether a value of the type field in the SLB entry indicates a hashed page table (HPT) search or a radix tree search. Based on determining that the value of the type field indicates the HPT search, a HPT is searched to determine a second address, the second address comprising a translation of the first address into a second address space; and based on determining that the value of the type field indicates the radix tree search, a radix tree is searched to determine the second address. | 10-03-2013 |
| 20130326189 | EXTENSIBLE METHOD AND SYSTEM FOR STORAGE METADATA - According to an aspect of an embodiment, a system of using an extensible language to represent storage metadata includes a computer-readable storage medium and a processing device. The computer-readable storage medium may have stored thereon storage metadata. The processing device may be configured to write the storage metadata to the computer-readable storage medium in an extensible language format. The processing device may also be configured to manipulate the storage metadata in the extensible language format. The processing device may also be configured to transfer the storage metadata in the extensible language format. | 12-05-2013 |
| 20140019711 | DISPERSED STORAGE NETWORK VIRTUAL ADDRESS SPACE - A dispersed storage network utilizes a virtual address space to store data. The dispersed storage network includes a dispersed storage device for receiving a request relating to a data object stored in the dispersed storage network and determining a virtual memory address assigned to the data object. The virtual memory address is within a virtual memory address range of the virtual address space that is allocated to a vault associated with a user of the data object. The virtual memory address is further assigned to a data slice of a plurality of data slices of the data object. The dispersed storage device uses the virtual memory address to determine an identifier of a storage unit within the dispersed storage network that has the data slice stored therein. | 01-16-2014 |
| 20140032875 | Physical Memory Forensics System and Method - The method of the present inventive concept is configured to utilize Operating System data structures related to memory-mapped binaries to reconstruct processes. These structures provide a system configured to facilitate the acquisition of data that traditional memory analysis tools fail to identify, including by providing a system configured to traverse a virtual address descriptor, determine a pointer to a control area, traverse a PPTE array, copy binary data identified in the PPTE array, generate markers to determine whether the binary data is compromised, and utilize the binary data to reconstruct a process. | 01-30-2014 |
| 20140189286 | WEAR LEVELING WITH MARCHING STRATEGY - A method for managing utilization of a memory including a physical address space comprises mapping logical addresses of data objects to locations within the physical address space, and defining a plurality of address segments in the space as an active window. The method comprises allowing writes of data objects having logical addresses mapped to locations within the plurality of address segments in the active window. The method comprises, upon detection of a request to write a data object having a logical address mapped to a location outside the active window, updating the mapping so that the logical address maps to a selected location within the active window, and then allowing the write to the selected location. The method comprises maintaining access data indicating utilization of the plurality of address segments in the active window, and adding and removing address segments from the active window in response to the access data. | 07-03-2014 |
| 20140304489 | VARIABLE LENGTH ENCODING IN A STORAGE SYSTEM - A system and method for maintaining a mapping table in a data storage subsystem. A data storage subsystem supports multiple mapping tables including a plurality of entries. Each of the entries comprise a tuple including a key. A data storage controller is configured to encode each tuple in the mapping table using a variable length encoding. Additionally, the mapping table may be organized as a plurality of time ordered levels, with each level including one or more mapping table entries. Further, a particular encoding of a plurality of encodings for a given tuple may be selected based at least in part on a size of the given tuple as unencoded, a size of the given tuple as encoded, and a time to encode the given tuple. | 10-09-2014 |
| 20150019834 | MEMORY HIERARCHY USING PAGE-BASED COMPRESSION - A system includes a device coupleable to a first memory. The device includes a second memory to cache data from the first memory. The second memory is to store a set of compressed pages of the first memory and a set of page descriptors. Each compressed page includes a set of compressed data blocks. Each page descriptor represents a corresponding page and includes a set of location identifiers that identify the locations of the compressed data blocks of the corresponding page in the second memory. The device further includes compression logic to compress data blocks of a page to be stored to the second memory and decompression logic to decompress compressed data blocks of a page accessed from the second memory. | 01-15-2015 |
| 20150339227 | System and Method for Simultaneously Storing and Reading Data from a Memory System - A system and method for providing high-speed memory operations is disclosed. The technique uses virtualization of memory space to map a virtual address space to a larger physical address space wherein no memory bank conflicts will occur. The larger physical address space is used to prevent memory bank conflicts from occurring by moving the virtualized memory addresses of data being written to memory to a different location in physical memory that will eliminate a memory bank conflict. This allows the memory system to both store and read data in the same cycle with no conflicts. | 11-26-2015 |
| 20150356023 | PARAVIRTUALIZATION-BASED INTERFACE FOR MEMORY MANAGEMENT IN VIRTUAL MACHINES - A method for memory virtualization in a system including guest virtual, guest physical and host physical address spaces, a guest pagetable for translating addresses of the guest virtual address space into addresses of the guest physical address space, a shadow pagetable for translating addresses of the guest virtual address space into addresses of the host physical address space, and a hypervisor configured for calculating address entries for the shadow pagetable from valid address entries in the guest pagetable, includes managing, by the hypervisor, one or more shadow pagetable(s) by the hypervisor while a guest context is executed by a guest operating system, wherein the number of shadow pagetable(s) is smaller than or equal to the number of guest contexts in a current working set. | 12-10-2015 |
| 20160019160 | Methods and Systems for Scalable and Distributed Address Mapping Using Non-Volatile Memory Modules - In a method to provide scalable and distributed address mapping in a storage device, a host command that specifies an operation to be performed and a logical address corresponding to a portion of memory within the storage device is received or accessed. A storage controller of the storage device maps the specified logical address to a first subset of a physical address, using a first address translation table, and identifies an NVM module of the plurality of NVM modules, in accordance with the first subset of a physical address. The method further includes, at the identified NVM module, mapping the specified logical address to a second subset of the physical address, using a second address translation table, identifying the portion of non-volatile memory within the identified NVM module corresponding to the specified logical address, and executing the specified operation on the portion of memory in the identified NVM module. | 01-21-2016 |
| 20160179662 | INSTRUCTION AND LOGIC FOR PAGE TABLE WALK CHANGE-BITS | 06-23-2016 |
