Entries |
Document | Title | Date |
20080201551 | Virtual disk router system and virtual disk access system and method therefor - A virtual disk (VD) router system, a VD access system, and a method therefor, applied to a dual-controller system including a first controller and a second controller, are provided. First, a mapping virtual block device (VBD) corresponding to a VD of the second controller and/or the first controller is established in the first controller and/or the second controller, and a mapping relation list and a data transmission channel of the VD and the corresponding VBD thereof are established. When the first controller/the second controller issues an access request to the VD of the second controller/the first controller, the data transmission channel is used to transmit the access request to the VD and transmit the response data to the access request from the VD. Therefore, the overall access to all the VDs in the dual-controller system can be achieved. | 08-21-2008 |
20080229053 | Expanding memory support for a processor using virtualization - In one embodiment, the present invention includes a system including a processor to access a maximum memory space of a first size using a memory address having a first length, a chipset coupled to the processor to interface the processor to a memory including a physical memory space, where the chipset is to access a maximum memory space larger than the first maximum memory space, and a virtual machine monitor (VMM) to enable the processor to access the full physical memory space of a memory. Other embodiments are described and claimed. | 09-18-2008 |
20080235485 | ECC implementation in non-ECC components - A method and apparatus for implementation of error correction code (ECC) checking in non-ECC-compliant components. The method includes receiving a logical address, wherein the logical address maps to first and second physical addresses of a memory. The first and second physical addresses of the memory correspond to memory locations that store data and a corresponding ECC, respectively. The method further comprises translating the logical address into the first and second physical addresses, accessing the data over a data path, separately accessing the ECC over the same data path, and checking the integrity of the data using the ECC. | 09-25-2008 |
20080250222 | Apparatus and method for providing virtualized hardware resources within a virtual execution environment - Embodiments described are generally directed to a system and method for providing virtualized hardware resources within a virtual execution environment. In one embodiment, it is determined whether an operating system (OS) is a guest OS running within a virtual execution environment of a host platform. If an OS is determined to be a guest OS within a virtual execution environment, a virtual driver is provided for the virtual execution to fetch host hardware initiator information from a host server via a virtualization layer. In one embodiment, no corresponding guest driver is available to the virtual execution environment. In one embodiment, the virtualization layer provides virtualized hardware resources, including the virtual driver, for a virtual execution environment. Using the host hardware initiator information, in one embodiment, one or more virtual storage devices may be created within the host attached storage of the host platform. Other embodiments are described and claimed. | 10-09-2008 |
20080270736 | Information processing apparatus and access control method - According to one embodiment, an information processing apparatus includes a processor including a register file which holds physical registers to which general purpose registers provided by an instruction set architecture are assigned, a virtual register assigning unit which assigns a virtual address in the main memory space to a physical register in the register file based on a request from a program, and records a correspondence between each of the virtual addresses and a corresponding one of the physical registers in a virtual register conversion table, and an access converting unit which determines whether or not a virtual address to be accessed is recorded in the virtual register conversion table managed by the virtual register assigning unit, and executes, when the virtual address is recorded therein, processing of accessing the physical register of which a correspondence to the virtual address is recorded in the virtual register conversion table. | 10-30-2008 |
20080270737 | Data Processing System And Method - Embodiments provide a data processing system comprising at least one hard partition comprising a plurality of virtual partitions; each of the virtual partitions comprising respective virtual address spaces accessible via a memory access means for relating virtual addresses to real addresses of a real memory; wherein each virtual address space comprises respective unique virtual addresses. | 10-30-2008 |
20080307190 | System and Method for Improved Virtual Real Memory - A method for providing virtual real memory includes receiving a request for a memory page from a requestor. A system determines whether the requested memory page is available. In the event the requested memory page is available, the system satisfies the request. In the event the requested memory page is not available, the system generates a page fault interrupt, wherein the page fault interrupt comprises a first page fault correlation number (PFCID) identifying a restorative process, and wherein the restorative process is configured to restore the requested memory page to available memory. The system monitors a plurality of pending processes and determines whether the restorative process is complete. In the event the restorative process is complete, the system notifies the requester that the restorative process is complete. | 12-11-2008 |
20080320269 | METHOD AND APPARATUS FOR RANKING OF TARGET SERVER PARTITIONS FOR VIRTUAL SERVER MOBILITY OPERATIONS - A computer implemented method, data processing system, and computer program product for automated ranking of target server partitions based on current workload partition performance state. When a violation of a stack tier policy for the virtualized process collection in a source logical partition is detected, the stack tier comprising the virtualized process collection is examined to determine a scalability of the stack tier. A set of logical partitions are examined to identify target logical partitions for the migration event, wherein the target logical partitions are compatible for migrating the virtualized process collection based on the scalability of the stack tier. A performance state of the virtualized process collection is analyzed, and the target logical partitions for selection in the migration event are ranked based on the performance states of the virtualized process collection and the stack tier policy. | 12-25-2008 |
20090006804 | BI-LEVEL MAP STRUCTURE FOR SPARSE ALLOCATION OF VIRTUAL STORAGE - Apparatus and method for accessing a virtual storage space. The space is arranged across a plurality of storage elements, and a skip list is used to map as individual nodes each of a plurality of non-overlapping ranges of virtual block addresses of the virtual storage space from a selected storage element. | 01-01-2009 |
20090013148 | BLOCK ADDRESSING FOR PARALLEL MEMORY ARRAYS - Apparatus and methods provide associative mapping of the blocks of two or more memory arrays such that data, such as pages of data, from the good blocks of the two or more memory arrays can be read in an alternating manner for speed or can be read in parallel for providing data to relatively wide data channels. This obviates the need for processor intervention to access data and can increase the throughput of data by providing, where configured, the ability to alternate reading of data from two or more arrays. For example, while one array is loading data to a cache, the memory device can be providing data that has already been loaded to the cache. | 01-08-2009 |
20090031102 | MAPPING AN N-BIT APPLICATION PORTED FROM AN M-BIT APPLICATION TO AN N-BIT ARCHITECTURE - Embodiments of the present invention provide a system that maps an N-bit application to virtual memory. The N-bit application may be obtained by porting an M-bit application to an N-bit architecture where N is greater than M. During operation, the system receives a request to map an N-bit application to a computer's virtual memory. The system then maps the N-bit application to a section of virtual memory which begins at a memory address that is greater than or equal to 2 | 01-29-2009 |
20090049270 | SYSTEM AND METHOD FOR USING A MEMORY MAPPING FUNCTION TO MAP MEMORY DEFECTS - A system and method are herein disclosed for managing memory defects in an information handling system. More particularly, a system and method are described for generating a usable memory map which excludes memory locations containing defect memory elements. In an information handling system, a memory defect map, which contains information about the location of defective memory elements, is coupled to the memory device. As a map of memory usable by the system is created, usable memory regions containing defective memory elements are excluded from the memory map. The memory map is passed to the operating system, which uses only those regions of memory designated as usable and non-defective. | 02-19-2009 |
20090055622 | Processor, virtual memory system, and virtual storing method - A processor includes an address specifying unit that specifies an address range on a virtual storage area; an instruction code setting unit that sets an instruction code for a process of deciding data corresponding to the specified address range; a calculating unit that calculates the data corresponding to the address range, according to the instruction code set for the address range; a load instruction obtaining unit that obtains a load instruction for the specified address range; and a data output unit that supplies the data calculated by the calculating unit corresponding to the address range indicated by the load instruction, as data for the load instruction. | 02-26-2009 |
20090055623 | Method and Apparatus for Supporting Shared Library Text Replication Across a Fork System Call - A fork system call by a first process is detected. A second process is created as a replication of the first process with a second affinity. If a replication of the replicated shared library is present in the second affinity domain, effective addresses of the replication of the replicated shared library are mapped using a mapping mechanism of the present invention to physical addresses in the second affinity domain. | 02-26-2009 |
20090089537 | APPARATUS AND METHOD FOR MEMORY ADDRESS TRANSLATION ACROSS MULTIPLE NODES - A method for translating memory addresses in a plurality of nodes, that includes receiving a first memory access request initiated by a processor of a first node of the plurality of nodes, wherein the first memory access request comprises a process virtual address and a first memory operation, translating the process virtual address to a global system address, wherein the global system address corresponds to a physical memory location on a second node of the plurality of nodes, translating the global system address to an identifier corresponding to the second node, and sending a first message requesting the first memory operation to the second node based on the identifier, wherein the second node performs the first memory operation on the physical memory location. | 04-02-2009 |
20090150642 | Indexing Page Attributes - Embodiments of the invention provide methods and apparatus for increasing the number of page attributes specified by a page table while minimizing an increase in size of the page table. According to embodiments of the invention, attribute index bits may be included within a page table and may be used to determine page attributes stored within an attribute index. Additionally, embodiments of the invention provide a plurality of new page attributes. | 06-11-2009 |
20090150643 | SAS reference Phys for virtualization and traffic isolation - Enabling virtualization in a SAS expander is disclosed. For each SAS address to be virtualized through one or more physical or virtual Phy, a reference Phy associated with each SAS address is created within the expander. Next, a route table is generated that includes an entry for each of the SAS addresses being virtualized, each entry associated with one or more of the physical or virtual Phy through which the SAS address is being virtualized. With the route table so established, requests for a virtualized SAS address are routed to a particular one of the one or more physical or virtual Phy associated with the virtualized SAS address in the route table. | 06-11-2009 |
20090172340 | Methods and arrangements to remap non-volatile storage - Methods and arrangements for remapping the map between logical space and physical space in non-volatile storage are described. Embodiments include transformations, code, state machines or other logic to divide the non-volatile storage of the computing device into two portions, a fixed portion and a floating portion. The embodiments may also include remapping in system firmware of the computing device the current map from logical space to physical space of the floating portion of the non-volatile storage. The embodiments may also include storing the revised map. The embodiments may also include using the revised map to access the floating portion of the non-volatile storage. | 07-02-2009 |
20090198948 | Techniques for Data Prefetching Using Indirect Addressing - A technique for performing indirect data prefetching includes determining a first memory address of a pointer associated with a data prefetch instruction. Content of a memory at the first memory address is then fetched. A second memory address is determined from the content of the memory at the first memory address. Finally, a data block (e.g., a cache line) including data at the second memory address is fetched (e.g., from the memory or another memory). | 08-06-2009 |
20090198949 | HYPERVOLUME DATA STORAGE OBJECT AND METHOD OF DATA STORAGE - The present disclosure relates to a data storage device having a hypervolume accessible by a plurality of servers operating on two or more data storage systems, a first physical volume, associated with the hypervolume, located at a first data storage system, and a second physical volume, associated with the hypervolume, located at a second storage system. The hypervolume directs input/output (I/O) from the servers to a primary physical volume comprising either the first or second physical volume, and the primary physical volume may be changed, transparently to the servers, to the other of the first or second physical volume. The present disclosure, in another embodiment, relates to a method for moving operation of a storage device from one data storage location to a second data storage location. A hypervolume is used to redirect input/output (I/O) from the a plurality of servers from the one physical volume to another. | 08-06-2009 |
20090204784 | METHOD AND SYSTEM FOR GEOMETRY-BASED VIRTUAL MEMORY MANAGEMENT - Methods, digital systems, and computer readable media are provided for managing a tiled virtual memory by maintaining a region quadtree representing a current allocation state of tiled virtual memory pages in the tiled virtual memory. | 08-13-2009 |
20090216991 | METHOD AND APPARATUS TO COMBINE SCATTERED BUFFER ADDRESSES INTO A CONTIGUOUS VIRTUAL ADDRESS SPACE - A method of combining scattered buffer addresses into a contiguous virtual address space comprises; receiving a plurality of read completion data portions corresponding to a single read request, storing the plurality of read completion data portions in a memory device such that an individual read completion data portion is stored in an individual address of the memory device, storing a valid indicator for a memory device address which contains the individual read completion data portion in an external storage location, storing a tag indicator associated with the read request for the individual read completion portion in an external storage location associated with the memory device address containing the individual read completion data portion, storing a sequence number associated with an individual read completion data portion in an external storage location associated with the memory device address containing the individual read completion data portion; and outputting an individual read completion data portion from the memory device to an external device. | 08-27-2009 |
20090307459 | SELECTIVELY MARK FREE FRAMES AS UNUSED FOR COOPERATIVE MEMORY OVER-COMMITMENT - Disclosed is a computer implemented method, apparatus and computer program product for communicating virtual memory page status to a virtual memory manager. An operating system may receive a request to free a virtual memory page from a first application. The operating system determines whether the virtual memory page is free due to an operating system page replacement. Responsive to a determination that the virtual memory page is free due to the operating system page replacement, the operating system inhibits marking the virtual memory page as unused. Finally, the operating system may insert the virtual memory page on an operating system free list. | 12-10-2009 |
20090307460 | Data Sharing Utilizing Virtual Memory - A method for sharing memory locations in a virtual memory system is disclosed. The method can include processing instructions and accessing data utilizing a virtual memory system with a paging device that is accessible by multiple clients. The method can also include configuring a first client to access the paging device, configuring a second client to access the paging device and allowing the first and second client to access the paging device via a virtual input output server. Other embodiments are also disclosed. | 12-10-2009 |
20090307461 | Arrangements for Storing and Retrieving Blocks of Data Having Different Dimensions - A method for storing and retrieving blocks of data having different dimensions is disclosed. The method can include receiving a first data segment to be stored in a block storage device where the first data segment has an address. The method can also include determining if the first data segment conforms to a standard dimension and sorting the first data segment according to the destination address if it does not have a standard dimension. The method can further include placing a non-standard data segment into a unfilled block allocation and placing a second non-standard data segment into the unfilled block allocation when the second data segment has the destination identifier. Other embodiments are also disclosed. | 12-10-2009 |
20090313452 | MANAGEMENT OF PERSISTENT MEMORY IN A MULTI-NODE COMPUTER SYSTEM - A method and apparatus creates and manages persistent memory (PM) in a multi-node computing system. A PM Manager in the service node creates and manages pools of nodes with various sizes of PM. A node manager uses the pools of nodes to load applications to the nodes according to the size of the available PM. The PM Manager can dynamically adjust the size of the PM according to the needs of the applications based on historical use or as determined by a system administrator. The PM Manager works with an operating system kernel on the nodes to provide persistent memory for application data and system metadata. The PM Manager uses the persistent memory to load applications to preserve data from one application to the next. Also, the data preserved in persistent memory may be system metadata such as file system data that will be available to subsequent applications. | 12-17-2009 |
20100005269 | Translation of virtual to physical addresses - Address translation circuitry for translating virtual addresses to physical addresses for a data processor in response to access requests from said data processor targeting virtual addresses is disclosed. The address translation circuitry comprises: a data store comprising a plurality of entries for storing a plurality of mappings of ranges of virtual addresses to ranges of physical addresses for said data processor and additional data associated with each of said plurality of mappings within a table; updating circuitry for updating said table in response to an access request for a virtual address that is not mapped by said table, said updating circuitry being responsive to receipt of a mapping for said virtual address to: select a plurality of entries in said table suitable for storing said received mapping; and determine one of said plurality of selected entries to be overwritten by said received mapping in dependence upon at least a portion of said additional data stored in said one of said plurality of selected entries. | 01-07-2010 |
20100049940 | Memory Controller for Non-Homogeneous Memory System - A memory controller includes at least one interface adapted to be coupled to one or more first memory devices of a first memory type having a first set of attributes, and to one or more second memory devices of a second memory type having a second set of attributes. The first and second sets of attributes have at least one differing attribute. The controller also includes interface logic configured to direct memory transactions having a predefined first characteristic to the first memory devices and to direct memory transactions having a predefined second characteristic to the second memory devices. Pages having a usage characteristic of large volumes of write operations may be mapped to the one or more first memory devices, while pages having a read-only or read-mostly usage characteristic may be mapped to the one or more second memory devices. | 02-25-2010 |
20100058024 | Data Transfer Apparatus, Data Transfer Method And Processor - A processor includes a CPU core which executes a user program, and a data transfer apparatus. The CPU core stores a transfer request from a user program in a specific area of a main memory, in which the transfer request specifies the virtual addresses of a transfer source and a transfer destination in a memory space allocated to the user program. The data transfer apparatus refers to the specific area of the main memory and acquires a transfer request asynchronously to processing performed by the CPU core. The data transfer apparatus then identifies physical addresses corresponding to virtual addresses specified in the transfer request. After that, the data transfer apparatus transcribes original data stored in a storage area indicated by the physical address of the transfer source, to a storage area in a cache memory related to the virtual address or physical address of the transfer destination. | 03-04-2010 |
20100115228 | Unified address space architecture - A multiprocessor computer system has a plurality of first processors having a first addressable memory space, and a plurality of second processors having a second addressable memory space. The second addressable memory space is of a different size than the first addressable memory space, and the first addressable memory space and second addressable memory space comprise a part of the same common address space. | 05-06-2010 |
20100250893 | BATCHED VIRTUAL MEMORY REMAPPING FOR EFFICIENT GARBAGE COLLECTION OF LARGE OBJECT AREAS - A method and system for batched remapping of virtual addresses for garbage collection in a large object area. A mapping from a table having a first set of virtual addresses and sizes of non-contiguous, page-aligned large objects in a large object area to a remapping table having a second set of virtual addresses is determined. In a single batch, a request is received that includes the second set of virtual addresses and requests a remapping of the large objects to the second set of virtual addresses. The second set of virtual memory addresses is validated. The large objects are remapped to the second set of virtual memory addresses according to the request. The remapping results in a compaction so that the large objects are contiguous in the large object area. The remapping does not require copying data in physical memory. | 09-30-2010 |
20100306498 | STORAGE SYSTEM AND STORAGE CONTROL METHOD THAT COMPRESS AND STORE DATA ELEMENTS - A pool is formed based on a plurality of storage devices. This pool is constituted by a plurality of real pages. Real pages of different lengths are included in this plurality of real pages. Among a plurality of virtual pages which make up a virtual volume, a controller compresses a write data element for a write destination virtual page, selects a real page of a real page length based on the data length of a data unit including the compressed write data element, and allocates the selected real page to the write destination virtual page. | 12-02-2010 |
20100325383 | ASYMMETRIC MEMORY MIGRATION IN HYBRID MAIN MEMORY - Main memory is managed by receiving a command from an application to read data associated with a virtual address that is mapped to the main memory. A memory controller determines that the virtual address is mapped to one of the symmetric memory components of the main memory, and accesses memory use characteristics indicating how the data associated with the virtual address has been accessed, The memory controller determines that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory and loads the data associated with the virtual address to the asymmetric memory component of the main memory. After the loading and using the memory management unit, a command is received from the application to read the data associated with the virtual address, and the data associated with the virtual address is retrieved from the asymmetric memory component. | 12-23-2010 |
20110087856 | Memory Device with Serial Protocol and Corresponding Method of Addressing - The memory device comprises a physical memory plane (PMP) comprising m first physical lines (RGP | 04-14-2011 |
20110107056 | METHOD FOR DETERMINING DATA CORRELATION AND A DATA PROCESSING METHOD FOR A MEMORY - A method for determining data correlation and a data processing method for a memory are disclosed. The data with correlation is collected and stored in the same block. Also the data with correlation is determined based on a specific function to be executed by the user. In other words, if the user needs to access some data in order to perform the specific function, those data has correlation. | 05-05-2011 |
20110145541 | METHOD AND SYSTEM TO ACCELERATE ADDRESS TRANSLATION - In a method to accelerate address translation into a physical address, a computer maps a virtual memory area with a large page, the virtual memory area including multiple virtual pages satisfying a predetermined condition and being handled in units of pages, the large page having a larger area than each of the virtual pages, and under a condition in which one of the virtual pages mapped with and included in the large page has a memory protection attribute different from a memory protection attribute of the other virtual page, sets physical memory protection information for protecting a physical page corresponding to the one virtual page having the different memory protection attribute. | 06-16-2011 |
20110225387 | Unified Virtual Contiguous Memory Manager - Memory management methods and computing apparatus with memory management capabilities are disclosed. One exemplary method includes mapping an address from an address space of a physically-mapped device to a first address of a common address space so as to create a first common mapping instance, and encapsulating an existing processor mapping that maps an address from an address space of a processor to a second address of the common address space to create a second common mapping instance. In addition, a third common mapping instance between an address from an address space of a memory-management-unit (MMU) device and a third address of the common address space is created, wherein the first, second, and third addresses of the common address space may be the same address or different addresses, and the first, second, and third common mapping instances may be manipulated using the same function calls. | 09-15-2011 |
20110238946 | Data Reorganization through Hardware-Supported Intermediate Addresses - A virtual address scheme for improving performance and efficiency of memory accesses of sparsely-stored data items in a cached memory system is disclosed. In a preferred embodiment of the present invention, a special address translation unit is used to translate sets of non-contiguous addresses in real memory into contiguous blocks of addresses in an “intermediate address space.” This intermediate address space is a fictitious or “virtual” address space, but is distinguishable from the virtual address space visible to application programs, and in user-level memory operations, effective addresses seen/manipulated by application programs are translated into intermediate addresses by an additional address translation unit for memory caching purposes. This scheme allows non-contiguous data items in memory to be assembled into contiguous cache lines for more efficient caching/access (due to the perceived spatial proximity of the data from the perspective of the processor). | 09-29-2011 |
20110264886 | System and Method for Managing Memory - Systems and methods that manage memory are provided. In one embodiment, a system for communications may include, for example, a memory management system that may handle a first application employing a virtual address based tagged offset and a second application employing a zero based tagged offset with a common set of memory algorithms. | 10-27-2011 |
20110283083 | Configuring Surrogate Memory Accessing Agents Using Non-Priviledged Processes - Configuring a surrogate memory accessing agent using an instruction for translating and storing a data value is described. In one embodiment, the instruction is received that includes a first operand specifying a data value to be translated and a second operand specifying a virtual address associated with a location of a surrogate memory accessing agent register in which to store the data value. The data value can be translated to a first physical address. The virtual address can be translated to a second physical address. The first physical address is stored in the surrogate memory accessing agent register based on the second physical address. | 11-17-2011 |
20110289295 | SYSTEM, METHOD, AND MEDIA FOR NETWORK TRAFFIC MEASUREMENT ON HIGH-SPEED ROUTERS - A data structure is provided for storing network contact information based on an array of physical memory locations. Virtual vectors are constructed for each source, wherein each element in each virtual vector is assigned to a corresponding physical memory location within the array. The physical memory locations are shared between the virtual vectors uniformly at random so that the noise introduced by sharing can be predicted and removed. A method for storing network contact information is also provided in which a hash function is performed using the address of a source host to find a virtual vector for holding information about the source host. A second hash function is performed using the address of a destination host to find a virtual memory location, within the virtual vector, for holding information about the destination host. Finally, information is stored at a physical memory location assigned to the virtual memory location. Estimation range enhancement is further provided by performing multiple estimations with different sampling probabilities and selecting a best estimation based on a maximum likelihood method. | 11-24-2011 |
20110307681 | Apparatus and method for mapping architectural registers to physical registers - An apparatus and method are provided for performing register renaming, whereby architectural registers from a set of architectural registers are mapped to physical registers from a set of physical registers. Available register identifying circuitry is provided which is responsive to a current state of the apparatus to identify which physical registers form a pool of physical registers available to be mapped by register renaming circuitry to an architectural register specified by an instruction to be executed. Configuration storage stores configuration data whose value is modified during operation of the processing circuitry, such that when the configuration data has a first value, the configuration data identifies at least one architectural register of the architectural register set which does not require mapping to a physical register by the register renaming circuitry. The available register identifying circuitry is arranged to reference the configuration storage, such that when the configuration data has the first value, the number of physical registers in the pool is increased due to the reduction in the number of architectural registers which require mapping to physical registers. This enables the performance benefits from performing register renaming to be improved, without the need to increase the number of physical registers within the physical register set. | 12-15-2011 |
20120005451 | DATA STORAGE DEVICE AND BAD BLOCK MANAGING METHOD THEREOF - A data storage device includes a storage unit, and a controller configured to control the storage unit, wherein the controller is configured to manage a mapping between a logical address space and a virtual address space of the storage unit, virtual address space of the storage unit being variable. | 01-05-2012 |
20120072696 | METHOD FOR DIAGNOSING A MEMORY OF AN ELECTRONIC DEVICE - A electronic device includes a diagnosing system, a processor, a storage system, a memory, and one or more programs. The one or more programs includes a determining module, an obtaining module, a processing module, and a display module. The determining module determines whether there is a bad sector in the memory. If there is a bad sector in the memory, the determining module generates an obtaining signal. The obtaining module obtains the virtual address of the bad sector according to the obtaining signal. The processing module converts the virtual address into the corresponding physical address. | 03-22-2012 |
20120089807 | METHOD AND APPARATUS FOR FLOATING POINT REGISTER CACHING - The present invention provides a method and apparatus for floating-point register caching. One embodiment of the method includes mapping a first set of architected registers defined by a first instruction set to a memory outside of a plurality of physical registers. The plurality of physical registers are configured to map to the first set, a second set of architected registers defined by a second construction set, and a set of rename registers. This embodiment of the method also includes adding the physical registers corresponding to the first set of architected registers to the set of rename registers. | 04-12-2012 |
20120102294 | Storage System and Storage Control Method that Compress and Store Data Elements - A pool is formed based on a plurality of storage devices. This pool is constituted by a plurality of real pages. Real pages of different lengths are included in this plurality of real pages. Among a plurality of virtual pages which make up a virtual volume, a controller compresses a write data element for a write destination virtual page, selects a real page of a real page length based on the data length of a data unit including the compressed write data element, and allocates the selected real page to the write destination virtual page. | 04-26-2012 |
20120110296 | ELECTRONIC APPARATUS - A diagnostic tool sends a request format designating a virtual address, which is different from a real address for an EEPROM. When a microcomputer determines that an address designated by the received request format is a virtual address assigned to the EEPROM, the microcomputer executes a process, which is designated by the received request format, with respect to the virtual address assigned to the EEPROM. | 05-03-2012 |
20120151177 | Data Deduplication in a Virtualization Environment - Techniques are described herein that are capable of optimizing (i.e., deduplicating) data in a virtualization environment. For example, optimization designations (a.k.a. deduplication designations) may be assigned to respective regions of a virtualized storage file. A virtualized storage file is a file that is configured to be mounted as a disk or a volume to provide a file system interface for accessing hosted files. In accordance with this example, each optimization designation indicates an extent to which the respective region is to be optimized (i.e., deduplicated). In another example, a virtualized storage file is mounted to provide a virtual disk that includes hosted files. In accordance with this example, optimization designations are assigned to the respective hosted files. In further accordance with this example, each optimization designation indicates an extent to which the respective hosted file is to be optimized. | 06-14-2012 |
20120159114 | REGISTER FILE AND COMPUTING DEVICE USING THE SAME - A register file is provided. The register file includes a plurality of registers configured to form at least one register cluster, each of the registers being configured to have a virtual index defined for each cluster and a physical index defined for each register, and an index converting unit configured to convert the virtual index to the physical index. | 06-21-2012 |
20120159115 | SOFTWARE ARCHITECTURE FOR SERVICE OF COLLECTIVE MEMORY AND METHOD FOR PROVIDING SERVICE OF COLLECTIVE MEMORY USING THE SAME - Disclosed is a software architecture supporting a large-capacity collective memory layer in a multi-node system by using a remote direct memory access technique and a software virtualization technique and a computing system performing computing processing by using the architecture. In particular, provided is a software architecture including: a memory region managing module collectively managing a predetermined memory region of a node, a memory service providing module providing a large-capacity collective memory service to a virtual address space in a user process, and a memory sharing support module supporting sharing of the large-capacity collective memory of the multi-node system. | 06-21-2012 |
20120166755 | Switching Apparatus and Data Management Method of Same - According to one embodiment, a switching apparatus includes a storage module, a setting module, a managing module and a reconstruction module. The storage module stores data pertaining to the switching function by dividing the data into a plurality of groups. The setting module sets, for each of the plurality of groups, a base address to be allocated by an operating system when the program is started up. The managing module records and manages the base address and data size information of each group when the program is terminated. The reconstruction module, when the program is started up, refers to the base address and the data size information recorded when the program is terminated last time, and reconstructs data in the virtual memory space for each of the plurality of groups based on a reference result. | 06-28-2012 |
20120179891 | EXTENSION OF WRITE ANYWHERE FILE SYSTEM LAYOUT - A file system layout apportions an underlying physical volume into one or more virtual volumes (vvols) of a storage system. The underlying physical volume is an aggregate comprising one or more groups of disks, such as RAID groups, of the storage system. The aggregate has its own physical volume block number (pvbn) space and maintains metadata, such as block allocation structures, within that pvbn space. Each vvol has its own virtual volume block number (vvbn) space and maintains metadata, such as block allocation structures, within that vvbn space. Notably, the block allocation structures of a vvol are sized to the vvol, and not to the underlying aggregate, to thereby allow operations that manage data served by the storage system (e.g., snapshot operations) to efficiently work over the vvols. | 07-12-2012 |
20120185667 | VIRTUAL-MEMORY SYSTEM WITH VARIABLE-SIZED PAGES - A method for managing a virtual memory system configured to allow variable-sized pages is provided. The size of a page is not required to be a power of two. Variable, arbitrarily-sized pages are mapped to a contiguous segment or virtual address space. The method also provides for efficient relocation, insertion, and removal of data in a virtual memory region. The method also provides virtual lookup-tables. | 07-19-2012 |
20120198204 | FAST MASKED SUMMING COMPARATOR - A fast masked summing comparator apparatus includes a comparator unit configured to compare a masked first number to a masked sum of a second number and a third number to determine whether the masked sum is equivalent to the masked first number without performing a summation portion of an addition operation between the second number and the third number. The comparator unit may concurrently mask both the sum and the first number using the same mask value. | 08-02-2012 |
20120254581 | SYSTEM AND METHOD FOR CONTROLLING NONVOLATILE MEMORY - A memory system, comprises a nonvolatile memory comprising multiple memory cells, and a memory controller configured to control respective cell levels of the memory cells by assigning a logical address of each memory cell to one of multiple address groups according to a frequency with which the logical address has been accessed, determining a cell level for each address group, and controlling each memory cell to have the cell level of the address group to which its logical address is assigned. | 10-04-2012 |
20120284485 | OPERATING SYSTEM VIRTUAL MEMORY MANAGEMENT FOR HARDWARE TRANSACTIONAL MEMORY - Operating system virtual memory management for hardware transactional memory. A system includes an operating system deciding to unmap a first virtual page. As a result, the operating system removes the mapping of the first virtual page to the first physical page from the virtual memory page table. As a result, the operating system performs an action to discard transactional memory hardware state for at least the first physical page. Embodiments may further suspend hardware transactions in kernel mode. Embodiments may further perform soft page fault handling without aborting a hardware transaction, resuming the hardware transaction upon return to user mode, and even successfully committing the hardware transaction. | 11-08-2012 |
20130013887 | MEMORY CONTROLLER - An address comparator stores an address of data read out by a host system. Also, a buffer reads out the data from a memory and stores the data. If an address of data which is expected to be newly read out by the host system is included in addresses which have already been stored in the address comparator, the host system | 01-10-2013 |
20130024644 | METHODS FOR OPTIMIZING DATA MOVEMENT IN SOLID STATE DEVICES - Techniques for optimizing data movement in electronic storage devices are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for optimizing data movement in electronic storage devices comprising maintaining, on the electronic storage device, a data structure associating virtual memory addresses with physical memory addresses. Information can be provided regarding the data structure to a host which is in communication with the electronic storage device. Commands can be received from the host to modify the data structure on the electronic storage device, and the data structure can be modified in response to the received command. | 01-24-2013 |
20130031328 | TECHNIQUES FOR BALANCING ACCESSES TO MEMORY HAVING DIFFERENT MEMORY TYPES - Embodiments of the present technology are directed toward techniques for balancing memory accesses to different memory types. | 01-31-2013 |
20130054933 | DYNAMIC ADDRESS CHANGE OPTIMIZATIONS - A method of setting an address of a component that includes determining a characterization value associated with a consumable, calculating a number of address change operations based upon the characterization value, and setting a last address generated from the number of address change operations as the new address of the component, wherein the characterization value is determined based upon a usage of the consumable. | 02-28-2013 |
20130054934 | Method and Apparatus for Performing Mapping Within a Data Processing System Having Virtual Machines - In an environment in which a processor operates a hypervisor and multiple guest partitions operating under the hypervisor's control, it is desirable to allow a guest partition access to a physical memory device without decreasing system performance. Accordingly, a conversion instruction for converting a logical address to a real address, i.e., an LTOR instruction, executable from a guest partition, is added to the processor. Upon the guest partition's execution of the conversion instruction with the logical address specified, the processor converts the logical address to an encrypted real address, and returns it to the guest partition. The guest partition is then able to pass the encrypted real address to an accelerator that converts the encrypted real address to a real address in order to access the memory device using the real address. | 02-28-2013 |
20130080730 | FLASH MEMORY SYSTEM - A method and system for controlling an MBC configured flash memory device to store data in an SBC storage mode, or a partial MBC storage mode. In a full MBC storage mode, pages of data are programmed sequentially from a first page to an Nth page for each physical row of memory cells. Up to N virtual page addresses per row of memory cells accompany each page to be programmed for designating the virtual position of the page in the row. For SBC or partial MBC data storage, a flash memory controller issues program command(s) to the MBC memory device using less than the maximum N virtual page addresses for each row. The MBC memory device sequentially executes programming operations up to the last received virtual page address for the row. | 03-28-2013 |
20130091338 | INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD AND PROGRAM PRODUCT - An information processing device includes a first storage unit configured to store a set value indicating a value corresponding to a set item to define a function and flag information indicating whether an initialization of the set value is required, a second storage unit configured to store a flag address identifying a storage location of the flag information in the first storage unit in association with the set item at least, and an initialization unit configured to identify the flag information for each set item by using the flag address corresponding to each set item, and if the identified flag address indicates that the initialization is required, initialize the set value corresponding to the set item. | 04-11-2013 |
20130111182 | STORING A SMALL FILE WITH A REDUCED STORAGE AND MEMORY FOOTPRINT | 05-02-2013 |
20130191609 | INFORMATION PROCESSING DEVICE INCLUDING HOST DEVICE AND SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE - A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information. | 07-25-2013 |
20130246732 | METHOD OF PROGRAMMING MEMORY CELLS AND READING DATA, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS USING THE SAME - A method of programming memory cells for a rewritable non-volatile memory module is provided. The method includes: receiving a command which indicates performing an update operation to a logical page; and identifying valid logical access addresses and invalid logical access addresses in the logical page according to the command. The method also includes: selecting a physical page; setting flags corresponding to the valid logical access addresses in a valid state, setting flags corresponding to the invalid logical access in an invalid state; programming the flags and data belonging to the valid logical access addresses to the selected physical page based on the update operation; and mapping the selected physical page to the logical page. Accordingly, the method can effectively increase the speed of programming the memory cells. | 09-19-2013 |
20130275715 | METHOD, APPARATUS, AND SYSTEM FOR EFFICIENTLY HANDLING MULTIPLE VIRTUAL ADDRESS MAPPINGS DURING TRANSACTIONAL EXECUTION - An apparatus and method is described herein for providing structures to support software memory re-ordering within atomic sections of code. Upon a start or end of a critical section, speculative bits of a translation buffer are reset. When a speculative memory access causes an address translation of a virtual address to a physical address, the translation buffer is searched to determine if another entry (a different virtual address) includes the same physical address. And if another entry does include the same physical address, the speculative execution is failed to provide protection from invalid execution resulting from the memory re-ordering. | 10-17-2013 |
20130290668 | METHOD AND APPARATUS FOR ADJUSTABLE VIRTUAL ADDRESSING FOR DATA STORAGE - Methods and apparatuses for adjusting the size of a virtual band or virtual zone of a storage medium are provided. In one embodiment, an apparatus may comprise a data storage device including a data storage medium having a physical zone; and a processor configured to receive a virtual addressing adjustment command, and adjust a number of virtual addresses in a virtual band mapped to the physical zone based on the virtual addressing adjustment command. In another embodiment, a method may comprise providing a data storage device configured to implement virtual addresses associated with a virtual band mapped to a physical zone of a data storage medium of the data storage device, receiving at the data storage device a virtual addressing adjustment command, and adjusting a number of virtual addresses in a virtual band based on the virtual addressing adjustment command. | 10-31-2013 |
20130305010 | DIFFERENTIAL DELAY COMPENSATION - In one embodiment, a method comprises receiving a plurality of data frames representing at least one virtually concatenated data stream, storing the plurality of data frames in a memory; and recording, for each of a plurality of data frames, a physical write address that indicates a position in the memory and a virtual write address that includes a multiframe indicator and a byte number indicator. | 11-14-2013 |
20140040592 | ACTIVE BUFFERED MEMORY - According to one embodiment of the present invention, a method for operating a memory device that includes memory and a processing element includes receiving, in the processing element, a command from a requestor, loading, in the processing element, a program based on the command, the program comprising a load instruction loaded from a first memory location in the memory, and performing, by the processing element, the program, the performing including loading data in the processing element from a second memory location in the memory. The method also includes generating, by the processing element, a virtual address of the second memory location based on the load instruction and translating, by the processing element, the virtual address into a real address. | 02-06-2014 |
20140068223 | Address Server - A mechanism is provided for attributing network addresses to virtual machines. A request for a number of addresses is received from a requesting entity, thereby forming a requested number of addresses. A length of continuous ranges of available addresses is compared to the requested number of addresses. A range of available addresses comprising a number of addresses greater than the requested number of addresses is selected from a memory, thereby forming a selected range of available addresses. A first new range comprising the requested number of addresses excised from the selected range of available addresses is defined and one or more further new ranges are defined comprising the remainder of the selected range of available addresses not belonging to the first new range. The first new range is attributed for the use of the requesting entity. | 03-06-2014 |
20140095827 | MEMORY STORAGE DEVICE, AND A RELATED ZONE-BASED BLOCK MANAGEMENT AND MAPPING METHOD - A storage device is disclosed, in which the device comprises memory ( | 04-03-2014 |
20140122826 | DETECTING MEMORY CORRUPTION - A device identifies, based on a program code instruction, an attempted write access operation to a fenced memory slab, where the fenced memory slab includes an alternating sequence of data buffers and guard buffers. The device assigns read-only protection to the fenced slab and invokes, based on the attempted write access operation, a page fault operation. When a faulting address of the attempted write operation is not an address for one of the multiple data buffers, the device performs a panic routine. When the faulting address of the attempted write operation is an address for one of the multiple data buffers, the device removes the read-only protection for the fenced slab and performs a single step processing routine for the program code instruction. | 05-01-2014 |
20140208059 | HIGHLY CONFIGURABLE MEMORY ARCHITECTURE FOR PARTITIONED GLOBAL ADDRESS SPACE MEMORY SYSTEMS - A system and method for identifying from an address an appropriate target node and a location in that node that holds desired data related to that address is provided. The system and method includes a logical address generator that generates a logical address. The system and method includes a subspace index extraction module that extracts a subspace index from the logical address. The system and method includes a subspace configuration table that retrieves a plurality of parameters of the subspace index to locate the desired data. | 07-24-2014 |
20140281350 | MULTI-LAYERED STORAGE ADMINISTRATION FOR FLEXIBLE PLACEMENT OF DATA - A storage administrator may maintain location information in separate layers. A data storage system may identify the location of particular data by identifying the virtual location of data, such as the logical extent to which the data belongs. Object stores may maintain mappings of virtual locations to physical locations, such as mappings of extent identifiers to virtual storage objects and mappings of virtual storage objects to storage unit locations. When particular data is relocated to a new location, a storage administrator may update mappings used to translate virtual locations to physical locations, such as an extent-object mapping or an object-storage unit mapping. References to the virtual locations, such as references to logical extent identifiers, may not be updated in response to the relocation of data. | 09-18-2014 |
20140310499 | SYSTEMS, METHODS AND INTERFACES FOR DATA VIRTUALIZATION - A data services module performs log storage operations in response to requests by storing data on one or more storage devices, and appending information pertaining to the requests to a separate metadata log. A log order of the metadata log may correspond to an order in which the requests were received, regardless of the order in which data of the requests are written to the storage devices. The requests may correspond to identifiers of a logical address space. The data services module implements an any-to-any translation layer configured to map identifiers of the logical address space to the stored data. The virtualization module may include a metadata management module configured to checkpoint the translation layer metadata by, inter alia, appending aggregate, checkpoint entries to the metadata log. The data services module may leverage the translation layer between the logical identifiers and underlying storage locations to efficiently implement logical manipulation operations. | 10-16-2014 |
20150012721 | SEAMLESS APPLICATION ACCESS TO HYBRID MAIN MEMORY - A command from an application is received to access a data structure associated with one or more virtual addresses mapped to main memory. A first subset of the virtual addresses for the data structure having constituent addresses that are mapped to the symmetric memory components and a second subset of the virtual addresses for the data structure having constituent addresses that are mapped to the asymmetric memory components are identified. Data associated with the virtual address from the first physical addresses and data associated with the virtual addresses from the second physical addresses are accessed. The data associated with the symmetric and asymmetric memory components is accessed by the application without providing the application with an indication of whether the data is accessed within the symmetric memory component or the asymmetric memory component. | 01-08-2015 |
20150039849 | Multi-Layer Data Storage Virtualization Using a Consistent Data Reference Model - A write request that includes a data object is processed. A hash function is executed on the data object, thereby generating a hash value that includes a first portion and a second portion. A hypervisor table is queried with the first portion, thereby obtaining a master storage node identifier. The data object and the hash value are sent to a master storage node associated with the master storage node identifier. At the master storage node, a master table is queried with the second portion, thereby obtaining a storage node identifier. The data object and the hash value are sent from the master storage node to a storage node associated with the storage node identifier. | 02-05-2015 |
20150106584 | System and Method for Simultaneously Storing and Read Data From A Memory System - A system and method for providing high-speed memory operations is disclosed. The technique uses virtualization of memory space to map a virtual address space to a larger physical address space wherein no memory bank conflicts will occur. The larger physical address space is used to prevent memory bank conflicts from occurring by moving the virtualized memory addresses of data being written to memory to a different location in physical memory that will eliminate a memory bank conflict. This allows the memory system to both store and read data in the same cycle with no conflicts. | 04-16-2015 |
20150106585 | ADDRESS GENERATION IN A DATA PROCESSING APPARATUS - A data processing apparatus is provided comprising processing circuitry and an instruction decoder responsive to program instructions to control processing circuitry to perform the data processing. The instruction decoder is responsive to an address calculating instruction to perform an address calculating operation for calculating a partial address result from a non-fixed reference address and a partial offset value such that a full address specifying a memory location of an information entity is calculable from said partial address result using at least one supplementary program instruction. The partial offset value has a bit-width greater than or equal to said instruction size and is encoded within at least one partial offset field of said address calculating instruction. A corresponding data processing method, virtual machine and computer program product are also provided. | 04-16-2015 |
20150121032 | Data Deduplication in a Virtualization Environment - Techniques are described herein that are capable of optimizing (i.e., deduplicating) data in a virtualization environment. For example, optimization designations (a.k.a. deduplication designations) may be assigned to respective regions of a virtualized storage file. A virtualized storage file is a file that is configured to be mounted as a disk or a volume to provide a file system interface for accessing hosted files. In accordance with this example, each optimization designation indicates an extent to which the respective region is to be optimized (i.e., deduplicated). In another example, a virtualized storage file is mounted to provide a virtual disk that includes hosted files. In accordance with this example, optimization designations are assigned to the respective hosted files. In further accordance with this example, each optimization designation indicates an extent to which the respective hosted file is to be optimized. | 04-30-2015 |
20150301945 | SYSTEM AND METHOD FOR ONE STEP ADDRESS TRANSLATION OF GRAPHICS ADDRESSES IN VIRTUALIZATION - A system and method including, in some embodiments, receiving a request for a graphics memory address for an input/output (I/O) device assigned to a virtual machine in a system that supports virtualization, and installing, in a graphics memory translation table, a physical guest graphics memory address to host physical memory address translation. | 10-22-2015 |
20160098355 | OPTIMISTIC DATA READ - A storage module may include a controller that is configured to perform a read operation to read data stored in at least one memory, where the data is associated with logical address information. In order to perform the read operation, the controller may be configured to retrieve a preliminary physical address associated with the logical address information, and initiate a data retrieval process for a first version of the data stored at the preliminary physical address prior to confirming a final physical address associated with the logical address information. | 04-07-2016 |
20160170679 | SECONDARY CPU MMU INITIALIZATION USING PAGE FAULT EXCEPTION | 06-16-2016 |
20160170902 | LOW OVERHEAD PAGED MEMORY RUNTIME PROTECTION | 06-16-2016 |
20160179432 | INFORMATION PROCESSING APPARATUS AND MEMORY MANAGEMENT METHOD | 06-23-2016 |
20160179797 | DATA EXPANSE USING MEMORY-MAPPED FILES ON A SYSTEM ARCHITECTURE INTERFACE LAYER-BASED MAINFRAME OPERATING SYSTEM | 06-23-2016 |
20160378676 | METHODS AND APPARATUS TO RE-DIRECT DETECTED ACCESS REQUESTS IN A MODULARIZED VIRTUALIZATION TOPOLOGY USING VIRTUAL HARD DISKS - Methods, apparatus are articles of manufacture are disclosed to re-direct detected access requests in a modularized virtualization topology using virtual hard disks. An example method includes detecting, with a processor, a request to access a software asset at a first path location on a first virtual hard disk. The example method also includes determining, with the processor, whether the first path location is mapped to a second path location in a virtual computing environment, the second path location corresponding to a second virtual hard disk encapsulating a functionality originally associated with the first path location. The example method also includes, when the first path location is mapped to the second path location, re-directing, with the processor, the request to the second virtual hard disk. | 12-29-2016 |
20180024923 | PAGE RANKING IN OPERATING SYSTEM VIRTUAL PAGES IN HYBRID MEMORY SYSTEMS | 01-25-2018 |